diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml index 104377d311..ed86a0b04c 100644 --- a/.gitlab/ci/pre_check.yml +++ b/.gitlab/ci/pre_check.yml @@ -75,7 +75,7 @@ check_chip_support_components: expire_in: 1 week script: - python tools/ci/check_soc_headers_leak.py - - find ${IDF_PATH}/components/soc/*/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py + - find ${IDF_PATH}/components/soc/**/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py - tools/ci/check_esp_memory_utils_headers.sh check_esp_err_to_name: diff --git a/Kconfig b/Kconfig index 0391cfcc89..1c6b973c44 100644 --- a/Kconfig +++ b/Kconfig @@ -119,6 +119,7 @@ mainmenu "Espressif IoT Development Framework Configuration" select FREERTOS_UNICORE select IDF_TARGET_ARCH_RISCV + # TODO: IDF-9197 choice IDF_TARGET_ESP32C5_VERSION prompt "ESP32-C5 version" depends on IDF_TARGET_ESP32C5 @@ -132,6 +133,11 @@ mainmenu "Espressif IoT Development Framework Configuration" bool prompt "ESP32-C5 beta3" select ESPTOOLPY_NO_STUB + + config IDF_TARGET_ESP32C5_MP_VERSION + bool + prompt "ESP32-C5 MP" + select ESPTOOLPY_NO_STUB endchoice config IDF_TARGET_ESP32P4 @@ -159,7 +165,8 @@ mainmenu "Espressif IoT Development Framework Configuration" default 0x000D if IDF_TARGET_ESP32C6 default 0x0010 if IDF_TARGET_ESP32H2 default 0x0012 if IDF_TARGET_ESP32P4 - default 0x0011 if IDF_TARGET_ESP32C5 + default 0x0011 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_BETA3_VERSION # TODO: IDF-9197 + default 0x0017 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_MP_VERSION # TODO: IDF-9197 default 0xFFFF diff --git a/components/bootloader/subproject/main/CMakeLists.txt b/components/bootloader/subproject/main/CMakeLists.txt index 90b9c47322..c66e46cc35 100644 --- a/components/bootloader/subproject/main/CMakeLists.txt +++ b/components/bootloader/subproject/main/CMakeLists.txt @@ -1,10 +1,18 @@ idf_component_register(SRCS "bootloader_start.c" REQUIRES bootloader bootloader_support) -idf_build_get_property(target IDF_TARGET) -set(scripts "ld/${target}/bootloader.ld") +if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) + set(target_folder "esp32c5/beta3") +elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + set(target_folder "esp32c5/mp") +else() + set(target_folder "${target}") +endif() -list(APPEND scripts "ld/${target}/bootloader.rom.ld") +idf_build_get_property(target IDF_TARGET) +set(scripts "ld/${target_folder}/bootloader.ld") + +list(APPEND scripts "ld/${target_folder}/bootloader.rom.ld") target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}") target_link_libraries(${COMPONENT_LIB} INTERFACE "-u bootloader_hooks_include") diff --git a/components/bootloader/subproject/main/ld/esp32c5/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld similarity index 100% rename from components/bootloader/subproject/main/ld/esp32c5/bootloader.ld rename to components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld diff --git a/components/bootloader/subproject/main/ld/esp32c5/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.rom.ld similarity index 100% rename from components/bootloader/subproject/main/ld/esp32c5/bootloader.rom.ld rename to components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.rom.ld diff --git a/components/bootloader/subproject/main/ld/esp32c5/mp/.gitkeep b/components/bootloader/subproject/main/ld/esp32c5/mp/.gitkeep new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index 54279d1e18..481310d587 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -8,6 +8,9 @@ #include #include "esp_assert.h" +// TODO: IDF-9197 +#include "sdkconfig.h" + /** * @brief ESP chip ID * @@ -21,7 +24,11 @@ typedef enum { ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */ ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */ ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */ - ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 */ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-9197 + ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/ +#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */ +#endif ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/components/esp_hw_support/include/esp_chip_info.h b/components/esp_hw_support/include/esp_chip_info.h index d4871a08bd..afe1d811e8 100644 --- a/components/esp_hw_support/include/esp_chip_info.h +++ b/components/esp_hw_support/include/esp_chip_info.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,7 +27,11 @@ typedef enum { CHIP_ESP32C2 = 12, //!< ESP32-C2 CHIP_ESP32C6 = 13, //!< ESP32-C6 CHIP_ESP32H2 = 16, //!< ESP32-H2 - CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3 TODO: [ESP32-C5] update when MP supported +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-9197 + CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3 (MPW) +#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + CHIP_ESP32C5 = 23, //!< ESP32-C5 MP +#endif CHIP_ESP32P4 = 18, //!< ESP32-P4 CHIP_POSIX_LINUX = 999, //!< The code is running on POSIX/Linux simulator } esp_chip_model_t; diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index de6d90dcae..a7bb2e0f68 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -1,6 +1,15 @@ idf_build_get_property(target IDF_TARGET) -set(include_dirs "include" "include/${target}") +# TODO: IDF-9197 +if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) + set(target_folder "esp32c5/beta3/esp32c5") +elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + set(target_folder "esp32c5/mp/esp32c5") +else() + set(target_folder "${target}") +endif() + +set(include_dirs "include" "include/${target_folder}") set(private_required_comp "") @@ -12,7 +21,10 @@ if(target STREQUAL "linux") "${target}/esp_rom_md5.c" "${target}/esp_rom_efuse.c") else() - list(APPEND include_dirs "${target}") + list(APPEND include_dirs "${target_folder}") + if(CONFIG_IDF_TARGET_ESP32C5) + list(APPEND include_dirs "include/${target_folder}/..") + endif() list(APPEND sources "patches/esp_rom_crc.c" "patches/esp_rom_sys.c" "patches/esp_rom_uart.c" @@ -67,7 +79,7 @@ set(ld_folder "ld") # Append a target linker script at the target-specific path, # only the 'name' part is different for each script function(rom_linker_script name) - target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.${name}.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.${name}.ld") endfunction() if(target STREQUAL "linux") @@ -79,7 +91,7 @@ if(target STREQUAL "linux") target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-integer-overflow -Wno-shift-count-overflow) endif() else() - target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld") rom_linker_script("api") if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB) diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in index fce9a24ae3..20c519bbcb 100644 --- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in @@ -3,78 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config ESP_ROM_HAS_CRC_LE - bool - default y +if IDF_TARGET_ESP32C5_BETA3_VERSION + source "$IDF_PATH/components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in" +endif -config ESP_ROM_HAS_CRC_BE - bool - default y - -config ESP_ROM_HAS_JPEG_DECODE - bool - default y - -config ESP_ROM_UART_CLK_IS_XTAL - bool - default y - -config ESP_ROM_USB_SERIAL_DEVICE_NUM - int - default 3 - -config ESP_ROM_HAS_RETARGETABLE_LOCKING - bool - default y - -config ESP_ROM_GET_CLK_FREQ - bool - default y - -config ESP_ROM_HAS_RVFPLIB - bool - default y - -config ESP_ROM_HAS_HAL_WDT - bool - default y - -config ESP_ROM_HAS_HAL_SYSTIMER - bool - default y - -config ESP_ROM_HAS_HEAP_TLSF - bool - default y - -config ESP_ROM_TLSF_CHECK_PATCH - bool - default y - -config ESP_ROM_HAS_LAYOUT_TABLE - bool - default y - -config ESP_ROM_HAS_SPI_FLASH - bool - default y - -config ESP_ROM_WITHOUT_REGI2C - bool - default y - -config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT - bool - default y - -config ESP_ROM_WDT_INIT_PATCH - bool - default y - -config ESP_ROM_RAM_APP_NEEDS_MMU_INIT - bool - default y - -config ESP_ROM_USB_OTG_NUM - int - default -1 +if IDF_TARGET_ESP32C5_MP_VERSION + source "$IDF_PATH/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in" +endif diff --git a/components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in new file mode 100644 index 0000000000..fce9a24ae3 --- /dev/null +++ b/components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in @@ -0,0 +1,80 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config ESP_ROM_HAS_CRC_LE + bool + default y + +config ESP_ROM_HAS_CRC_BE + bool + default y + +config ESP_ROM_HAS_JPEG_DECODE + bool + default y + +config ESP_ROM_UART_CLK_IS_XTAL + bool + default y + +config ESP_ROM_USB_SERIAL_DEVICE_NUM + int + default 3 + +config ESP_ROM_HAS_RETARGETABLE_LOCKING + bool + default y + +config ESP_ROM_GET_CLK_FREQ + bool + default y + +config ESP_ROM_HAS_RVFPLIB + bool + default y + +config ESP_ROM_HAS_HAL_WDT + bool + default y + +config ESP_ROM_HAS_HAL_SYSTIMER + bool + default y + +config ESP_ROM_HAS_HEAP_TLSF + bool + default y + +config ESP_ROM_TLSF_CHECK_PATCH + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y + +config ESP_ROM_WITHOUT_REGI2C + bool + default y + +config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT + bool + default y + +config ESP_ROM_WDT_INIT_PATCH + bool + default y + +config ESP_ROM_RAM_APP_NEEDS_MMU_INIT + bool + default y + +config ESP_ROM_USB_OTG_NUM + int + default -1 diff --git a/components/esp_rom/esp32c5/beta3/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/beta3/esp32c5/esp_rom_caps.h new file mode 100644 index 0000000000..924a30c23a --- /dev/null +++ b/components/esp_rom/esp32c5/beta3/esp32c5/esp_rom_caps.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian +#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian +#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library +#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM +#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. +#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking +#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib +#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver +#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver +#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs +#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions) +#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init +#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.api.ld similarity index 100% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.api.ld diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.heap.ld similarity index 96% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.heap.ld index 62200c5af5..0996a0a515 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.heap.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM function interface esp32c5.rom.heap.ld for esp32c5 * * diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.ld similarity index 99% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.ld index ce63a26314..58e5292c71 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM function interface esp32c5.rom.ld for esp32c5 * * @@ -575,4 +580,3 @@ slc_reattach = 0x40000c64; slc_send_to_host_chain = 0x40000c68; slc_set_host_io_max_window = 0x40000c6c; slc_to_host_chain_recycle = 0x40000c70; - diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.libgcc.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.libgcc.ld similarity index 95% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.libgcc.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.libgcc.ld index 2634ce20ba..a8e0ba9edf 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.libgcc.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.libgcc.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM function interface esp32c5.rom.libgcc.ld for esp32c5 * * @@ -112,4 +117,3 @@ __umodsi3 = 0x400009d0; __unorddf2 = 0x400009d4; __extenddftf2 = 0x400009d8; __trunctfdf2 = 0x400009dc; - diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-normal.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib-normal.ld similarity index 88% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-normal.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib-normal.ld index aa93ad1355..6c55b0270c 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-normal.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib-normal.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5 * * @@ -34,4 +39,3 @@ vsnprintf = 0x40000614; vsniprintf = 0x40000618; sscanf = 0x4000061c; siscanf = 0x40000620; - diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib.ld similarity index 94% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.newlib.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib.ld index d36e57b7ec..aa6bfaf1a4 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM function interface esp32c5.rom.newlib.ld for esp32c5 * * @@ -92,4 +97,3 @@ __swsetup_r = 0x400005cc; /* Data (.data, .bss, .rodata) */ syscall_table_ptr = 0x4087ffd4; _global_impure_ptr = 0x4087ffd0; - diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.rvfp.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.rvfp.ld similarity index 96% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.rvfp.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.rvfp.ld index 8fbe9c2651..c1e585036b 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.rvfp.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.rvfp.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM function interface esp32c5.rom.rvfp.ld for esp32c5 * * diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.spiflash.ld similarity index 97% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.spiflash.ld index 7528ca7c74..89c04f538f 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.spiflash.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM function interface esp32c5.rom.spiflash.ld for esp32c5 * * @@ -158,4 +163,3 @@ spi_flash_encryption_hal_prepare = 0x40000380; spi_flash_encryption_hal_done = 0x40000384; spi_flash_encryption_hal_destroy = 0x40000388; spi_flash_encryption_hal_check = 0x4000038c; - diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.version.ld b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.version.ld similarity index 66% rename from components/esp_rom/esp32c5/ld/esp32c5.rom.version.ld rename to components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.version.ld index e139c043c9..3683e2c38b 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.version.ld +++ b/components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.version.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* ROM version variables for esp32c5 * * These addresses should be compatible with any ROM version for this chip. diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h index 924a30c23a..b64679dd98 100644 --- a/components/esp_rom/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/esp_rom_caps.h @@ -1,27 +1,17 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian -#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian -#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM -#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. -#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking -#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` -#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib -#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver -#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver -#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library -#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() -#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table -#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver -#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs -#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions) -#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock -#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init -#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. +#include "sdkconfig.h" + +// TODO: IDF-9197 This file is created to glob the version specific soc_caps correctly + +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION +#include "beta3/esp32c5/esp_rom_caps.h" // recursive, condition: IDF_TARGET_ESP32C5_BETA3_VERSION +#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION +#include "mp/esp32c5/esp_rom_caps.h" // recursive, condition: IDF_TARGET_ESP32C5_MP_VERSION +#endif diff --git a/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in new file mode 100644 index 0000000000..51b3aa0d10 --- /dev/null +++ b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in @@ -0,0 +1,4 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### diff --git a/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h new file mode 100644 index 0000000000..dd3f635e54 --- /dev/null +++ b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once diff --git a/components/esp_rom/include/esp32c5/rom/aes.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/aes.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/aes.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/aes.h diff --git a/components/esp_rom/include/esp32c5/rom/bigint.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/bigint.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/bigint.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/bigint.h diff --git a/components/esp_rom/include/esp32c5/rom/cache.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/cache.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/cache.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/cache.h diff --git a/components/esp_rom/include/esp32c5/rom/crc.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/crc.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/crc.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/crc.h diff --git a/components/esp_rom/include/esp32c5/rom/digital_signature.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/digital_signature.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/digital_signature.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/digital_signature.h diff --git a/components/esp_rom/include/esp32c5/rom/ecdsa.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/ecdsa.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/ecdsa.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/ecdsa.h diff --git a/components/esp_rom/include/esp32c5/rom/efuse.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/efuse.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/efuse.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/efuse.h diff --git a/components/esp_rom/include/esp32c5/rom/ets_sys.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/ets_sys.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/ets_sys.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/ets_sys.h diff --git a/components/esp_rom/include/esp32c5/rom/hmac.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/hmac.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/hmac.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/hmac.h diff --git a/components/esp_rom/include/esp32c5/rom/libc_stubs.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/libc_stubs.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/libc_stubs.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/libc_stubs.h diff --git a/components/esp_rom/include/esp32c5/rom/lldesc.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/lldesc.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/lldesc.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/lldesc.h diff --git a/components/esp_rom/include/esp32c5/rom/md5_hash.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/md5_hash.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/md5_hash.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/md5_hash.h diff --git a/components/esp_rom/include/esp32c5/rom/miniz.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/miniz.h similarity index 86% rename from components/esp_rom/include/esp32c5/rom/miniz.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/miniz.h index f0baecabdc..8dbb16a8bf 100644 --- a/components/esp_rom/include/esp32c5/rom/miniz.h +++ b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/miniz.h @@ -5,4 +5,4 @@ */ #warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead" -#include "../../miniz.h" +#include "../../../../miniz.h" diff --git a/components/esp_rom/include/esp32c5/rom/rom_layout.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rom_layout.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/rom_layout.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rom_layout.h diff --git a/components/esp_rom/include/esp32c5/rom/rsa_pss.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rsa_pss.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/rsa_pss.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rsa_pss.h diff --git a/components/esp_rom/include/esp32c5/rom/rtc.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/rtc.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h diff --git a/components/esp_rom/include/esp32c5/rom/secure_boot.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/secure_boot.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/secure_boot.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/secure_boot.h diff --git a/components/esp_rom/include/esp32c5/rom/sha.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/sha.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/sha.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/sha.h diff --git a/components/esp_rom/include/esp32c5/rom/spi_flash.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/spi_flash.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/spi_flash.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/spi_flash.h diff --git a/components/esp_rom/include/esp32c5/rom/uart.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/uart.h similarity index 100% rename from components/esp_rom/include/esp32c5/rom/uart.h rename to components/esp_rom/include/esp32c5/beta3/esp32c5/rom/uart.h diff --git a/components/esp_rom/include/esp32c5/mp/esp32c5/rom/.gitkeep b/components/esp_rom/include/esp32c5/mp/esp32c5/rom/.gitkeep new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/esp_system/ld/esp32c5/memory.ld.in b/components/esp_system/ld/esp32c5/beta3/memory.ld.in similarity index 100% rename from components/esp_system/ld/esp32c5/memory.ld.in rename to components/esp_system/ld/esp32c5/beta3/memory.ld.in diff --git a/components/esp_system/ld/esp32c5/sections.ld.in b/components/esp_system/ld/esp32c5/beta3/sections.ld.in similarity index 100% rename from components/esp_system/ld/esp32c5/sections.ld.in rename to components/esp_system/ld/esp32c5/beta3/sections.ld.in diff --git a/components/esp_system/ld/esp32c5/mp/.gitkeep b/components/esp_system/ld/esp32c5/mp/.gitkeep new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/esp_system/ld/ld.cmake b/components/esp_system/ld/ld.cmake index aa8c1b8121..02abddc286 100644 --- a/components/esp_system/ld/ld.cmake +++ b/components/esp_system/ld/ld.cmake @@ -19,8 +19,16 @@ string(REPLACE "\\n" "\n" TEXT "${PREPROCESSED_LINKER_SCRIPT}") file(WRITE "${TARGET}" "${TEXT}") ]=]) +if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) + set(target_folder "esp32c5/beta3") +elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + set(target_folder "esp32c5/mp") +else() + set(target_folder "${target}") +endif() + function(preprocess_linker_file name_in name_out out_path) - set(script_in "${CMAKE_CURRENT_LIST_DIR}/${target}/${name_in}") + set(script_in "${CMAKE_CURRENT_LIST_DIR}/${target_folder}/${name_in}") set(script_out "${CMAKE_CURRENT_BINARY_DIR}/ld/${name_out}") set(${out_path} ${script_out} PARENT_SCOPE) diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index 78041897f0..63877c882b 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -8,10 +8,12 @@ idf_build_get_property(idf_path IDF_PATH) set(chip_model ${target}) -# TODO: [ESP32C5] remove this 'if' block when esp32C5 beta3 is no longer supported +# TODO: [ESP32C5] IDF-9197 remove this 'if' block when esp32C5 beta3 is no longer supported if(target STREQUAL "esp32c5") if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) set(chip_model esp32c5beta3) + elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + set(chip_model esp32c5) endif() endif() diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 7a4edbe222..9f9b4afd25 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -1,143 +1,151 @@ idf_build_get_property(target IDF_TARGET) +if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) + set(target_folder "esp32c5/beta3") +elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + set(target_folder "esp32c5/mp") +else() + set(target_folder "${target}") +endif() + # On Linux the soc component is a simple wrapper, without much functionality if(NOT ${target} STREQUAL "linux") set(srcs "lldesc.c" "dport_access_common.c" - "${target}/interrupts.c" - "${target}/gpio_periph.c" - "${target}/uart_periph.c") + "${target_folder}/interrupts.c" + "${target_folder}/gpio_periph.c" + "${target_folder}/uart_periph.c") endif() -set(includes "include" "${target}") +set(includes "include" "${target_folder}") -if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target}/include") - list(APPEND includes "${target}/include") +if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include") + list(APPEND includes "${target_folder}/include") endif() if(target STREQUAL "esp32") - list(APPEND srcs "${target}/dport_access.c") + list(APPEND srcs "${target_folder}/dport_access.c") endif() if(CONFIG_SOC_ADC_SUPPORTED) - list(APPEND srcs "${target}/adc_periph.c") + list(APPEND srcs "${target_folder}/adc_periph.c") endif() if(CONFIG_SOC_ANA_CMPR_SUPPORTED) - list(APPEND srcs "${target}/ana_cmpr_periph.c") + list(APPEND srcs "${target_folder}/ana_cmpr_periph.c") endif() if(CONFIG_SOC_DEDICATED_GPIO_SUPPORTED) - list(APPEND srcs "${target}/dedic_gpio_periph.c") + list(APPEND srcs "${target_folder}/dedic_gpio_periph.c") endif() if(CONFIG_SOC_GDMA_SUPPORTED) - list(APPEND srcs "${target}/gdma_periph.c") + list(APPEND srcs "${target_folder}/gdma_periph.c") endif() if(CONFIG_SOC_DMA2D_SUPPORTED) - list(APPEND srcs "${target}/dma2d_periph.c") + list(APPEND srcs "${target_folder}/dma2d_periph.c") endif() if(CONFIG_SOC_GPSPI_SUPPORTED) - list(APPEND srcs "${target}/spi_periph.c") + list(APPEND srcs "${target_folder}/spi_periph.c") endif() if(CONFIG_SOC_LEDC_SUPPORTED) - list(APPEND srcs "${target}/ledc_periph.c") + list(APPEND srcs "${target_folder}/ledc_periph.c") endif() if(CONFIG_SOC_PCNT_SUPPORTED) - list(APPEND srcs "${target}/pcnt_periph.c") + list(APPEND srcs "${target_folder}/pcnt_periph.c") endif() if(CONFIG_SOC_RMT_SUPPORTED) - list(APPEND srcs "${target}/rmt_periph.c") + list(APPEND srcs "${target_folder}/rmt_periph.c") endif() if(CONFIG_SOC_SDM_SUPPORTED) - list(APPEND srcs "${target}/sdm_periph.c") + list(APPEND srcs "${target_folder}/sdm_periph.c") endif() if(CONFIG_SOC_I2S_SUPPORTED) - list(APPEND srcs "${target}/i2s_periph.c") + list(APPEND srcs "${target_folder}/i2s_periph.c") endif() if(CONFIG_SOC_I2C_SUPPORTED) - list(APPEND srcs "${target}/i2c_periph.c") + list(APPEND srcs "${target_folder}/i2c_periph.c") endif() if(CONFIG_SOC_TEMP_SENSOR_SUPPORTED) - list(APPEND srcs "${target}/temperature_sensor_periph.c") + list(APPEND srcs "${target_folder}/temperature_sensor_periph.c") endif() if(CONFIG_SOC_GPTIMER_SUPPORTED) - list(APPEND srcs "${target}/timer_periph.c") + list(APPEND srcs "${target_folder}/timer_periph.c") endif() if(CONFIG_SOC_LCDCAM_SUPPORTED OR CONFIG_SOC_LCD_I80_SUPPORTED) - list(APPEND srcs "${target}/lcd_periph.c") + list(APPEND srcs "${target_folder}/lcd_periph.c") endif() if(CONFIG_SOC_MIPI_DSI_SUPPORTED) - list(APPEND srcs "${target}/mipi_dsi_periph.c") + list(APPEND srcs "${target_folder}/mipi_dsi_periph.c") endif() if(CONFIG_SOC_MIPI_CSI_SUPPORTED) - list(APPEND srcs "${target}/mipi_csi_periph.c") + list(APPEND srcs "${target_folder}/mipi_csi_periph.c") endif() if(CONFIG_SOC_PARLIO_SUPPORTED) - list(APPEND srcs "${target}/parlio_periph.c") + list(APPEND srcs "${target_folder}/parlio_periph.c") endif() if(CONFIG_SOC_MCPWM_SUPPORTED) - list(APPEND srcs "${target}/mcpwm_periph.c") + list(APPEND srcs "${target_folder}/mcpwm_periph.c") endif() if(CONFIG_SOC_MPI_SUPPORTED) - list(APPEND srcs "${target}/mpi_periph.c") + list(APPEND srcs "${target_folder}/mpi_periph.c") endif() if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) - list(APPEND srcs "${target}/sdmmc_periph.c") + list(APPEND srcs "${target_folder}/sdmmc_periph.c") endif() if(CONFIG_SOC_TOUCH_SENSOR_SUPPORTED) - list(APPEND srcs "${target}/touch_sensor_periph.c") + list(APPEND srcs "${target_folder}/touch_sensor_periph.c") endif() if(CONFIG_SOC_TWAI_SUPPORTED) - list(APPEND srcs "${target}/twai_periph.c") + list(APPEND srcs "${target_folder}/twai_periph.c") endif() if(CONFIG_SOC_IEEE802154_SUPPORTED) if(NOT target STREQUAL "esp32h4") - list(APPEND srcs "${target}/ieee802154_periph.c") + list(APPEND srcs "${target_folder}/ieee802154_periph.c") endif() endif() if(CONFIG_SOC_USB_OTG_SUPPORTED) if(NOT ${target} STREQUAL "esp32p4") - list(APPEND srcs "${target}/usb_periph.c" - "${target}/usb_dwc_periph.c") + list(APPEND srcs "${target_folder}/usb_periph.c" + "${target_folder}/usb_dwc_periph.c") endif() endif() if(CONFIG_SOC_DAC_SUPPORTED) - list(APPEND srcs "${target}/dac_periph.c") + list(APPEND srcs "${target_folder}/dac_periph.c") endif() if(CONFIG_SOC_RTCIO_PIN_COUNT GREATER 0) - list(APPEND srcs "${target}/rtc_io_periph.c") + list(APPEND srcs "${target_folder}/rtc_io_periph.c") endif() if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED) - list(APPEND srcs "${target}/sdio_slave_periph.c") + list(APPEND srcs "${target_folder}/sdio_slave_periph.c") endif() if(CONFIG_SOC_PAU_SUPPORTED) - list(APPEND srcs "${target}/system_retention_periph.c") + list(APPEND srcs "${target_folder}/system_retention_periph.c") endif() idf_component_register(SRCS ${srcs} @@ -158,5 +166,5 @@ if(target STREQUAL "esp32") endif() if(NOT CONFIG_IDF_TARGET_LINUX) - target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/ld/${target}.peripherals.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld") endif() diff --git a/components/soc/esp32c5/gdma_periph.c b/components/soc/esp32c5/beta3/gdma_periph.c similarity index 100% rename from components/soc/esp32c5/gdma_periph.c rename to components/soc/esp32c5/beta3/gdma_periph.c diff --git a/components/soc/esp32c5/beta3/gpio_periph.c b/components/soc/esp32c5/beta3/gpio_periph.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/soc/esp32c5/i2c_periph.c b/components/soc/esp32c5/beta3/i2c_periph.c similarity index 100% rename from components/soc/esp32c5/i2c_periph.c rename to components/soc/esp32c5/beta3/i2c_periph.c diff --git a/components/soc/esp32c5/include/modem/modem_lpcon_reg.h b/components/soc/esp32c5/beta3/include/modem/modem_lpcon_reg.h similarity index 100% rename from components/soc/esp32c5/include/modem/modem_lpcon_reg.h rename to components/soc/esp32c5/beta3/include/modem/modem_lpcon_reg.h diff --git a/components/soc/esp32c5/include/modem/modem_lpcon_struct.h b/components/soc/esp32c5/beta3/include/modem/modem_lpcon_struct.h similarity index 100% rename from components/soc/esp32c5/include/modem/modem_lpcon_struct.h rename to components/soc/esp32c5/beta3/include/modem/modem_lpcon_struct.h diff --git a/components/soc/esp32c5/include/modem/modem_syscon_reg.h b/components/soc/esp32c5/beta3/include/modem/modem_syscon_reg.h similarity index 100% rename from components/soc/esp32c5/include/modem/modem_syscon_reg.h rename to components/soc/esp32c5/beta3/include/modem/modem_syscon_reg.h diff --git a/components/soc/esp32c5/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/beta3/include/modem/modem_syscon_struct.h similarity index 100% rename from components/soc/esp32c5/include/modem/modem_syscon_struct.h rename to components/soc/esp32c5/beta3/include/modem/modem_syscon_struct.h diff --git a/components/soc/esp32c5/include/modem/reg_base.h b/components/soc/esp32c5/beta3/include/modem/reg_base.h similarity index 100% rename from components/soc/esp32c5/include/modem/reg_base.h rename to components/soc/esp32c5/beta3/include/modem/reg_base.h diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in new file mode 100644 index 0000000000..9ee4745d3f --- /dev/null +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,456 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_UART_SUPPORTED + bool + default y + +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_AHB_GDMA_SUPPORTED + bool + default y + +config SOC_GPTIMER_SUPPORTED + bool + default y + +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_EFUSE_SUPPORTED + bool + default y + +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_I2C_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_ECC_SUPPORTED + bool + default y + +config SOC_ECC_EXTENDED_MODES_SUPPORTED + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_LP_PERIPHERALS_SUPPORTED + bool + default y + +config SOC_SPI_FLASH_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_40M + bool + default y + +config SOC_XTAL_SUPPORT_48M + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 1 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 7 + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CACHE_FREEZE_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_CLIC_SUPPORTED + bool + default y + +config SOC_INT_HW_NESTED_SUPPORTED + bool + default y + +config SOC_BRANCH_PREDICTOR_SUPPORTED + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE + hex + default 0x100 + +config SOC_CPU_HAS_PMA + bool + default y + +config SOC_CPU_IDRAM_SPLIT_USING_PMP + bool + default y + +config SOC_AHB_GDMA_VERSION + int + default 1 + +config SOC_GDMA_NUM_GROUPS_MAX + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP_MAX + int + default 3 + +config SOC_GPIO_PORT + int + default 1 + +config SOC_GPIO_PIN_COUNT + int + default 27 + +config SOC_GPIO_SUPPORT_PIN_HYS_FILTER + bool + default y + +config SOC_GPIO_ETM_EVENTS_PER_GROUP + int + default 8 + +config SOC_GPIO_ETM_TASKS_PER_GROUP + int + default 8 + +config SOC_GPIO_SUPPORT_RTC_INDEPENDENT + bool + default y + +config SOC_GPIO_IN_RANGE_MAX + int + default 26 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 26 + +config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK + int + default 0 + +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x0000000007FFFF00 + +config SOC_GPIO_SUPPORT_FORCE_HOLD + bool + default y + +config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + bool + default y + +config SOC_RTCIO_PIN_COUNT + bool + default n + +config SOC_I2C_NUM + int + default 1 + +config SOC_I2C_FIFO_LEN + int + default 32 + +config SOC_I2C_CMD_REG_NUM + int + default 8 + +config SOC_I2C_SUPPORT_SLAVE + bool + default y + +config SOC_I2C_SUPPORT_HW_FSM_RST + bool + default y + +config SOC_I2C_SUPPORT_HW_CLR_BUS + bool + default y + +config SOC_I2C_SUPPORT_XTAL + bool + default y + +config SOC_I2C_SUPPORT_10BIT_ADDR + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_BROADCAST + bool + default y + +config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS + bool + default y + +config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_CHANNEL_NUM + int + default 6 + +config SOC_MMU_PERIPH_NUM + int + default 1 + +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 1 + +config SOC_MMU_DI_VADDR_SHARED + bool + default y + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_SUPPORT_RC_FAST + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 64 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_UART_NUM + int + default 3 + +config SOC_UART_HP_NUM + int + default 2 + +config SOC_UART_LP_NUM + int + default 1 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_LP_UART_FIFO_LEN + int + default 16 + +config SOC_UART_BITRATE_MAX + int + default 5000000 + +config SOC_UART_SUPPORT_PLL_F80M_CLK + bool + default y + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_UART_SUPPORT_WAKEUP_INT + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + +config SOC_PM_SUPPORT_VDDSDIO_PD + bool + default y + +config SOC_PM_SUPPORT_HP_AON_PD + bool + default y + +config SOC_PM_SUPPORT_RTC_PERIPH_PD + bool + default y + +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + +config SOC_CLK_OSC_SLOW_SUPPORTED + bool + default y + +config SOC_CLK_RC32K_SUPPORTED + bool + default y + +config SOC_RCC_IS_INDEPENDENT + bool + default y diff --git a/components/soc/esp32c5/include/soc/adc_channel.h b/components/soc/esp32c5/beta3/include/soc/adc_channel.h similarity index 100% rename from components/soc/esp32c5/include/soc/adc_channel.h rename to components/soc/esp32c5/beta3/include/soc/adc_channel.h diff --git a/components/soc/esp32c5/include/soc/aes_reg.h b/components/soc/esp32c5/beta3/include/soc/aes_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/aes_reg.h rename to components/soc/esp32c5/beta3/include/soc/aes_reg.h diff --git a/components/soc/esp32c5/include/soc/aes_struct.h b/components/soc/esp32c5/beta3/include/soc/aes_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/aes_struct.h rename to components/soc/esp32c5/beta3/include/soc/aes_struct.h diff --git a/components/soc/esp32c5/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/beta3/include/soc/apb_saradc_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/apb_saradc_reg.h rename to components/soc/esp32c5/beta3/include/soc/apb_saradc_reg.h diff --git a/components/soc/esp32c5/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/beta3/include/soc/apb_saradc_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/apb_saradc_struct.h rename to components/soc/esp32c5/beta3/include/soc/apb_saradc_struct.h diff --git a/components/soc/esp32c5/include/soc/assist_debug_reg.h b/components/soc/esp32c5/beta3/include/soc/assist_debug_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/assist_debug_reg.h rename to components/soc/esp32c5/beta3/include/soc/assist_debug_reg.h diff --git a/components/soc/esp32c5/include/soc/assist_debug_struct.h b/components/soc/esp32c5/beta3/include/soc/assist_debug_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/assist_debug_struct.h rename to components/soc/esp32c5/beta3/include/soc/assist_debug_struct.h diff --git a/components/soc/esp32c5/include/soc/bitscrambler_reg.h b/components/soc/esp32c5/beta3/include/soc/bitscrambler_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/bitscrambler_reg.h rename to components/soc/esp32c5/beta3/include/soc/bitscrambler_reg.h diff --git a/components/soc/esp32c5/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/beta3/include/soc/bitscrambler_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/bitscrambler_struct.h rename to components/soc/esp32c5/beta3/include/soc/bitscrambler_struct.h diff --git a/components/soc/esp32c5/include/soc/cache_reg.h b/components/soc/esp32c5/beta3/include/soc/cache_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/cache_reg.h rename to components/soc/esp32c5/beta3/include/soc/cache_reg.h diff --git a/components/soc/esp32c5/include/soc/cache_struct.h b/components/soc/esp32c5/beta3/include/soc/cache_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/cache_struct.h rename to components/soc/esp32c5/beta3/include/soc/cache_struct.h diff --git a/components/soc/esp32c5/include/soc/clic_reg.h b/components/soc/esp32c5/beta3/include/soc/clic_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/clic_reg.h rename to components/soc/esp32c5/beta3/include/soc/clic_reg.h diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h similarity index 100% rename from components/soc/esp32c5/include/soc/clk_tree_defs.h rename to components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h diff --git a/components/soc/esp32c5/include/soc/dport_access.h b/components/soc/esp32c5/beta3/include/soc/dport_access.h similarity index 100% rename from components/soc/esp32c5/include/soc/dport_access.h rename to components/soc/esp32c5/beta3/include/soc/dport_access.h diff --git a/components/soc/esp32c5/include/soc/ds_reg.h b/components/soc/esp32c5/beta3/include/soc/ds_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ds_reg.h rename to components/soc/esp32c5/beta3/include/soc/ds_reg.h diff --git a/components/soc/esp32c5/include/soc/ds_struct.h b/components/soc/esp32c5/beta3/include/soc/ds_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ds_struct.h rename to components/soc/esp32c5/beta3/include/soc/ds_struct.h diff --git a/components/soc/esp32c5/include/soc/ecc_mult_reg.h b/components/soc/esp32c5/beta3/include/soc/ecc_mult_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecc_mult_reg.h rename to components/soc/esp32c5/beta3/include/soc/ecc_mult_reg.h diff --git a/components/soc/esp32c5/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/beta3/include/soc/ecc_mult_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecc_mult_struct.h rename to components/soc/esp32c5/beta3/include/soc/ecc_mult_struct.h diff --git a/components/soc/esp32c5/include/soc/ecdsa_reg.h b/components/soc/esp32c5/beta3/include/soc/ecdsa_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecdsa_reg.h rename to components/soc/esp32c5/beta3/include/soc/ecdsa_reg.h diff --git a/components/soc/esp32c5/include/soc/ecdsa_struct.h b/components/soc/esp32c5/beta3/include/soc/ecdsa_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ecdsa_struct.h rename to components/soc/esp32c5/beta3/include/soc/ecdsa_struct.h diff --git a/components/soc/esp32c5/include/soc/efuse_reg.h b/components/soc/esp32c5/beta3/include/soc/efuse_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/efuse_reg.h rename to components/soc/esp32c5/beta3/include/soc/efuse_reg.h diff --git a/components/soc/esp32c5/include/soc/efuse_struct.h b/components/soc/esp32c5/beta3/include/soc/efuse_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/efuse_struct.h rename to components/soc/esp32c5/beta3/include/soc/efuse_struct.h diff --git a/components/soc/esp32c5/include/soc/ext_mem_defs.h b/components/soc/esp32c5/beta3/include/soc/ext_mem_defs.h similarity index 100% rename from components/soc/esp32c5/include/soc/ext_mem_defs.h rename to components/soc/esp32c5/beta3/include/soc/ext_mem_defs.h diff --git a/components/soc/esp32c5/include/soc/gdma_channel.h b/components/soc/esp32c5/beta3/include/soc/gdma_channel.h similarity index 100% rename from components/soc/esp32c5/include/soc/gdma_channel.h rename to components/soc/esp32c5/beta3/include/soc/gdma_channel.h diff --git a/components/soc/esp32c5/include/soc/gdma_reg.h b/components/soc/esp32c5/beta3/include/soc/gdma_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/gdma_reg.h rename to components/soc/esp32c5/beta3/include/soc/gdma_reg.h diff --git a/components/soc/esp32c5/include/soc/gdma_struct.h b/components/soc/esp32c5/beta3/include/soc/gdma_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/gdma_struct.h rename to components/soc/esp32c5/beta3/include/soc/gdma_struct.h diff --git a/components/soc/esp32c5/include/soc/gpio_ext_reg.h b/components/soc/esp32c5/beta3/include/soc/gpio_ext_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_ext_reg.h rename to components/soc/esp32c5/beta3/include/soc/gpio_ext_reg.h diff --git a/components/soc/esp32c5/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/beta3/include/soc/gpio_ext_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_ext_struct.h rename to components/soc/esp32c5/beta3/include/soc/gpio_ext_struct.h diff --git a/components/soc/esp32c5/include/soc/gpio_num.h b/components/soc/esp32c5/beta3/include/soc/gpio_num.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_num.h rename to components/soc/esp32c5/beta3/include/soc/gpio_num.h diff --git a/components/soc/esp32c5/include/soc/gpio_pins.h b/components/soc/esp32c5/beta3/include/soc/gpio_pins.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_pins.h rename to components/soc/esp32c5/beta3/include/soc/gpio_pins.h diff --git a/components/soc/esp32c5/include/soc/gpio_reg.h b/components/soc/esp32c5/beta3/include/soc/gpio_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_reg.h rename to components/soc/esp32c5/beta3/include/soc/gpio_reg.h diff --git a/components/soc/esp32c5/include/soc/gpio_sig_map.h b/components/soc/esp32c5/beta3/include/soc/gpio_sig_map.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_sig_map.h rename to components/soc/esp32c5/beta3/include/soc/gpio_sig_map.h diff --git a/components/soc/esp32c5/include/soc/gpio_struct.h b/components/soc/esp32c5/beta3/include/soc/gpio_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/gpio_struct.h rename to components/soc/esp32c5/beta3/include/soc/gpio_struct.h diff --git a/components/soc/esp32c5/include/soc/hardware_lock_reg.h b/components/soc/esp32c5/beta3/include/soc/hardware_lock_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hardware_lock_reg.h rename to components/soc/esp32c5/beta3/include/soc/hardware_lock_reg.h diff --git a/components/soc/esp32c5/include/soc/hardware_lock_struct.h b/components/soc/esp32c5/beta3/include/soc/hardware_lock_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/hardware_lock_struct.h rename to components/soc/esp32c5/beta3/include/soc/hardware_lock_struct.h diff --git a/components/soc/esp32c5/include/soc/hmac_reg.h b/components/soc/esp32c5/beta3/include/soc/hmac_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hmac_reg.h rename to components/soc/esp32c5/beta3/include/soc/hmac_reg.h diff --git a/components/soc/esp32c5/include/soc/hmac_struct.h b/components/soc/esp32c5/beta3/include/soc/hmac_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/hmac_struct.h rename to components/soc/esp32c5/beta3/include/soc/hmac_struct.h diff --git a/components/soc/esp32c5/include/soc/hp_apm_reg.h b/components/soc/esp32c5/beta3/include/soc/hp_apm_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_apm_reg.h rename to components/soc/esp32c5/beta3/include/soc/hp_apm_reg.h diff --git a/components/soc/esp32c5/include/soc/hp_apm_struct.h b/components/soc/esp32c5/beta3/include/soc/hp_apm_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_apm_struct.h rename to components/soc/esp32c5/beta3/include/soc/hp_apm_struct.h diff --git a/components/soc/esp32c5/include/soc/hp_system_reg.h b/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_system_reg.h rename to components/soc/esp32c5/beta3/include/soc/hp_system_reg.h diff --git a/components/soc/esp32c5/include/soc/hp_system_struct.h b/components/soc/esp32c5/beta3/include/soc/hp_system_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/hp_system_struct.h rename to components/soc/esp32c5/beta3/include/soc/hp_system_struct.h diff --git a/components/soc/esp32c5/include/soc/huk_reg.h b/components/soc/esp32c5/beta3/include/soc/huk_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/huk_reg.h rename to components/soc/esp32c5/beta3/include/soc/huk_reg.h diff --git a/components/soc/esp32c5/include/soc/huk_struct.h b/components/soc/esp32c5/beta3/include/soc/huk_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/huk_struct.h rename to components/soc/esp32c5/beta3/include/soc/huk_struct.h diff --git a/components/soc/esp32c5/include/soc/hwcrypto_reg.h b/components/soc/esp32c5/beta3/include/soc/hwcrypto_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/hwcrypto_reg.h rename to components/soc/esp32c5/beta3/include/soc/hwcrypto_reg.h diff --git a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/beta3/include/soc/i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h rename to components/soc/esp32c5/beta3/include/soc/i2c_ana_mst_reg.h diff --git a/components/soc/esp32c5/include/soc/i2c_reg.h b/components/soc/esp32c5/beta3/include/soc/i2c_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2c_reg.h rename to components/soc/esp32c5/beta3/include/soc/i2c_reg.h diff --git a/components/soc/esp32c5/include/soc/i2c_struct.h b/components/soc/esp32c5/beta3/include/soc/i2c_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2c_struct.h rename to components/soc/esp32c5/beta3/include/soc/i2c_struct.h diff --git a/components/soc/esp32c5/include/soc/i2s_reg.h b/components/soc/esp32c5/beta3/include/soc/i2s_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2s_reg.h rename to components/soc/esp32c5/beta3/include/soc/i2s_reg.h diff --git a/components/soc/esp32c5/include/soc/i2s_struct.h b/components/soc/esp32c5/beta3/include/soc/i2s_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/i2s_struct.h rename to components/soc/esp32c5/beta3/include/soc/i2s_struct.h diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/interrupt_matrix_reg.h rename to components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/interrupt_matrix_struct.h rename to components/soc/esp32c5/beta3/include/soc/interrupt_matrix_struct.h diff --git a/components/soc/esp32c5/include/soc/interrupt_reg.h b/components/soc/esp32c5/beta3/include/soc/interrupt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/interrupt_reg.h rename to components/soc/esp32c5/beta3/include/soc/interrupt_reg.h diff --git a/components/soc/esp32c5/include/soc/interrupts.h b/components/soc/esp32c5/beta3/include/soc/interrupts.h similarity index 100% rename from components/soc/esp32c5/include/soc/interrupts.h rename to components/soc/esp32c5/beta3/include/soc/interrupts.h diff --git a/components/soc/esp32c5/include/soc/intpri_reg.h b/components/soc/esp32c5/beta3/include/soc/intpri_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/intpri_reg.h rename to components/soc/esp32c5/beta3/include/soc/intpri_reg.h diff --git a/components/soc/esp32c5/include/soc/intpri_struct.h b/components/soc/esp32c5/beta3/include/soc/intpri_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/intpri_struct.h rename to components/soc/esp32c5/beta3/include/soc/intpri_struct.h diff --git a/components/soc/esp32c5/include/soc/io_mux_reg.h b/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/io_mux_reg.h rename to components/soc/esp32c5/beta3/include/soc/io_mux_reg.h diff --git a/components/soc/esp32c5/include/soc/io_mux_struct.h b/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/io_mux_struct.h rename to components/soc/esp32c5/beta3/include/soc/io_mux_struct.h diff --git a/components/soc/esp32c5/include/soc/keymng_reg.h b/components/soc/esp32c5/beta3/include/soc/keymng_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/keymng_reg.h rename to components/soc/esp32c5/beta3/include/soc/keymng_reg.h diff --git a/components/soc/esp32c5/include/soc/keymng_struct.h b/components/soc/esp32c5/beta3/include/soc/keymng_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/keymng_struct.h rename to components/soc/esp32c5/beta3/include/soc/keymng_struct.h diff --git a/components/soc/esp32c5/include/soc/ledc_reg.h b/components/soc/esp32c5/beta3/include/soc/ledc_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/ledc_reg.h rename to components/soc/esp32c5/beta3/include/soc/ledc_reg.h diff --git a/components/soc/esp32c5/include/soc/ledc_struct.h b/components/soc/esp32c5/beta3/include/soc/ledc_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/ledc_struct.h rename to components/soc/esp32c5/beta3/include/soc/ledc_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_analog_peri_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_analog_peri_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_analog_peri_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_analog_peri_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_aon_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_aon_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_aon_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_aon_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_aon_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_aon_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_aon_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_aon_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_apm0_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_apm0_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm0_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_apm0_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_apm0_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm0_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_apm0_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_apm_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_apm_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_apm_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_apm_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_apm_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_apm_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_apm_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_clkrst_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_clkrst_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_clkrst_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_clkrst_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_clkrst_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_clkrst_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_i2c_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_i2c_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_i2c_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_io_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_io_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_io_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_io_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_io_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_io_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_io_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_io_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_tee_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_tee_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_tee_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_tee_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_tee_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_tee_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_tee_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_tee_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_timer_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_timer_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_timer_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_timer_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_timer_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_timer_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_timer_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_timer_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_uart_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_uart_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_uart_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_uart_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_uart_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_uart_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_uart_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_uart_struct.h diff --git a/components/soc/esp32c5/include/soc/lp_wdt_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_wdt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_wdt_reg.h rename to components/soc/esp32c5/beta3/include/soc/lp_wdt_reg.h diff --git a/components/soc/esp32c5/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_wdt_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lp_wdt_struct.h rename to components/soc/esp32c5/beta3/include/soc/lp_wdt_struct.h diff --git a/components/soc/esp32c5/include/soc/lpperi_reg.h b/components/soc/esp32c5/beta3/include/soc/lpperi_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/lpperi_reg.h rename to components/soc/esp32c5/beta3/include/soc/lpperi_reg.h diff --git a/components/soc/esp32c5/include/soc/lpperi_struct.h b/components/soc/esp32c5/beta3/include/soc/lpperi_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/lpperi_struct.h rename to components/soc/esp32c5/beta3/include/soc/lpperi_struct.h diff --git a/components/soc/esp32c5/include/soc/mcpwm_reg.h b/components/soc/esp32c5/beta3/include/soc/mcpwm_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/mcpwm_reg.h rename to components/soc/esp32c5/beta3/include/soc/mcpwm_reg.h diff --git a/components/soc/esp32c5/include/soc/mcpwm_struct.h b/components/soc/esp32c5/beta3/include/soc/mcpwm_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/mcpwm_struct.h rename to components/soc/esp32c5/beta3/include/soc/mcpwm_struct.h diff --git a/components/soc/esp32c5/include/soc/mem_monitor_reg.h b/components/soc/esp32c5/beta3/include/soc/mem_monitor_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/mem_monitor_reg.h rename to components/soc/esp32c5/beta3/include/soc/mem_monitor_reg.h diff --git a/components/soc/esp32c5/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/beta3/include/soc/mem_monitor_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/mem_monitor_struct.h rename to components/soc/esp32c5/beta3/include/soc/mem_monitor_struct.h diff --git a/components/soc/esp32c5/include/soc/otp_debug_reg.h b/components/soc/esp32c5/beta3/include/soc/otp_debug_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/otp_debug_reg.h rename to components/soc/esp32c5/beta3/include/soc/otp_debug_reg.h diff --git a/components/soc/esp32c5/include/soc/otp_debug_struct.h b/components/soc/esp32c5/beta3/include/soc/otp_debug_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/otp_debug_struct.h rename to components/soc/esp32c5/beta3/include/soc/otp_debug_struct.h diff --git a/components/soc/esp32c5/include/soc/parl_io_reg.h b/components/soc/esp32c5/beta3/include/soc/parl_io_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/parl_io_reg.h rename to components/soc/esp32c5/beta3/include/soc/parl_io_reg.h diff --git a/components/soc/esp32c5/include/soc/parl_io_struct.h b/components/soc/esp32c5/beta3/include/soc/parl_io_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/parl_io_struct.h rename to components/soc/esp32c5/beta3/include/soc/parl_io_struct.h diff --git a/components/soc/esp32c5/include/soc/pau_reg.h b/components/soc/esp32c5/beta3/include/soc/pau_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pau_reg.h rename to components/soc/esp32c5/beta3/include/soc/pau_reg.h diff --git a/components/soc/esp32c5/include/soc/pau_struct.h b/components/soc/esp32c5/beta3/include/soc/pau_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pau_struct.h rename to components/soc/esp32c5/beta3/include/soc/pau_struct.h diff --git a/components/soc/esp32c5/include/soc/pcnt_reg.h b/components/soc/esp32c5/beta3/include/soc/pcnt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcnt_reg.h rename to components/soc/esp32c5/beta3/include/soc/pcnt_reg.h diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/beta3/include/soc/pcnt_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcnt_struct.h rename to components/soc/esp32c5/beta3/include/soc/pcnt_struct.h diff --git a/components/soc/esp32c5/include/soc/pcr_reg.h b/components/soc/esp32c5/beta3/include/soc/pcr_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcr_reg.h rename to components/soc/esp32c5/beta3/include/soc/pcr_reg.h diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/beta3/include/soc/pcr_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pcr_struct.h rename to components/soc/esp32c5/beta3/include/soc/pcr_struct.h diff --git a/components/soc/esp32c5/include/soc/periph_defs.h b/components/soc/esp32c5/beta3/include/soc/periph_defs.h similarity index 100% rename from components/soc/esp32c5/include/soc/periph_defs.h rename to components/soc/esp32c5/beta3/include/soc/periph_defs.h diff --git a/components/soc/esp32c5/include/soc/pmu_icg_mapping.h b/components/soc/esp32c5/beta3/include/soc/pmu_icg_mapping.h similarity index 100% rename from components/soc/esp32c5/include/soc/pmu_icg_mapping.h rename to components/soc/esp32c5/beta3/include/soc/pmu_icg_mapping.h diff --git a/components/soc/esp32c5/include/soc/pmu_reg.h b/components/soc/esp32c5/beta3/include/soc/pmu_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/pmu_reg.h rename to components/soc/esp32c5/beta3/include/soc/pmu_reg.h diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/beta3/include/soc/pmu_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/pmu_struct.h rename to components/soc/esp32c5/beta3/include/soc/pmu_struct.h diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/beta3/include/soc/reg_base.h similarity index 100% rename from components/soc/esp32c5/include/soc/reg_base.h rename to components/soc/esp32c5/beta3/include/soc/reg_base.h diff --git a/components/soc/esp32c5/include/soc/regi2c_bbpll.h b/components/soc/esp32c5/beta3/include/soc/regi2c_bbpll.h similarity index 100% rename from components/soc/esp32c5/include/soc/regi2c_bbpll.h rename to components/soc/esp32c5/beta3/include/soc/regi2c_bbpll.h diff --git a/components/soc/esp32c5/include/soc/regi2c_defs.h b/components/soc/esp32c5/beta3/include/soc/regi2c_defs.h similarity index 100% rename from components/soc/esp32c5/include/soc/regi2c_defs.h rename to components/soc/esp32c5/beta3/include/soc/regi2c_defs.h diff --git a/components/soc/esp32c5/include/soc/regi2c_dig_reg.h b/components/soc/esp32c5/beta3/include/soc/regi2c_dig_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/regi2c_dig_reg.h rename to components/soc/esp32c5/beta3/include/soc/regi2c_dig_reg.h diff --git a/components/soc/esp32c5/include/soc/reset_reasons.h b/components/soc/esp32c5/beta3/include/soc/reset_reasons.h similarity index 100% rename from components/soc/esp32c5/include/soc/reset_reasons.h rename to components/soc/esp32c5/beta3/include/soc/reset_reasons.h diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/beta3/include/soc/retention_periph_defs.h similarity index 100% rename from components/soc/esp32c5/include/soc/retention_periph_defs.h rename to components/soc/esp32c5/beta3/include/soc/retention_periph_defs.h diff --git a/components/soc/esp32c5/include/soc/rmt_reg.h b/components/soc/esp32c5/beta3/include/soc/rmt_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/rmt_reg.h rename to components/soc/esp32c5/beta3/include/soc/rmt_reg.h diff --git a/components/soc/esp32c5/include/soc/rmt_struct.h b/components/soc/esp32c5/beta3/include/soc/rmt_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/rmt_struct.h rename to components/soc/esp32c5/beta3/include/soc/rmt_struct.h diff --git a/components/soc/esp32c5/include/soc/rsa_reg.h b/components/soc/esp32c5/beta3/include/soc/rsa_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/rsa_reg.h rename to components/soc/esp32c5/beta3/include/soc/rsa_reg.h diff --git a/components/soc/esp32c5/include/soc/rsa_struct.h b/components/soc/esp32c5/beta3/include/soc/rsa_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/rsa_struct.h rename to components/soc/esp32c5/beta3/include/soc/rsa_struct.h diff --git a/components/soc/esp32c5/include/soc/rtc_io_channel.h b/components/soc/esp32c5/beta3/include/soc/rtc_io_channel.h similarity index 100% rename from components/soc/esp32c5/include/soc/rtc_io_channel.h rename to components/soc/esp32c5/beta3/include/soc/rtc_io_channel.h diff --git a/components/soc/esp32c5/include/soc/sha_reg.h b/components/soc/esp32c5/beta3/include/soc/sha_reg.h similarity index 100% rename from components/soc/esp32c5/include/soc/sha_reg.h rename to components/soc/esp32c5/beta3/include/soc/sha_reg.h diff --git a/components/soc/esp32c5/include/soc/sha_struct.h b/components/soc/esp32c5/beta3/include/soc/sha_struct.h similarity index 100% rename from components/soc/esp32c5/include/soc/sha_struct.h rename to components/soc/esp32c5/beta3/include/soc/sha_struct.h diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/beta3/include/soc/soc.h similarity index 100% rename from components/soc/esp32c5/include/soc/soc.h rename to components/soc/esp32c5/beta3/include/soc/soc.h diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h new file mode 100644 index 0000000000..a35c6fd255 --- /dev/null +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -0,0 +1,567 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725 +#define SOC_UART_SUPPORTED 1 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_AHB_GDMA_SUPPORTED 1 +#define SOC_GPTIMER_SUPPORTED 1 +// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683 +// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709 +// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 +// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693 +// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727 +// #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32C5] IDF-8622, IDF-8674 +// #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8637 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32C5] IDF-8674, need check +#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8674 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 +// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 +// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726 +// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687 +// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8698, IDF-8699 +// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684 +#define SOC_I2C_SUPPORTED 1 +#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 +// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8624 +// #define SOC_RSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8620 +// #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616 +// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619 +#define SOC_ECC_SUPPORTED 1 +#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 +#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622 +// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623 +// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 +// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615 +// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 +// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 +// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 +// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 +#define SOC_LP_PERIPHERALS_SUPPORTED 1 +// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634 +// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633 +// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8642 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8663 +// #define SOC_WDT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8650 +#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32C5] IDF-8715 +// #define SOC_BITSCRAMBLER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8711 +// #define SOC_ECDSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8618 +// #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 +// #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_40M 1 +#define SOC_XTAL_SUPPORT_48M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +// #define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +// #define SOC_AES_GDMA (1) + +// #define SOC_AES_SUPPORT_AES_128 (1) +// #define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (1U) +// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) +#define SOC_ADC_MAX_CHANNEL_NUM (7) +// #define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +// #define SOC_ADC_DIGI_MAX_BITWIDTH (12) +// #define SOC_ADC_DIGI_MIN_BITWIDTH (12) +// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +// #define SOC_ADC_DIGI_MONITOR_NUM (2) +// #define SOC_ADC_DIGI_RESULT_BYTES (4) +// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ +// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +// #define SOC_ADC_RTC_MIN_BITWIDTH (12) +// #define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ + +/*!< Interrupt */ +// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) + +/*!< ADC power control is shared by PWDET */ +// #define SOC_ADC_SHARED_POWER 1 + +// ESP32C5-TODO: Copy from esp32C5, need check +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +// #define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +// #define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_CACHE_FREEZE_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_CLIC_SUPPORTED 1 +#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting +#define SOC_BRANCH_PREDICTOR_SUPPORTED 1 + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x100 // bytes + +#define SOC_CPU_HAS_PMA 1 +#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +// #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +// #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_AHB_GDMA_VERSION 1U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9224 +// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-9225 + +/*-------------------------- ETM CAPS --------------------------------------*/ +// #define SOC_ETM_GROUPS 1U // Number of ETM groups +// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C5 has 1 GPIO peripheral +#define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 27 // TODO: update C5bate3 to C5 MP +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 +#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 +#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +#define SOC_GPIO_ETM_TASKS_PER_GROUP 8 + +// Target has the full LP IO subsystem +// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup +// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: [ESP32C5] IDF-8719 + +#define SOC_GPIO_VALID_GPIO_MASK ((1U< SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +// #define SOC_MEMSPI_IS_INDEPENDENT 1 +// #define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +// #define SOC_SPI_MEM_SUPPORT_WRAP (1) + +// TODO: [ESP32C5] IDF-8649 +#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +// TODO: [ESP32C5] IDF-8707 +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +// #define SOC_TIMER_SUPPORT_ETM (1) + +/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ +// #define SOC_MWDT_SUPPORT_XTAL (1) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +// #define SOC_TWAI_CONTROLLER_NUM 2 +// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 +// #define SOC_TWAI_BRP_MIN 2 +// #define SOC_TWAI_BRP_MAX 32768 +// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- eFuse CAPS----------------------------*/ +// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +// #define SOC_EFUSE_DIS_PAD_JTAG 1 +// #define SOC_EFUSE_DIS_USB_JTAG 1 +// #define SOC_EFUSE_DIS_DIRECT_BOOT 1 +// #define SOC_EFUSE_SOFT_DIS_JTAG 1 +// #define SOC_EFUSE_DIS_ICACHE 1 +// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block + +/*-------------------------- Secure Boot CAPS----------------------------*/ +// #define SOC_SECURE_BOOT_V2_RSA 1 +// #define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // TODO: [ESP32C5] IDF-8674 +// #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +// #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) // TODO: [ESP32C5] IDF-8622 +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 // TODO: [ESP32C5] IDF-8622 + +/*------------------------ Anti DPA (Security) CAPS --------------------------*/ +// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART) +#define SOC_UART_NUM (3) +#define SOC_UART_HP_NUM (2) +#define SOC_UART_LP_NUM (1U) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ +// #define SOC_UART_SUPPORT_RTC_CLK (1) // TODO: [ESP32C5] IDF-8642 +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +// #define SOC_COEX_HW_PTI (1) + +/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ +// #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +/*-------------------------- Power Management CAPS ----------------------------*/ +// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) +// #define SOC_PM_SUPPORT_BT_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -// #define SOC_MEMSPI_IS_INDEPENDENT 1 -// #define SOC_SPI_MAX_PRE_DIVIDER 16 - -/*-------------------------- SPI MEM CAPS ---------------------------------------*/ -// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) -// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) -// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) -// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) -// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) -// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) -// #define SOC_SPI_MEM_SUPPORT_WRAP (1) - -// TODO: [ESP32C5] IDF-8649 -#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 - -/*-------------------------- SYSTIMER CAPS ----------------------------------*/ -// TODO: [ESP32C5] IDF-8707 -#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units -#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part -#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 -#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source -#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt -#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) -// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event - -/*-------------------------- LP_TIMER CAPS ----------------------------------*/ -// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part -// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part - -/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ -#define SOC_TIMER_GROUPS (2) -#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) -#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) -#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) -// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) -#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) -// #define SOC_TIMER_SUPPORT_ETM (1) - -/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ -// #define SOC_MWDT_SUPPORT_XTAL (1) - -/*-------------------------- TWAI CAPS ---------------------------------------*/ -// #define SOC_TWAI_CONTROLLER_NUM 2 -// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 -// #define SOC_TWAI_BRP_MIN 2 -// #define SOC_TWAI_BRP_MAX 32768 -// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 - -/*-------------------------- eFuse CAPS----------------------------*/ -// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 -// #define SOC_EFUSE_DIS_PAD_JTAG 1 -// #define SOC_EFUSE_DIS_USB_JTAG 1 -// #define SOC_EFUSE_DIS_DIRECT_BOOT 1 -// #define SOC_EFUSE_SOFT_DIS_JTAG 1 -// #define SOC_EFUSE_DIS_ICACHE 1 -// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block - -/*-------------------------- Secure Boot CAPS----------------------------*/ -// #define SOC_SECURE_BOOT_V2_RSA 1 -// #define SOC_SECURE_BOOT_V2_ECC 1 -#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // TODO: [ESP32C5] IDF-8674 -// #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 -// #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 - -/*-------------------------- Flash Encryption CAPS----------------------------*/ -#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) // TODO: [ESP32C5] IDF-8622 -#define SOC_FLASH_ENCRYPTION_XTS_AES 1 -#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 // TODO: [ESP32C5] IDF-8622 - -/*------------------------ Anti DPA (Security) CAPS --------------------------*/ -// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 - -/*-------------------------- UART CAPS ---------------------------------------*/ -// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART) -#define SOC_UART_NUM (3) -#define SOC_UART_HP_NUM (2) -#define SOC_UART_LP_NUM (1U) -#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ -#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ -#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ -// #define SOC_UART_SUPPORT_RTC_CLK (1) // TODO: [ESP32C5] IDF-8642 -#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ -#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ - -// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled -#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) - -/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ -// #define SOC_COEX_HW_PTI (1) - -/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ -// #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ -// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ - -/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ -// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) - -/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ -// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) - -/*-------------------------- Power Management CAPS ----------------------------*/ -// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) -// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) -// #define SOC_PM_SUPPORT_BT_WAKEUP (1) -// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) -// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! iram0_text``. Since the default scheme specifies an ``iram -> iram0_text`` entry, it too is placed wherever ``iram0_text`` is referenced by a marker. Since it is a rule generated from the default scheme, it comes first among all other rules collected under the same target name. +.. only:: not esp32c5 + The linker script template currently used is :component_file:`esp_system/ld/{IDF_TARGET_PATH_NAME}/sections.ld.in`; the generated output script ``sections.ld`` is put under its build directory. + +.. only:: esp32c5 + + The linker script template currently used is :component_file:`esp_system/ld/esp32c5/beta3/sections.ld.in`; the generated output script ``sections.ld`` is put under its build directory. diff --git a/docs/en/api-reference/peripherals/index.rst b/docs/en/api-reference/peripherals/index.rst index 3c733331d3..ea096ea642 100644 --- a/docs/en/api-reference/peripherals/index.rst +++ b/docs/en/api-reference/peripherals/index.rst @@ -10,7 +10,7 @@ Peripherals API :SOC_ADC_DMA_SUPPORTED: adc_continuous :SOC_ADC_SUPPORTED: adc_calibration :SOC_ANA_CMPR_SUPPORTED: ana_cmpr - clk_tree + :SOC_CLK_TREE_SUPPORTED: clk_tree :SOC_DAC_SUPPORTED: dac :SOC_ECDSA_SUPPORTED: ecdsa :SOC_ETM_SUPPORTED: etm diff --git a/docs/zh_CN/api-guides/linker-script-generation.rst b/docs/zh_CN/api-guides/linker-script-generation.rst index f037498db0..e8327f75de 100644 --- a/docs/zh_CN/api-guides/linker-script-generation.rst +++ b/docs/zh_CN/api-guides/linker-script-generation.rst @@ -629,4 +629,10 @@ 这是根据默认协议条目 ``iram -> iram0_text`` 生成的规则。默认协议指定了 ``iram -> iram0_text`` 条目，因此生成的规则同样也放在被 ``iram0_text`` 标记的地方。由于该规则是根据默认协议生成的，因此在同一目标下收集的所有规则下排在第一位。 +.. only:: not esp32c5 + 目前使用的链接器脚本模板是 :component_file:`esp_system/ld/{IDF_TARGET_PATH_NAME}/sections.ld.in`，生成的脚本存放在构建目录下。 + +.. only:: esp32c5 + + 目前使用的链接器脚本模板是 :component_file:`esp_system/ld/esp32c5/beta3/sections.ld.in`，生成的脚本存放在构建目录下。 diff --git a/docs/zh_CN/api-reference/peripherals/index.rst b/docs/zh_CN/api-reference/peripherals/index.rst index 860bc5fab0..44925a87cc 100644 --- a/docs/zh_CN/api-reference/peripherals/index.rst +++ b/docs/zh_CN/api-reference/peripherals/index.rst @@ -10,7 +10,7 @@ :SOC_ADC_DMA_SUPPORTED: adc_continuous :SOC_ADC_SUPPORTED: adc_calibration :SOC_ANA_CMPR_SUPPORTED: ana_cmpr - clk_tree + :SOC_CLK_TREE_SUPPORTED: clk_tree :SOC_DAC_SUPPORTED: dac :SOC_ECDSA_SUPPORTED: ecdsa :SOC_ETM_SUPPORTED: etm diff --git a/tools/ci/check_public_headers.py b/tools/ci/check_public_headers.py index a68622c96f..9a641a95ad 100644 --- a/tools/ci/check_public_headers.py +++ b/tools/ci/check_public_headers.py @@ -2,12 +2,9 @@ # # Checks all public headers in IDF in the ci # -# SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # - -from __future__ import print_function, unicode_literals - import argparse import fnmatch import json @@ -16,9 +13,13 @@ import queue import re import subprocess import tempfile -from io import open -from threading import Event, Thread -from typing import List, Optional, Set, Tuple, Union +from threading import Event +from threading import Thread +from typing import List +from typing import Optional +from typing import Set +from typing import Tuple +from typing import Union class HeaderFailed(Exception): @@ -105,7 +106,7 @@ class PublicHeaderChecker: self.kconfig_macro = re.compile(r'\bCONFIG_[A-Z0-9_]+') self.static_assert = re.compile(r'(_Static_assert|static_assert)') self.defines_assert = re.compile(r'#define[ \t]+ESP_STATIC_ASSERT') - self.auto_soc_header = re.compile(r'components/soc/esp[a-z0-9_]+/include(?:/rev[0-9]+)?/(soc|modem)/[a-zA-Z0-9_]+.h') + self.auto_soc_header = re.compile(r'components/soc/esp[a-z0-9_]+(?:/\w+)?/include/(soc|modem)/[a-zA-Z0-9_]+.h') self.assembly_nocode = r'^\s*(\.file|\.text|\.ident|\.option|\.attribute).*$' self.check_threads: List[Thread] = [] diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index 003bb04e5e..dce714d15c 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -97,10 +97,11 @@ components/esp_rom/include/esp32c3/rom/rtc.h components/esp_rom/include/esp32s2/rom/rtc.h components/esp_rom/include/esp32s3/rom/rtc.h components/esp_rom/include/esp32c2/rom/rtc.h +# TODO: IDF-9197 +components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h components/esp_rom/include/esp32c6/rom/rtc.h components/esp_rom/include/esp32h2/rom/rtc.h components/esp_rom/include/esp32p4/rom/rtc.h -components/esp_rom/include/esp32c5/rom/rtc.h components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/secure_boot.h components/esp_rom/include/esp32c3/rom/spi_flash.h diff --git a/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py b/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py index 3ba6608652..293a25c133 100755 --- a/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py +++ b/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py @@ -28,6 +28,8 @@ from pyparsing import OneOrMore from pyparsing import Optional from pyparsing import ParserElement from pyparsing import QuotedString +from pyparsing import restOfLine +from pyparsing import Suppress from pyparsing import Word pyparsing.usePackrat = True @@ -52,6 +54,12 @@ class KconfigWriter(): $entry_type default $value ''')) + KCONFIG_CONDITION_SOURCE_TEMPLATE = Template( + inspect.cleandoc(''' + if $condition + source "$source_path" + endif + ''')) def __init__(self): # type: () -> None self.entries = set('') @@ -77,6 +85,14 @@ class KconfigWriter(): entry = self.KCONFIG_ENTRY_TEMPLATE.substitute(name=name, entry_type=entry_type, value=value) self.kconfig_text.write(entry) + def add_source(self, source_path, condition): # type: (str, str) -> None + self.kconfig_text.write('\n\n') + if condition: + source = self.KCONFIG_CONDITION_SOURCE_TEMPLATE.substitute(source_path=source_path, condition=condition) + self.kconfig_text.write(source) + else: + self.kconfig_text.write('source "' + source_path + '"') + def update_file(self, kconfig_path, always_write): # type: (Path, bool) -> bool try: @@ -105,6 +121,22 @@ class KconfigWriter(): return file_needs_update +def parse_include(inc_line): # type: (str) -> typing.Any[typing.Type[ParserElement]] + # Comment with recursive pattern + recursive_deli = OneOrMore(Group(Literal(' ') | Literal(',') | Literal('.'))) + recursive = CaselessLiteral('// recursive')('recursive') + Optional(recursive_deli) + + # Comment with condition pattern + condition_deli = OneOrMore(Group(Literal(' ') | Literal(':'))) + condition = CaselessLiteral('condition') + Optional(condition_deli) + restOfLine('condition') + + # Parse the include line + # e.g. #include "../../beta3/include/soc/soc_caps.h" // recursive, condition: IDF_TARGET_ESP32C5_VERSION_BETA3 + expr = Suppress('#include') + QuotedString('"')('inc_path') + recursive + Optional(condition) + res = expr.parseString(inc_line) + return res + + def parse_define(define_line): # type: (str) -> typing.Any[typing.Type[ParserElement]] # Group for parsing literal suffix of a numbers, e.g. 100UL @@ -144,6 +176,17 @@ def generate_defines(soc_caps_dir, filename, always_write): # type: (Path, str, writer = KconfigWriter() for line in defines: + try: + inc = parse_include(line) + if 'inc_path' in inc and 'recursive' in inc and inc['inc_path'][-6:] == 'caps.h': + source_path = path.join('$IDF_PATH', str(soc_caps_dir), path.dirname(inc['inc_path']), 'Kconfig.soc_caps.in') + condition = inc['condition'].strip(' ') if 'condition' in inc else '' + writer.add_source(source_path, condition) + sub_soc_cap_dir = soc_caps_dir.joinpath(str(inc['inc_path'])).parent + generate_defines(sub_soc_cap_dir, filename, always_write) + continue + except pyparsing.ParseException: + pass try: res = parse_define(line)