sleep: restore analog calibration registers after waking up from light sleep

Closes https://github.com/espressif/esp-idf/issues/8287
Closes https://github.com/espressif/esp-idf/issues/7921

components/esp_hw_support/port/esp32/CMakeLists.txt

@@ -1,5 +1,5 @@
 target_include_directories(${COMPONENT_LIB} PUBLIC .)
-target_include_directories(${COMPONENT_LIB} PRIVATE private_include)
+target_include_directories(${COMPONENT_LIB} PUBLIC private_include)
 
 set(srcs
     "rtc_clk.c"

components/esp_hw_support/port/esp32c3/private_include/regi2c_saradc.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -77,3 +77,10 @@
 #define I2C_SARADC_TSENS_DAC 0x6
 #define I2C_SARADC_TSENS_DAC_MSB 3
 #define I2C_SARADC_TSENS_DAC_LSB 0
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#define REGI2C_ANA_CALI_PD_WORKAROUND    1
+#define REGI2C_ANA_CALI_BYTE_NUM         8

components/esp_hw_support/port/esp32c3/regi2c_ctrl.h

@@ -82,6 +82,16 @@ void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 #define REGI2C_READ(block, reg_add) \
       regi2c_ctrl_read_reg(block, block##_HOSTID,  reg_add)
 
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#if REGI2C_ANA_CALI_PD_WORKAROUND
+void regi2c_analog_cali_reg_read(void);
+void regi2c_analog_cali_reg_write(void);
+#endif   //#if ADC_CALI_PD_WORKAROUND
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32s2/private_include/regi2c_saradc.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -73,3 +73,10 @@
 #define I2C_SARADC_TSENS_DAC 0x6
 #define I2C_SARADC_TSENS_DAC_MSB 3
 #define I2C_SARADC_TSENS_DAC_LSB 0
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#define REGI2C_ANA_CALI_PD_WORKAROUND    1
+#define REGI2C_ANA_CALI_BYTE_NUM         8

components/esp_hw_support/port/esp32s2/regi2c_ctrl.h

@@ -77,6 +77,16 @@ void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 #define REGI2C_READ(block, reg_add) \
       regi2c_ctrl_read_reg(block, block##_HOSTID,  reg_add)
 
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#if REGI2C_ANA_CALI_PD_WORKAROUND
+void regi2c_analog_cali_reg_read(void);
+void regi2c_analog_cali_reg_write(void);
+#endif   //#if ADC_CALI_PD_WORKAROUND
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32s3/private_include/regi2c_saradc.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -73,3 +73,10 @@
 #define I2C_SARADC_TSENS_DAC 0x6
 #define I2C_SARADC_TSENS_DAC_MSB 3
 #define I2C_SARADC_TSENS_DAC_LSB 0
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#define REGI2C_ANA_CALI_PD_WORKAROUND    1
+#define REGI2C_ANA_CALI_BYTE_NUM         8

components/esp_hw_support/port/esp32s3/regi2c_ctrl.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -81,6 +81,15 @@ void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
       regi2c_ctrl_read_reg(block, block##_HOSTID,  reg_add)
 
 
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#if REGI2C_ANA_CALI_PD_WORKAROUND
+void regi2c_analog_cali_reg_read(void);
+void regi2c_analog_cali_reg_write(void);
+#endif   //#if ADC_CALI_PD_WORKAROUND
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/regi2c_ctrl.c

@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "regi2c_ctrl.h"
+#include "esp_attr.h"
 #include <stdint.h>
 #include <freertos/FreeRTOS.h>
 #include <freertos/semphr.h>
@@ -40,3 +41,27 @@ void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_
     i2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
     portEXIT_CRITICAL_ISR(&mux);
 }
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#if REGI2C_ANA_CALI_PD_WORKAROUND
+
+static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM];
+
+void IRAM_ATTR regi2c_analog_cali_reg_read(void)
+{
+    for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
+        reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i);
+    }
+}
+
+void IRAM_ATTR regi2c_analog_cali_reg_write(void)
+{
+    for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
+        regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
+    }
+}
+
+#endif   //#if ADC_CALI_PD_WORKAROUND

components/esp_hw_support/sleep_modes.c

@@ -28,6 +28,7 @@
 #include "soc/cpu.h"
 #include "soc/rtc.h"
 #include "soc/soc_caps.h"
+#include "regi2c_ctrl.h"
 
 #include "hal/wdt_hal.h"
 #include "hal/rtc_hal.h"
@@ -316,6 +317,9 @@ static void IRAM_ATTR resume_uarts(void)
     }
 }
 
+/**
+ * These save-restore workaround should be moved to lower layer
+ */
 inline static void IRAM_ATTR misc_modules_sleep_prepare(void)
 {
 #if CONFIG_MAC_BB_PD
@@ -327,8 +331,14 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(void)
 #if SOC_PM_SUPPORT_CPU_PD || SOC_PM_SUPPORT_TAGMEM_PD
     sleep_enable_memory_retention();
 #endif
+#if REGI2C_ANA_CALI_PD_WORKAROUND
+    regi2c_analog_cali_reg_read();
+#endif
 }
 
+/**
+ * These save-restore workaround should be moved to lower layer
+ */
 inline static void IRAM_ATTR misc_modules_wake_prepare(void)
 {
 #if SOC_PM_SUPPORT_CPU_PD || SOC_PM_SUPPORT_TAGMEM_PD
@@ -340,6 +350,9 @@ inline static void IRAM_ATTR misc_modules_wake_prepare(void)
 #if CONFIG_MAC_BB_PD
     mac_bb_power_up_cb_execute();
 #endif
+#if REGI2C_ANA_CALI_PD_WORKAROUND
+    regi2c_analog_cali_reg_write();
+#endif
 }
 
 inline static uint32_t IRAM_ATTR call_rtc_sleep_start(uint32_t reject_triggers, uint32_t lslp_mem_inf_fpu);

components/hal/adc_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -566,8 +566,8 @@ static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
     return (uint32_t)adc_ll_rtc_get_convert_value(adc_n);
 }
 
-#elif SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
 //For those RTC controller not supported chips, they use digital controller to do the single read. e.g.: esp32c3
+#elif SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
 static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
 {
     adc_ll_onetime_sample_enable(ADC_NUM_1, false);