diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 5bf113b946..b67db862e2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -26,7 +26,8 @@ variables: # If the "recursive" strategy is used we have a problem with using relative URLs for sub-submodules. GIT_SUBMODULE_STRATEGY: normal - UNIT_TEST_BUILD_SYSTEM: make + UNIT_TEST_BUILD_SYSTEM: cmake + EXAMPLE_TEST_BUILD_SYSTEM: cmake # IDF environment IDF_PATH: "$CI_PROJECT_DIR" diff --git a/components/app_update/test/CMakeLists.txt b/components/app_update/test/CMakeLists.txt index e56fd72838..2259c1ffe9 100644 --- a/components/app_update/test/CMakeLists.txt +++ b/components/app_update/test/CMakeLists.txt @@ -1,3 +1,5 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - REQUIRES unity test_utils app_update bootloader_support nvs_flash) \ No newline at end of file +if(IDF_TARGET STREQUAL "esp32") + idf_component_register(SRC_DIRS "." + INCLUDE_DIRS "." + REQUIRES unity test_utils app_update bootloader_support nvs_flash) +endif() diff --git a/components/app_update/test/test_ota_ops.c b/components/app_update/test/test_ota_ops.c index e7773ac245..b1d168d046 100644 --- a/components/app_update/test/test_ota_ops.c +++ b/components/app_update/test/test_ota_ops.c @@ -58,7 +58,7 @@ TEST_CASE("esp_ota_get_next_update_partition logic", "[ota]") TEST_ASSERT_NOT_NULL(ota_1); TEST_ASSERT_NULL(ota_2); /* this partition shouldn't exist in test partition table */ - TEST_ASSERT_EQUAL_PTR(factory, running); /* this may not be true if/when we get OTA tests that do OTA updates */ + TEST_ASSERT_EQUAL_PTR(factory, running); /* this may not be true if/when we get OTA tests that do OTA updates */ /* (The test steps verify subtypes before verifying pointer equality, because the failure messages are more readable this way.) diff --git a/components/app_update/test/test_switch_ota.c b/components/app_update/test/test_switch_ota.c index f0d056d9bd..9d95bb009d 100644 --- a/components/app_update/test/test_switch_ota.c +++ b/components/app_update/test/test_switch_ota.c @@ -7,9 +7,13 @@ #include "string.h" #include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/spi_flash.h" #include "esp32/rom/rtc.h" -#include "esp32/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/spi_flash.h" +#include "esp32s2beta/rom/rtc.h" +#endif #include "freertos/FreeRTOS.h" #include "freertos/task.h" diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index f9ed448ab5..c66b4207be 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -1,4 +1,4 @@ -set(srcs +set(srcs "src/bootloader_clock.c" "src/bootloader_common.c" "src/bootloader_flash.c" @@ -10,7 +10,7 @@ set(srcs "src/bootloader_flash_config_${IDF_TARGET}.c" ) -if(CONFIG_IDF_TARGET_ESP32) +if(IDF_TARGET STREQUAL "esp32") # Not supported on ESP32S2Beta yet list(APPEND srcs "src/flash_encrypt.c") endif() diff --git a/components/bootloader_support/test/test_verify_image.c b/components/bootloader_support/test/test_verify_image.c index d5a7c84ae2..530beaa560 100644 --- a/components/bootloader_support/test/test_verify_image.c +++ b/components/bootloader_support/test/test_verify_image.c @@ -5,7 +5,6 @@ #include #include #include "string.h" -#include "esp32/rom/ets_sys.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -34,7 +33,7 @@ TEST_CASE("Verify bootloader image in flash", "[bootloader_support]") TEST_ASSERT_EQUAL(data.image_len, bootloader_length); } -TEST_CASE("Verify unit test app image", "[bootloader_support]") +TEST_CASE_ESP32("Verify unit test app image", "[bootloader_support]") { esp_image_metadata_t data = { 0 }; const esp_partition_t *running = esp_ota_get_running_partition(); diff --git a/components/bt/Kconfig b/components/bt/Kconfig index 8553cc9f70..83194beeb7 100644 --- a/components/bt/Kconfig +++ b/components/bt/Kconfig @@ -2,6 +2,7 @@ menu Bluetooth config BT_ENABLED bool "Bluetooth" + depends on IDF_TARGET_ESP32 help Select this option to enable Bluetooth and show the submenu with Bluetooth configuration choices. diff --git a/components/cxx/test/test_cxx.cpp b/components/cxx/test/test_cxx.cpp index 0bf92f324b..138e2f4eed 100644 --- a/components/cxx/test/test_cxx.cpp +++ b/components/cxx/test/test_cxx.cpp @@ -276,14 +276,14 @@ TEST_CASE("c++ exceptions emergency pool", "[cxx] [ignore]") #else // !CONFIG_COMPILER_CXX_EXCEPTIONS -TEST_CASE("std::out_of_range exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]") +TEST_CASE_ESP32("std::out_of_range exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]") { std::vector v(10); v.at(20) = 42; TEST_FAIL_MESSAGE("Unreachable because we are aborted on the line above"); } -TEST_CASE("std::bad_alloc exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]") +TEST_CASE_ESP32("std::bad_alloc exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]") { std::string s = std::string(2000000000, 'a'); (void)s; diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index cf1f7e7c1a..31dce58c68 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -20,7 +20,7 @@ set(srcs set(includes "include") -if(CONFIG_IDF_TARGET_ESP32) +if(IDF_TARGET STREQUAL "esp32") # SDMMC and MCPWM are in ESP32 only. list(APPEND srcs "mcpwm.c" "sdio_slave.c" @@ -28,7 +28,7 @@ if(CONFIG_IDF_TARGET_ESP32) "sdmmc_transaction.c") endif() -if(CONFIG_IDF_TARGET_ESP32S2BETA) +if(IDF_TARGET STREQUAL "esp32s2beta") list(APPEND srcs "esp32s2beta/rtc_tempsensor.c" "esp32s2beta/rtc_touchpad.c") # currently only S2 beta has its own target-specific includes diff --git a/components/driver/include/driver/mcpwm.h b/components/driver/include/driver/mcpwm.h index 03483cc4ad..ea85a83d44 100644 --- a/components/driver/include/driver/mcpwm.h +++ b/components/driver/include/driver/mcpwm.h @@ -20,6 +20,11 @@ #include "driver/gpio.h" #include "driver/periph_ctrl.h" #include "esp_intr_alloc.h" +#include "soc/soc_caps.h" + +#ifndef SOC_MCPWM_SUPPORTED +#error MCPWM is not supported in this chip target +#endif #ifdef __cplusplus extern "C" { diff --git a/components/driver/include/driver/sdmmc_host.h b/components/driver/include/driver/sdmmc_host.h index 8cd403d859..1cae99e2dd 100644 --- a/components/driver/include/driver/sdmmc_host.h +++ b/components/driver/include/driver/sdmmc_host.h @@ -20,6 +20,12 @@ #include "sdmmc_types.h" #include "driver/gpio.h" +#include "soc/soc_caps.h" + +#ifndef SOC_SDMMC_HOST_SUPPORTED +#error SDMMC host is not supported in this chip target +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/components/driver/include/driver/sdspi_host.h b/components/driver/include/driver/sdspi_host.h index 8cb922803f..6eb24587de 100644 --- a/components/driver/include/driver/sdspi_host.h +++ b/components/driver/include/driver/sdspi_host.h @@ -20,7 +20,6 @@ #include "sdmmc_types.h" #include "driver/gpio.h" #include "driver/spi_master.h" -#include "driver/sdmmc_host.h" #ifdef __cplusplus extern "C" { diff --git a/components/driver/sdspi_transaction.c b/components/driver/sdspi_transaction.c index f8dec0a2ee..93f2ec66ca 100644 --- a/components/driver/sdspi_transaction.c +++ b/components/driver/sdspi_transaction.c @@ -18,7 +18,7 @@ #include "sys/lock.h" #include "driver/sdmmc_types.h" #include "driver/sdmmc_defs.h" -#include "driver/sdmmc_host.h" +#include "driver/sdmmc_types.h" #include "sdspi_private.h" #include "sdspi_crc.h" diff --git a/components/driver/test/CMakeLists.txt b/components/driver/test/CMakeLists.txt index 7102bae72e..f6245349c2 100644 --- a/components/driver/test/CMakeLists.txt +++ b/components/driver/test/CMakeLists.txt @@ -1,3 +1,9 @@ -idf_component_register(SRC_DIRS "." "param_test" - INCLUDE_DIRS "include" "param_test/include" - REQUIRES unity test_utils driver nvs_flash) \ No newline at end of file +set(srcdirs . param_test) +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcdirs "esp32") +endif() + +idf_component_register(SRC_DIRS ${srcdirs} + INCLUDE_DIRS include param_test/include + REQUIRES unity test_utils driver nvs_flash + ) diff --git a/components/driver/test/component.mk b/components/driver/test/component.mk index 2f9f42ccdb..f37a1fa51c 100644 --- a/components/driver/test/component.mk +++ b/components/driver/test/component.mk @@ -2,6 +2,7 @@ #Component Makefile # +COMPONENT_SRCDIRS += esp32 COMPONENT_SRCDIRS += param_test COMPONENT_PRIV_INCLUDEDIRS += param_test/include diff --git a/components/driver/test/test_adc2.c b/components/driver/test/esp32/test_adc2.c similarity index 100% rename from components/driver/test/test_adc2.c rename to components/driver/test/esp32/test_adc2.c diff --git a/components/driver/test/test_gpio.c b/components/driver/test/esp32/test_gpio.c similarity index 99% rename from components/driver/test/test_gpio.c rename to components/driver/test/esp32/test_gpio.c index c40815683c..8777e5207f 100644 --- a/components/driver/test/test_gpio.c +++ b/components/driver/test/esp32/test_gpio.c @@ -4,7 +4,7 @@ */ #include #include -#include "esp32/rom/uart.h" + #include "esp_system.h" #include "esp_sleep.h" #include "unity.h" @@ -12,6 +12,13 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" +#include "sdkconfig.h" + +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/uart.h" +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/uart.h" +#endif #define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated. #define GPIO_OUTPUT_IO 18 // default output GPIO diff --git a/components/driver/test/esp32/test_i2c.c b/components/driver/test/esp32/test_i2c.c new file mode 100644 index 0000000000..75eec14d7f --- /dev/null +++ b/components/driver/test/esp32/test_i2c.c @@ -0,0 +1,356 @@ +/** + * test environment UT_T2_I2C: + * please prepare two ESP32-WROVER-KIT board. + * Then connect GPIO18 and GPIO18, GPIO19 and GPIO19 between these two boards. + */ +#include +#include +#include "unity.h" +#include "test_utils.h" +#include "unity_config.h" +#include "driver/i2c.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "soc/gpio_periph.h" +#include "soc/i2c_periph.h" +#include "esp_system.h" +#include "driver/pcnt.h" + + +#define DATA_LENGTH 512 /*! #include #include -#include "esp32/rom/ets_sys.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" diff --git a/components/driver/test/test_pcnt.c b/components/driver/test/esp32/test_pcnt.c similarity index 99% rename from components/driver/test/test_pcnt.c rename to components/driver/test/esp32/test_pcnt.c index 90dc2c4ece..826cab0cdb 100644 --- a/components/driver/test/test_pcnt.c +++ b/components/driver/test/esp32/test_pcnt.c @@ -22,7 +22,6 @@ #include "esp_log.h" #include "soc/gpio_periph.h" #include "unity.h" -#include "esp32/rom/ets_sys.h" #define PULSE_IO 18 #define PCNT_INPUT_IO 4 diff --git a/components/driver/test/test_pwm.c b/components/driver/test/esp32/test_pwm.c similarity index 99% rename from components/driver/test/test_pwm.c rename to components/driver/test/esp32/test_pwm.c index b787f8e3ab..34780da3f1 100644 --- a/components/driver/test/test_pwm.c +++ b/components/driver/test/esp32/test_pwm.c @@ -25,7 +25,6 @@ #include "esp_attr.h" #include "esp_log.h" #include "soc/rtc.h" -#include "esp32/rom/ets_sys.h" #define GPIO_PWMA_OUT 4 #define GPIO_PWMB_OUT 13 diff --git a/components/driver/test/test_rmt.c b/components/driver/test/esp32/test_rmt.c similarity index 100% rename from components/driver/test/test_rmt.c rename to components/driver/test/esp32/test_rmt.c diff --git a/components/driver/test/esp32/test_rs485.c b/components/driver/test/esp32/test_rs485.c new file mode 100644 index 0000000000..c81686b24f --- /dev/null +++ b/components/driver/test/esp32/test_rs485.c @@ -0,0 +1,281 @@ +/* This file is from test_uart.c, but mainly about RS485 */ + + +#include +#include +#include "unity.h" +#include "test_utils.h" // unity_send_signal +#include "driver/uart.h" // for the uart driver access +#include "esp_log.h" +#include "esp_system.h" // for uint32_t esp_random() + +#define UART_TAG "Uart" +#define UART_NUM1 (UART_NUM_1) +#define BUF_SIZE (100) +#define UART1_RX_PIN (22) +#define UART1_TX_PIN (23) +#define UART_BAUD_11520 (11520) +#define UART_BAUD_115200 (115200) +#define TOLERANCE (0.02) //baud rate error tolerance 2%. + +#define UART_TOLERANCE_CHECK(val, uper_limit, lower_limit) ( (val) <= (uper_limit) && (val) >= (lower_limit) ) + +// RTS for RS485 Half-Duplex Mode manages DE/~RE +#define UART1_RTS_PIN (18) + +// Number of packets to be send during test +#define PACKETS_NUMBER (10) + +// Wait timeout for uart driver +#define PACKET_READ_TICS (1000 / portTICK_RATE_MS) + +// The table for fast CRC16 calculation +static const uint8_t crc_hi[] = { + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, + 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, + 0x40, 0x01, 0xC0, + 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, + 0x81, 0x40, 0x01, + 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, + 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, + 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, + 0x41, 0x01, 0xC0, + 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, + 0x80, 0x41, 0x01, + 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, + 0xC1, 0x81, 0x40, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, + 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, + 0x40, 0x01, 0xC0, + 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, + 0x81, 0x40, 0x01, + 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, + 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, + 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, + 0x40, 0x01, 0xC0, + 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, + 0x80, 0x41, 0x01, + 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, + 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, + 0x00, 0xC1, 0x81, + 0x40 +}; + +static const uint8_t crc_low[] = { + 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, + 0x05, 0xC5, 0xC4, + 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, + 0x0B, 0xC9, 0x09, + 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, + 0xDF, 0x1F, 0xDD, + 0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, + 0x12, 0x13, 0xD3, + 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, + 0x36, 0xF6, 0xF7, + 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, + 0xFE, 0xFA, 0x3A, + 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, + 0x2A, 0xEA, 0xEE, + 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, + 0xE7, 0xE6, 0x26, + 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, + 0x63, 0xA3, 0xA2, + 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, + 0x6D, 0xAF, 0x6F, + 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, + 0xB9, 0x79, 0xBB, + 0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, + 0x74, 0x75, 0xB5, + 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, + 0x50, 0x90, 0x91, + 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, + 0x54, 0x9C, 0x5C, + 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, + 0x58, 0x98, 0x88, + 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, + 0x4D, 0x4C, 0x8C, + 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, + 0x41, 0x81, 0x80, + 0x40 +}; + + +// Calculate buffer checksum using tables +// The checksum CRC16 algorithm is specific +// for Modbus standard and uses polynomial value = 0xA001 +static uint16_t get_buffer_crc16( uint8_t * frame_ptr, uint16_t length ) +{ + TEST_ASSERT( frame_ptr != NULL); + + uint8_t crc_hi_byte = 0xFF; + uint8_t crc_low_byte = 0xFF; + int index; + + while ( length-- ) + { + index = crc_low_byte ^ *(frame_ptr++); + crc_low_byte = crc_hi_byte ^ crc_hi[index]; + crc_hi_byte = crc_low[index]; + } + return ((crc_hi_byte << 8) | crc_low_byte); +} + +// Fill the buffer with random numbers and apply CRC16 at the end +static uint16_t buffer_fill_random(uint8_t *buffer, size_t length) +{ + TEST_ASSERT( buffer != NULL); + // Packet is too short + if (length < 4) { + return 0; + } + for (int i = 0; i < length; i += 4) { + uint32_t random = esp_random(); + memcpy(buffer + i, &random, MIN(length - i, 4)); + } + // Get checksum of the buffer + uint16_t crc = get_buffer_crc16((uint8_t*)buffer, (length - 2)); + // Apply checksum bytes into packet + buffer[length - 2] = (uint8_t)(crc & 0xFF); // Set Low byte CRC + buffer[length - 1] = (uint8_t)(crc >> 8); // Set High byte CRC + return crc; +} + +static void rs485_init(void) +{ + uart_config_t uart_config = { + .baud_rate = UART_BAUD_115200, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, + .rx_flow_ctrl_thresh = 122, + }; + printf("RS485 port initialization...\r\n"); + // Configure UART1 parameters + uart_param_config(UART_NUM1, &uart_config); + // Set UART1 pins(TX: IO4, RX: I05, RTS: IO18, CTS: IO19) + uart_set_pin(UART_NUM1, UART1_TX_PIN, UART1_RX_PIN, UART1_RTS_PIN, UART_PIN_NO_CHANGE); + // Install UART driver (we don't need an event queue here) + uart_driver_install(UART_NUM1, BUF_SIZE * 2, 0, 0, NULL, 0); + // Setup rs485 half duplex mode + //uart_set_rs485_hd_mode(uart_num, true); + uart_set_mode(UART_NUM1, UART_MODE_RS485_HALF_DUPLEX); +} + +static esp_err_t print_packet_data(const char *str, uint8_t *buffer, uint16_t buffer_size) +{ + TEST_ASSERT( buffer != NULL); + TEST_ASSERT( str != NULL); + + // Calculate the checksum of the buffer + uint16_t crc16_calc = get_buffer_crc16(buffer, (buffer_size - 2)); + uint16_t crc16_in = ((uint16_t)(buffer[buffer_size - 1]) << 8) | buffer[buffer_size - 2]; + const char* state_str = (crc16_in != crc16_calc) ? "incorrect " : "correct "; + // Print an array of data + printf("%s%s RS485 packet = [ ", str, state_str); + for (int i = 0; i < buffer_size; i++) { + printf("0x%.2X ", (uint8_t)buffer[i]); + } + printf(" ]\r\n"); + printf("crc_in = 0x%.4X\r\n", (uint16_t)crc16_in); + printf("crc_calc = 0x%.4X\r\n", (uint16_t)crc16_calc); + esp_err_t result = (crc16_in != crc16_calc) ? ESP_ERR_INVALID_CRC : ESP_OK; + return result; +} + +// Slave test case for multi device +static void rs485_slave(void) +{ + rs485_init(); + uint8_t* slave_data = (uint8_t*) malloc(BUF_SIZE); + uint16_t err_count = 0, good_count = 0; + printf("Start recieve loop.\r\n"); + unity_send_signal("Slave_ready"); + unity_wait_for_signal("Master_started"); + for(int pack_count = 0; pack_count < PACKETS_NUMBER; pack_count++) { + //Read slave_data from UART + int len = uart_read_bytes(UART_NUM1, slave_data, BUF_SIZE, (PACKET_READ_TICS * 2)); + //Write slave_data back to UART + if (len > 2) { + esp_err_t status = print_packet_data("Received ", slave_data, len); + + // If received packet is correct then send it back + if (status == ESP_OK) { + uart_write_bytes(UART_NUM1, (char*)slave_data, len); + good_count++; + } else { + printf("Incorrect packet received.\r\n"); + err_count++; + } + } else { + printf("Incorrect data packet[%d] received.\r\n", pack_count); + err_count++; + } + } + printf("Test completed. Received packets = %d, errors = %d\r\n", good_count, err_count); + // Wait for packet to be sent + uart_wait_tx_done(UART_NUM1, PACKET_READ_TICS); + free(slave_data); + uart_driver_delete(UART_NUM1); + TEST_ASSERT(err_count < 2); +} + +// Master test of multi device test case. +// It forms packet with random data, apply generated CRC16 and sends to slave. +// If response recieved correctly from slave means RS485 channel works. +static void rs485_master(void) +{ + uint16_t err_count = 0, good_count = 0; + rs485_init(); + uint8_t* master_buffer = (uint8_t*) malloc(BUF_SIZE); + uint8_t* slave_buffer = (uint8_t*) malloc(BUF_SIZE); + // The master test case should be synchronized with slave + unity_wait_for_signal("Slave_ready"); + unity_send_signal("Master_started"); + printf("Start recieve loop.\r\n"); + for(int i = 0; i < PACKETS_NUMBER; i++) { + // Form random buffer with CRC16 + buffer_fill_random(master_buffer, BUF_SIZE); + // Print created packet for debugging + esp_err_t status = print_packet_data("Send ", master_buffer, BUF_SIZE); + TEST_ASSERT(status == ESP_OK); + uart_write_bytes(UART_NUM1, (char*)master_buffer, BUF_SIZE); + // Read translated packet from slave + int len = uart_read_bytes(UART_NUM1, slave_buffer, BUF_SIZE, (PACKET_READ_TICS * 2)); + // Check if the received packet is too short + if (len > 2) { + // Print received packet and check checksum + esp_err_t status = print_packet_data("Received ", slave_buffer, len); + if (status == ESP_OK) { + good_count++; + printf("Received: %d\r\n", good_count); + } else { + err_count++; + printf("Errors: %d\r\n", err_count); + } + } + else { + printf("Incorrect answer from slave.\r\n"); + err_count++; + } + } + // Free the buffer and delete driver at the end + free(master_buffer); + uart_driver_delete(UART_NUM1); + TEST_ASSERT(err_count <= 1); + printf("Test completed. Received packets = %d, errors = %d\r\n", (uint16_t)good_count, (uint16_t)err_count); +} + +/* + * This multi devices test case verifies RS485 mode of the uart driver and checks + * correctness of RS485 interface channel communication. It requires + * RS485 bus driver hardware to be connected to boards. +*/ +TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[driver_RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave); diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/esp32/test_spi_master.c similarity index 89% rename from components/driver/test/test_spi_master.c rename to components/driver/test/esp32/test_spi_master.c index 2772a8af4f..3e6eee29b9 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/esp32/test_spi_master.c @@ -7,7 +7,6 @@ #include #include #include -#include "esp32/rom/ets_sys.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" @@ -54,10 +53,12 @@ static void check_spi_pre_n_for(int clk, int pre, int n) t.tx_buffer=sendbuf; ret=spi_device_transmit(handle, &t); - printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, SPI2.clock.clkdiv_pre+1, SPI2.clock.clkcnt_n+1); + spi_dev_t* hw = spi_periph_signal[TEST_SPI_HOST].hw; - TEST_ASSERT(SPI2.clock.clkcnt_n+1==n); - TEST_ASSERT(SPI2.clock.clkdiv_pre+1==pre); + printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, hw->clock.clkdiv_pre+1, hw->clock.clkcnt_n+1); + + TEST_ASSERT(hw->clock.clkcnt_n+1==n); + TEST_ASSERT(hw->clock.clkdiv_pre+1==pre); ret=spi_bus_remove_device(handle); TEST_ASSERT(ret==ESP_OK); @@ -330,7 +331,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 6 iomux output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -339,7 +340,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 4 iomux output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -349,7 +350,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 6 output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -359,7 +360,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 4 output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -368,14 +369,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD; - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -383,14 +384,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO; - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -398,7 +399,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "check native flag for 6 output pins..."); flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); @@ -406,61 +407,61 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "check native flag for 4 output pins..."); flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check sclk flag..."); flags_expected = SPICOMMON_BUSFLAG_SCLK; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = -1, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check mosi flag..."); flags_expected = SPICOMMON_BUSFLAG_MOSI; - cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check miso flag..."); flags_expected = SPICOMMON_BUSFLAG_MISO; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = -1, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check quad flag..."); flags_expected = SPICOMMON_BUSFLAG_QUAD; - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); diff --git a/components/driver/test/test_spi_param.c b/components/driver/test/esp32/test_spi_param.c similarity index 100% rename from components/driver/test/test_spi_param.c rename to components/driver/test/esp32/test_spi_param.c diff --git a/components/driver/test/test_spi_sio.c b/components/driver/test/esp32/test_spi_sio.c similarity index 100% rename from components/driver/test/test_spi_sio.c rename to components/driver/test/esp32/test_spi_sio.c diff --git a/components/driver/test/test_spi_slave.c b/components/driver/test/esp32/test_spi_slave.c similarity index 90% rename from components/driver/test/test_spi_slave.c rename to components/driver/test/esp32/test_spi_slave.c index 13f2f2c348..ba79393f51 100644 --- a/components/driver/test/test_spi_slave.c +++ b/components/driver/test/esp32/test_spi_slave.c @@ -88,10 +88,10 @@ TEST_CASE("test slave send unaligned","[spi]") slave_init(); //do internal connection - int_connect( PIN_NUM_MOSI, HSPID_OUT_IDX, VSPIQ_IN_IDX ); - int_connect( PIN_NUM_MISO, VSPIQ_OUT_IDX, HSPID_IN_IDX ); - int_connect( PIN_NUM_CS, HSPICS0_OUT_IDX, VSPICS0_IN_IDX ); - int_connect( PIN_NUM_CLK, HSPICLK_OUT_IDX, VSPICLK_IN_IDX ); + int_connect( PIN_NUM_MOSI, spi_periph_signal[TEST_SPI_HOST].spid_out, spi_periph_signal[TEST_SLAVE_HOST].spiq_in ); + int_connect( PIN_NUM_MISO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out, spi_periph_signal[TEST_SPI_HOST].spid_in ); + int_connect( PIN_NUM_CS, spi_periph_signal[TEST_SPI_HOST].spics_out[0], spi_periph_signal[TEST_SLAVE_HOST].spics_in ); + int_connect( PIN_NUM_CLK, spi_periph_signal[TEST_SPI_HOST].spiclk_out, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in ); for ( int i = 0; i < 4; i ++ ) { //slave send diff --git a/components/driver/test/include/test/test_common_spi.h b/components/driver/test/include/test/test_common_spi.h index 38fa59237c..fea4df7d01 100644 --- a/components/driver/test/include/test/test_common_spi.h +++ b/components/driver/test/include/test/test_common_spi.h @@ -13,9 +13,43 @@ // All the tests using the header should use this definition as much as possible, // so that the working host can be changed easily in the future. +#if CONFIG_IDF_TARGET_ESP32 #define TEST_SPI_HOST HSPI_HOST #define TEST_SLAVE_HOST VSPI_HOST +#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO +#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI +#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK +#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS +#define PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP +#define PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD + +#define SLAVE_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO +#define SLAVE_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI +#define SLAVE_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK +#define SLAVE_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS +#define SLAVE_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP +#define SLAVE_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#define TEST_SPI_HOST FSPI_HOST +#define TEST_SLAVE_HOST HSPI_HOST + +#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO +#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI +#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK +#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS +#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP +#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD + +#define SLAVE_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO +#define SLAVE_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI +#define SLAVE_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK +#define SLAVE_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS +#define SLAVE_PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP +#define SLAVE_PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD +#endif + + #define FUNC_SPI 1 #define FUNC_GPIO 2 @@ -52,11 +86,6 @@ 0,\ } -#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO -#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI -#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK -#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS - //default bus config for tests #define SPI_BUS_TEST_DEFAULT_CONFIG() {\ .miso_io_num=PIN_NUM_MISO, \ diff --git a/components/driver/test/test_i2c.c b/components/driver/test/test_i2c.c index bde591cb3f..d26d458614 100644 --- a/components/driver/test/test_i2c.c +++ b/components/driver/test/test_i2c.c @@ -62,19 +62,6 @@ static esp_err_t i2c_master_write_slave(i2c_port_t i2c_num, uint8_t *data_wr, si return ret; } -// print the reading buffer -static void disp_buf(uint8_t *buf, int len) -{ - int i; - for (i = 0; i < len; i++) { - printf("%02x ", buf[i]); - if (( i + 1 ) % 16 == 0) { - printf("\n"); - } - } - printf("\n"); -} - static i2c_config_t i2c_master_init(void) { i2c_config_t conf_master = { @@ -252,260 +239,6 @@ TEST_CASE("I2C driver memory leaking check", "[i2c]") TEST_ASSERT_INT_WITHIN(100, size, esp_get_free_heap_size()); } -static void i2c_master_write_test(void) -{ - uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH); - int i; - - i2c_config_t conf_master = i2c_master_init(); - TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master)); - - TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER, - I2C_MASTER_RX_BUF_DISABLE, - I2C_MASTER_TX_BUF_DISABLE, 0)); - unity_wait_for_signal("i2c slave init finish"); - - unity_send_signal("master write"); - for (i = 0; i < DATA_LENGTH / 2; i++) { - data_wr[i] = i; - } - i2c_master_write_slave(I2C_MASTER_NUM, data_wr, DATA_LENGTH / 2); - disp_buf(data_wr, i + 1); - free(data_wr); - unity_wait_for_signal("ready to delete"); - TEST_ESP_OK(i2c_driver_delete(I2C_MASTER_NUM)); -} - -static void i2c_slave_read_test(void) -{ - uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH); - int size_rd = 0; - int len = 0; - - i2c_config_t conf_slave = i2c_slave_init(); - TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave)); - TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE, - I2C_SLAVE_RX_BUF_LEN, - I2C_SLAVE_TX_BUF_LEN, 0)); - unity_send_signal("i2c slave init finish"); - - unity_wait_for_signal("master write"); - while (1) { - len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_RATE_MS); - if (len == 0) { - break; - } - size_rd += len; - } - disp_buf(data_rd, size_rd); - for (int i = 0; i < size_rd; i++) { - TEST_ASSERT(data_rd[i] == i); - } - free(data_rd); - unity_send_signal("ready to delete"); - TEST_ESP_OK(i2c_driver_delete(I2C_SLAVE_NUM)); -} - -TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_test, i2c_slave_read_test); - -static void master_read_slave_test(void) -{ - uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH); - memset(data_rd, 0, DATA_LENGTH); - i2c_config_t conf_master = i2c_master_init(); - TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master)); - TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER, - I2C_MASTER_RX_BUF_DISABLE, - I2C_MASTER_TX_BUF_DISABLE, 0)); - unity_wait_for_signal("i2c slave init finish"); - - i2c_cmd_handle_t cmd = i2c_cmd_link_create(); - i2c_master_start(cmd); - i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN); - - unity_send_signal("slave write"); - unity_wait_for_signal("master read"); - i2c_master_read(cmd, data_rd, RW_TEST_LENGTH-1, ACK_VAL); - i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH-1, NACK_VAL); - i2c_master_stop(cmd); - i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS); - i2c_cmd_link_delete(cmd); - vTaskDelay(100 / portTICK_RATE_MS); - for (int i = 0; i < RW_TEST_LENGTH; i++) { - printf("%d\n", data_rd[i]); - TEST_ASSERT(data_rd[i]==i); - } - free(data_rd); - unity_send_signal("ready to delete"); - i2c_driver_delete(I2C_MASTER_NUM); -} - -static void slave_write_buffer_test(void) -{ - uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH); - int size_rd; - - i2c_config_t conf_slave = i2c_slave_init(); - TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave)); - TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE, - I2C_SLAVE_RX_BUF_LEN, - I2C_SLAVE_TX_BUF_LEN, 0)); - unity_send_signal("i2c slave init finish"); - - unity_wait_for_signal("slave write"); - for (int i = 0; i < DATA_LENGTH / 2; i++) { - data_wr[i] = i; - } - size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS); - disp_buf(data_wr, size_rd); - unity_send_signal("master read"); - unity_wait_for_signal("ready to delete"); - free(data_wr); - i2c_driver_delete(I2C_SLAVE_NUM); -} - - -TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", master_read_slave_test, slave_write_buffer_test); - -static void i2c_master_write_read_test(void) -{ - uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH); - memset(data_rd, 0, DATA_LENGTH); - uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH); - - i2c_config_t conf_master = i2c_master_init(); - TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master)); - TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER, - I2C_MASTER_RX_BUF_DISABLE, - I2C_MASTER_TX_BUF_DISABLE, 0)); - unity_wait_for_signal("i2c slave init finish"); - i2c_cmd_handle_t cmd = i2c_cmd_link_create(); - i2c_master_start(cmd); - i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN); - - unity_send_signal("slave write"); - unity_wait_for_signal("master read and write"); - i2c_master_read(cmd, data_rd, RW_TEST_LENGTH, ACK_VAL); - i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH, NACK_VAL); - i2c_master_stop(cmd); - i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS); - i2c_cmd_link_delete(cmd); - vTaskDelay(100 / portTICK_RATE_MS); - disp_buf(data_rd, RW_TEST_LENGTH); - for (int i = 0; i < RW_TEST_LENGTH; i++) { - TEST_ASSERT(data_rd[i] == i/2); - } - - for (int i = 0; i < DATA_LENGTH; i++) { - data_wr[i] = i % 3; - } - - vTaskDelay(100 / portTICK_RATE_MS); - i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH); - free(data_wr); - free(data_rd); - unity_send_signal("slave read"); - unity_wait_for_signal("ready to delete"); - i2c_driver_delete(I2C_MASTER_NUM); -} - -static void i2c_slave_read_write_test(void) -{ - uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH); - memset(data_rd, 0, DATA_LENGTH); - uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH); - int size_rd; - - i2c_config_t conf_slave = i2c_slave_init(); - TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave)); - TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE, - I2C_SLAVE_RX_BUF_LEN, - I2C_SLAVE_TX_BUF_LEN, 0)); - unity_send_signal("i2c slave init finish"); - unity_wait_for_signal("slave write"); - - for (int i = 0; i < DATA_LENGTH / 2; i++) { - data_wr[i] = i/2; - } - size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS); - disp_buf(data_wr, size_rd); - unity_send_signal("master read and write"); - unity_wait_for_signal("slave read"); - size_rd = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 1000 / portTICK_RATE_MS); - printf("slave read data is:\n"); - disp_buf(data_rd, size_rd); - for (int i = 0; i < RW_TEST_LENGTH; i++) { - TEST_ASSERT(data_rd[i] == i % 3); - } - free(data_wr); - free(data_rd); - unity_send_signal("ready to delete"); - i2c_driver_delete(I2C_SLAVE_NUM); -} - -TEST_CASE_MULTIPLE_DEVICES("I2C read and write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_read_test, i2c_slave_read_write_test); - -static void i2c_master_repeat_write(void) -{ - uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH); - int times = 3; - - i2c_config_t conf_master = i2c_master_init(); - TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master)); - - TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER, - I2C_MASTER_RX_BUF_DISABLE, - I2C_MASTER_TX_BUF_DISABLE, 0)); - unity_wait_for_signal("i2c slave init finish"); - - for (int j = 0; j < times; j++) { - for (int i = 0; i < DATA_LENGTH; i++) { - data_wr[i] = j + i; - } - i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH); - disp_buf(data_wr, RW_TEST_LENGTH); - } - free(data_wr); - unity_send_signal("master write"); - unity_wait_for_signal("ready to delete"); - i2c_driver_delete(I2C_MASTER_NUM); -} - -static void i2c_slave_repeat_read(void) -{ - int size_rd = 0; - int times = 3; - uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH * 3); - - i2c_config_t conf_slave = i2c_slave_init(); - TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave)); - TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE, - I2C_SLAVE_RX_BUF_LEN, - I2C_SLAVE_TX_BUF_LEN, 0)); - unity_send_signal("i2c slave init finish"); - unity_wait_for_signal("master write"); - - while (1) { - int len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, RW_TEST_LENGTH * 3, 10000 / portTICK_RATE_MS); - if (len == 0) { - break; - } - size_rd += len; - } - disp_buf(data_rd, size_rd); - for (int j = 0; j < times; j++) { - for (int i = 0; i < RW_TEST_LENGTH; i++) { - printf("data: %d, %d\n", data_rd[j * RW_TEST_LENGTH + i], (i % 129 + j)); - TEST_ASSERT(data_rd[j * RW_TEST_LENGTH + i] == (i % 129 + j)); - } - } - free(data_rd); - unity_send_signal("ready to delete"); - i2c_driver_delete(I2C_SLAVE_NUM); -} - -TEST_CASE_MULTIPLE_DEVICES("I2C repeat write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_repeat_write, i2c_slave_repeat_read); - static volatile bool exit_flag; static bool test_read_func; diff --git a/components/driver/test/test_sdmmc_sdspi_init.cpp b/components/driver/test/test_sdmmc_sdspi_init.cpp index d2406f582c..b6bedecdb8 100644 --- a/components/driver/test/test_sdmmc_sdspi_init.cpp +++ b/components/driver/test/test_sdmmc_sdspi_init.cpp @@ -1,4 +1,9 @@ +#include "soc/soc_caps.h" + +#if SOC_SDMMC_HOST_SUPPORTED #include "driver/sdmmc_host.h" +#endif + #include "driver/sdspi_host.h" @@ -9,10 +14,12 @@ static void test_initializers() __attribute__((unused)); static void test_initializers() { +#if SOC_SDMMC_HOST_SUPPORTED sdmmc_host_t sdmmc_host = SDMMC_HOST_DEFAULT(); (void) sdmmc_host; sdmmc_slot_config_t sdmmc_slot = SDMMC_SLOT_CONFIG_DEFAULT(); (void) sdmmc_slot; +#endif sdmmc_host_t sdspi_host = SDSPI_HOST_DEFAULT(); (void) sdspi_host; sdspi_slot_config_t sdspi_slot = SDSPI_SLOT_CONFIG_DEFAULT(); diff --git a/components/driver/test/test_uart.c b/components/driver/test/test_uart.c index 0196044032..3283b9f6f0 100644 --- a/components/driver/test/test_uart.c +++ b/components/driver/test/test_uart.c @@ -26,83 +26,6 @@ // Wait timeout for uart driver #define PACKET_READ_TICS (1000 / portTICK_RATE_MS) -// The table for fast CRC16 calculation -static const uint8_t crc_hi[] = { - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, - 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, - 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, - 0x41, 0x01, 0xC0, - 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, - 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, - 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, - 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, - 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40 -}; - -static const uint8_t crc_low[] = { - 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, - 0x05, 0xC5, 0xC4, - 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, - 0x0B, 0xC9, 0x09, - 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, - 0xDF, 0x1F, 0xDD, - 0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, - 0x12, 0x13, 0xD3, - 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, - 0x36, 0xF6, 0xF7, - 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, - 0xFE, 0xFA, 0x3A, - 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, - 0x2A, 0xEA, 0xEE, - 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, - 0xE7, 0xE6, 0x26, - 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, - 0x63, 0xA3, 0xA2, - 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, - 0x6D, 0xAF, 0x6F, - 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, - 0xB9, 0x79, 0xBB, - 0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, - 0x74, 0x75, 0xB5, - 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, - 0x50, 0x90, 0x91, - 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, - 0x54, 0x9C, 0x5C, - 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, - 0x58, 0x98, 0x88, - 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, - 0x4D, 0x4C, 0x8C, - 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, - 0x41, 0x81, 0x80, - 0x40 -}; - static void uart_config(uint32_t baud_rate, bool use_ref_tick) { uart_config_t uart_config = { @@ -203,177 +126,3 @@ TEST_CASE("test uart tx data with break", "[uart]") free(psend); uart_driver_delete(UART_NUM1); } - -// Calculate buffer checksum using tables -// The checksum CRC16 algorithm is specific -// for Modbus standard and uses polynomial value = 0xA001 -static uint16_t get_buffer_crc16( uint8_t * frame_ptr, uint16_t length ) -{ - TEST_ASSERT( frame_ptr != NULL); - - uint8_t crc_hi_byte = 0xFF; - uint8_t crc_low_byte = 0xFF; - int index; - - while ( length-- ) - { - index = crc_low_byte ^ *(frame_ptr++); - crc_low_byte = crc_hi_byte ^ crc_hi[index]; - crc_hi_byte = crc_low[index]; - } - return ((crc_hi_byte << 8) | crc_low_byte); -} - -// Fill the buffer with random numbers and apply CRC16 at the end -static uint16_t buffer_fill_random(uint8_t *buffer, size_t length) -{ - TEST_ASSERT( buffer != NULL); - // Packet is too short - if (length < 4) { - return 0; - } - for (int i = 0; i < length; i += 4) { - uint32_t random = esp_random(); - memcpy(buffer + i, &random, MIN(length - i, 4)); - } - // Get checksum of the buffer - uint16_t crc = get_buffer_crc16((uint8_t*)buffer, (length - 2)); - // Apply checksum bytes into packet - buffer[length - 2] = (uint8_t)(crc & 0xFF); // Set Low byte CRC - buffer[length - 1] = (uint8_t)(crc >> 8); // Set High byte CRC - return crc; -} - -static void rs485_init(void) -{ - uart_config_t uart_config = { - .baud_rate = UART_BAUD_115200, - .data_bits = UART_DATA_8_BITS, - .parity = UART_PARITY_DISABLE, - .stop_bits = UART_STOP_BITS_1, - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, - .rx_flow_ctrl_thresh = 122, - }; - printf("RS485 port initialization...\r\n"); - // Configure UART1 parameters - uart_param_config(UART_NUM1, &uart_config); - // Set UART1 pins(TX: IO4, RX: I05, RTS: IO18, CTS: IO19) - uart_set_pin(UART_NUM1, UART1_TX_PIN, UART1_RX_PIN, UART1_RTS_PIN, UART_PIN_NO_CHANGE); - // Install UART driver (we don't need an event queue here) - uart_driver_install(UART_NUM1, BUF_SIZE * 2, 0, 0, NULL, 0); - // Setup rs485 half duplex mode - //uart_set_rs485_hd_mode(uart_num, true); - uart_set_mode(UART_NUM1, UART_MODE_RS485_HALF_DUPLEX); -} - -static esp_err_t print_packet_data(const char *str, uint8_t *buffer, uint16_t buffer_size) -{ - TEST_ASSERT( buffer != NULL); - TEST_ASSERT( str != NULL); - - // Calculate the checksum of the buffer - uint16_t crc16_calc = get_buffer_crc16(buffer, (buffer_size - 2)); - uint16_t crc16_in = ((uint16_t)(buffer[buffer_size - 1]) << 8) | buffer[buffer_size - 2]; - const char* state_str = (crc16_in != crc16_calc) ? "incorrect " : "correct "; - // Print an array of data - printf("%s%s RS485 packet = [ ", str, state_str); - for (int i = 0; i < buffer_size; i++) { - printf("0x%.2X ", (uint8_t)buffer[i]); - } - printf(" ]\r\n"); - printf("crc_in = 0x%.4X\r\n", (uint16_t)crc16_in); - printf("crc_calc = 0x%.4X\r\n", (uint16_t)crc16_calc); - esp_err_t result = (crc16_in != crc16_calc) ? ESP_ERR_INVALID_CRC : ESP_OK; - return result; -} - -// Slave test case for multi device -static void rs485_slave(void) -{ - rs485_init(); - uint8_t* slave_data = (uint8_t*) malloc(BUF_SIZE); - uint16_t err_count = 0, good_count = 0; - printf("Start recieve loop.\r\n"); - unity_send_signal("Slave_ready"); - unity_wait_for_signal("Master_started"); - for(int pack_count = 0; pack_count < PACKETS_NUMBER; pack_count++) { - //Read slave_data from UART - int len = uart_read_bytes(UART_NUM1, slave_data, BUF_SIZE, (PACKET_READ_TICS * 2)); - //Write slave_data back to UART - if (len > 2) { - esp_err_t status = print_packet_data("Received ", slave_data, len); - - // If received packet is correct then send it back - if (status == ESP_OK) { - uart_write_bytes(UART_NUM1, (char*)slave_data, len); - good_count++; - } else { - printf("Incorrect packet received.\r\n"); - err_count++; - } - } else { - printf("Incorrect data packet[%d] received.\r\n", pack_count); - err_count++; - } - } - printf("Test completed. Received packets = %d, errors = %d\r\n", good_count, err_count); - // Wait for packet to be sent - uart_wait_tx_done(UART_NUM1, PACKET_READ_TICS); - free(slave_data); - uart_driver_delete(UART_NUM1); - TEST_ASSERT(err_count < 2); -} - -// Master test of multi device test case. -// It forms packet with random data, apply generated CRC16 and sends to slave. -// If response recieved correctly from slave means RS485 channel works. -static void rs485_master(void) -{ - uint16_t err_count = 0, good_count = 0; - rs485_init(); - uint8_t* master_buffer = (uint8_t*) malloc(BUF_SIZE); - uint8_t* slave_buffer = (uint8_t*) malloc(BUF_SIZE); - // The master test case should be synchronized with slave - unity_wait_for_signal("Slave_ready"); - unity_send_signal("Master_started"); - printf("Start recieve loop.\r\n"); - for(int i = 0; i < PACKETS_NUMBER; i++) { - // Form random buffer with CRC16 - buffer_fill_random(master_buffer, BUF_SIZE); - // Print created packet for debugging - esp_err_t status = print_packet_data("Send ", master_buffer, BUF_SIZE); - TEST_ASSERT(status == ESP_OK); - uart_write_bytes(UART_NUM1, (char*)master_buffer, BUF_SIZE); - // Read translated packet from slave - int len = uart_read_bytes(UART_NUM1, slave_buffer, BUF_SIZE, (PACKET_READ_TICS * 2)); - // Check if the received packet is too short - if (len > 2) { - // Print received packet and check checksum - esp_err_t status = print_packet_data("Received ", slave_buffer, len); - if (status == ESP_OK) { - good_count++; - printf("Received: %d\r\n", good_count); - } else { - err_count++; - printf("Errors: %d\r\n", err_count); - } - } - else { - printf("Incorrect answer from slave.\r\n"); - err_count++; - } - } - // Free the buffer and delete driver at the end - free(master_buffer); - uart_driver_delete(UART_NUM1); - TEST_ASSERT(err_count <= 1); - printf("Test completed. Received packets = %d, errors = %d\r\n", (uint16_t)good_count, (uint16_t)err_count); -} - -/* - * This multi devices test case verifies RS485 mode of the uart driver and checks - * correctness of RS485 interface channel communication. It requires - * RS485 bus driver hardware to be connected to boards. -*/ -TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[driver_RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave); - diff --git a/components/driver/uart.c b/components/driver/uart.c index 4dec742016..569ef53e0a 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -948,9 +948,9 @@ static void uart_rx_intr_handler_default(void *param) //We have to read out all data in RX FIFO to clear the interrupt signal for(buf_idx = 0; buf_idx < rx_fifo_len; buf_idx++) { #if CONFIG_IDF_TARGET_ESP32 - p_uart->rx_data_buf[buf_idx++] = uart_reg->fifo.rw_byte; + p_uart->rx_data_buf[buf_idx] = uart_reg->fifo.rw_byte; #elif CONFIG_IDF_TARGET_ESP32S2BETA - p_uart->rx_data_buf[buf_idx++] = READ_PERI_REG(UART_FIFO_AHB_REG(uart_num)); + p_uart->rx_data_buf[buf_idx] = READ_PERI_REG(UART_FIFO_AHB_REG(uart_num)); #endif } uint8_t pat_chr = uart_reg->at_cmd_char.data; diff --git a/components/efuse/test/CMakeLists.txt b/components/efuse/test/CMakeLists.txt index e239bfe5ce..9524509ea0 100644 --- a/components/efuse/test/CMakeLists.txt +++ b/components/efuse/test/CMakeLists.txt @@ -1,3 +1,6 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." "include" - REQUIRES unity test_utils efuse bootloader_support) \ No newline at end of file +if(IDF_TARGET STREQUAL "esp32") + idf_component_register(SRC_DIRS . + INCLUDE_DIRS . include + REQUIRES unity test_utils efuse bootloader_support + ) +endif() diff --git a/components/esp32/test/CMakeLists.txt b/components/esp32/test/CMakeLists.txt index 624f11d598..74ed23aeeb 100644 --- a/components/esp32/test/CMakeLists.txt +++ b/components/esp32/test/CMakeLists.txt @@ -1,16 +1,19 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." "${CMAKE_CURRENT_BINARY_DIR}" - REQUIRES unity test_utils nvs_flash ulp esp_common) +if(IDF_TARGET STREQUAL "esp32") + idf_component_register(SRC_DIRS . + INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR} + REQUIRES unity test_utils nvs_flash ulp esp_common + ) -add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h" - COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h" - WORKING_DIRECTORY ${COMPONENT_DIR} - DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg") + add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h" + COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h" + WORKING_DIRECTORY ${COMPONENT_DIR} + DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg") -add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h") + add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h") -add_dependencies(${COMPONENT_LIB} esp32_test_logo) + add_dependencies(${COMPONENT_LIB} esp32_test_logo) -idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND) + idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5") +endif() -target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5") diff --git a/components/esp32/test/test_aes_sha_rsa.c b/components/esp32/test/test_aes_sha_rsa.c index 8453b68f57..c4aff1d5ed 100644 --- a/components/esp32/test/test_aes_sha_rsa.c +++ b/components/esp32/test/test_aes_sha_rsa.c @@ -2,7 +2,6 @@ #include #include #include "esp_types.h" -#include "esp32/clk.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" diff --git a/components/esp32/test/test_intr_alloc.c b/components/esp32/test/test_intr_alloc.c index b17fb9e83e..a372675dd0 100644 --- a/components/esp32/test/test_intr_alloc.c +++ b/components/esp32/test/test_intr_alloc.c @@ -4,8 +4,11 @@ #include #include +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/ets_sys.h" - +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/ets_sys.h" +#endif #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" diff --git a/components/esp32/test/test_sleep.c b/components/esp32/test/test_sleep.c index 12e268e358..dc40af52c0 100644 --- a/components/esp32/test/test_sleep.c +++ b/components/esp32/test/test_sleep.c @@ -18,6 +18,7 @@ #include "test_utils.h" #include "sdkconfig.h" + #define ESP_EXT0_WAKEUP_LEVEL_LOW 0 #define ESP_EXT0_WAKEUP_LEVEL_HIGH 1 @@ -330,7 +331,7 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 low)", "[deepsleep][igno static float get_time_ms(void) { gettimeofday(&tv_stop, NULL); - + float dt = (tv_stop.tv_sec - tv_start.tv_sec) * 1e3f + (tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f; return fabs(dt); @@ -343,20 +344,20 @@ static uint32_t get_cause(void) return wakeup_cause; } -// This test case verifies deactivation of trigger for wake up sources +// This test case verifies deactivation of trigger for wake up sources TEST_CASE("disable source trigger behavior", "[deepsleep]") { float dt = 0; printf("Setup timer and ext0 to wake up immediately from GPIO_13 \n"); - + // Setup ext0 configuration to wake up almost immediately // The wakeup time is proportional to input capacitance * pullup resistance ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13)); ESP_ERROR_CHECK(gpio_pullup_en(GPIO_NUM_13)); ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13)); ESP_ERROR_CHECK(esp_sleep_enable_ext0_wakeup(GPIO_NUM_13, ESP_EXT0_WAKEUP_LEVEL_HIGH)); - + // Setup timer to wakeup with timeout esp_sleep_enable_timer_wakeup(2000000); @@ -367,22 +368,22 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]") dt = get_time_ms(); printf("Ext0 sleep time = %d \n", (int) dt); - // Check wakeup from Ext0 using time measurement because wakeup cause is + // Check wakeup from Ext0 using time measurement because wakeup cause is // not available in light sleep mode TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt); - + TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0); - + // Disable Ext0 source. Timer source should be triggered ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0)); printf("Disable ext0 trigger and leave timer active.\n"); - + gettimeofday(&tv_start, NULL); esp_light_sleep_start(); dt = get_time_ms(); printf("Timer sleep time = %d \n", (int) dt); - + TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt); // Additionally check wakeup cause @@ -407,8 +408,8 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]") TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt); TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0); - - // Check error message when source is already disabled + + // Check error message when source is already disabled esp_err_t err_code = esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TIMER); TEST_ASSERT(err_code == ESP_ERR_INVALID_STATE); } @@ -429,7 +430,7 @@ static void trigger_deepsleep(void) // Save start time. Deep sleep. gettimeofday(&start, NULL); esp_sleep_enable_timer_wakeup(1000); - // In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc() + // In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc() // to prevent a negative time after wake up. esp_deep_sleep_start(); } diff --git a/components/esp32s2beta/Kconfig b/components/esp32s2beta/Kconfig index ffc8d8e80e..6d25c77090 100644 --- a/components/esp32s2beta/Kconfig +++ b/components/esp32s2beta/Kconfig @@ -149,10 +149,7 @@ menu "ESP32S2-specific" choice SPIRAM_TYPE prompt "Type of SPI RAM chip in use" - default SPIRAM_TYPE_AUTO - - config SPIRAM_TYPE_AUTO - bool "Auto-detect" + default SPIRAM_TYPE_ESPPSRAM32 config SPIRAM_TYPE_ESPPSRAM32 bool "ESP-PSRAM32 or IS25WP032" @@ -163,7 +160,6 @@ menu "ESP32S2-specific" config SPIRAM_SIZE int - default -1 if SPIRAM_TYPE_AUTO default 4194304 if SPIRAM_TYPE_ESPPSRAM32 default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 0 diff --git a/components/esp32s2beta/ld/esp32s2beta.ld b/components/esp32s2beta/ld/esp32s2beta.ld index e69b47e19f..cc97c4b2fc 100644 --- a/components/esp32s2beta/ld/esp32s2beta.ld +++ b/components/esp32s2beta/ld/esp32s2beta.ld @@ -85,11 +85,10 @@ MEMORY Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled. */ rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM, - len = 0x1000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM + len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM - /* RTC fast memory (same block as above), viewed from data bus - * TODO: check whether rtc_data_seg address is correct - IDF-760 */ - rtc_data_seg(RW) : org = 0x3ff9e000, len = 0 + /* RTC fast memory (same block as above), viewed from data bus */ + rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 } _static_data_end = _bss_end; diff --git a/components/esp_eth/test/CMakeLists.txt b/components/esp_eth/test/CMakeLists.txt index c4041b1feb..789ab04cd1 100644 --- a/components/esp_eth/test/CMakeLists.txt +++ b/components/esp_eth/test/CMakeLists.txt @@ -1,3 +1,5 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - PRIV_REQUIRES "unity" "test_utils" "esp_eth") +if(IDF_TARGET STREQUAL "esp32") + idf_component_register(SRC_DIRS . + INCLUDE_DIRS . + PRIV_REQUIRES unity test_utils esp_eth) +endif() diff --git a/components/esp_event/test/CMakeLists.txt b/components/esp_event/test/CMakeLists.txt index 8264f10dda..79398640b5 100644 --- a/components/esp_event/test/CMakeLists.txt +++ b/components/esp_event/test/CMakeLists.txt @@ -1,3 +1,8 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "../private_include" "." - REQUIRES unity test_utils esp_event driver) +set(srcdirs .) +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcdirs "esp32") +endif() + +idf_component_register(SRC_DIRS ${srcdirs} + PRIV_INCLUDE_DIRS . ../private_include + PRIV_REQUIRES unity test_utils esp_event driver) diff --git a/components/esp_event/test/component.mk b/components/esp_event/test/component.mk index 22e49eddde..d74f156e8e 100644 --- a/components/esp_event/test/component.mk +++ b/components/esp_event/test/component.mk @@ -1,5 +1,7 @@ # #Component Makefile # + +COMPONENT_SRCDIRS += esp32 COMPONENT_PRIV_INCLUDEDIRS := ../private_include . COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive \ No newline at end of file diff --git a/components/esp_event/test/esp32/test_event.c b/components/esp_event/test/esp32/test_event.c new file mode 100644 index 0000000000..e66c860475 --- /dev/null +++ b/components/esp_event/test/esp32/test_event.c @@ -0,0 +1,1220 @@ +#include +#include + +#include "esp_event.h" +#include "sdkconfig.h" + +#include "freertos/FreeRTOS.h" +#include "esp_event_loop.h" +#include "freertos/task.h" +#include "freertos/portmacro.h" +#include "esp_log.h" +#include "driver/periph_ctrl.h" +#include "driver/timer.h" + +#include "esp_event.h" +#include "esp_event_private.h" +#include "esp_event_internal.h" + +#include "esp_heap_caps.h" + +#include "sdkconfig.h" +#include "unity.h" + +#include "test_utils.h" + +static const char* TAG = "test_event"; + +// #define TEST_CONFIG_ITEMS_TO_REGISTER 5 +#define TEST_CONFIG_TASKS_TO_SPAWN 2 + +#define TEST_CONFIG_WAIT_MULTIPLIER 5 + +// The initial logging "initializing test" is to ensure mutex allocation is not counted against memory not being freed +// during teardown. +#define TEST_SETUP() \ + ESP_LOGI(TAG, "initializing test"); \ + size_t free_mem_before = heap_caps_get_free_size(MALLOC_CAP_DEFAULT); \ + test_setup(); \ + s_test_core_id = xPortGetCoreID(); \ + s_test_priority = uxTaskPriorityGet(NULL); + +#define TEST_TEARDOWN() \ + test_teardown(); \ + vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); \ + TEST_ASSERT_EQUAL(free_mem_before, heap_caps_get_free_size(MALLOC_CAP_DEFAULT)); + +// typedef struct { +// void* data; +// SemaphoreHandle_t start; +// SemaphoreHandle_t done; +// } task_arg_t; + +// typedef struct { +// esp_event_base_t base; +// int32_t id; +// esp_event_handler_t* handles; +// int32_t num; +// esp_event_loop_handle_t loop; +// bool is_registration; +// } handler_registration_data_t; + +// typedef struct { +// esp_event_base_t base; +// int32_t id; +// esp_event_loop_handle_t loop; +// int32_t num; +// } post_event_data_t; + +// typedef struct { +// int performed; +// int expected; +// SemaphoreHandle_t done; +// } performance_data_t; + +// typedef struct { +// void* data; +// SemaphoreHandle_t mutex; +// } simple_arg_t; + +// typedef struct { +// int *arr; +// int index; +// } ordered_data_t; + +static BaseType_t s_test_core_id; +static UBaseType_t s_test_priority; + +ESP_EVENT_DECLARE_BASE(s_test_base1); +ESP_EVENT_DECLARE_BASE(s_test_base2); + +// ESP_EVENT_DEFINE_BASE(s_test_base1); +// ESP_EVENT_DEFINE_BASE(s_test_base2); + +enum { + TEST_EVENT_BASE1_EV1, + TEST_EVENT_BASE1_EV2, + TEST_EVENT_BASE1_MAX +}; + +// enum { +// TEST_EVENT_BASE2_EV1, +// TEST_EVENT_BASE2_EV2, +// TEST_EVENT_BASE2_MAX +// }; + +// static BaseType_t test_event_get_core() +// { +// static int calls = 0; + +// if (portNUM_PROCESSORS > 1) { +// return (s_test_core_id + calls++) % portNUM_PROCESSORS; +// } else { +// return s_test_core_id; +// } +// } + +// static esp_event_loop_args_t test_event_get_default_loop_args() +// { +// esp_event_loop_args_t loop_config = { +// .queue_size = CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE, +// .task_name = "loop", +// .task_priority = s_test_priority, +// .task_stack_size = 2048, +// .task_core_id = test_event_get_core() +// }; + +// return loop_config; +// } + +// static void test_event_simple_handler(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data) +// { +// if (!event_handler_arg) { +// return; +// } +// simple_arg_t* arg = (simple_arg_t*) event_handler_arg; +// xSemaphoreTake(arg->mutex, portMAX_DELAY); + +// int* count = (int*) arg->data; + +// if (event_data == NULL) { +// (*count)++; +// } else { +// (*count) += *((int*) event_data); +// } + +// xSemaphoreGive(arg->mutex); +// } + +// static void test_event_ordered_dispatch(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data) +// { +// int *arg = (int*) event_handler_arg; +// ordered_data_t *data = *((ordered_data_t**) (event_data)); + +// data->arr[data->index++] = *arg; +// } + +// static void test_event_performance_handler(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data) +// { +// performance_data_t* data = (performance_data_t*) event_handler_arg; + +// data->performed++; + +// if (data->performed >= data->expected) { +// xSemaphoreGive(data->done); +// } +// } + +// static void test_event_post_task(void* args) +// { +// task_arg_t* arg = (task_arg_t*) args; +// post_event_data_t* data = arg->data; + +// xSemaphoreTake(arg->start, portMAX_DELAY); + +// for (int i = 0; i < data->num; i++) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(data->loop, data->base, data->id, NULL, 0, portMAX_DELAY)); +// vTaskDelay(1); +// } + +// xSemaphoreGive(arg->done); + +// vTaskDelete(NULL); +// } + +// static void test_event_simple_handler_registration_task(void* args) +// { +// task_arg_t* arg = (task_arg_t*) args; +// handler_registration_data_t* data = (handler_registration_data_t*) arg->data; + +// xSemaphoreTake(arg->start, portMAX_DELAY); + +// for(int i = 0; i < data->num; i++) { +// if (data->is_registration) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(data->loop, data->base, data->id, data->handles[i], NULL)); +// } else { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_unregister_with(data->loop, data->base, data->id, data->handles[i])); +// } +// vTaskDelay(1); +// } + +// xSemaphoreGive(arg->done); + +// vTaskDelete(NULL); +// } + +// static void test_handler_post_w_task(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data) +// { +// simple_arg_t* arg = (simple_arg_t*) event_handler_arg; + +// esp_event_loop_handle_t* loop = (esp_event_loop_handle_t*) event_data; +// int* count = (int*) arg->data; + +// (*count)++; + +// if (*count <= 2) { +// if (event_base == s_test_base1 && event_id == TEST_EVENT_BASE1_EV1) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// } else{ +// xSemaphoreGive((SemaphoreHandle_t) arg->mutex); +// } +// } else { +// // Test that once the queue is full and the handler attempts to post to the same loop, +// // posting does not block indefinitely. +// if (event_base == s_test_base1 && event_id == TEST_EVENT_BASE1_EV1) { +// xSemaphoreTake((SemaphoreHandle_t) arg->mutex, portMAX_DELAY); +// TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// } +// } +// } + +// static void test_handler_post_wo_task(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data) +// { +// simple_arg_t* arg = (simple_arg_t*) event_handler_arg; + +// esp_event_loop_handle_t* loop = (esp_event_loop_handle_t*) event_data; +// int* count = (int*) arg->data; + +// (*count)++; + +// if (*count <= 2) { +// if (event_base == s_test_base1 && event_id == TEST_EVENT_BASE1_EV1) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// } else{ +// xSemaphoreGive((SemaphoreHandle_t) arg->mutex); +// } +// } else { +// // Test that once the queue is full and the handler attempts to post to the same loop, +// // posting does not block indefinitely. +// if (event_base == s_test_base1 && event_id == TEST_EVENT_BASE1_EV1) { +// xSemaphoreTake((SemaphoreHandle_t) arg->mutex, portMAX_DELAY); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// } +// } +// } + +// static void test_post_from_handler_loop_task(void* args) +// { +// esp_event_loop_handle_t event_loop = (esp_event_loop_handle_t) args; + +// while(1) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(event_loop, portMAX_DELAY)); +// } +// } + +static void test_setup(void) +{ + TEST_ASSERT_TRUE(TEST_CONFIG_TASKS_TO_SPAWN >= 2); + TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create_default()); +} + +static void test_teardown(void) +{ + TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete_default()); +} + +#define TIMER_DIVIDER 16 // Hardware timer clock divider +#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) // convert counter value to seconds +#define TIMER_INTERVAL0_SEC (2.0) // sample test interval for the first timer + +#if CONFIG_ESP_EVENT_POST_FROM_ISR +static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data) +{ + SemaphoreHandle_t *sem = (SemaphoreHandle_t*) event_handler_arg; + // Event data is just the address value (maybe have been truncated due to casting). + int *data = (int*) event_data; + TEST_ASSERT_EQUAL(*data, (int) (*sem)); + xSemaphoreGive(*sem); +} + +void IRAM_ATTR test_event_on_timer_alarm(void* para) +{ + /* Retrieve the interrupt status and the counter value + from the timer that reported the interrupt */ + uint64_t timer_counter_value = + timer_group_get_counter_value_in_isr(TIMER_GROUP_0, TIMER_0); + timer_group_intr_clr_in_isr(TIMER_GROUP_0, TIMER_0); + timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE); + timer_group_set_alarm_value_in_isr(TIMER_GROUP_0, TIMER_0, timer_counter_value); + + int data = (int) para; + // Posting events with data more than 4 bytes should fail. + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, 5, NULL)); + // This should succeedd, as data is int-sized. The handler for the event checks that the passed event data + // is correct. + BaseType_t task_unblocked; + TEST_ASSERT_EQUAL(ESP_OK, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, sizeof(data), &task_unblocked)); + if (task_unblocked == pdTRUE) { + portYIELD_FROM_ISR(); + } +} +#endif //CONFIG_ESP_EVENT_POST_FROM_ISR + +// TEST_CASE("can create and delete event loops", "[event]") +// { +// /* this test aims to verify that: +// * - creating loops with and without a task succeeds +// * - event queue can accomodate the set queue size, and drops the post when exceeded +// * - deleting loops with unconsumed posts and unregistered handlers (when unregistration is enabled) does not leak memory */ + +// TEST_SETUP(); + +// esp_event_loop_handle_t loop1; // with dedicated task +// esp_event_loop_handle_t loop2; // without dedicated task +// esp_event_loop_handle_t loop3; // with leftover post and handlers + +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop1)); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop2)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop3)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop3, s_test_base1, TEST_EVENT_BASE1_EV1, (void*) 0x00000001, NULL)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop3, s_test_base1, TEST_EVENT_BASE1_EV2, (void*) 0x00000002, NULL)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop3, s_test_base2, TEST_EVENT_BASE1_EV1, (void*) 0x00000003, NULL)); + +// for (int i = 0; i < loop_args.queue_size; i++) { +// int mod = i % 4; + +// switch(mod) { +// case 0: +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop3, s_test_base1, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); +// break; +// case 1: +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop3, s_test_base2, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); +// break; +// case 2: +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop3, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// break; +// case 3: +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop3, s_test_base2, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// break; +// default: +// break; +// } +// } + +// TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(loop3, s_test_base1, TEST_EVENT_BASE1_EV1, NULL, 0, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop1)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop2)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop3)); + +// TEST_TEARDOWN(); +// } + +// TEST_CASE("can register/unregister handlers for all events/all events for a specific base", "[event]") +// { +// /* this test aims to verify that handlers can be registered to be called on all events +// * or for all events with specific bases */ + +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; + +// int count = 0; + +// simple_arg_t arg = { +// .data = &count, +// .mutex = xSemaphoreCreateMutex() +// }; + +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// /* Register the handler twice to the same base and id but with a different argument (expects to return ESP_OK and log a warning) +// * This aims to verify: 1) Handler's argument to be updated +// * 2) Registration not to leak memory +// */ +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, ESP_EVENT_ANY_BASE, ESP_EVENT_ANY_ID, test_event_simple_handler, NULL)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, ESP_EVENT_ANY_BASE, ESP_EVENT_ANY_ID, test_event_simple_handler, &arg)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, ESP_EVENT_ANY_ID, test_event_simple_handler, &arg)); +// TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_handler_register_with(loop, ESP_EVENT_ANY_BASE, TEST_EVENT_BASE1_EV1, test_event_simple_handler, &arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_event_simple_handler, &arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_simple_handler, &arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base2, TEST_EVENT_BASE1_EV1, test_event_simple_handler, &arg)); + +// TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_post_to(loop, ESP_EVENT_ANY_BASE, ESP_EVENT_ANY_ID, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_post_to(loop, s_test_base1, ESP_EVENT_ANY_ID, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_post_to(loop, ESP_EVENT_ANY_BASE, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); // exec loop, base and id level (+3) +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); // exec loop, base and id level (+3) + +// // Post unknown events. Respective loop level and base level handlers should still execute. +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_MAX, NULL, 0, portMAX_DELAY)); // exec loop and base level (+2) +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base2, TEST_EVENT_BASE2_MAX, NULL, 0, portMAX_DELAY)); // exec loop level (+1) + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(9, count); // 3 + 3 + 2 + 1 + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// vSemaphoreDelete(arg.mutex); + +// TEST_TEARDOWN(); +// } + +// TEST_CASE("can unregister handler", "[event]") +// { +// /* this test aims to verify that unregistered handlers no longer execute when events are raised */ + +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// int count = 0; + +// simple_arg_t arg = { +// .data = &count, +// .mutex = xSemaphoreCreateMutex() +// }; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_event_simple_handler, &arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base2, TEST_EVENT_BASE1_EV1, test_event_simple_handler, &arg)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base2, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(2, count); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_unregister_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_event_simple_handler)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base2, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(3, count); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// vSemaphoreDelete(arg.mutex); + +// TEST_TEARDOWN(); +// } + +// TEST_CASE("can exit running loop at approximately the set amount of time", "[event]") +// { +// /* this test aims to verify that running loop does not block indefinitely in cases where +// * events are posted frequently */ + +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// performance_data_t handler_data = { +// .performed = 0, +// .expected = INT32_MAX, +// .done = xSemaphoreCreateBinary() +// }; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_event_performance_handler, &handler_data)); + +// post_event_data_t post_event_data = { +// .base = s_test_base1, +// .id = TEST_EVENT_BASE1_EV1, +// .loop = loop, +// .num = INT32_MAX +// }; + +// task_arg_t post_event_arg = { +// .data = &post_event_data, +// .done = xSemaphoreCreateBinary(), +// .start = xSemaphoreCreateBinary() +// }; + +// TaskHandle_t post_task; + +// xTaskCreatePinnedToCore(test_event_post_task, "post", 2048, &post_event_arg, s_test_priority, &post_task, test_event_get_core()); + +// int runtime_ms = 10; +// int runtime_us = runtime_ms * 1000; + +// int64_t start, diff; +// start = esp_timer_get_time(); + +// xSemaphoreGive(post_event_arg.start); + +// // Run the loop for the runtime_ms set amount of time, regardless of whether events +// // are still being posted to the loop. +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(runtime_ms))); + +// diff = (esp_timer_get_time() - start); + +// // Threshold is 25 percent. +// TEST_ASSERT(diff < runtime_us * 1.25f); + +// // Verify that the post task still continues +// TEST_ASSERT_NOT_EQUAL(pdTRUE, xSemaphoreTake(post_event_arg.done, pdMS_TO_TICKS(10))); + +// vSemaphoreDelete(post_event_arg.done); +// vSemaphoreDelete(post_event_arg.start); +// vSemaphoreDelete(handler_data.done); +// vTaskDelete(post_task); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// TEST_TEARDOWN(); +// } + +// TEST_CASE("can register/unregister handlers simultaneously", "[event]") +// { +// /* this test aims to verify that the event handlers list remains consistent despite +// * simultaneous access by differenct tasks */ + +// TEST_SETUP(); + +// const char* base = "base"; +// int32_t id = 0; + +// esp_event_loop_handle_t loop; +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// ESP_LOGI(TAG, "registering handlers"); + +// handler_registration_data_t* registration_data = calloc(TEST_CONFIG_TASKS_TO_SPAWN, sizeof(*registration_data)); +// task_arg_t* registration_arg = calloc(TEST_CONFIG_TASKS_TO_SPAWN, sizeof(*registration_arg)); + +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// registration_data[i].base = base; +// registration_data[i].id = id; +// registration_data[i].loop = loop; +// registration_data[i].handles = calloc(TEST_CONFIG_ITEMS_TO_REGISTER, sizeof(esp_event_handler_t)); +// registration_data[i].num = TEST_CONFIG_ITEMS_TO_REGISTER; +// registration_data[i].is_registration = true; + +// for (int j = 0; j < TEST_CONFIG_ITEMS_TO_REGISTER; j++) { +// registration_data[i].handles[j] = (void*) (i * TEST_CONFIG_ITEMS_TO_REGISTER) + (j + TEST_CONFIG_ITEMS_TO_REGISTER); +// } + +// registration_arg[i].start = xSemaphoreCreateBinary(); +// registration_arg[i].done = xSemaphoreCreateBinary(); +// registration_arg[i].data = ®istration_data[i]; + +// xTaskCreatePinnedToCore(test_event_simple_handler_registration_task, "register", 2048, ®istration_arg[i], s_test_priority, NULL, test_event_get_core()); +// } + +// // Give the semaphores to the spawned registration task +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// xSemaphoreGive(registration_arg[i].start); +// } + +// // Take the same semaphores in order to proceed +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// xSemaphoreTake(registration_arg[i].done, portMAX_DELAY); +// } + +// ESP_LOGI(TAG, "checking consistency of handlers list"); + +// // Check consistency of events list +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// for (int j = 0; j < TEST_CONFIG_ITEMS_TO_REGISTER; j++) { +// TEST_ASSERT_TRUE(esp_event_is_handler_registered(loop, base, id, registration_data[i].handles[j])); +// } +// } + +// ESP_LOGI(TAG, "unregistering handlers"); + +// /* Test if tasks can unregister simultaneously */ + +// // Unregister registered events +// handler_registration_data_t* unregistration_data = calloc(TEST_CONFIG_TASKS_TO_SPAWN, sizeof(*unregistration_data)); +// task_arg_t* unregistration_arg = calloc(TEST_CONFIG_TASKS_TO_SPAWN, sizeof(*unregistration_arg)); + +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// unregistration_data[i].base = base; +// unregistration_data[i].id = id; +// unregistration_data[i].loop = loop; +// unregistration_data[i].handles = calloc(TEST_CONFIG_ITEMS_TO_REGISTER, sizeof(esp_event_handler_t)); +// unregistration_data[i].num = TEST_CONFIG_ITEMS_TO_REGISTER; +// unregistration_data[i].is_registration = false; + +// memcpy(unregistration_data[i].handles, registration_data[i].handles, TEST_CONFIG_ITEMS_TO_REGISTER * sizeof(esp_event_handler_t)); + +// unregistration_arg[i].data = &unregistration_data[i]; +// unregistration_arg[i].start = xSemaphoreCreateBinary(); +// unregistration_arg[i].done = xSemaphoreCreateBinary(); + +// xTaskCreatePinnedToCore(test_event_simple_handler_registration_task, "unregister", 2048, &unregistration_arg[i], s_test_priority, NULL, test_event_get_core()); +// } + +// // Give the semaphores to the spawned unregistration task +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// xSemaphoreGive(unregistration_arg[i].start); +// } + +// // Take the same semaphores in order to proceed +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// xSemaphoreTake(unregistration_arg[i].done, portMAX_DELAY); +// } + +// ESP_LOGI(TAG, "checking consistency of handlers list"); + +// // Check consistency of events list +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// for (int j = 0; j < TEST_CONFIG_ITEMS_TO_REGISTER; j++) { +// TEST_ASSERT_FALSE(esp_event_is_handler_registered(loop, base, id, registration_data[i].handles[j])); +// } +// } + +// // Do cleanup +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// free(registration_data[i].handles); +// vSemaphoreDelete(registration_arg[i].start); +// vSemaphoreDelete(registration_arg[i].done); + +// free(unregistration_data[i].handles); +// vSemaphoreDelete(unregistration_arg[i].start); +// vSemaphoreDelete(unregistration_arg[i].done); +// } + +// free(registration_data); +// free(unregistration_data); +// free(registration_arg); +// free(unregistration_arg); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// TEST_TEARDOWN(); +// } + +// TEST_CASE("can post and run events", "[event]") +// { +// /* this test aims to verify that: +// * - multiple tasks can post to the queue simultaneously +// * - handlers recieve the appropriate handler arg and associated event data */ + +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; + +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// loop_args.queue_size = TEST_CONFIG_TASKS_TO_SPAWN * TEST_CONFIG_ITEMS_TO_REGISTER; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// int count = 0; + +// simple_arg_t arg = { +// .data = &count, +// .mutex = xSemaphoreCreateMutex() +// }; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_event_simple_handler, &arg)); + +// post_event_data_t* post_event_data = calloc(TEST_CONFIG_TASKS_TO_SPAWN, sizeof(*post_event_data)); +// task_arg_t* post_event_arg = calloc(TEST_CONFIG_TASKS_TO_SPAWN, sizeof(*post_event_arg)); + +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) +// { +// post_event_data[i].base = s_test_base1; +// post_event_data[i].id = TEST_EVENT_BASE1_EV1; +// post_event_data[i].loop = loop; +// post_event_data[i].num = TEST_CONFIG_ITEMS_TO_REGISTER; + +// post_event_arg[i].data = &post_event_data[i]; +// post_event_arg[i].start = xSemaphoreCreateBinary(); +// post_event_arg[i].done = xSemaphoreCreateBinary(); + +// xTaskCreatePinnedToCore(test_event_post_task, "post", 2048, &post_event_arg[i], s_test_priority, NULL, test_event_get_core()); +// } + +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// xSemaphoreGive(post_event_arg[i].start); +// } + +// // Execute some events as they are posted +// for (int i = 0; i < (TEST_CONFIG_TASKS_TO_SPAWN * TEST_CONFIG_ITEMS_TO_REGISTER) / 2; i++) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); +// } + +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// xSemaphoreTake(post_event_arg[i].done, portMAX_DELAY); +// } + +// // Execute the rest +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(TEST_CONFIG_TASKS_TO_SPAWN * TEST_CONFIG_ITEMS_TO_REGISTER, count); + +// // Cleanup +// for (int i = 0; i < TEST_CONFIG_TASKS_TO_SPAWN; i++) { +// vSemaphoreDelete(post_event_arg[i].start); +// vSemaphoreDelete(post_event_arg[i].done); +// } + +// free(post_event_data); +// free(post_event_arg); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// vSemaphoreDelete(arg.mutex); + +// TEST_TEARDOWN(); +// } + +// static void loop_run_task(void* args) +// { +// esp_event_loop_handle_t event_loop = (esp_event_loop_handle_t) args; + +// while(1) { +// esp_event_loop_run(event_loop, portMAX_DELAY); +// } +// } + +// static void performance_test(bool dedicated_task) +// { +// // rand() seems to do a one-time allocation. Call it here so that the memory it allocates +// // is not counted as a leak. +// unsigned int _rand __attribute__((unused)) = rand(); + +// TEST_SETUP(); + +// const char test_base[] = "qwertyuiopasdfghjklzxvbnmmnbvcxzqwertyuiopasdfghjklzxvbnmmnbvcxz"; + +// #define TEST_CONFIG_BASES (sizeof(test_base) - 1) +// #define TEST_CONFIG_IDS (TEST_CONFIG_BASES / 2) + +// // Create loop +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); +// esp_event_loop_handle_t loop; + +// if (!dedicated_task) { +// loop_args.task_name = NULL; +// } + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// performance_data_t data; + +// // Register the handlers +// for (int base = 0; base < TEST_CONFIG_BASES; base++) { +// for (int id = 0; id < TEST_CONFIG_IDS; id++) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, test_base + base, id, test_event_performance_handler, &data)); +// } +// } + +// TaskHandle_t mtask = NULL; + +// if (!dedicated_task) { +// xTaskCreate(loop_run_task, "loop_run", loop_args.task_stack_size, (void*) loop, loop_args.task_priority, &mtask); +// } + +// // Perform performance test +// float running_sum = 0; +// float running_count = 0; + +// for (int bases = 1; bases <= TEST_CONFIG_BASES; bases *= 2) { +// for (int ids = 1; ids <= TEST_CONFIG_IDS; ids *= 2) { + +// data.performed = 0; +// data.expected = bases * ids; +// data.done = xSemaphoreCreateBinary(); + +// // Generate randomized list of posts +// int post_bases[TEST_CONFIG_BASES]; +// int post_ids[TEST_CONFIG_IDS]; + +// for (int i = 0; i < bases; i++) { +// post_bases[i] = i; +// } + +// for (int i = 0; i < ids; i++) { +// post_ids[i] = i; +// } + +// for (int i = 0; i < bases; i++) { +// int rand_a = rand() % bases; +// int rand_b = rand() % bases; + +// int temp = post_bases[rand_a]; +// post_bases[rand_a]= post_bases[rand_b]; +// post_bases[rand_b] = temp; +// } + +// for (int i = 0; i < ids; i++) { +// int rand_a = rand() % ids; +// int rand_b = rand() % ids; + +// int temp = post_ids[rand_a]; +// post_ids[rand_a]= post_ids[rand_b]; +// post_ids[rand_b] = temp; +// } + +// // Post the events +// int64_t start = esp_timer_get_time(); +// for (int base = 0; base < bases; base++) { +// for (int id = 0; id < ids; id++) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, test_base + post_bases[base], post_ids[id], NULL, 0, portMAX_DELAY)); +// } +// } + +// xSemaphoreTake(data.done, portMAX_DELAY); +// int64_t elapsed = esp_timer_get_time() - start; + +// // Record data +// TEST_ASSERT_EQUAL(data.expected, data.performed); + +// running_count++; +// running_sum += data.performed / (elapsed / (1000000.0)); + +// vSemaphoreDelete(data.done); +// } +// } + +// int average = (int) (running_sum / (running_count)); + +// if (!dedicated_task) { +// ((esp_event_loop_instance_t*) loop)->task = mtask; +// } + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// TEST_TEARDOWN(); + +// #ifdef CONFIG_ESP_EVENT_LOOP_PROFILING +// ESP_LOGI(TAG, "events dispatched/second with profiling enabled: %d", average); +// // Enabling profiling will slow down event dispatch, so the set threshold +// // is not valid when it is enabled. +// #else +// #ifndef CONFIG_SPIRAM +// TEST_PERFORMANCE_GREATER_THAN(EVENT_DISPATCH, "%d", average); +// #else +// TEST_PERFORMANCE_GREATER_THAN(EVENT_DISPATCH_PSRAM, "%d", average); +// #endif // CONFIG_SPIRAM +// #endif // CONFIG_ESP_EVENT_LOOP_PROFILING +// } + +// TEST_CASE("performance test - dedicated task", "[event]") +// { +// performance_test(true); +// } + +// TEST_CASE("performance test - no dedicated task", "[event]") +// { +// performance_test(false); +// } + +// TEST_CASE("can post to loop from handler - dedicated task", "[event]") +// { +// TEST_SETUP(); + +// esp_event_loop_handle_t loop_w_task; + +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// int count; + +// simple_arg_t arg = { +// .data = &count, +// .mutex = xSemaphoreCreateBinary() +// }; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop_w_task)); + +// count = 0; + +// // Test that a handler can post to a different loop while there is still slots on the queue +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV1, test_handler_post_w_task, &arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV2, test_handler_post_w_task, &arg)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV1, &loop_w_task, sizeof(&loop_w_task), portMAX_DELAY)); + +// xSemaphoreTake(arg.mutex, portMAX_DELAY); + +// TEST_ASSERT_EQUAL(2, count); + +// // Test that other tasks can still post while there is still slots in the queue, while handler is executing +// count = 100; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV1, &loop_w_task, sizeof(&loop_w_task), portMAX_DELAY)); + +// for (int i = 0; i < loop_args.queue_size; i++) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// } + +// TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, +// pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER))); + +// xSemaphoreGive(arg.mutex); + +// vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop_w_task)); + +// vSemaphoreDelete(arg.mutex); + +// TEST_TEARDOWN(); +// } + +// TEST_CASE("can post to loop from handler - no dedicated task", "[event]") +// { +// TEST_SETUP(); + +// esp_event_loop_handle_t loop_wo_task; + +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// int count; + +// simple_arg_t arg = { +// .data = &count, +// .mutex = xSemaphoreCreateBinary() +// }; + +// count = 0; + +// loop_args.queue_size = 1; +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop_wo_task)); + +// TaskHandle_t mtask; + +// xTaskCreate(test_post_from_handler_loop_task, "task", 2584, (void*) loop_wo_task, s_test_priority, &mtask); + +// // Test that a handler can post to a different loop while there is still slots on the queue +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV1, test_handler_post_wo_task, &arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV2, test_handler_post_wo_task, &arg)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV1, &loop_wo_task, sizeof(&loop_wo_task), portMAX_DELAY)); + +// xSemaphoreTake(arg.mutex, portMAX_DELAY); + +// TEST_ASSERT_EQUAL(2, count); + +// count = 100; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV1, &loop_wo_task, sizeof(&loop_wo_task), portMAX_DELAY)); + +// vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); + +// // For loop without tasks, posting is more restrictive. Posting should wait until execution of handler finishes +// TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, +// pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER))); + +// xSemaphoreGive(arg.mutex); + +// vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); + +// vTaskDelete(mtask); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop_wo_task)); + +// vSemaphoreDelete(arg.mutex); + +// TEST_TEARDOWN(); +// } + +// static void test_event_simple_handler_template(void* handler_arg, esp_event_base_t base, int32_t id, void* event_arg) +// { +// int* count = (int*) handler_arg; +// (*count)++; +// } + +// static void test_event_simple_handler_1(void* handler_arg, esp_event_base_t base, int32_t id, void* event_arg) +// { +// test_event_simple_handler_template(handler_arg, base, id, event_arg); +// } + +// static void test_event_simple_handler_3(void* handler_arg, esp_event_base_t base, int32_t id, void* event_arg) +// { +// test_event_simple_handler_template(handler_arg, base, id, event_arg); +// } + +// static void test_event_simple_handler_2(void* handler_arg, esp_event_base_t base, int32_t id, void* event_arg) +// { +// test_event_simple_handler_template(handler_arg, base, id, event_arg); +// } + +// static void test_registration_from_handler_hdlr(void* handler_arg, esp_event_base_t base, int32_t id, void* event_arg) +// { +// esp_event_loop_handle_t* loop = (esp_event_loop_handle_t*) event_arg; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_simple_handler_1, handler_arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_simple_handler_2, handler_arg)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_simple_handler_3, handler_arg)); +// } + +// static void test_unregistration_from_handler_hdlr(void* handler_arg, esp_event_base_t base, int32_t id, void* event_arg) +// { +// esp_event_loop_handle_t* loop = (esp_event_loop_handle_t*) event_arg; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_unregister_with(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_simple_handler_1)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_unregister_with(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_simple_handler_2)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_unregister_with(*loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_simple_handler_3)); +// } + +// TEST_CASE("can register from handler", "[event]") +// { +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; + +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// int count = 0; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_registration_from_handler_hdlr, &count)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base2, TEST_EVENT_BASE2_EV1, test_unregistration_from_handler_hdlr, &count)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, &loop, sizeof(&loop), portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(3, count); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base2, TEST_EVENT_BASE2_EV1, &loop, sizeof(&loop), portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(3, count); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// TEST_TEARDOWN(); +// } + +// static void test_create_loop_handler(void* handler_args, esp_event_base_t base, int32_t id, void* event_data) +// { +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// if (id == TEST_EVENT_BASE1_EV1) { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, (esp_event_loop_handle_t*) handler_args)); +// } else { +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(*((esp_event_loop_handle_t*) handler_args))); +// } +// } + +// TEST_CASE("can create and delete loop from handler", "[event]") +// { +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; +// esp_event_loop_handle_t test_loop; + +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_create_loop_handler, &test_loop)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_create_loop_handler, &test_loop)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// TEST_TEARDOWN(); +// } + +// TEST_CASE("events are dispatched in the order they are registered", "[event]") +// { +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// int id_arr[7]; + +// for (int i = 0; i < 7; i++) { +// id_arr[i] = i; +// } + +// int data_arr[12] = {0}; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base2, TEST_EVENT_BASE2_EV1, test_event_ordered_dispatch, id_arr + 0)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, ESP_EVENT_ANY_BASE, ESP_EVENT_ANY_ID, test_event_ordered_dispatch, id_arr + 1)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, ESP_EVENT_ANY_ID, test_event_ordered_dispatch, id_arr + 2)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base2, TEST_EVENT_BASE2_EV2, test_event_ordered_dispatch, id_arr + 3)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV1, test_event_ordered_dispatch, id_arr + 4)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base2, ESP_EVENT_ANY_ID, test_event_ordered_dispatch, id_arr + 5)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register_with(loop, s_test_base1, TEST_EVENT_BASE1_EV2, test_event_ordered_dispatch, id_arr + 6)); + +// esp_event_dump(stdout); + +// ordered_data_t data = { +// .arr = data_arr, +// .index = 0 +// }; + +// ordered_data_t* dptr = &data; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base2, TEST_EVENT_BASE1_EV2, &dptr, sizeof(dptr), portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, &dptr, sizeof(dptr), portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV2, &dptr, sizeof(dptr), portMAX_DELAY)); +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base2, TEST_EVENT_BASE1_EV1, &dptr, sizeof(dptr), portMAX_DELAY)); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_run(loop, pdMS_TO_TICKS(10))); + +// // Expected data executing the posts above +// int ref_arr[12] = {1, 3, 5, 1, 2, 4, 1, 2, 6, 0, 1, 5}; + +// for (int i = 0; i < 12; i++) { +// TEST_ASSERT_EQUAL(ref_arr[i], data_arr[i]); +// } + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// TEST_TEARDOWN(); +// } + +#if CONFIG_ESP_EVENT_POST_FROM_ISR +// TEST_CASE("can properly prepare event data posted to loop", "[event]") +// { +// TEST_SETUP(); + +// esp_event_loop_handle_t loop; +// esp_event_loop_args_t loop_args = test_event_get_default_loop_args(); + +// loop_args.task_name = NULL; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create(&loop_args, &loop)); + +// esp_event_post_instance_t post; +// esp_event_loop_instance_t* loop_def = (esp_event_loop_instance_t*) loop; + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, NULL, 0, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(pdTRUE, xQueueReceive(loop_def->queue, &post, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(false, post.data_set); +// TEST_ASSERT_EQUAL(false, post.data_allocated); +// TEST_ASSERT_EQUAL(NULL, post.data.ptr); + +// int sample = 0; +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_isr_post_to(loop, s_test_base1, TEST_EVENT_BASE1_EV1, &sample, sizeof(sample), NULL)); +// TEST_ASSERT_EQUAL(pdTRUE, xQueueReceive(loop_def->queue, &post, portMAX_DELAY)); +// TEST_ASSERT_EQUAL(true, post.data_set); +// TEST_ASSERT_EQUAL(false, post.data_allocated); +// TEST_ASSERT_EQUAL(false, post.data.val); + +// TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop)); + +// TEST_TEARDOWN(); +// } + +TEST_CASE("can post events from interrupt handler", "[event]") +{ + SemaphoreHandle_t sem = xSemaphoreCreateBinary(); + + /* Select and initialize basic parameters of the timer */ + timer_config_t config; + config.divider = TIMER_DIVIDER; + config.counter_dir = TIMER_COUNT_UP; + config.counter_en = TIMER_PAUSE; + config.alarm_en = TIMER_ALARM_EN; + config.intr_type = TIMER_INTR_LEVEL; + config.auto_reload = false; + timer_init(TIMER_GROUP_0, TIMER_0, &config); + + /* Timer's counter will initially start from value below. + Also, if auto_reload is set, this value will be automatically reload on alarm */ + timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL); + + /* Configure the alarm value and the interrupt on alarm. */ + timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, TIMER_INTERVAL0_SEC * TIMER_SCALE); + timer_enable_intr(TIMER_GROUP_0, TIMER_0); + timer_isr_register(TIMER_GROUP_0, TIMER_0, test_event_on_timer_alarm, + (void *) sem, ESP_INTR_FLAG_IRAM, NULL); + + timer_start(TIMER_GROUP_0, TIMER_0); + + TEST_SETUP(); + + TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register(s_test_base1, TEST_EVENT_BASE1_EV1, + test_handler_post_from_isr, &sem)); + + xSemaphoreTake(sem, portMAX_DELAY); + + TEST_TEARDOWN(); +} +#endif // CONFIG_ESP_EVENT_POST_FROM_ISR diff --git a/components/esp_event/test/test_event.c b/components/esp_event/test/test_event.c index d598acfbd0..df0c4bfd47 100644 --- a/components/esp_event/test/test_event.c +++ b/components/esp_event/test/test_event.c @@ -278,44 +278,6 @@ static void test_teardown(void) #define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) // convert counter value to seconds #define TIMER_INTERVAL0_SEC (2.0) // sample test interval for the first timer -#if CONFIG_ESP_EVENT_POST_FROM_ISR -static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data) -{ - SemaphoreHandle_t *sem = (SemaphoreHandle_t*) event_handler_arg; - // Event data is just the address value (maybe have been truncated due to casting). - int *data = (int*) event_data; - TEST_ASSERT_EQUAL(*data, (int) (*sem)); - xSemaphoreGive(*sem); -} -#endif - -#if CONFIG_IDF_TARGET_ESP32S2BETA -#warning "test_event_on_timer_alarm not ported to esp32s2beta" -#else -#if CONFIG_ESP_EVENT_POST_FROM_ISR -void IRAM_ATTR test_event_on_timer_alarm(void* para) -{ - /* Retrieve the interrupt status and the counter value - from the timer that reported the interrupt */ - uint64_t timer_counter_value = - timer_group_get_counter_value_in_isr(TIMER_GROUP_0, TIMER_0); - timer_group_intr_clr_in_isr(TIMER_GROUP_0, TIMER_0); - timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE); - timer_group_set_alarm_value_in_isr(TIMER_GROUP_0, TIMER_0, timer_counter_value); - - int data = (int) para; - // Posting events with data more than 4 bytes should fail. - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, 5, NULL)); - // This should succeedd, as data is int-sized. The handler for the event checks that the passed event data - // is correct. - BaseType_t task_unblocked; - TEST_ASSERT_EQUAL(ESP_OK, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, sizeof(data), &task_unblocked)); - if (task_unblocked == pdTRUE) { - portYIELD_FROM_ISR(); - } -} -#endif //CONFIG_ESP_EVENT_POST_FROM_ISR -#endif //CONFIG_IDF_TARGET_ESP32S2BETA TEST_CASE("can create and delete event loops", "[event]") { @@ -876,7 +838,7 @@ TEST_CASE("performance test - dedicated task", "[event]") performance_test(true); } -TEST_CASE("performance test - no dedicated task", "[event]") +TEST_CASE_ESP32("performance test - no dedicated task", "[event]") { performance_test(false); } @@ -1188,45 +1150,6 @@ TEST_CASE("can properly prepare event data posted to loop", "[event]") TEST_TEARDOWN(); } -#if CONFIG_IDF_TARGET_ESP32S2BETA -#warning "can post events from interrupt handler not ported to esp32s2beta" -#else -TEST_CASE("can post events from interrupt handler", "[event]") -{ - SemaphoreHandle_t sem = xSemaphoreCreateBinary(); - - /* Select and initialize basic parameters of the timer */ - timer_config_t config; - config.divider = TIMER_DIVIDER; - config.counter_dir = TIMER_COUNT_UP; - config.counter_en = TIMER_PAUSE; - config.alarm_en = TIMER_ALARM_EN; - config.intr_type = TIMER_INTR_LEVEL; - config.auto_reload = false; - timer_init(TIMER_GROUP_0, TIMER_0, &config); - - /* Timer's counter will initially start from value below. - Also, if auto_reload is set, this value will be automatically reload on alarm */ - timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL); - - /* Configure the alarm value and the interrupt on alarm. */ - timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, TIMER_INTERVAL0_SEC * TIMER_SCALE); - timer_enable_intr(TIMER_GROUP_0, TIMER_0); - timer_isr_register(TIMER_GROUP_0, TIMER_0, test_event_on_timer_alarm, - (void *) sem, ESP_INTR_FLAG_IRAM, NULL); - - timer_start(TIMER_GROUP_0, TIMER_0); - - TEST_SETUP(); - - TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register(s_test_base1, TEST_EVENT_BASE1_EV1, - test_handler_post_from_isr, &sem)); - - xSemaphoreTake(sem, portMAX_DELAY); - - TEST_TEARDOWN(); -} -#endif // CONFIG_IDF_TARGET_ESP32S2BETA #endif // CONFIG_ESP_EVENT_POST_FROM_ISR #ifdef CONFIG_ESP_EVENT_LOOP_PROFILING diff --git a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.spiflash.ld b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.spiflash.ld index 7b1f49e6a3..71195da2bc 100644 --- a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.spiflash.ld +++ b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.spiflash.ld @@ -26,3 +26,5 @@ PROVIDE ( esp_rom_spiflash_erase_sector = SPIEraseSector ); PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock ); PROVIDE ( esp_rom_spiflash_wait_idle = SPI_Wait_Idle ); PROVIDE ( esp_rom_spiflash_config_readmode = SPIReadModeCnfig ); +PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock ); +PROVIDE ( esp_rom_spiflash_write_encrypted = SPI_Encrypt_Write ); \ No newline at end of file diff --git a/components/esp_wifi/lib_esp32 b/components/esp_wifi/lib_esp32 index 75c9095783..7d93cbf05b 160000 --- a/components/esp_wifi/lib_esp32 +++ b/components/esp_wifi/lib_esp32 @@ -1 +1 @@ -Subproject commit 75c9095783d095f28c6dab283f314d2b13918713 +Subproject commit 7d93cbf05bb521520700b2cbcc8e104d9cb9efec diff --git a/components/esp_wifi/lib_esp32s2beta b/components/esp_wifi/lib_esp32s2beta index ef025b8fd5..adea187bc0 160000 --- a/components/esp_wifi/lib_esp32s2beta +++ b/components/esp_wifi/lib_esp32s2beta @@ -1 +1 @@ -Subproject commit ef025b8fd540f1fc9b6d2665684be033724b46c8 +Subproject commit adea187bc049130900d993a4578710fa54610a31 diff --git a/components/esp_wifi/test/CMakeLists.txt b/components/esp_wifi/test/CMakeLists.txt index e7cf4b12c8..049a1ec682 100644 --- a/components/esp_wifi/test/CMakeLists.txt +++ b/components/esp_wifi/test/CMakeLists.txt @@ -1,6 +1,12 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." "${CMAKE_CURRENT_BINARY_DIR}" - REQUIRES unity test_utils nvs_flash ulp esp_common) +set(srcdirs ".") +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcdirs "esp32") +endif() + +idf_component_register(SRC_DIRS ${srcdirs} + INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR} + REQUIRES unity test_utils nvs_flash ulp esp_common + ) idf_component_get_property(esp_wifi_dir esp_wifi COMPONENT_DIR) diff --git a/components/esp_wifi/test/component.mk b/components/esp_wifi/test/component.mk index 7dbb988dd0..3c4a6bb67a 100644 --- a/components/esp_wifi/test/component.mk +++ b/components/esp_wifi/test/component.mk @@ -5,6 +5,7 @@ COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_SRCDIRS := . +COMPONENT_SRCDIRS += esp32 # Calculate MD5 value of header file esp_wifi_os_adapter.h WIFI_OS_ADAPTER_MD5_VAL=\"$(shell md5sum $(IDF_PATH)/components/esp_wifi/include/esp_private/wifi_os_adapter.h | cut -c 1-7)\" diff --git a/components/esp_wifi/test/test_phy_rtc.c b/components/esp_wifi/test/esp32/test_phy_rtc.c similarity index 94% rename from components/esp_wifi/test/test_phy_rtc.c rename to components/esp_wifi/test/esp32/test_phy_rtc.c index 133a62c355..9bbe9544a5 100644 --- a/components/esp_wifi/test/test_phy_rtc.c +++ b/components/esp_wifi/test/esp32/test_phy_rtc.c @@ -11,18 +11,23 @@ #include #include #include +#include "soc/soc_caps.h" //Function just extern, need not test +#ifdef SOC_BT_SUPPORTED extern void bt_bb_init_cmplx(void); +#endif extern void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void); extern void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void); //Functions in librtc.a called by WIFI or Blutooth directly in ISR +#ifdef SOC_BT_SUPPORTED extern void bt_bb_init_cmplx_reg(void); +extern void bt_track_pll_cap(void); +#endif extern void force_wifi_mode(int); extern void unforce_wifi_mode(void); -extern void bt_track_pll_cap(void); static const char* TAG = "test_phy_rtc"; @@ -39,7 +44,9 @@ static void test_phy_rtc_init(void) } TEST_ESP_OK(ret); +#ifdef SOC_BT_SUPPORTED esp_phy_load_cal_and_init(PHY_BT_MODULE); +#endif esp_phy_load_cal_and_init(PHY_WIFI_MODULE); //must run here, not blocking in above code @@ -51,11 +58,6 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg) { test_phy_rtc_init(); - ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()..."); - spi_flash_disable_interrupts_caches_and_other_cpu(); - bt_bb_init_cmplx_reg(); - spi_flash_enable_interrupts_caches_and_other_cpu(); - for (int i = 0; i < 2; i++) { ESP_LOGI(TAG, "Test force_wifi_mode(%d)...", i); spi_flash_disable_interrupts_caches_and_other_cpu(); @@ -68,10 +70,17 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg) spi_flash_enable_interrupts_caches_and_other_cpu(); } +#ifdef SOC_BT_SUPPORTED + ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()..."); + spi_flash_disable_interrupts_caches_and_other_cpu(); + bt_bb_init_cmplx_reg(); + spi_flash_enable_interrupts_caches_and_other_cpu(); + ESP_LOGI(TAG, "Test bt_track_pll_cap()..."); spi_flash_disable_interrupts_caches_and_other_cpu(); bt_track_pll_cap(); spi_flash_enable_interrupts_caches_and_other_cpu(); +#endif TEST_ASSERT( xSemaphoreGive(semphr_done) ); diff --git a/components/esp_wifi/test/esp32/test_wifi.c b/components/esp_wifi/test/esp32/test_wifi.c new file mode 100644 index 0000000000..5e601f3222 --- /dev/null +++ b/components/esp_wifi/test/esp32/test_wifi.c @@ -0,0 +1,233 @@ +/* + Tests for the Wi-Fi +*/ +#include "string.h" +#include "esp_system.h" +#include "unity.h" +#include "esp_system.h" +#include "esp_event_loop.h" +#include "esp_wifi.h" +#include "esp_wifi_types.h" +#include "esp_log.h" +#include "nvs_flash.h" +#include "test_utils.h" +#include "freertos/task.h" +#include "freertos/event_groups.h" + +static const char* TAG = "test_wifi"; + +#define DEFAULT_SSID "TEST_SSID" +#define DEFAULT_PWD "TEST_PASS" + +#define GOT_IP_EVENT 0x00000001 +#define DISCONNECT_EVENT 0x00000002 + +#define EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT 0x00000001 + +static uint32_t wifi_event_handler_flag; + +static EventGroupHandle_t wifi_events; + +static esp_err_t event_handler(void *ctx, system_event_t *event) +{ + printf("ev_handle_called.\n"); + switch(event->event_id) { + case SYSTEM_EVENT_STA_START: + ESP_LOGI(TAG, "SYSTEM_EVENT_STA_START"); + //do not actually connect in test case + //; + break; + case SYSTEM_EVENT_STA_GOT_IP: + ESP_LOGI(TAG, "SYSTEM_EVENT_STA_GOT_IP"); + ESP_LOGI(TAG, "got ip:%s\n", + ip4addr_ntoa(&event->event_info.got_ip.ip_info.ip)); + if (wifi_events) { + xEventGroupSetBits(wifi_events, GOT_IP_EVENT); + } + break; + case SYSTEM_EVENT_STA_DISCONNECTED: + ESP_LOGI(TAG, "SYSTEM_EVENT_STA_DISCONNECTED"); + if (! (EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT & wifi_event_handler_flag) ) { + TEST_ESP_OK(esp_wifi_connect()); + } + if (wifi_events) { + xEventGroupSetBits(wifi_events, DISCONNECT_EVENT); + } + break; + default: + break; + } + return ESP_OK; +} + + +static void start_wifi_as_softap(void) +{ + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + cfg.nvs_enable = false; + + wifi_config_t w_config = { + .ap.ssid = DEFAULT_SSID, + .ap.password = DEFAULT_PWD, + .ap.ssid_len = 0, + .ap.channel = 1, + .ap.authmode = WIFI_AUTH_WPA2_PSK, + .ap.ssid_hidden = false, + .ap.max_connection = 4, + .ap.beacon_interval = 100, + }; + + TEST_ESP_OK(esp_event_loop_init(event_handler, NULL)); + + // can't deinit event loop, need to reset leak check + unity_reset_leak_checks(); + + if (wifi_events == NULL) { + wifi_events = xEventGroupCreate(); + } + + TEST_ESP_OK(esp_wifi_init(&cfg)); + TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_AP)); + TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_AP, &w_config)); + TEST_ESP_OK(esp_wifi_start()); +} + +static void start_wifi_as_sta(void) +{ + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + cfg.nvs_enable = false; + + // do not auto connect + wifi_event_handler_flag |= EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT; + TEST_ESP_OK(esp_event_loop_init(event_handler, NULL)); + + // can't deinit event loop, need to reset leak check + unity_reset_leak_checks(); + + if (wifi_events == NULL) { + wifi_events = xEventGroupCreate(); + } else { + xEventGroupClearBits(wifi_events, 0x00ffffff); + } + + TEST_ESP_OK(esp_wifi_init(&cfg)); + TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA)); + TEST_ESP_OK(esp_wifi_start()); + +} + +static void stop_wifi(void) +{ + printf("stop wifi\n"); + TEST_ESP_OK(esp_wifi_stop()); + TEST_ESP_OK(esp_wifi_deinit()); + if (wifi_events) { + vEventGroupDelete(wifi_events); + wifi_events = NULL; + } + vTaskDelay(1000/portTICK_PERIOD_MS); +} + +static void receive_ds2ds_packet(void) +{ + test_case_uses_tcpip(); + start_wifi_as_softap(); + unity_wait_for_signal("sender ready"); + unity_send_signal("receiver ready"); + + // wait for sender to send packets + vTaskDelay(1000/portTICK_PERIOD_MS); + stop_wifi(); +} + +static const char ds2ds_pdu[] = { + 0x48, 0x03, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x60, 0x94, 0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x1C, 0x26, 0xB9, + 0x0D, 0x02, 0x7D, 0x13, 0x00, 0x00, 0x01, 0xE8, 0x65, 0xD4, 0xCB, 0x74, + 0x1C, 0x00, 0x00, 0x26, 0xB9, 0x00, 0x00, 0x00, 0x00 +}; + +static void send_ds2ds_packet(void) +{ + test_case_uses_tcpip(); + start_wifi_as_softap(); + unity_send_signal("sender ready"); + unity_wait_for_signal("receiver ready"); + + // send packet 20 times to make sure receiver will get this packet + for (uint16_t i = 0; i < 20; i++) { + esp_wifi_80211_tx(ESP_IF_WIFI_AP, ds2ds_pdu, sizeof(ds2ds_pdu), true); + vTaskDelay(50 / portTICK_PERIOD_MS); + } + stop_wifi(); +} + +TEST_CASE_MULTIPLE_DEVICES("receive ds2ds packet without exception", "[wifi][test_env=UT_T2_1]", receive_ds2ds_packet, send_ds2ds_packet); + +static void wifi_connect_by_bssid(uint8_t *bssid) +{ + EventBits_t bits; + + wifi_config_t w_config = { + .sta.ssid = DEFAULT_SSID, + .sta.password = DEFAULT_PWD, + .sta.bssid_set = true, + }; + + memcpy(w_config.sta.bssid, bssid, 6); + + TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &w_config)); + TEST_ESP_OK(esp_wifi_connect()); + bits = xEventGroupWaitBits(wifi_events, GOT_IP_EVENT, 1, 0, 5000/portTICK_RATE_MS); + TEST_ASSERT(bits == GOT_IP_EVENT); +} + +static void test_wifi_connection_sta(void) +{ + char mac_str[19]; + uint8_t mac[6]; + EventBits_t bits; + + test_case_uses_tcpip(); + + start_wifi_as_sta(); + + unity_wait_for_signal_param("SoftAP mac", mac_str, 19); + + TEST_ASSERT_TRUE(unity_util_convert_mac_from_string(mac_str, mac)); + + wifi_connect_by_bssid(mac); + + unity_send_signal("STA connected"); + + bits = xEventGroupWaitBits(wifi_events, DISCONNECT_EVENT, 1, 0, 60000 / portTICK_RATE_MS); + // disconnect event not triggered + printf("wait finish\n"); + TEST_ASSERT(bits == 0); + + stop_wifi(); +} + +static void test_wifi_connection_softap(void) +{ + char mac_str[19] = {0}; + uint8_t mac[6]; + + test_case_uses_tcpip(); + + start_wifi_as_softap(); + + TEST_ESP_OK(esp_wifi_get_mac(ESP_IF_WIFI_AP, mac)); + sprintf(mac_str, MACSTR, MAC2STR(mac)); + + unity_send_signal_param("SoftAP mac", mac_str); + + unity_wait_for_signal("STA connected"); + + vTaskDelay(60000 / portTICK_PERIOD_MS); + + stop_wifi(); +} + +TEST_CASE_MULTIPLE_DEVICES("test wifi retain connection for 60s", "[wifi][test_env=UT_T2_1][timeout=90]", test_wifi_connection_sta, test_wifi_connection_softap); \ No newline at end of file diff --git a/components/esp_wifi/test/test_wifi.c b/components/esp_wifi/test/test_wifi.c index 08996d9de3..df6908e398 100644 --- a/components/esp_wifi/test/test_wifi.c +++ b/components/esp_wifi/test/test_wifi.c @@ -110,7 +110,7 @@ TEST_CASE("wifi stop and deinit","[wifi]") .password = DEFAULT_PWD }, }; - + //init nvs ESP_LOGI(TAG, EMPH_STR("nvs_flash_init")); esp_err_t r = nvs_flash_init(); @@ -118,7 +118,7 @@ TEST_CASE("wifi stop and deinit","[wifi]") ESP_LOGI(TAG, EMPH_STR("no free pages or nvs version mismatch, erase..")); TEST_ESP_OK(nvs_flash_erase()); r = nvs_flash_init(); - } + } TEST_ESP_OK(r); //init tcpip ESP_LOGI(TAG, EMPH_STR("tcpip_adapter_init")); @@ -126,7 +126,7 @@ TEST_CASE("wifi stop and deinit","[wifi]") //init event loop ESP_LOGI(TAG, EMPH_STR("esp_event_loop_init")); TEST_ESP_OK(esp_event_loop_init(event_handler, NULL)); - + ESP_LOGI(TAG, "test wifi init & deinit..."); test_wifi_init_deinit(&cfg, &wifi_config); ESP_LOGI(TAG, "wifi init & deinit seem to be OK."); @@ -140,175 +140,4 @@ TEST_CASE("wifi stop and deinit","[wifi]") ESP_LOGI(TAG, "test passed..."); TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of tcpip_adapter and event_loop."); -} - -static void start_wifi_as_softap(void) -{ - wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); - cfg.nvs_enable = false; - - wifi_config_t w_config = { - .ap.ssid = DEFAULT_SSID, - .ap.password = DEFAULT_PWD, - .ap.ssid_len = 0, - .ap.channel = 1, - .ap.authmode = WIFI_AUTH_WPA2_PSK, - .ap.ssid_hidden = false, - .ap.max_connection = 4, - .ap.beacon_interval = 100, - }; - - TEST_ESP_OK(esp_event_loop_init(event_handler, NULL)); - - // can't deinit event loop, need to reset leak check - unity_reset_leak_checks(); - - if (wifi_events == NULL) { - wifi_events = xEventGroupCreate(); - } - - TEST_ESP_OK(esp_wifi_init(&cfg)); - TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_AP)); - TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_AP, &w_config)); - TEST_ESP_OK(esp_wifi_start()); -} - -static void start_wifi_as_sta(void) -{ - wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); - cfg.nvs_enable = false; - - // do not auto connect - wifi_event_handler_flag |= EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT; - TEST_ESP_OK(esp_event_loop_init(event_handler, NULL)); - - // can't deinit event loop, need to reset leak check - unity_reset_leak_checks(); - - if (wifi_events == NULL) { - wifi_events = xEventGroupCreate(); - } else { - xEventGroupClearBits(wifi_events, 0x00ffffff); - } - - TEST_ESP_OK(esp_wifi_init(&cfg)); - TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA)); - TEST_ESP_OK(esp_wifi_start()); - -} - -static void stop_wifi(void) -{ - printf("stop wifi\n"); - TEST_ESP_OK(esp_wifi_stop()); - TEST_ESP_OK(esp_wifi_deinit()); - if (wifi_events) { - vEventGroupDelete(wifi_events); - wifi_events = NULL; - } - vTaskDelay(1000/portTICK_PERIOD_MS); -} - -static void receive_ds2ds_packet(void) -{ - test_case_uses_tcpip(); - start_wifi_as_softap(); - unity_wait_for_signal("sender ready"); - unity_send_signal("receiver ready"); - - // wait for sender to send packets - vTaskDelay(1000/portTICK_PERIOD_MS); - stop_wifi(); -} - -static const char ds2ds_pdu[] = { - 0x48, 0x03, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0x60, 0x94, 0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x1C, 0x26, 0xB9, - 0x0D, 0x02, 0x7D, 0x13, 0x00, 0x00, 0x01, 0xE8, 0x65, 0xD4, 0xCB, 0x74, - 0x1C, 0x00, 0x00, 0x26, 0xB9, 0x00, 0x00, 0x00, 0x00 -}; - -static void send_ds2ds_packet(void) -{ - test_case_uses_tcpip(); - start_wifi_as_softap(); - unity_send_signal("sender ready"); - unity_wait_for_signal("receiver ready"); - - // send packet 20 times to make sure receiver will get this packet - for (uint16_t i = 0; i < 20; i++) { - esp_wifi_80211_tx(ESP_IF_WIFI_AP, ds2ds_pdu, sizeof(ds2ds_pdu), true); - vTaskDelay(50 / portTICK_PERIOD_MS); - } - stop_wifi(); -} - -TEST_CASE_MULTIPLE_DEVICES("receive ds2ds packet without exception", "[wifi][test_env=UT_T2_1]", receive_ds2ds_packet, send_ds2ds_packet); - -static void wifi_connect_by_bssid(uint8_t *bssid) -{ - EventBits_t bits; - - wifi_config_t w_config = { - .sta.ssid = DEFAULT_SSID, - .sta.password = DEFAULT_PWD, - .sta.bssid_set = true, - }; - - memcpy(w_config.sta.bssid, bssid, 6); - - TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &w_config)); - TEST_ESP_OK(esp_wifi_connect()); - bits = xEventGroupWaitBits(wifi_events, GOT_IP_EVENT, 1, 0, 5000/portTICK_RATE_MS); - TEST_ASSERT(bits == GOT_IP_EVENT); -} - -static void test_wifi_connection_sta(void) -{ - char mac_str[19]; - uint8_t mac[6]; - EventBits_t bits; - - test_case_uses_tcpip(); - - start_wifi_as_sta(); - - unity_wait_for_signal_param("SoftAP mac", mac_str, 19); - - TEST_ASSERT_TRUE(unity_util_convert_mac_from_string(mac_str, mac)); - - wifi_connect_by_bssid(mac); - - unity_send_signal("STA connected"); - - bits = xEventGroupWaitBits(wifi_events, DISCONNECT_EVENT, 1, 0, 60000 / portTICK_RATE_MS); - // disconnect event not triggered - printf("wait finish\n"); - TEST_ASSERT(bits == 0); - - stop_wifi(); -} - -static void test_wifi_connection_softap(void) -{ - char mac_str[19] = {0}; - uint8_t mac[6]; - - test_case_uses_tcpip(); - - start_wifi_as_softap(); - - TEST_ESP_OK(esp_wifi_get_mac(ESP_IF_WIFI_AP, mac)); - sprintf(mac_str, MACSTR, MAC2STR(mac)); - - unity_send_signal_param("SoftAP mac", mac_str); - - unity_wait_for_signal("STA connected"); - - vTaskDelay(60000 / portTICK_PERIOD_MS); - - stop_wifi(); -} - -TEST_CASE_MULTIPLE_DEVICES("test wifi retain connection for 60s", "[wifi][test_env=UT_T2_1][timeout=90]", test_wifi_connection_sta, test_wifi_connection_softap); +} \ No newline at end of file diff --git a/components/fatfs/CMakeLists.txt b/components/fatfs/CMakeLists.txt index 2cd91bf005..b5f3af8de5 100644 --- a/components/fatfs/CMakeLists.txt +++ b/components/fatfs/CMakeLists.txt @@ -1,12 +1,18 @@ -idf_component_register(SRCS "diskio/diskio.c" - "diskio/diskio_rawflash.c" - "diskio/diskio_sdmmc.c" - "diskio/diskio_wl.c" - "src/ff.c" - "port/freertos/ffsystem.c" - "src/ffunicode.c" - "vfs/vfs_fat.c" - "vfs/vfs_fat_sdmmc.c" - "vfs/vfs_fat_spiflash.c" - INCLUDE_DIRS diskio vfs src - REQUIRES wear_levelling sdmmc) +set(srcs "diskio/diskio.c" + "diskio/diskio_rawflash.c" + "diskio/diskio_sdmmc.c" + "diskio/diskio_wl.c" + "src/ff.c" + "port/freertos/ffsystem.c" + "src/ffunicode.c" + "vfs/vfs_fat.c" + "vfs/vfs_fat_spiflash.c") + +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcs "vfs/vfs_fat_sdmmc.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS diskio vfs src + REQUIRES wear_levelling sdmmc + ) diff --git a/components/fatfs/test/CMakeLists.txt b/components/fatfs/test/CMakeLists.txt index 2796e95eb4..c3596a0f4c 100644 --- a/components/fatfs/test/CMakeLists.txt +++ b/components/fatfs/test/CMakeLists.txt @@ -1,4 +1,10 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - REQUIRES unity test_utils vfs fatfs - EMBED_TXTFILES fatfs.img) \ No newline at end of file +set(srcdirs ".") +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcdirs "esp32") +endif() + +idf_component_register(SRC_DIRS ${src_dirs} + INCLUDE_DIRS . + REQUIRES unity test_utils vfs fatfs + EMBED_TXTFILES fatfs.img + ) \ No newline at end of file diff --git a/components/fatfs/test/component.mk b/components/fatfs/test/component.mk index c7e0582205..4278d928c1 100644 --- a/components/fatfs/test/component.mk +++ b/components/fatfs/test/component.mk @@ -1,2 +1,3 @@ COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_EMBED_TXTFILES := fatfs.img +COMPONENT_SRCDIRS += esp32 diff --git a/components/fatfs/test/test_fatfs_sdmmc.c b/components/fatfs/test/esp32/test_fatfs_sdmmc.c similarity index 99% rename from components/fatfs/test/test_fatfs_sdmmc.c rename to components/fatfs/test/esp32/test_fatfs_sdmmc.c index 50e1eb5a08..d1d5e369fc 100644 --- a/components/fatfs/test/test_fatfs_sdmmc.c +++ b/components/fatfs/test/esp32/test_fatfs_sdmmc.c @@ -29,7 +29,7 @@ #include "driver/sdmmc_defs.h" #include "sdmmc_cmd.h" #include "ff.h" -#include "test_fatfs_common.h" +#include "../test_fatfs_common.h" static void test_setup(void) diff --git a/components/fatfs/vfs/esp_vfs_fat.h b/components/fatfs/vfs/esp_vfs_fat.h index d3f9caa688..b7b2ee78b5 100644 --- a/components/fatfs/vfs/esp_vfs_fat.h +++ b/components/fatfs/vfs/esp_vfs_fat.h @@ -17,7 +17,6 @@ #include "esp_err.h" #include "driver/gpio.h" #include "driver/sdmmc_types.h" -#include "driver/sdmmc_host.h" #include "driver/sdspi_host.h" #include "ff.h" #include "wear_levelling.h" diff --git a/components/freertos/include/freertos/portmacro.h b/components/freertos/include/freertos/portmacro.h index 4b187f7193..010f60f250 100644 --- a/components/freertos/include/freertos/portmacro.h +++ b/components/freertos/include/freertos/portmacro.h @@ -353,13 +353,29 @@ static inline unsigned portENTER_CRITICAL_NESTED(void) { * ESP32 (portMUX assertions would fail). */ static inline void uxPortCompareSet(volatile uint32_t *addr, uint32_t compare, uint32_t *set) { -#ifndef CONFIG_FREERTOS_UNICORE +#if XCHAL_HAVE_S32C1I __asm__ __volatile__ ( "WSR %2,SCOMPARE1 \n" "S32C1I %0, %1, 0 \n" :"=r"(*set) :"r"(addr), "r"(compare), "0"(*set) ); +#else + // No S32C1I, so do this by disabling and re-enabling interrupts (slower) + uint32_t intlevel, old_value; + __asm__ __volatile__ ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) "\n" + : "=r"(intlevel)); + + old_value = *addr; + if (old_value == compare) { + *addr = *set; + } + + __asm__ __volatile__ ("memw \n" + "wsr %0, ps\n" + :: "r"(intlevel)); + + *set = old_value; #endif } diff --git a/components/freertos/portmux_impl.h b/components/freertos/portmux_impl.h index 541973167a..af170bb3ea 100644 --- a/components/freertos/portmux_impl.h +++ b/components/freertos/portmux_impl.h @@ -91,16 +91,21 @@ static inline bool __attribute__((always_inline)) vPortCPUAcquireMutexIntsDisabled(PORTMUX_AQUIRE_MUX_FN_ARGS) { +#if !defined(CONFIG_FREERTOS_UNICORE) #if defined(CONFIG_SPIRAM) if (esp_ptr_external_ram(mux)) { return vPortCPUAcquireMutexIntsDisabledExtram(PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(mux)); } #endif return vPortCPUAcquireMutexIntsDisabledInternal(PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(mux)); +#else + return true; +#endif } static inline void vPortCPUReleaseMutexIntsDisabled(PORTMUX_RELEASE_MUX_FN_ARGS) { +#if !defined(CONFIG_FREERTOS_UNICORE) #if defined(CONFIG_SPIRAM) if (esp_ptr_external_ram(mux)) { vPortCPUReleaseMutexIntsDisabledExtram(PORTMUX_RELEASE_MUX_FN_CALL_ARGS(mux)); @@ -108,5 +113,6 @@ static inline void vPortCPUReleaseMutexIntsDisabled(PORTMUX_RELEASE_MUX_FN_ARGS) } #endif vPortCPUReleaseMutexIntsDisabledInternal(PORTMUX_RELEASE_MUX_FN_CALL_ARGS(mux)); +#endif } diff --git a/components/freertos/test/CMakeLists.txt b/components/freertos/test/CMakeLists.txt index b531a14504..8f40b2df02 100644 --- a/components/freertos/test/CMakeLists.txt +++ b/components/freertos/test/CMakeLists.txt @@ -1,3 +1,11 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - REQUIRES unity test_utils) \ No newline at end of file +set(srcdirs .) + +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcdirs esp32) +endif() + + +idf_component_register(SRC_DIRS ${src_dirs} + INCLUDE_DIRS . + REQUIRES unity test_utils + ) \ No newline at end of file diff --git a/components/freertos/test/component.mk b/components/freertos/test/component.mk index 5dd172bdb7..b2b7d9048f 100644 --- a/components/freertos/test/component.mk +++ b/components/freertos/test/component.mk @@ -2,4 +2,5 @@ #Component Makefile # +COMPONENT_SRCDIRS += esp32 COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive diff --git a/components/freertos/test/test_freertos_task_delay_until.c b/components/freertos/test/esp32/test_freertos_task_delay_until.c similarity index 95% rename from components/freertos/test/test_freertos_task_delay_until.c rename to components/freertos/test/esp32/test_freertos_task_delay_until.c index c725bf22c3..b4cc7d5d6c 100644 --- a/components/freertos/test/test_freertos_task_delay_until.c +++ b/components/freertos/test/esp32/test_freertos_task_delay_until.c @@ -27,10 +27,6 @@ static SemaphoreHandle_t task_delete_semphr; -#if CONFIG_IDF_TARGET_ESP32S2BETA -#warning "Test not ported to esp32s2beta" -#else - static void delaying_task(void* arg) { uint64_t ref_prev, ref_current; @@ -76,5 +72,3 @@ TEST_CASE("Test vTaskDelayUntil", "[freertos]") vSemaphoreDelete(task_delete_semphr); ref_clock_deinit(); } - -#endif // CONFIG_IDF_TARGET_ESP32S2BETA diff --git a/components/heap/test/test_leak.c b/components/heap/test/test_leak.c index 6fce4e6ffd..1153fe1bc9 100644 --- a/components/heap/test/test_leak.c +++ b/components/heap/test/test_leak.c @@ -57,4 +57,4 @@ static void test_fn3(void) check_calloc(7000); } -TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (manual reset)", "[heap][leaks][reset=SW_CPU_RESET, SW_CPU_RESET]", test_fn2, test_fn2, test_fn3); +TEST_CASE_MULTIPLE_STAGES_ESP32("Check for leaks in MULTIPLE_STAGES mode (manual reset)", "[heap][leaks][reset=SW_CPU_RESET, SW_CPU_RESET]", test_fn2, test_fn2, test_fn3); diff --git a/components/heap/test/test_malloc.c b/components/heap/test/test_malloc.c index 42f73cfe70..cfc634bada 100644 --- a/components/heap/test/test_malloc.c +++ b/components/heap/test/test_malloc.c @@ -4,7 +4,6 @@ #include #include -#include "esp32/rom/ets_sys.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" diff --git a/components/heap/test/test_malloc_caps.c b/components/heap/test/test_malloc_caps.c index 74c8084771..9fdbec5716 100644 --- a/components/heap/test/test_malloc_caps.c +++ b/components/heap/test/test_malloc_caps.c @@ -11,7 +11,7 @@ #include #include -TEST_CASE("Capabilities allocator test", "[heap]") +TEST_CASE_ESP32("Capabilities allocator test", "[heap]") { char *m1, *m2[10]; int x; diff --git a/components/heap/test/test_realloc.c b/components/heap/test/test_realloc.c index 290ee3da6e..6781c2af3f 100644 --- a/components/heap/test/test_realloc.c +++ b/components/heap/test/test_realloc.c @@ -22,7 +22,7 @@ TEST_CASE("realloc shrink buffer in place", "[heap]") #endif -TEST_CASE("realloc move data to a new heap type", "[heap]") +TEST_CASE_ESP32("realloc move data to a new heap type", "[heap]") { const char *test = "I am some test content to put in the heap"; char buf[64]; diff --git a/components/libsodium/test/test_sodium.c b/components/libsodium/test/test_sodium.c index f7f37d509f..ffbc1d1acd 100644 --- a/components/libsodium/test/test_sodium.c +++ b/components/libsodium/test/test_sodium.c @@ -39,7 +39,7 @@ TEST_CASE("box tests", "[libsodium]") extern int ed25519_convert_xmain(void); -TEST_CASE("ed25519_convert tests", "[libsodium][timeout=60]") +TEST_CASE_ESP32("ed25519_convert tests", "[libsodium][timeout=60]") { printf("Running ed25519_convert\n"); TEST_ASSERT_EQUAL(0, ed25519_convert_xmain() ); diff --git a/components/lwip/weekend_test/net_suite_test.py b/components/lwip/weekend_test/net_suite_test.py index ce6340a2da..59e763b44c 100644 --- a/components/lwip/weekend_test/net_suite_test.py +++ b/components/lwip/weekend_test/net_suite_test.py @@ -9,6 +9,7 @@ from shutil import copyfile try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -83,7 +84,7 @@ def lwip_test_suite(env, extra_data): 3. Execute ttcn3 test suite 4. Collect result from ttcn3 """ - dut1 = env.get_dut("net_suite", "examples/system/network_tests") + dut1 = env.get_dut("net_suite", "examples/system/network_tests", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "net_suite.bin") bin_size = os.path.getsize(binary_file) diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt index b69d59b9ef..0c4c263fef 100644 --- a/components/mbedtls/CMakeLists.txt +++ b/components/mbedtls/CMakeLists.txt @@ -41,5 +41,7 @@ foreach(target ${mbedtls_targets}) target_compile_definitions(${target} PUBLIC -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h") endforeach() +set_property(TARGET mbedcrypto APPEND PROPERTY LINK_INTERFACE_LIBRARIES mbedtls) + # Link mbedtls libraries to component library -target_link_libraries(${COMPONENT_LIB} INTERFACE ${mbedtls_targets}) +target_link_libraries(${COMPONENT_LIB} INTERFACE ${mbedtls_targets}) \ No newline at end of file diff --git a/components/mbedtls/port/esp32s2beta/esp_bignum.c b/components/mbedtls/port/esp32s2beta/esp_bignum.c index 4bad12ccdb..5c74fbc16c 100644 --- a/components/mbedtls/port/esp32s2beta/esp_bignum.c +++ b/components/mbedtls/port/esp32s2beta/esp_bignum.c @@ -61,7 +61,7 @@ static IRAM_ATTR void rsa_complete_isr(void *arg) } } -static void rsa_isr_initialise() +static void rsa_isr_initialise(void) { if (op_complete_sem == NULL) { op_complete_sem = xSemaphoreCreateBinary(); diff --git a/components/mbedtls/test/test_ecp.c b/components/mbedtls/test/test_ecp.c index 0c8f571db1..e6f5602a60 100644 --- a/components/mbedtls/test/test_ecp.c +++ b/components/mbedtls/test/test_ecp.c @@ -21,7 +21,7 @@ error hex value (mbedTLS uses -N for error codes) */ #define TEST_ASSERT_MBEDTLS_OK(X) TEST_ASSERT_EQUAL_HEX32(0, -(X)) -TEST_CASE("mbedtls ECDH Generate Key", "[mbedtls]") +TEST_CASE_ESP32("mbedtls ECDH Generate Key", "[mbedtls]") { mbedtls_ecdh_context ctx; mbedtls_entropy_context entropy; @@ -48,7 +48,7 @@ TEST_CASE("mbedtls ECP self-tests", "[mbedtls]") TEST_ASSERT_EQUAL(0, mbedtls_ecp_self_test(1)); } -TEST_CASE("mbedtls ECP mul w/ koblitz", "[mbedtls]") +TEST_CASE_ESP32("mbedtls ECP mul w/ koblitz", "[mbedtls]") { /* Test case code via https://github.com/espressif/esp-idf/issues/1556 */ mbedtls_entropy_context ctxEntropy; diff --git a/components/mbedtls/test/test_mbedtls_mpi.c b/components/mbedtls/test/test_mbedtls_mpi.c index 084fe34845..056a1cf14d 100644 --- a/components/mbedtls/test/test_mbedtls_mpi.c +++ b/components/mbedtls/test/test_mbedtls_mpi.c @@ -143,7 +143,7 @@ static bool test_bignum_modexp(const char *z_str, const char *x_str, const char if (ret_error != mbedtls_mpi_exp_mod(&Z, &X, &Y, &M, NULL)) { fail = true; } - + if (ret_error == MBEDTLS_OK) { mbedtls_mpi_write_string(&Z, 16, z_buf, sizeof(z_buf)-1, &z_buf_len); if (memcmp(z_str, z_buf, strlen(z_str)) != 0) { @@ -165,7 +165,7 @@ static bool test_bignum_modexp(const char *z_str, const char *x_str, const char return fail; } -TEST_CASE("test MPI modexp", "[bignum]") +TEST_CASE_ESP32("test MPI modexp", "[bignum]") { bool test_error = false; printf("Z = (X ^ Y) mod M \n"); diff --git a/components/mbedtls/test/test_mbedtls_sha.c b/components/mbedtls/test/test_mbedtls_sha.c index 7b94e52cf7..8c12b6616b 100644 --- a/components/mbedtls/test/test_mbedtls_sha.c +++ b/components/mbedtls/test/test_mbedtls_sha.c @@ -15,7 +15,7 @@ #include "sdkconfig.h" #include "test_apb_dport_access.h" -TEST_CASE("mbedtls SHA self-tests", "[mbedtls]") +TEST_CASE_ESP32("mbedtls SHA self-tests", "[mbedtls]") { start_apb_access_loop(); TEST_ASSERT_FALSE_MESSAGE(mbedtls_sha1_self_test(1), "SHA1 self-tests should pass."); @@ -121,7 +121,7 @@ static void tskRunSHA256Test(void *pvParameters) #define SHA_TASK_STACK_SIZE (10*1024) -TEST_CASE("mbedtls SHA multithreading", "[mbedtls]") +TEST_CASE_ESP32("mbedtls SHA multithreading", "[mbedtls]") { done_sem = xSemaphoreCreateCounting(4, 0); xTaskCreate(tskRunSHA1Test, "SHA1Task1", SHA_TASK_STACK_SIZE, NULL, 3, NULL); @@ -164,7 +164,7 @@ void tskRunSHASelftests(void *param) vTaskDelete(NULL); } -TEST_CASE("mbedtls SHA self-tests multithreaded", "[mbedtls]") +TEST_CASE_ESP32("mbedtls SHA self-tests multithreaded", "[mbedtls]") { done_sem = xSemaphoreCreateCounting(2, 0); xTaskCreate(tskRunSHASelftests, "SHASelftests1", SHA_TASK_STACK_SIZE, NULL, 3, NULL); @@ -180,7 +180,7 @@ TEST_CASE("mbedtls SHA self-tests multithreaded", "[mbedtls]") vSemaphoreDelete(done_sem); } -TEST_CASE("mbedtls SHA512 clone", "[mbedtls]") +TEST_CASE_ESP32("mbedtls SHA512 clone", "[mbedtls]") { mbedtls_sha512_context ctx; mbedtls_sha512_context clone; @@ -205,7 +205,7 @@ TEST_CASE("mbedtls SHA512 clone", "[mbedtls]") TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha512_thousand_bs, sha512, 64, "SHA512 cloned calculation"); } -TEST_CASE("mbedtls SHA384 clone", "[mbedtls]") +TEST_CASE_ESP32("mbedtls SHA384 clone", "[mbedtls]") { mbedtls_sha512_context ctx; mbedtls_sha512_context clone; @@ -231,7 +231,7 @@ TEST_CASE("mbedtls SHA384 clone", "[mbedtls]") } -TEST_CASE("mbedtls SHA256 clone", "[mbedtls]") +TEST_CASE_ESP32("mbedtls SHA256 clone", "[mbedtls]") { mbedtls_sha256_context ctx; mbedtls_sha256_context clone; @@ -276,7 +276,7 @@ static void tskFinaliseSha(void *v_param) vTaskDelete(NULL); } -TEST_CASE("mbedtls SHA session passed between tasks" , "[mbedtls]") +TEST_CASE_ESP32("mbedtls SHA session passed between tasks" , "[mbedtls]") { finalise_sha_param_t param = { 0 }; diff --git a/components/mqtt/weekend_test/mqtt_publish_test.py b/components/mqtt/weekend_test/mqtt_publish_test.py index 9263f3ada7..f3d081b4cf 100644 --- a/components/mqtt/weekend_test/mqtt_publish_test.py +++ b/components/mqtt/weekend_test/mqtt_publish_test.py @@ -13,6 +13,7 @@ import random try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -138,7 +139,7 @@ def test_weekend_mqtt_publish(env, extra_data): 3. Test evaluates python client received correct qos0 message 4. Test ESP32 client received correct qos0 message """ - dut1 = env.get_dut("mqtt_publish", "examples/protocols/mqtt/publish_test") + dut1 = env.get_dut("mqtt_publish", "examples/protocols/mqtt/publish_test", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "mqtt_publish.bin") bin_size = os.path.getsize(binary_file) diff --git a/components/newlib/test/test_time.c b/components/newlib/test/test_time.c index 92f1bf8999..cca57d924f 100644 --- a/components/newlib/test/test_time.c +++ b/components/newlib/test/test_time.c @@ -9,7 +9,6 @@ #include "freertos/semphr.h" #include "sdkconfig.h" #include "soc/rtc.h" -#include "esp32/clk.h" #include "esp_system.h" #include "test_utils.h" @@ -223,16 +222,26 @@ static void get_time_task(void *pvParameters) static void start_measure(int64_t* sys_time, int64_t* real_time) { struct timeval tv_time; - *real_time = esp_timer_get_time(); - gettimeofday(&tv_time, NULL); + int64_t t1, t2; + do { + t1 = esp_timer_get_time(); + gettimeofday(&tv_time, NULL); + t2 = esp_timer_get_time(); + } while (t2 - t1 > 40); + *real_time = t2; *sys_time = (int64_t)tv_time.tv_sec * 1000000L + tv_time.tv_usec; } static void end_measure(int64_t* sys_time, int64_t* real_time) { struct timeval tv_time; - gettimeofday(&tv_time, NULL); - *real_time = esp_timer_get_time(); + int64_t t1, t2; + do { + t1 = esp_timer_get_time(); + gettimeofday(&tv_time, NULL); + t2 = esp_timer_get_time(); + } while (t2 - t1 > 40); + *real_time = t2; *sys_time = (int64_t)tv_time.tv_sec * 1000000L + tv_time.tv_usec; } @@ -253,51 +262,55 @@ static int64_t calc_correction(const char* tag, int64_t* sys_time, int64_t* real static void measure_time_task(void *pvParameters) { - struct timeval tv_time; - int64_t real_time_us[2]; - int64_t sys_time_us[2]; - int64_t delay_us = 2 * 1000000; // 2 sec xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters; + int64_t main_real_time_us[2]; + int64_t main_sys_time_us[2]; + struct timeval tv_time = {.tv_sec = 1550000000, .tv_usec = 0}; + TEST_ASSERT_EQUAL(0, settimeofday(&tv_time, NULL)); + struct timeval delta = {.tv_sec = 2000, .tv_usec = 900000}; + adjtime(&delta, NULL); gettimeofday(&tv_time, NULL); - start_measure(&sys_time_us[0], &real_time_us[0]); - // although exit flag is set in another task, checking (exit_flag == false) is safe - while (exit_flag == false) { - ets_delay_us(delay_us); + start_measure(&main_sys_time_us[0], &main_real_time_us[0]); - end_measure(&sys_time_us[1], &real_time_us[1]); - result_adjtime_correction_us[1] += calc_correction("measure", sys_time_us, real_time_us); + { + int64_t real_time_us[2]; + int64_t sys_time_us[2]; + int64_t delay_us = 2 * 1000000; // 2 sec + start_measure(&sys_time_us[0], &real_time_us[0]); + // although exit flag is set in another task, checking (exit_flag == false) is safe + while (exit_flag == false) { + ets_delay_us(delay_us); - sys_time_us[0] = sys_time_us[1]; - real_time_us[0] = real_time_us[1]; + end_measure(&sys_time_us[1], &real_time_us[1]); + result_adjtime_correction_us[1] += calc_correction("measure", sys_time_us, real_time_us); + + sys_time_us[0] = sys_time_us[1]; + real_time_us[0] = real_time_us[1]; + } } + + end_measure(&main_sys_time_us[1], &main_real_time_us[1]); + result_adjtime_correction_us[0] = calc_correction("main", main_sys_time_us, main_real_time_us); + int64_t delta_us = result_adjtime_correction_us[0] - result_adjtime_correction_us[1]; + printf("\nresult of adjtime correction: %lli us, %lli us. delta = %lli us\n", result_adjtime_correction_us[0], result_adjtime_correction_us[1], delta_us); + TEST_ASSERT_INT_WITHIN(100, 0, delta_us); + xSemaphoreGive(*sema); vTaskDelete(NULL); } TEST_CASE("test time adjustment happens linearly", "[newlib][timeout=35]") { - int64_t real_time_us[2]; - int64_t sys_time_us[2]; - exit_flag = false; - struct timeval tv_time = {.tv_sec = 1550000000, .tv_usec = 0}; - TEST_ASSERT_EQUAL(0, settimeofday(&tv_time, NULL)); - - struct timeval delta = {.tv_sec = 2000, .tv_usec = 900000}; - adjtime(&delta, NULL); - gettimeofday(&tv_time, NULL); - xSemaphoreHandle exit_sema[2]; for (int i = 0; i < 2; ++i) { exit_sema[i] = xSemaphoreCreateBinary(); result_adjtime_correction_us[i] = 0; } - start_measure(&sys_time_us[0], &real_time_us[0]); - - xTaskCreatePinnedToCore(get_time_task, "get_time_task", 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, NULL, 0); - xTaskCreatePinnedToCore(measure_time_task, "measure_time_task", 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, NULL, 1); + xTaskCreatePinnedToCore(get_time_task, "get_time_task", 4096, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, NULL, 0); + xTaskCreatePinnedToCore(measure_time_task, "measure_time_task", 4096, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, NULL, 1); printf("start waiting for 30 seconds\n"); vTaskDelay(30000 / portTICK_PERIOD_MS); @@ -311,13 +324,6 @@ TEST_CASE("test time adjustment happens linearly", "[newlib][timeout=35]") } } - end_measure(&sys_time_us[1], &real_time_us[1]); - result_adjtime_correction_us[0] = calc_correction("main", sys_time_us, real_time_us); - - int64_t delta_us = result_adjtime_correction_us[0] - result_adjtime_correction_us[1]; - printf("\nresult of adjtime correction: %lli us, %lli us. delta = %lli us\n", result_adjtime_correction_us[0], result_adjtime_correction_us[1], delta_us); - TEST_ASSERT_INT_WITHIN(100, 0, delta_us); - for (int i = 0; i < 2; ++i) { vSemaphoreDelete(exit_sema[i]); } @@ -424,7 +430,7 @@ void test_posix_timers_clock (void) #endif // defined( WITH_FRC ) || defined( WITH_RTC ) } -TEST_CASE("test posix_timers clock_... functions", "[newlib]") +TEST_CASE_ESP32("test posix_timers clock_... functions", "[newlib]") { test_posix_timers_clock(); } diff --git a/components/protocomm/test/test_protocomm.c b/components/protocomm/test/test_protocomm.c index 33d547b3d5..1523ddf405 100644 --- a/components/protocomm/test/test_protocomm.c +++ b/components/protocomm/test/test_protocomm.c @@ -1098,7 +1098,7 @@ static esp_err_t test_security0 (void) return ESP_OK; } -TEST_CASE("leak test", "[PROTOCOMM]") +TEST_CASE_ESP32("leak test", "[PROTOCOMM]") { #ifdef CONFIG_HEAP_TRACING heap_trace_init_standalone(trace_record, NUM_RECORDS); @@ -1144,17 +1144,17 @@ TEST_CASE("security 0 basic test", "[PROTOCOMM]") TEST_ASSERT(test_security0() == ESP_OK); } -TEST_CASE("security 1 basic test", "[PROTOCOMM]") +TEST_CASE_ESP32("security 1 basic test", "[PROTOCOMM]") { TEST_ASSERT(test_security1() == ESP_OK); } -TEST_CASE("security 1 no encryption test", "[PROTOCOMM]") +TEST_CASE_ESP32("security 1 no encryption test", "[PROTOCOMM]") { TEST_ASSERT(test_security1_no_encryption() == ESP_OK); } -TEST_CASE("security 1 session overflow test", "[PROTOCOMM]") +TEST_CASE_ESP32("security 1 session overflow test", "[PROTOCOMM]") { TEST_ASSERT(test_security1_session_overflow() == ESP_OK); } @@ -1164,12 +1164,12 @@ TEST_CASE("security 1 wrong pop test", "[PROTOCOMM]") TEST_ASSERT(test_security1_wrong_pop() == ESP_OK); } -TEST_CASE("security 1 insecure client test", "[PROTOCOMM]") +TEST_CASE_ESP32("security 1 insecure client test", "[PROTOCOMM]") { TEST_ASSERT(test_security1_insecure_client() == ESP_OK); } -TEST_CASE("security 1 weak session test", "[PROTOCOMM]") +TEST_CASE_ESP32("security 1 weak session test", "[PROTOCOMM]") { TEST_ASSERT(test_security1_weak_session() == ESP_OK); } diff --git a/components/sdmmc/test/CMakeLists.txt b/components/sdmmc/test/CMakeLists.txt index c7c2d52a9b..43d6f24a50 100644 --- a/components/sdmmc/test/CMakeLists.txt +++ b/components/sdmmc/test/CMakeLists.txt @@ -1,3 +1,5 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - REQUIRES unity sdmmc) \ No newline at end of file +if(IDF_TARGET STREQUAL "esp32") + idf_component_register(SRC_DIRS "." + INCLUDE_DIRS "." + REQUIRES unity sdmmc) +endif() \ No newline at end of file diff --git a/components/sdmmc/test/test_sdio.c b/components/sdmmc/test/test_sdio.c index 0e5be1d6fd..3622932dca 100644 --- a/components/sdmmc/test/test_sdio.c +++ b/components/sdmmc/test/test_sdio.c @@ -40,7 +40,6 @@ /* TODO: add SDIO slave header files, remove these definitions */ -#define DR_REG_SLC_BASE 0x3ff58000 #define DR_REG_SLC_MASK 0xfffffc00 #define SLCCONF1 (DR_REG_SLC_BASE + 0x60) @@ -52,7 +51,6 @@ #define SLC_SLC0_TXLINK_RESTART (BIT(30)) #define SLC_SLC0_TXLINK_START (BIT(29)) -#define DR_REG_SLCHOST_BASE 0x3ff55000 #define DR_REG_SLCHOST_MASK 0xfffffc00 #define SLCHOST_STATE_W0 (DR_REG_SLCHOST_BASE + 0x64) #define SLCHOST_CONF_W0 (DR_REG_SLCHOST_BASE + 0x6C) diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 2965d8a9ee..83c0dbb931 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -20,7 +20,7 @@ list(APPEND srcs ) # TODO: SPI Flash HAL for ESP32S2Beta also -if(CONFIG_IDF_TARGET_ESP32) +if(IDF_TARGET STREQUAL "esp32") list(APPEND srcs "src/hal/spi_flash_hal.c" "src/hal/spi_flash_hal_iram.c" ) diff --git a/components/soc/esp32/include/hal/spi_ll.h b/components/soc/esp32/include/hal/spi_ll.h index b66bc1baaf..aaa4fa7aba 100644 --- a/components/soc/esp32/include/hal/spi_ll.h +++ b/components/soc/esp32/include/hal/spi_ll.h @@ -36,6 +36,8 @@ /// Swap the bit order to its correct place to send #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len)) +#define SPI_LL_GET_HW(ID) ((ID)==0? &SPI1:((ID)==1? &SPI2 : &SPI3)) + /** * The data structure holding calculated clock configuration. Since the * calculation needs long time, it should be calculated during initialization and diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h new file mode 100644 index 0000000000..224c2657d3 --- /dev/null +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -0,0 +1,8 @@ +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// seperate these information into periph_caps.h for each peripheral and +// include them here. + +#define SOC_MCPWM_SUPPORTED 1 +#define SOC_SDMMC_HOST_SUPPORTED 1 +#define SOC_BT_SUPPORTED 1 \ No newline at end of file diff --git a/components/soc/esp32/soc_memory_layout.c b/components/soc/esp32/soc_memory_layout.c index 3070e86bbd..d8ba94d905 100644 --- a/components/soc/esp32/soc_memory_layout.c +++ b/components/soc/esp32/soc_memory_layout.c @@ -68,6 +68,13 @@ const soc_memory_type_desc_t soc_memory_types[] = { const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t); +#if CONFIG_SPIRAM_SIZE == -1 +// Assume we need to reserve 4MB in the auto-detection case +#define RESERVE_SPIRAM_SIZE (4*1024*1024) +#else +#define RESERVE_SPIRAM_SIZE CONFIG_SPIRAM_SIZE +#endif + /* Region descriptors. These describe all regions of memory available, and map them to a type in the above type. @@ -76,7 +83,7 @@ from low to high start address. */ const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM - { SOC_EXTRAM_DATA_LOW, CONFIG_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available + { SOC_EXTRAM_DATA_LOW, RESERVE_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available #endif { 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code { 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory @@ -167,7 +174,7 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me #endif #ifdef CONFIG_SPIRAM -SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now +SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + RESERVE_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now #endif #endif /* BOOTLOADER_BUILD */ diff --git a/components/soc/esp32s2beta/include/hal/spi_ll.h b/components/soc/esp32s2beta/include/hal/spi_ll.h index c6c11e215e..70b0c170ad 100644 --- a/components/soc/esp32s2beta/include/hal/spi_ll.h +++ b/components/soc/esp32s2beta/include/hal/spi_ll.h @@ -36,6 +36,8 @@ /// Swap the bit order to its correct place to send #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len)) +#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : ((ID)==2? &GPSPI3: &GPSPI4))) + /** * The data structure holding calculated clock configuration. Since the * calculation needs long time, it should be calculated during initialization and diff --git a/components/soc/esp32s2beta/include/soc/mcpwm_reg.h b/components/soc/esp32s2beta/include/soc/mcpwm_reg.h deleted file mode 100644 index 1dce94d469..0000000000 --- a/components/soc/esp32s2beta/include/soc/mcpwm_reg.h +++ /dev/null @@ -1,3028 +0,0 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_MCPWM_REG_H_ -#define _SOC_MCPWM_REG_H_ -#include "soc.h" - -#define REG_MCPWM_BASE(i) (DR_REG_PWM_BASE + i * (0xE000)) -#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) -/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ -#define MCPWM_CLK_PRESCALE 0x000000FF -#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S)) -#define MCPWM_CLK_PRESCALE_V 0xFF -#define MCPWM_CLK_PRESCALE_S 0 - -#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0004) -/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: Update method for active reg of PWM timer0 period 0: immediate - 1: TEZ 2: sync 3: TEZ or sync. TEZ here and below means timer equal zero event*/ -#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: Period shadow reg of PWM timer0*/ -#define MCPWM_TIMER0_PERIOD 0x0000FFFF -#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S)) -#define MCPWM_TIMER0_PERIOD_V 0xFFFF -#define MCPWM_TIMER0_PERIOD_S 8 -/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ -#define MCPWM_TIMER0_PRESCALE 0x000000FF -#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S)) -#define MCPWM_TIMER0_PRESCALE_V 0xFF -#define MCPWM_TIMER0_PRESCALE_S 0 - -#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0008) -/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: PWM timer0 working mode 0: freeze 1: increase mod 2: decrease - mod 3: up-down mod*/ -#define MCPWM_TIMER0_MOD 0x00000003 -#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S)) -#define MCPWM_TIMER0_MOD_V 0x3 -#define MCPWM_TIMER0_MOD_S 3 -/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP - 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ -#define MCPWM_TIMER0_START 0x00000007 -#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S)) -#define MCPWM_TIMER0_START_V 0x7 -#define MCPWM_TIMER0_START_S 0 - -#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x000c) -/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: Phase for timer reload on sync event*/ -#define MCPWM_TIMER0_PHASE 0x0001FFFF -#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S)) -#define MCPWM_TIMER0_PHASE_V 0x1FFFF -#define MCPWM_TIMER0_PHASE_S 4 -/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ -#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S)) -#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER0_SYNCO_SEL_S 2 -/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Toggling this bit will trigger a software sync*/ -#define MCPWM_TIMER0_SYNC_SW (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_V 0x1 -#define MCPWM_TIMER0_SYNC_SW_S 1 -/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: When set timer reload with phase on sync input event is enabled*/ -#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_V 0x1 -#define MCPWM_TIMER0_SYNCI_EN_S 0 - -#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0010) -/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Current PWM timer0 counter direction 0: increment 1: decrement*/ -#define MCPWM_TIMER0_DIRECTION (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_V 0x1 -#define MCPWM_TIMER0_DIRECTION_S 16 -/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Current PWM timer0 counter value*/ -#define MCPWM_TIMER0_VALUE 0x0000FFFF -#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S)) -#define MCPWM_TIMER0_VALUE_V 0xFFFF -#define MCPWM_TIMER0_VALUE_S 0 - -#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0014) -/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: Update method for active reg of PWM timer1 period 0: immediate - 1: TEZ 2: sync 3: TEZ or sync*/ -#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: Period shadow reg of PWM timer1*/ -#define MCPWM_TIMER1_PERIOD 0x0000FFFF -#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S)) -#define MCPWM_TIMER1_PERIOD_V 0xFFFF -#define MCPWM_TIMER1_PERIOD_S 8 -/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/ -#define MCPWM_TIMER1_PRESCALE 0x000000FF -#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S)) -#define MCPWM_TIMER1_PRESCALE_V 0xFF -#define MCPWM_TIMER1_PRESCALE_S 0 - -#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0018) -/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: PWM timer1 working mode 0: freeze 1: increase mod 2: decrease - mod 3: up-down mod*/ -#define MCPWM_TIMER1_MOD 0x00000003 -#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S)) -#define MCPWM_TIMER1_MOD_V 0x3 -#define MCPWM_TIMER1_MOD_S 3 -/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: PWM timer1 start and stop control. 0: stop @ TEZ 1: stop @ TEP - 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ -#define MCPWM_TIMER1_START 0x00000007 -#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S)) -#define MCPWM_TIMER1_START_V 0x7 -#define MCPWM_TIMER1_START_S 0 - -#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x001c) -/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: Phase for timer reload on sync event*/ -#define MCPWM_TIMER1_PHASE 0x0001FFFF -#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S)) -#define MCPWM_TIMER1_PHASE_V 0x1FFFF -#define MCPWM_TIMER1_PHASE_S 4 -/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: PWM timer1 synco selection 0: synci 1: TEZ 2: TEP else 0*/ -#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S)) -#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER1_SYNCO_SEL_S 2 -/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Toggling this bit will trigger a software sync*/ -#define MCPWM_TIMER1_SYNC_SW (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_V 0x1 -#define MCPWM_TIMER1_SYNC_SW_S 1 -/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: When set timer reload with phase on sync input event is enabled*/ -#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_V 0x1 -#define MCPWM_TIMER1_SYNCI_EN_S 0 - -#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0020) -/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Current PWM timer1 counter direction 0: increment 1: decrement*/ -#define MCPWM_TIMER1_DIRECTION (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_V 0x1 -#define MCPWM_TIMER1_DIRECTION_S 16 -/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Current PWM timer1 counter value*/ -#define MCPWM_TIMER1_VALUE 0x0000FFFF -#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S)) -#define MCPWM_TIMER1_VALUE_V 0xFFFF -#define MCPWM_TIMER1_VALUE_S 0 - -#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0024) -/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: Update method for active reg of PWM timer2 period 0: immediate - 1: TEZ 2: sync 3: TEZ or sync*/ -#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 -/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: Period shadow reg of PWM timer2*/ -#define MCPWM_TIMER2_PERIOD 0x0000FFFF -#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S)) -#define MCPWM_TIMER2_PERIOD_V 0xFFFF -#define MCPWM_TIMER2_PERIOD_S 8 -/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/ -#define MCPWM_TIMER2_PRESCALE 0x000000FF -#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S)) -#define MCPWM_TIMER2_PRESCALE_V 0xFF -#define MCPWM_TIMER2_PRESCALE_S 0 - -#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0028) -/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: PWM timer2 working mode 0: freeze 1: increase mod 2: decrease - mod 3: up-down mod*/ -#define MCPWM_TIMER2_MOD 0x00000003 -#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S)) -#define MCPWM_TIMER2_MOD_V 0x3 -#define MCPWM_TIMER2_MOD_S 3 -/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: PWM timer2 start and stop control. 0: stop @ TEZ 1: stop @ TEP - 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ -#define MCPWM_TIMER2_START 0x00000007 -#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S)) -#define MCPWM_TIMER2_START_V 0x7 -#define MCPWM_TIMER2_START_S 0 - -#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x002c) -/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: Phase for timer reload on sync event*/ -#define MCPWM_TIMER2_PHASE 0x0001FFFF -#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S)) -#define MCPWM_TIMER2_PHASE_V 0x1FFFF -#define MCPWM_TIMER2_PHASE_S 4 -/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: PWM timer2 synco selection 0: synci 1: TEZ 2: TEP else 0*/ -#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S)) -#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER2_SYNCO_SEL_S 2 -/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Toggling this bit will trigger a software sync*/ -#define MCPWM_TIMER2_SYNC_SW (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_V 0x1 -#define MCPWM_TIMER2_SYNC_SW_S 1 -/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: When set timer reload with phase on sync input event is enabled*/ -#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_V 0x1 -#define MCPWM_TIMER2_SYNCI_EN_S 0 - -#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0030) -/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Current PWM timer2 counter direction 0: increment 1: decrement*/ -#define MCPWM_TIMER2_DIRECTION (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_V 0x1 -#define MCPWM_TIMER2_DIRECTION_S 16 -/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Current PWM timer2 counter value*/ -#define MCPWM_TIMER2_VALUE 0x0000FFFF -#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S)) -#define MCPWM_TIMER2_VALUE_V 0xFFFF -#define MCPWM_TIMER2_VALUE_S 0 - -#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0034) -/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: Onvert SYNC2 from GPIO matrix*/ -#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 -/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Invert SYNC1 from GPIO matrix*/ -#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 -/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Invert SYNC0 from GPIO matrix*/ -#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 -/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */ -/*description: Select sync input for PWM timer2 1: PWM timer0 synco 2: PWM - timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ -#define MCPWM_TIMER2_SYNCISEL 0x00000007 -#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S)) -#define MCPWM_TIMER2_SYNCISEL_V 0x7 -#define MCPWM_TIMER2_SYNCISEL_S 6 -/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */ -/*description: Select sync input for PWM timer1 1: PWM timer0 synco 2: PWM - timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ -#define MCPWM_TIMER1_SYNCISEL 0x00000007 -#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S)) -#define MCPWM_TIMER1_SYNCISEL_V 0x7 -#define MCPWM_TIMER1_SYNCISEL_S 3 -/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */ -/*description: Select sync input for PWM timer0 1: PWM timer0 synco 2: PWM - timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ -#define MCPWM_TIMER0_SYNCISEL 0x00000007 -#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S)) -#define MCPWM_TIMER0_SYNCISEL_V 0x7 -#define MCPWM_TIMER0_SYNCISEL_S 0 - -#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x0038) -/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Select which PWM timer's is the timing reference for PWM operator2 - 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S)) -#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR2_TIMERSEL_S 4 -/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Select which PWM timer's is the timing reference for PWM operator1 - 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S)) -#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR1_TIMERSEL_S 2 -/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Select which PWM timer's is the timing reference for PWM operator0 - 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S)) -#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR0_TIMERSEL_S 0 - -#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x003c) -/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 0 time stamp - B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) -#define MCPWM_GEN0_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_GEN0_B_SHDW_FULL_V 0x1 -#define MCPWM_GEN0_B_SHDW_FULL_S 9 -/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 0 time stamp - A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) -#define MCPWM_GEN0_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_GEN0_A_SHDW_FULL_V 0x1 -#define MCPWM_GEN0_A_SHDW_FULL_S 8 -/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 0 time stamp B's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN0_B_UPMETHOD 0x0000000F -#define MCPWM_GEN0_B_UPMETHOD_M ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S)) -#define MCPWM_GEN0_B_UPMETHOD_V 0xF -#define MCPWM_GEN0_B_UPMETHOD_S 4 -/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 0 time stamp A's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN0_A_UPMETHOD 0x0000000F -#define MCPWM_GEN0_A_UPMETHOD_M ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S)) -#define MCPWM_GEN0_A_UPMETHOD_V 0xF -#define MCPWM_GEN0_A_UPMETHOD_S 0 - -#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0040) -/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 0 time stamp A's shadow reg*/ -#define MCPWM_GEN0_A 0x0000FFFF -#define MCPWM_GEN0_A_M ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S)) -#define MCPWM_GEN0_A_V 0xFFFF -#define MCPWM_GEN0_A_S 0 - -#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x0044) -/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 0 time stamp B's shadow reg*/ -#define MCPWM_GEN0_B 0x0000FFFF -#define MCPWM_GEN0_B_M ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S)) -#define MCPWM_GEN0_B_V 0xFFFF -#define MCPWM_GEN0_B_S 0 - -#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0048) -/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: Source selection for PWM generator 0 event_t1 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN0_T1_SEL 0x00000007 -#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S)) -#define MCPWM_GEN0_T1_SEL_V 0x7 -#define MCPWM_GEN0_T1_SEL_S 7 -/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: Source selection for PWM generator 0 event_t0 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN0_T0_SEL 0x00000007 -#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S)) -#define MCPWM_GEN0_T0_SEL_V 0x7 -#define MCPWM_GEN0_T0_SEL_S 4 -/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 0's active reg of configuration. - 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ -#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S)) -#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF -#define MCPWM_GEN0_CFG_UPMETHOD_S 0 - -#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x004c) -/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM0B 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM0B a - toggle will trigger a force event*/ -#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_V 0x1 -#define MCPWM_GEN0_B_NCIFORCE_S 13 -/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM0A 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM0A a - toggle will trigger a force event*/ -#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_V 0x1 -#define MCPWM_GEN0_A_NCIFORCE_S 10 -/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM0B. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM0A. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: Update method for continuous software force of PWM generator0. - 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 - -#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x0050) -/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN0_A_DT1 0x00000003 -#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S)) -#define MCPWM_GEN0_A_DT1_V 0x3 -#define MCPWM_GEN0_A_DT1_S 22 -/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN0_A_DT0 0x00000003 -#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S)) -#define MCPWM_GEN0_A_DT0_V 0x3 -#define MCPWM_GEN0_A_DT0_S 20 -/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN0_A_DTEB 0x00000003 -#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S)) -#define MCPWM_GEN0_A_DTEB_V 0x3 -#define MCPWM_GEN0_A_DTEB_S 18 -/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN0_A_DTEA 0x00000003 -#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S)) -#define MCPWM_GEN0_A_DTEA_V 0x3 -#define MCPWM_GEN0_A_DTEA_S 16 -/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN0_A_DTEP 0x00000003 -#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S)) -#define MCPWM_GEN0_A_DTEP_V 0x3 -#define MCPWM_GEN0_A_DTEP_S 14 -/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN0_A_DTEZ 0x00000003 -#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S)) -#define MCPWM_GEN0_A_DTEZ_V 0x3 -#define MCPWM_GEN0_A_DTEZ_S 12 -/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN0_A_UT1 0x00000003 -#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S)) -#define MCPWM_GEN0_A_UT1_V 0x3 -#define MCPWM_GEN0_A_UT1_S 10 -/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN0_A_UT0 0x00000003 -#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S)) -#define MCPWM_GEN0_A_UT0_V 0x3 -#define MCPWM_GEN0_A_UT0_S 8 -/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEB when timer increasing*/ -#define MCPWM_GEN0_A_UTEB 0x00000003 -#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S)) -#define MCPWM_GEN0_A_UTEB_V 0x3 -#define MCPWM_GEN0_A_UTEB_S 6 -/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEA when timer increasing*/ -#define MCPWM_GEN0_A_UTEA 0x00000003 -#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S)) -#define MCPWM_GEN0_A_UTEA_V 0x3 -#define MCPWM_GEN0_A_UTEA_S 4 -/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEP when timer increasing*/ -#define MCPWM_GEN0_A_UTEP 0x00000003 -#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S)) -#define MCPWM_GEN0_A_UTEP_V 0x3 -#define MCPWM_GEN0_A_UTEP_S 2 -/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM0A triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN0_A_UTEZ 0x00000003 -#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S)) -#define MCPWM_GEN0_A_UTEZ_V 0x3 -#define MCPWM_GEN0_A_UTEZ_S 0 - -#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x0054) -/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN0_B_DT1 0x00000003 -#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S)) -#define MCPWM_GEN0_B_DT1_V 0x3 -#define MCPWM_GEN0_B_DT1_S 22 -/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN0_B_DT0 0x00000003 -#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S)) -#define MCPWM_GEN0_B_DT0_V 0x3 -#define MCPWM_GEN0_B_DT0_S 20 -/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN0_B_DTEB 0x00000003 -#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S)) -#define MCPWM_GEN0_B_DTEB_V 0x3 -#define MCPWM_GEN0_B_DTEB_S 18 -/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN0_B_DTEA 0x00000003 -#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S)) -#define MCPWM_GEN0_B_DTEA_V 0x3 -#define MCPWM_GEN0_B_DTEA_S 16 -/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN0_B_DTEP 0x00000003 -#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S)) -#define MCPWM_GEN0_B_DTEP_V 0x3 -#define MCPWM_GEN0_B_DTEP_S 14 -/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN0_B_DTEZ 0x00000003 -#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S)) -#define MCPWM_GEN0_B_DTEZ_V 0x3 -#define MCPWM_GEN0_B_DTEZ_S 12 -/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN0_B_UT1 0x00000003 -#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S)) -#define MCPWM_GEN0_B_UT1_V 0x3 -#define MCPWM_GEN0_B_UT1_S 10 -/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN0_B_UT0 0x00000003 -#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S)) -#define MCPWM_GEN0_B_UT0_V 0x3 -#define MCPWM_GEN0_B_UT0_S 8 -/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEB when timer increasing*/ -#define MCPWM_GEN0_B_UTEB 0x00000003 -#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S)) -#define MCPWM_GEN0_B_UTEB_V 0x3 -#define MCPWM_GEN0_B_UTEB_S 6 -/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEA when timer increasing*/ -#define MCPWM_GEN0_B_UTEA 0x00000003 -#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S)) -#define MCPWM_GEN0_B_UTEA_V 0x3 -#define MCPWM_GEN0_B_UTEA_S 4 -/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEP when timer increasing*/ -#define MCPWM_GEN0_B_UTEP 0x00000003 -#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S)) -#define MCPWM_GEN0_B_UTEP_V 0x3 -#define MCPWM_GEN0_B_UTEP_S 2 -/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM0B triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN0_B_UTEZ 0x00000003 -#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S)) -#define MCPWM_GEN0_B_UTEZ_V 0x3 -#define MCPWM_GEN0_B_UTEZ_S 0 - -#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0058) -/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Dead time generator 0 clock selection. 0: PWM_clk 1: PT_clk*/ -#define MCPWM_DT0_CLK_SEL (BIT(17)) -#define MCPWM_DT0_CLK_SEL_M (BIT(17)) -#define MCPWM_DT0_CLK_SEL_V 0x1 -#define MCPWM_DT0_CLK_SEL_S 17 -/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: S0 in documentation*/ -#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) -#define MCPWM_DT0_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DT0_B_OUTBYPASS_V 0x1 -#define MCPWM_DT0_B_OUTBYPASS_S 16 -/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: S1 in documentation*/ -#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) -#define MCPWM_DT0_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DT0_A_OUTBYPASS_V 0x1 -#define MCPWM_DT0_A_OUTBYPASS_S 15 -/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: S3 in documentation*/ -#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) -#define MCPWM_DT0_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DT0_FED_OUTINVERT_V 0x1 -#define MCPWM_DT0_FED_OUTINVERT_S 14 -/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: S2 in documentation*/ -#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) -#define MCPWM_DT0_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DT0_RED_OUTINVERT_V 0x1 -#define MCPWM_DT0_RED_OUTINVERT_S 13 -/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: S5 in documentation*/ -#define MCPWM_DT0_FED_INSEL (BIT(12)) -#define MCPWM_DT0_FED_INSEL_M (BIT(12)) -#define MCPWM_DT0_FED_INSEL_V 0x1 -#define MCPWM_DT0_FED_INSEL_S 12 -/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: S4 in documentation*/ -#define MCPWM_DT0_RED_INSEL (BIT(11)) -#define MCPWM_DT0_RED_INSEL_M (BIT(11)) -#define MCPWM_DT0_RED_INSEL_V 0x1 -#define MCPWM_DT0_RED_INSEL_S 11 -/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: S7 in documentation*/ -#define MCPWM_DT0_B_OUTSWAP (BIT(10)) -#define MCPWM_DT0_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DT0_B_OUTSWAP_V 0x1 -#define MCPWM_DT0_B_OUTSWAP_S 10 -/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: S6 in documentation*/ -#define MCPWM_DT0_A_OUTSWAP (BIT(9)) -#define MCPWM_DT0_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DT0_A_OUTSWAP_V 0x1 -#define MCPWM_DT0_A_OUTSWAP_S 9 -/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect - on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ -#define MCPWM_DT0_DEB_MODE (BIT(8)) -#define MCPWM_DT0_DEB_MODE_M (BIT(8)) -#define MCPWM_DT0_DEB_MODE_V 0x1 -#define MCPWM_DT0_DEB_MODE_S 8 -/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for RED (rising edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT0_RED_UPMETHOD 0x0000000F -#define MCPWM_DT0_RED_UPMETHOD_M ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S)) -#define MCPWM_DT0_RED_UPMETHOD_V 0xF -#define MCPWM_DT0_RED_UPMETHOD_S 4 -/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for FED (falling edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT0_FED_UPMETHOD 0x0000000F -#define MCPWM_DT0_FED_UPMETHOD_M ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S)) -#define MCPWM_DT0_FED_UPMETHOD_V 0xF -#define MCPWM_DT0_FED_UPMETHOD_S 0 - -#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x005c) -/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for FED*/ -#define MCPWM_DT0_FED 0x0000FFFF -#define MCPWM_DT0_FED_M ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S)) -#define MCPWM_DT0_FED_V 0xFFFF -#define MCPWM_DT0_FED_S 0 - -#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0060) -/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for RED*/ -#define MCPWM_DT0_RED 0x0000FFFF -#define MCPWM_DT0_RED_M ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S)) -#define MCPWM_DT0_RED_V 0xFFFF -#define MCPWM_DT0_RED_S 0 - -#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0064) -/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: When set invert the input of PWM0A and PWM0B for this submodule*/ -#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) -#define MCPWM_CARRIER0_IN_INVERT_M (BIT(13)) -#define MCPWM_CARRIER0_IN_INVERT_V 0x1 -#define MCPWM_CARRIER0_IN_INVERT_S 13 -/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: When set invert the output of PWM0A and PWM0B for this submodule*/ -#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) -#define MCPWM_CARRIER0_OUT_INVERT_M (BIT(12)) -#define MCPWM_CARRIER0_OUT_INVERT_V 0x1 -#define MCPWM_CARRIER0_OUT_INVERT_S 12 -/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: Width of the fist pulse in number of periods of the carrier*/ -#define MCPWM_CARRIER0_OSHWTH 0x0000000F -#define MCPWM_CARRIER0_OSHWTH_M ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S)) -#define MCPWM_CARRIER0_OSHWTH_V 0xF -#define MCPWM_CARRIER0_OSHWTH_S 8 -/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ -#define MCPWM_CARRIER0_DUTY 0x00000007 -#define MCPWM_CARRIER0_DUTY_M ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S)) -#define MCPWM_CARRIER0_DUTY_V 0x7 -#define MCPWM_CARRIER0_DUTY_S 5 -/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk - = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ -#define MCPWM_CARRIER0_PRESCALE 0x0000000F -#define MCPWM_CARRIER0_PRESCALE_M ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S)) -#define MCPWM_CARRIER0_PRESCALE_V 0xF -#define MCPWM_CARRIER0_PRESCALE_S 1 -/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set carrier0 function is enabled. When cleared carrier0 is bypassed*/ -#define MCPWM_CARRIER0_EN (BIT(0)) -#define MCPWM_CARRIER0_EN_M (BIT(0)) -#define MCPWM_CARRIER0_EN_V 0x1 -#define MCPWM_CARRIER0_EN_S 0 - -#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0068) -/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0B when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_OST_U 0x00000003 -#define MCPWM_FH0_B_OST_U_M ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S)) -#define MCPWM_FH0_B_OST_U_V 0x3 -#define MCPWM_FH0_B_OST_U_S 22 -/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0B when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_OST_D 0x00000003 -#define MCPWM_FH0_B_OST_D_M ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S)) -#define MCPWM_FH0_B_OST_D_V 0x3 -#define MCPWM_FH0_B_OST_D_S 20 -/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_CBC_U 0x00000003 -#define MCPWM_FH0_B_CBC_U_M ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S)) -#define MCPWM_FH0_B_CBC_U_V 0x3 -#define MCPWM_FH0_B_CBC_U_S 18 -/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_B_CBC_D 0x00000003 -#define MCPWM_FH0_B_CBC_D_M ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S)) -#define MCPWM_FH0_B_CBC_D_V 0x3 -#define MCPWM_FH0_B_CBC_D_S 16 -/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0A when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_OST_U 0x00000003 -#define MCPWM_FH0_A_OST_U_M ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S)) -#define MCPWM_FH0_A_OST_U_V 0x3 -#define MCPWM_FH0_A_OST_U_S 14 -/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM0A when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_OST_D 0x00000003 -#define MCPWM_FH0_A_OST_D_M ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S)) -#define MCPWM_FH0_A_OST_D_V 0x3 -#define MCPWM_FH0_A_OST_D_S 12 -/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_CBC_U 0x00000003 -#define MCPWM_FH0_A_CBC_U_M ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S)) -#define MCPWM_FH0_A_CBC_U_V 0x3 -#define MCPWM_FH0_A_CBC_U_S 10 -/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH0_A_CBC_D 0x00000003 -#define MCPWM_FH0_A_CBC_D_M ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S)) -#define MCPWM_FH0_A_CBC_D_V 0x3 -#define MCPWM_FH0_A_CBC_D_S 8 -/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F0_OST (BIT(7)) -#define MCPWM_FH0_F0_OST_M (BIT(7)) -#define MCPWM_FH0_F0_OST_V 0x1 -#define MCPWM_FH0_F0_OST_S 7 -/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F1_OST (BIT(6)) -#define MCPWM_FH0_F1_OST_M (BIT(6)) -#define MCPWM_FH0_F1_OST_V 0x1 -#define MCPWM_FH0_F1_OST_S 6 -/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F2_OST (BIT(5)) -#define MCPWM_FH0_F2_OST_M (BIT(5)) -#define MCPWM_FH0_F2_OST_V 0x1 -#define MCPWM_FH0_F2_OST_S 5 -/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_SW_OST (BIT(4)) -#define MCPWM_FH0_SW_OST_M (BIT(4)) -#define MCPWM_FH0_SW_OST_V 0x1 -#define MCPWM_FH0_SW_OST_S 4 -/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F0_CBC (BIT(3)) -#define MCPWM_FH0_F0_CBC_M (BIT(3)) -#define MCPWM_FH0_F0_CBC_V 0x1 -#define MCPWM_FH0_F0_CBC_S 3 -/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F1_CBC (BIT(2)) -#define MCPWM_FH0_F1_CBC_M (BIT(2)) -#define MCPWM_FH0_F1_CBC_V 0x1 -#define MCPWM_FH0_F1_CBC_S 2 -/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH0_F2_CBC (BIT(1)) -#define MCPWM_FH0_F2_CBC_M (BIT(1)) -#define MCPWM_FH0_F2_CBC_V 0x1 -#define MCPWM_FH0_F2_CBC_S 1 -/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Enable register for software force cycle-by-cycle mode action. - 0: disable 1: enable*/ -#define MCPWM_FH0_SW_CBC (BIT(0)) -#define MCPWM_FH0_SW_CBC_M (BIT(0)) -#define MCPWM_FH0_SW_CBC_V 0x1 -#define MCPWM_FH0_SW_CBC_S 0 - -#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x006c) -/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) triggers a - one-shot mode action*/ -#define MCPWM_FH0_FORCE_OST (BIT(4)) -#define MCPWM_FH0_FORCE_OST_M (BIT(4)) -#define MCPWM_FH0_FORCE_OST_V 0x1 -#define MCPWM_FH0_FORCE_OST_S 4 -/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle triggers a cycle-by-cycle mode action*/ -#define MCPWM_FH0_FORCE_CBC (BIT(3)) -#define MCPWM_FH0_FORCE_CBC_M (BIT(3)) -#define MCPWM_FH0_FORCE_CBC_V 0x1 -#define MCPWM_FH0_FORCE_CBC_S 3 -/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ -#define MCPWM_FH0_CBCPULSE 0x00000003 -#define MCPWM_FH0_CBCPULSE_M ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S)) -#define MCPWM_FH0_CBCPULSE_V 0x3 -#define MCPWM_FH0_CBCPULSE_S 1 -/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: A toggle will clear on going one-shot mode action*/ -#define MCPWM_FH0_CLR_OST (BIT(0)) -#define MCPWM_FH0_CLR_OST_M (BIT(0)) -#define MCPWM_FH0_CLR_OST_V 0x1 -#define MCPWM_FH0_CLR_OST_S 0 - -#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0070) -/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ -#define MCPWM_FH0_OST_ON (BIT(1)) -#define MCPWM_FH0_OST_ON_M (BIT(1)) -#define MCPWM_FH0_OST_ON_V 0x1 -#define MCPWM_FH0_OST_ON_S 1 -/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ -#define MCPWM_FH0_CBC_ON (BIT(0)) -#define MCPWM_FH0_CBC_ON_M (BIT(0)) -#define MCPWM_FH0_CBC_ON_V 0x1 -#define MCPWM_FH0_CBC_ON_S 0 - -#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0074) -/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 1 time stamp - B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) -#define MCPWM_GEN1_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_GEN1_B_SHDW_FULL_V 0x1 -#define MCPWM_GEN1_B_SHDW_FULL_S 9 -/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 1 time stamp - A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) -#define MCPWM_GEN1_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_GEN1_A_SHDW_FULL_V 0x1 -#define MCPWM_GEN1_A_SHDW_FULL_S 8 -/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 1 time stamp B's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN1_B_UPMETHOD 0x0000000F -#define MCPWM_GEN1_B_UPMETHOD_M ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S)) -#define MCPWM_GEN1_B_UPMETHOD_V 0xF -#define MCPWM_GEN1_B_UPMETHOD_S 4 -/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 1 time stamp A's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN1_A_UPMETHOD 0x0000000F -#define MCPWM_GEN1_A_UPMETHOD_M ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S)) -#define MCPWM_GEN1_A_UPMETHOD_V 0xF -#define MCPWM_GEN1_A_UPMETHOD_S 0 - -#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0078) -/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 1 time stamp A's shadow reg*/ -#define MCPWM_GEN1_A 0x0000FFFF -#define MCPWM_GEN1_A_M ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S)) -#define MCPWM_GEN1_A_V 0xFFFF -#define MCPWM_GEN1_A_S 0 - -#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x007c) -/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 1 time stamp B's shadow reg*/ -#define MCPWM_GEN1_B 0x0000FFFF -#define MCPWM_GEN1_B_M ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S)) -#define MCPWM_GEN1_B_V 0xFFFF -#define MCPWM_GEN1_B_S 0 - -#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0080) -/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate1 event_t1 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN1_T1_SEL 0x00000007 -#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S)) -#define MCPWM_GEN1_T1_SEL_V 0x7 -#define MCPWM_GEN1_T1_SEL_S 7 -/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate1 event_t0 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN1_T0_SEL 0x00000007 -#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S)) -#define MCPWM_GEN1_T0_SEL_V 0x7 -#define MCPWM_GEN1_T0_SEL_S 4 -/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generate1's active reg of configuration. - 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ -#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S)) -#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF -#define MCPWM_GEN1_CFG_UPMETHOD_S 0 - -#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x0084) -/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM1B 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM1B a - toggle will trigger a force event*/ -#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_V 0x1 -#define MCPWM_GEN1_B_NCIFORCE_S 13 -/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM1A 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM1A a - toggle will trigger a force event*/ -#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_V 0x1 -#define MCPWM_GEN1_A_NCIFORCE_S 10 -/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM1B. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM1A. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: Update method for continuous software force of PWM generator1. - 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 - -#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x0088) -/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN1_A_DT1 0x00000003 -#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S)) -#define MCPWM_GEN1_A_DT1_V 0x3 -#define MCPWM_GEN1_A_DT1_S 22 -/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN1_A_DT0 0x00000003 -#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S)) -#define MCPWM_GEN1_A_DT0_V 0x3 -#define MCPWM_GEN1_A_DT0_S 20 -/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN1_A_DTEB 0x00000003 -#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S)) -#define MCPWM_GEN1_A_DTEB_V 0x3 -#define MCPWM_GEN1_A_DTEB_S 18 -/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN1_A_DTEA 0x00000003 -#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S)) -#define MCPWM_GEN1_A_DTEA_V 0x3 -#define MCPWM_GEN1_A_DTEA_S 16 -/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN1_A_DTEP 0x00000003 -#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S)) -#define MCPWM_GEN1_A_DTEP_V 0x3 -#define MCPWM_GEN1_A_DTEP_S 14 -/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN1_A_DTEZ 0x00000003 -#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S)) -#define MCPWM_GEN1_A_DTEZ_V 0x3 -#define MCPWM_GEN1_A_DTEZ_S 12 -/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN1_A_UT1 0x00000003 -#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S)) -#define MCPWM_GEN1_A_UT1_V 0x3 -#define MCPWM_GEN1_A_UT1_S 10 -/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN1_A_UT0 0x00000003 -#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S)) -#define MCPWM_GEN1_A_UT0_V 0x3 -#define MCPWM_GEN1_A_UT0_S 8 -/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEB when timer increasing*/ -#define MCPWM_GEN1_A_UTEB 0x00000003 -#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S)) -#define MCPWM_GEN1_A_UTEB_V 0x3 -#define MCPWM_GEN1_A_UTEB_S 6 -/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEA when timer increasing*/ -#define MCPWM_GEN1_A_UTEA 0x00000003 -#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S)) -#define MCPWM_GEN1_A_UTEA_V 0x3 -#define MCPWM_GEN1_A_UTEA_S 4 -/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEP when timer increasing*/ -#define MCPWM_GEN1_A_UTEP 0x00000003 -#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S)) -#define MCPWM_GEN1_A_UTEP_V 0x3 -#define MCPWM_GEN1_A_UTEP_S 2 -/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM1A triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN1_A_UTEZ 0x00000003 -#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S)) -#define MCPWM_GEN1_A_UTEZ_V 0x3 -#define MCPWM_GEN1_A_UTEZ_S 0 - -#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x008c) -/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN1_B_DT1 0x00000003 -#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S)) -#define MCPWM_GEN1_B_DT1_V 0x3 -#define MCPWM_GEN1_B_DT1_S 22 -/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN1_B_DT0 0x00000003 -#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S)) -#define MCPWM_GEN1_B_DT0_V 0x3 -#define MCPWM_GEN1_B_DT0_S 20 -/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN1_B_DTEB 0x00000003 -#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S)) -#define MCPWM_GEN1_B_DTEB_V 0x3 -#define MCPWM_GEN1_B_DTEB_S 18 -/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN1_B_DTEA 0x00000003 -#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S)) -#define MCPWM_GEN1_B_DTEA_V 0x3 -#define MCPWM_GEN1_B_DTEA_S 16 -/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN1_B_DTEP 0x00000003 -#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S)) -#define MCPWM_GEN1_B_DTEP_V 0x3 -#define MCPWM_GEN1_B_DTEP_S 14 -/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN1_B_DTEZ 0x00000003 -#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S)) -#define MCPWM_GEN1_B_DTEZ_V 0x3 -#define MCPWM_GEN1_B_DTEZ_S 12 -/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN1_B_UT1 0x00000003 -#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S)) -#define MCPWM_GEN1_B_UT1_V 0x3 -#define MCPWM_GEN1_B_UT1_S 10 -/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN1_B_UT0 0x00000003 -#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S)) -#define MCPWM_GEN1_B_UT0_V 0x3 -#define MCPWM_GEN1_B_UT0_S 8 -/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEB when timer increasing*/ -#define MCPWM_GEN1_B_UTEB 0x00000003 -#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S)) -#define MCPWM_GEN1_B_UTEB_V 0x3 -#define MCPWM_GEN1_B_UTEB_S 6 -/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEA when timer increasing*/ -#define MCPWM_GEN1_B_UTEA 0x00000003 -#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S)) -#define MCPWM_GEN1_B_UTEA_V 0x3 -#define MCPWM_GEN1_B_UTEA_S 4 -/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEP when timer increasing*/ -#define MCPWM_GEN1_B_UTEP 0x00000003 -#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S)) -#define MCPWM_GEN1_B_UTEP_V 0x3 -#define MCPWM_GEN1_B_UTEP_S 2 -/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM1B triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN1_B_UTEZ 0x00000003 -#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S)) -#define MCPWM_GEN1_B_UTEZ_V 0x3 -#define MCPWM_GEN1_B_UTEZ_S 0 - -#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0090) -/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ -#define MCPWM_DT1_CLK_SEL (BIT(17)) -#define MCPWM_DT1_CLK_SEL_M (BIT(17)) -#define MCPWM_DT1_CLK_SEL_V 0x1 -#define MCPWM_DT1_CLK_SEL_S 17 -/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: S0 in documentation*/ -#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) -#define MCPWM_DT1_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DT1_B_OUTBYPASS_V 0x1 -#define MCPWM_DT1_B_OUTBYPASS_S 16 -/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: S1 in documentation*/ -#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) -#define MCPWM_DT1_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DT1_A_OUTBYPASS_V 0x1 -#define MCPWM_DT1_A_OUTBYPASS_S 15 -/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: S3 in documentation*/ -#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) -#define MCPWM_DT1_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DT1_FED_OUTINVERT_V 0x1 -#define MCPWM_DT1_FED_OUTINVERT_S 14 -/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: S2 in documentation*/ -#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) -#define MCPWM_DT1_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DT1_RED_OUTINVERT_V 0x1 -#define MCPWM_DT1_RED_OUTINVERT_S 13 -/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: S5 in documentation*/ -#define MCPWM_DT1_FED_INSEL (BIT(12)) -#define MCPWM_DT1_FED_INSEL_M (BIT(12)) -#define MCPWM_DT1_FED_INSEL_V 0x1 -#define MCPWM_DT1_FED_INSEL_S 12 -/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: S4 in documentation*/ -#define MCPWM_DT1_RED_INSEL (BIT(11)) -#define MCPWM_DT1_RED_INSEL_M (BIT(11)) -#define MCPWM_DT1_RED_INSEL_V 0x1 -#define MCPWM_DT1_RED_INSEL_S 11 -/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: S7 in documentation*/ -#define MCPWM_DT1_B_OUTSWAP (BIT(10)) -#define MCPWM_DT1_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DT1_B_OUTSWAP_V 0x1 -#define MCPWM_DT1_B_OUTSWAP_S 10 -/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: S6 in documentation*/ -#define MCPWM_DT1_A_OUTSWAP (BIT(9)) -#define MCPWM_DT1_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DT1_A_OUTSWAP_V 0x1 -#define MCPWM_DT1_A_OUTSWAP_S 9 -/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect - on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ -#define MCPWM_DT1_DEB_MODE (BIT(8)) -#define MCPWM_DT1_DEB_MODE_M (BIT(8)) -#define MCPWM_DT1_DEB_MODE_V 0x1 -#define MCPWM_DT1_DEB_MODE_S 8 -/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for RED (rising edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT1_RED_UPMETHOD 0x0000000F -#define MCPWM_DT1_RED_UPMETHOD_M ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S)) -#define MCPWM_DT1_RED_UPMETHOD_V 0xF -#define MCPWM_DT1_RED_UPMETHOD_S 4 -/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for FED (falling edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT1_FED_UPMETHOD 0x0000000F -#define MCPWM_DT1_FED_UPMETHOD_M ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S)) -#define MCPWM_DT1_FED_UPMETHOD_V 0xF -#define MCPWM_DT1_FED_UPMETHOD_S 0 - -#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0094) -/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for FED*/ -#define MCPWM_DT1_FED 0x0000FFFF -#define MCPWM_DT1_FED_M ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S)) -#define MCPWM_DT1_FED_V 0xFFFF -#define MCPWM_DT1_FED_S 0 - -#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0098) -/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for RED*/ -#define MCPWM_DT1_RED 0x0000FFFF -#define MCPWM_DT1_RED_M ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S)) -#define MCPWM_DT1_RED_V 0xFFFF -#define MCPWM_DT1_RED_S 0 - -#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x009c) -/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: When set invert the input of PWM1A and PWM1B for this submodule*/ -#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) -#define MCPWM_CARRIER1_IN_INVERT_M (BIT(13)) -#define MCPWM_CARRIER1_IN_INVERT_V 0x1 -#define MCPWM_CARRIER1_IN_INVERT_S 13 -/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: When set invert the output of PWM1A and PWM1B for this submodule*/ -#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) -#define MCPWM_CARRIER1_OUT_INVERT_M (BIT(12)) -#define MCPWM_CARRIER1_OUT_INVERT_V 0x1 -#define MCPWM_CARRIER1_OUT_INVERT_S 12 -/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: Width of the fist pulse in number of periods of the carrier*/ -#define MCPWM_CARRIER1_OSHWTH 0x0000000F -#define MCPWM_CARRIER1_OSHWTH_M ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S)) -#define MCPWM_CARRIER1_OSHWTH_V 0xF -#define MCPWM_CARRIER1_OSHWTH_S 8 -/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/ -#define MCPWM_CARRIER1_DUTY 0x00000007 -#define MCPWM_CARRIER1_DUTY_M ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S)) -#define MCPWM_CARRIER1_DUTY_V 0x7 -#define MCPWM_CARRIER1_DUTY_S 5 -/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk - = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/ -#define MCPWM_CARRIER1_PRESCALE 0x0000000F -#define MCPWM_CARRIER1_PRESCALE_M ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S)) -#define MCPWM_CARRIER1_PRESCALE_V 0xF -#define MCPWM_CARRIER1_PRESCALE_S 1 -/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set carrier1 function is enabled. When cleared carrier1 is bypassed*/ -#define MCPWM_CARRIER1_EN (BIT(0)) -#define MCPWM_CARRIER1_EN_M (BIT(0)) -#define MCPWM_CARRIER1_EN_V 0x1 -#define MCPWM_CARRIER1_EN_S 0 - -#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00a0) -/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1B when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_OST_U 0x00000003 -#define MCPWM_FH1_B_OST_U_M ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S)) -#define MCPWM_FH1_B_OST_U_V 0x3 -#define MCPWM_FH1_B_OST_U_S 22 -/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1B when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_OST_D 0x00000003 -#define MCPWM_FH1_B_OST_D_M ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S)) -#define MCPWM_FH1_B_OST_D_V 0x3 -#define MCPWM_FH1_B_OST_D_S 20 -/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_CBC_U 0x00000003 -#define MCPWM_FH1_B_CBC_U_M ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S)) -#define MCPWM_FH1_B_CBC_U_V 0x3 -#define MCPWM_FH1_B_CBC_U_S 18 -/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_B_CBC_D 0x00000003 -#define MCPWM_FH1_B_CBC_D_M ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S)) -#define MCPWM_FH1_B_CBC_D_V 0x3 -#define MCPWM_FH1_B_CBC_D_S 16 -/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1A when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_OST_U 0x00000003 -#define MCPWM_FH1_A_OST_U_M ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S)) -#define MCPWM_FH1_A_OST_U_V 0x3 -#define MCPWM_FH1_A_OST_U_S 14 -/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM1A when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_OST_D 0x00000003 -#define MCPWM_FH1_A_OST_D_M ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S)) -#define MCPWM_FH1_A_OST_D_V 0x3 -#define MCPWM_FH1_A_OST_D_S 12 -/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_CBC_U 0x00000003 -#define MCPWM_FH1_A_CBC_U_M ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S)) -#define MCPWM_FH1_A_CBC_U_V 0x3 -#define MCPWM_FH1_A_CBC_U_S 10 -/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH1_A_CBC_D 0x00000003 -#define MCPWM_FH1_A_CBC_D_M ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S)) -#define MCPWM_FH1_A_CBC_D_V 0x3 -#define MCPWM_FH1_A_CBC_D_S 8 -/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F0_OST (BIT(7)) -#define MCPWM_FH1_F0_OST_M (BIT(7)) -#define MCPWM_FH1_F0_OST_V 0x1 -#define MCPWM_FH1_F0_OST_S 7 -/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F1_OST (BIT(6)) -#define MCPWM_FH1_F1_OST_M (BIT(6)) -#define MCPWM_FH1_F1_OST_V 0x1 -#define MCPWM_FH1_F1_OST_S 6 -/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F2_OST (BIT(5)) -#define MCPWM_FH1_F2_OST_M (BIT(5)) -#define MCPWM_FH1_F2_OST_V 0x1 -#define MCPWM_FH1_F2_OST_S 5 -/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_SW_OST (BIT(4)) -#define MCPWM_FH1_SW_OST_M (BIT(4)) -#define MCPWM_FH1_SW_OST_V 0x1 -#define MCPWM_FH1_SW_OST_S 4 -/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F0_CBC (BIT(3)) -#define MCPWM_FH1_F0_CBC_M (BIT(3)) -#define MCPWM_FH1_F0_CBC_V 0x1 -#define MCPWM_FH1_F0_CBC_S 3 -/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F1_CBC (BIT(2)) -#define MCPWM_FH1_F1_CBC_M (BIT(2)) -#define MCPWM_FH1_F1_CBC_V 0x1 -#define MCPWM_FH1_F1_CBC_S 2 -/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH1_F2_CBC (BIT(1)) -#define MCPWM_FH1_F2_CBC_M (BIT(1)) -#define MCPWM_FH1_F2_CBC_V 0x1 -#define MCPWM_FH1_F2_CBC_S 1 -/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Enable register for software force cycle-by-cycle mode action. - 0: disable 1: enable*/ -#define MCPWM_FH1_SW_CBC (BIT(0)) -#define MCPWM_FH1_SW_CBC_M (BIT(0)) -#define MCPWM_FH1_SW_CBC_V 0x1 -#define MCPWM_FH1_SW_CBC_S 0 - -#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00a4) -/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) triggers a - one-shot mode action*/ -#define MCPWM_FH1_FORCE_OST (BIT(4)) -#define MCPWM_FH1_FORCE_OST_M (BIT(4)) -#define MCPWM_FH1_FORCE_OST_V 0x1 -#define MCPWM_FH1_FORCE_OST_S 4 -/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle triggers a cycle-by-cycle mode action*/ -#define MCPWM_FH1_FORCE_CBC (BIT(3)) -#define MCPWM_FH1_FORCE_CBC_M (BIT(3)) -#define MCPWM_FH1_FORCE_CBC_V 0x1 -#define MCPWM_FH1_FORCE_CBC_S 3 -/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ -#define MCPWM_FH1_CBCPULSE 0x00000003 -#define MCPWM_FH1_CBCPULSE_M ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S)) -#define MCPWM_FH1_CBCPULSE_V 0x3 -#define MCPWM_FH1_CBCPULSE_S 1 -/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: A toggle will clear on going one-shot mode action*/ -#define MCPWM_FH1_CLR_OST (BIT(0)) -#define MCPWM_FH1_CLR_OST_M (BIT(0)) -#define MCPWM_FH1_CLR_OST_V 0x1 -#define MCPWM_FH1_CLR_OST_S 0 - -#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00a8) -/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ -#define MCPWM_FH1_OST_ON (BIT(1)) -#define MCPWM_FH1_OST_ON_M (BIT(1)) -#define MCPWM_FH1_OST_ON_V 0x1 -#define MCPWM_FH1_OST_ON_S 1 -/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ -#define MCPWM_FH1_CBC_ON (BIT(0)) -#define MCPWM_FH1_CBC_ON_M (BIT(0)) -#define MCPWM_FH1_CBC_ON_V 0x1 -#define MCPWM_FH1_CBC_ON_S 0 - -#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00ac) -/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 2 time stamp - B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) -#define MCPWM_GEN2_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_GEN2_B_SHDW_FULL_V 0x1 -#define MCPWM_GEN2_B_SHDW_FULL_S 9 -/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set PWM generator 2 time stamp - A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ -#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) -#define MCPWM_GEN2_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_GEN2_A_SHDW_FULL_V 0x1 -#define MCPWM_GEN2_A_SHDW_FULL_S 8 -/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 2 time stamp B's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN2_B_UPMETHOD 0x0000000F -#define MCPWM_GEN2_B_UPMETHOD_M ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S)) -#define MCPWM_GEN2_B_UPMETHOD_V 0xF -#define MCPWM_GEN2_B_UPMETHOD_S 4 -/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generator 2 time stamp A's active reg. - 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_GEN2_A_UPMETHOD 0x0000000F -#define MCPWM_GEN2_A_UPMETHOD_M ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S)) -#define MCPWM_GEN2_A_UPMETHOD_V 0xF -#define MCPWM_GEN2_A_UPMETHOD_S 0 - -#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x00b0) -/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 2 time stamp A's shadow reg*/ -#define MCPWM_GEN2_A 0x0000FFFF -#define MCPWM_GEN2_A_M ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S)) -#define MCPWM_GEN2_A_V 0xFFFF -#define MCPWM_GEN2_A_S 0 - -#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x00b4) -/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: PWM generator 2 time stamp B's shadow reg*/ -#define MCPWM_GEN2_B 0x0000FFFF -#define MCPWM_GEN2_B_M ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S)) -#define MCPWM_GEN2_B_V 0xFFFF -#define MCPWM_GEN2_B_S 0 - -#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00b8) -/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate2 event_t1 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN2_T1_SEL 0x00000007 -#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S)) -#define MCPWM_GEN2_T1_SEL_V 0x7 -#define MCPWM_GEN2_T1_SEL_S 7 -/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: Source selection for PWM generate2 event_t0 take effect immediately - 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ -#define MCPWM_GEN2_T0_SEL 0x00000007 -#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S)) -#define MCPWM_GEN2_T0_SEL_V 0x7 -#define MCPWM_GEN2_T0_SEL_S 4 -/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for PWM generate2's active reg of configuration. - 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ -#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S)) -#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF -#define MCPWM_GEN2_CFG_UPMETHOD_S 0 - -#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x00bc) -/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM2B 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 -/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM2B a - toggle will trigger a force event*/ -#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_V 0x1 -#define MCPWM_GEN2_B_NCIFORCE_S 13 -/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: Non-continuous immediate software force mode for PWM2A 0: disabled - 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 -/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Non-continuous immediate software force trigger for PWM2A a - toggle will trigger a force event*/ -#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_V 0x1 -#define MCPWM_GEN2_A_NCIFORCE_S 10 -/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM2B. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 -/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Continuous software force mode for PWM2A. 0: disabled 1: low - 2: high 3: disabled*/ -#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 -/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: Update method for continuous software force of PWM generator2. - 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 - -#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0x00c0) -/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN2_A_DT1 0x00000003 -#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S)) -#define MCPWM_GEN2_A_DT1_V 0x3 -#define MCPWM_GEN2_A_DT1_S 22 -/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN2_A_DT0 0x00000003 -#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S)) -#define MCPWM_GEN2_A_DT0_V 0x3 -#define MCPWM_GEN2_A_DT0_S 20 -/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN2_A_DTEB 0x00000003 -#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S)) -#define MCPWM_GEN2_A_DTEB_V 0x3 -#define MCPWM_GEN2_A_DTEB_S 18 -/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN2_A_DTEA 0x00000003 -#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S)) -#define MCPWM_GEN2_A_DTEA_V 0x3 -#define MCPWM_GEN2_A_DTEA_S 16 -/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN2_A_DTEP 0x00000003 -#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S)) -#define MCPWM_GEN2_A_DTEP_V 0x3 -#define MCPWM_GEN2_A_DTEP_S 14 -/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN2_A_DTEZ 0x00000003 -#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S)) -#define MCPWM_GEN2_A_DTEZ_V 0x3 -#define MCPWM_GEN2_A_DTEZ_S 12 -/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN2_A_UT1 0x00000003 -#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S)) -#define MCPWM_GEN2_A_UT1_V 0x3 -#define MCPWM_GEN2_A_UT1_S 10 -/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN2_A_UT0 0x00000003 -#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S)) -#define MCPWM_GEN2_A_UT0_V 0x3 -#define MCPWM_GEN2_A_UT0_S 8 -/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEB when timer increasing*/ -#define MCPWM_GEN2_A_UTEB 0x00000003 -#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S)) -#define MCPWM_GEN2_A_UTEB_V 0x3 -#define MCPWM_GEN2_A_UTEB_S 6 -/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEA when timer increasing*/ -#define MCPWM_GEN2_A_UTEA 0x00000003 -#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S)) -#define MCPWM_GEN2_A_UTEA_V 0x3 -#define MCPWM_GEN2_A_UTEA_S 4 -/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEP when timer increasing*/ -#define MCPWM_GEN2_A_UTEP 0x00000003 -#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S)) -#define MCPWM_GEN2_A_UTEP_V 0x3 -#define MCPWM_GEN2_A_UTEP_S 2 -/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM2A triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN2_A_UTEZ 0x00000003 -#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S)) -#define MCPWM_GEN2_A_UTEZ_V 0x3 -#define MCPWM_GEN2_A_UTEZ_S 0 - -#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0x00c4) -/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t1 when timer decreasing. - 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN2_B_DT1 0x00000003 -#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S)) -#define MCPWM_GEN2_B_DT1_V 0x3 -#define MCPWM_GEN2_B_DT1_S 22 -/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/ -#define MCPWM_GEN2_B_DT0 0x00000003 -#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S)) -#define MCPWM_GEN2_B_DT0_V 0x3 -#define MCPWM_GEN2_B_DT0_S 20 -/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEB when timer decreasing*/ -#define MCPWM_GEN2_B_DTEB 0x00000003 -#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S)) -#define MCPWM_GEN2_B_DTEB_V 0x3 -#define MCPWM_GEN2_B_DTEB_S 18 -/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEA when timer decreasing*/ -#define MCPWM_GEN2_B_DTEA 0x00000003 -#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S)) -#define MCPWM_GEN2_B_DTEA_V 0x3 -#define MCPWM_GEN2_B_DTEA_S 16 -/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEP when timer decreasing*/ -#define MCPWM_GEN2_B_DTEP 0x00000003 -#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S)) -#define MCPWM_GEN2_B_DTEP_V 0x3 -#define MCPWM_GEN2_B_DTEP_S 14 -/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/ -#define MCPWM_GEN2_B_DTEZ 0x00000003 -#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S)) -#define MCPWM_GEN2_B_DTEZ_V 0x3 -#define MCPWM_GEN2_B_DTEZ_S 12 -/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t1 when timer increasing*/ -#define MCPWM_GEN2_B_UT1 0x00000003 -#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S)) -#define MCPWM_GEN2_B_UT1_V 0x3 -#define MCPWM_GEN2_B_UT1_S 10 -/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event_t0 when timer increasing*/ -#define MCPWM_GEN2_B_UT0 0x00000003 -#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S)) -#define MCPWM_GEN2_B_UT0_V 0x3 -#define MCPWM_GEN2_B_UT0_S 8 -/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEB when timer increasing*/ -#define MCPWM_GEN2_B_UTEB 0x00000003 -#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S)) -#define MCPWM_GEN2_B_UTEB_V 0x3 -#define MCPWM_GEN2_B_UTEB_S 6 -/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEA when timer increasing*/ -#define MCPWM_GEN2_B_UTEA 0x00000003 -#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S)) -#define MCPWM_GEN2_B_UTEA_V 0x3 -#define MCPWM_GEN2_B_UTEA_S 4 -/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEP when timer increasing*/ -#define MCPWM_GEN2_B_UTEP 0x00000003 -#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S)) -#define MCPWM_GEN2_B_UTEP_V 0x3 -#define MCPWM_GEN2_B_UTEP_S 2 -/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: Action on PWM2B triggered by event TEZ when timer increasing*/ -#define MCPWM_GEN2_B_UTEZ 0x00000003 -#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S)) -#define MCPWM_GEN2_B_UTEZ_V 0x3 -#define MCPWM_GEN2_B_UTEZ_S 0 - -#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00c8) -/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ -#define MCPWM_DT2_CLK_SEL (BIT(17)) -#define MCPWM_DT2_CLK_SEL_M (BIT(17)) -#define MCPWM_DT2_CLK_SEL_V 0x1 -#define MCPWM_DT2_CLK_SEL_S 17 -/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: S0 in documentation*/ -#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) -#define MCPWM_DT2_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DT2_B_OUTBYPASS_V 0x1 -#define MCPWM_DT2_B_OUTBYPASS_S 16 -/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: S1 in documentation*/ -#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) -#define MCPWM_DT2_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DT2_A_OUTBYPASS_V 0x1 -#define MCPWM_DT2_A_OUTBYPASS_S 15 -/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: S3 in documentation*/ -#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) -#define MCPWM_DT2_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DT2_FED_OUTINVERT_V 0x1 -#define MCPWM_DT2_FED_OUTINVERT_S 14 -/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: S2 in documentation*/ -#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) -#define MCPWM_DT2_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DT2_RED_OUTINVERT_V 0x1 -#define MCPWM_DT2_RED_OUTINVERT_S 13 -/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: S5 in documentation*/ -#define MCPWM_DT2_FED_INSEL (BIT(12)) -#define MCPWM_DT2_FED_INSEL_M (BIT(12)) -#define MCPWM_DT2_FED_INSEL_V 0x1 -#define MCPWM_DT2_FED_INSEL_S 12 -/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: S4 in documentation*/ -#define MCPWM_DT2_RED_INSEL (BIT(11)) -#define MCPWM_DT2_RED_INSEL_M (BIT(11)) -#define MCPWM_DT2_RED_INSEL_V 0x1 -#define MCPWM_DT2_RED_INSEL_S 11 -/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: S7 in documentation*/ -#define MCPWM_DT2_B_OUTSWAP (BIT(10)) -#define MCPWM_DT2_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DT2_B_OUTSWAP_V 0x1 -#define MCPWM_DT2_B_OUTSWAP_S 10 -/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: S6 in documentation*/ -#define MCPWM_DT2_A_OUTSWAP (BIT(9)) -#define MCPWM_DT2_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DT2_A_OUTSWAP_V 0x1 -#define MCPWM_DT2_A_OUTSWAP_S 9 -/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect - on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ -#define MCPWM_DT2_DEB_MODE (BIT(8)) -#define MCPWM_DT2_DEB_MODE_M (BIT(8)) -#define MCPWM_DT2_DEB_MODE_V 0x1 -#define MCPWM_DT2_DEB_MODE_S 8 -/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: Update method for RED (rising edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT2_RED_UPMETHOD 0x0000000F -#define MCPWM_DT2_RED_UPMETHOD_M ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S)) -#define MCPWM_DT2_RED_UPMETHOD_V 0xF -#define MCPWM_DT2_RED_UPMETHOD_S 4 -/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: Update method for FED (falling edge delay) active reg. 0: immediate - bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ -#define MCPWM_DT2_FED_UPMETHOD 0x0000000F -#define MCPWM_DT2_FED_UPMETHOD_M ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S)) -#define MCPWM_DT2_FED_UPMETHOD_V 0xF -#define MCPWM_DT2_FED_UPMETHOD_S 0 - -#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00cc) -/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for FED*/ -#define MCPWM_DT2_FED 0x0000FFFF -#define MCPWM_DT2_FED_M ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S)) -#define MCPWM_DT2_FED_V 0xFFFF -#define MCPWM_DT2_FED_S 0 - -#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d0) -/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: Shadow reg for RED*/ -#define MCPWM_DT2_RED 0x0000FFFF -#define MCPWM_DT2_RED_M ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S)) -#define MCPWM_DT2_RED_V 0xFFFF -#define MCPWM_DT2_RED_S 0 - -#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d4) -/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: When set invert the input of PWM2A and PWM2B for this submodule*/ -#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) -#define MCPWM_CARRIER2_IN_INVERT_M (BIT(13)) -#define MCPWM_CARRIER2_IN_INVERT_V 0x1 -#define MCPWM_CARRIER2_IN_INVERT_S 13 -/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: When set invert the output of PWM2A and PWM2B for this submodule*/ -#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) -#define MCPWM_CARRIER2_OUT_INVERT_M (BIT(12)) -#define MCPWM_CARRIER2_OUT_INVERT_V 0x1 -#define MCPWM_CARRIER2_OUT_INVERT_S 12 -/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: Width of the fist pulse in number of periods of the carrier*/ -#define MCPWM_CARRIER2_OSHWTH 0x0000000F -#define MCPWM_CARRIER2_OSHWTH_M ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S)) -#define MCPWM_CARRIER2_OSHWTH_V 0xF -#define MCPWM_CARRIER2_OSHWTH_S 8 -/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/ -#define MCPWM_CARRIER2_DUTY 0x00000007 -#define MCPWM_CARRIER2_DUTY_M ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S)) -#define MCPWM_CARRIER2_DUTY_V 0x7 -#define MCPWM_CARRIER2_DUTY_S 5 -/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk - = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/ -#define MCPWM_CARRIER2_PRESCALE 0x0000000F -#define MCPWM_CARRIER2_PRESCALE_M ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S)) -#define MCPWM_CARRIER2_PRESCALE_V 0xF -#define MCPWM_CARRIER2_PRESCALE_S 1 -/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set carrier2 function is enabled. When cleared carrier2 is bypassed*/ -#define MCPWM_CARRIER2_EN (BIT(0)) -#define MCPWM_CARRIER2_EN_M (BIT(0)) -#define MCPWM_CARRIER2_EN_V 0x1 -#define MCPWM_CARRIER2_EN_S 0 - -#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00d8) -/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2B when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_OST_U 0x00000003 -#define MCPWM_FH2_B_OST_U_M ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S)) -#define MCPWM_FH2_B_OST_U_V 0x3 -#define MCPWM_FH2_B_OST_U_S 22 -/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2B when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_OST_D 0x00000003 -#define MCPWM_FH2_B_OST_D_M ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S)) -#define MCPWM_FH2_B_OST_D_V 0x3 -#define MCPWM_FH2_B_OST_D_S 20 -/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_CBC_U 0x00000003 -#define MCPWM_FH2_B_CBC_U_M ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S)) -#define MCPWM_FH2_B_CBC_U_V 0x3 -#define MCPWM_FH2_B_CBC_U_S 18 -/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_B_CBC_D 0x00000003 -#define MCPWM_FH2_B_CBC_D_M ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S)) -#define MCPWM_FH2_B_CBC_D_V 0x3 -#define MCPWM_FH2_B_CBC_D_S 16 -/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2A when fault event occurs and timer - is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_OST_U 0x00000003 -#define MCPWM_FH2_A_OST_U_M ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S)) -#define MCPWM_FH2_A_OST_U_V 0x3 -#define MCPWM_FH2_A_OST_U_S 14 -/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: One-shot mode action on PWM2A when fault event occurs and timer - is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_OST_D 0x00000003 -#define MCPWM_FH2_A_OST_D_M ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S)) -#define MCPWM_FH2_A_OST_D_V 0x3 -#define MCPWM_FH2_A_OST_D_S 12 -/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and - timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_CBC_U 0x00000003 -#define MCPWM_FH2_A_CBC_U_M ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S)) -#define MCPWM_FH2_A_CBC_U_V 0x3 -#define MCPWM_FH2_A_CBC_U_S 10 -/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and - timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_FH2_A_CBC_D 0x00000003 -#define MCPWM_FH2_A_CBC_D_M ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S)) -#define MCPWM_FH2_A_CBC_D_V 0x3 -#define MCPWM_FH2_A_CBC_D_S 8 -/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F0_OST (BIT(7)) -#define MCPWM_FH2_F0_OST_M (BIT(7)) -#define MCPWM_FH2_F0_OST_V 0x1 -#define MCPWM_FH2_F0_OST_S 7 -/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F1_OST (BIT(6)) -#define MCPWM_FH2_F1_OST_M (BIT(6)) -#define MCPWM_FH2_F1_OST_V 0x1 -#define MCPWM_FH2_F1_OST_S 6 -/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F2_OST (BIT(5)) -#define MCPWM_FH2_F2_OST_M (BIT(5)) -#define MCPWM_FH2_F2_OST_V 0x1 -#define MCPWM_FH2_F2_OST_S 5 -/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_SW_OST (BIT(4)) -#define MCPWM_FH2_SW_OST_M (BIT(4)) -#define MCPWM_FH2_SW_OST_V 0x1 -#define MCPWM_FH2_SW_OST_S 4 -/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F0_CBC (BIT(3)) -#define MCPWM_FH2_F0_CBC_M (BIT(3)) -#define MCPWM_FH2_F0_CBC_V 0x1 -#define MCPWM_FH2_F0_CBC_S 3 -/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F1_CBC (BIT(2)) -#define MCPWM_FH2_F1_CBC_M (BIT(2)) -#define MCPWM_FH2_F1_CBC_V 0x1 -#define MCPWM_FH2_F1_CBC_S 2 -/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ -#define MCPWM_FH2_F2_CBC (BIT(1)) -#define MCPWM_FH2_F2_CBC_M (BIT(1)) -#define MCPWM_FH2_F2_CBC_V 0x1 -#define MCPWM_FH2_F2_CBC_S 1 -/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Enable register for software force cycle-by-cycle mode action. - 0: disable 1: enable*/ -#define MCPWM_FH2_SW_CBC (BIT(0)) -#define MCPWM_FH2_SW_CBC_M (BIT(0)) -#define MCPWM_FH2_SW_CBC_V 0x1 -#define MCPWM_FH2_SW_CBC_S 0 - -#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00dc) -/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) triggers a - one-shot mode action*/ -#define MCPWM_FH2_FORCE_OST (BIT(4)) -#define MCPWM_FH2_FORCE_OST_M (BIT(4)) -#define MCPWM_FH2_FORCE_OST_V 0x1 -#define MCPWM_FH2_FORCE_OST_S 4 -/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle triggers a cycle-by-cycle mode action*/ -#define MCPWM_FH2_FORCE_CBC (BIT(3)) -#define MCPWM_FH2_FORCE_CBC_M (BIT(3)) -#define MCPWM_FH2_FORCE_CBC_V 0x1 -#define MCPWM_FH2_FORCE_CBC_S 3 -/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ -#define MCPWM_FH2_CBCPULSE 0x00000003 -#define MCPWM_FH2_CBCPULSE_M ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S)) -#define MCPWM_FH2_CBCPULSE_V 0x3 -#define MCPWM_FH2_CBCPULSE_S 1 -/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: A toggle will clear on going one-shot mode action*/ -#define MCPWM_FH2_CLR_OST (BIT(0)) -#define MCPWM_FH2_CLR_OST_M (BIT(0)) -#define MCPWM_FH2_CLR_OST_V 0x1 -#define MCPWM_FH2_CLR_OST_S 0 - -#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00e0) -/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ -#define MCPWM_FH2_OST_ON (BIT(1)) -#define MCPWM_FH2_OST_ON_M (BIT(1)) -#define MCPWM_FH2_OST_ON_V 0x1 -#define MCPWM_FH2_OST_ON_S 1 -/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ -#define MCPWM_FH2_CBC_ON (BIT(0)) -#define MCPWM_FH2_CBC_ON_M (BIT(0)) -#define MCPWM_FH2_CBC_ON_V 0x1 -#define MCPWM_FH2_CBC_ON_S 0 - -#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0x00e4) -/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set event_f2 is on going*/ -#define MCPWM_EVENT_F2 (BIT(8)) -#define MCPWM_EVENT_F2_M (BIT(8)) -#define MCPWM_EVENT_F2_V 0x1 -#define MCPWM_EVENT_F2_S 8 -/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set event_f1 is on going*/ -#define MCPWM_EVENT_F1 (BIT(7)) -#define MCPWM_EVENT_F1_M (BIT(7)) -#define MCPWM_EVENT_F1_V 0x1 -#define MCPWM_EVENT_F1_S 7 -/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */ -/*description: Set and reset by hardware. If set event_f0 is on going*/ -#define MCPWM_EVENT_F0 (BIT(6)) -#define MCPWM_EVENT_F0_M (BIT(6)) -#define MCPWM_EVENT_F0_V 0x1 -#define MCPWM_EVENT_F0_S 6 -/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. - 0: level low 1: level high*/ -#define MCPWM_F2_POLE (BIT(5)) -#define MCPWM_F2_POLE_M (BIT(5)) -#define MCPWM_F2_POLE_V 0x1 -#define MCPWM_F2_POLE_S 5 -/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. - 0: level low 1: level high*/ -#define MCPWM_F1_POLE (BIT(4)) -#define MCPWM_F1_POLE_M (BIT(4)) -#define MCPWM_F1_POLE_V 0x1 -#define MCPWM_F1_POLE_S 4 -/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. - 0: level low 1: level high*/ -#define MCPWM_F0_POLE (BIT(3)) -#define MCPWM_F0_POLE_M (BIT(3)) -#define MCPWM_F0_POLE_V 0x1 -#define MCPWM_F0_POLE_S 3 -/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: Set to enable generation of event_f2*/ -#define MCPWM_F2_EN (BIT(2)) -#define MCPWM_F2_EN_M (BIT(2)) -#define MCPWM_F2_EN_V 0x1 -#define MCPWM_F2_EN_S 2 -/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set to enable generation of event_f1*/ -#define MCPWM_F1_EN (BIT(1)) -#define MCPWM_F1_EN_M (BIT(1)) -#define MCPWM_F1_EN_V 0x1 -#define MCPWM_F1_EN_S 1 -/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set to enable generation of event_f0*/ -#define MCPWM_F0_EN (BIT(0)) -#define MCPWM_F0_EN_M (BIT(0)) -#define MCPWM_F0_EN_V 0x1 -#define MCPWM_F0_EN_S 0 - -#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00e8) -/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */ -/*description: Set this bit to force a capture timer sync capture timer is - loaded with value in phase register.*/ -#define MCPWM_CAP_SYNC_SW (BIT(5)) -#define MCPWM_CAP_SYNC_SW_M (BIT(5)) -#define MCPWM_CAP_SYNC_SW_V 0x1 -#define MCPWM_CAP_SYNC_SW_S 5 -/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: Capture module sync input selection. 0: none 1: timer0 synco - 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ -#define MCPWM_CAP_SYNCI_SEL 0x00000007 -#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S)) -#define MCPWM_CAP_SYNCI_SEL_V 0x7 -#define MCPWM_CAP_SYNCI_SEL_S 2 -/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: When set capture timer sync is enabled.*/ -#define MCPWM_CAP_SYNCI_EN (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_V 0x1 -#define MCPWM_CAP_SYNCI_EN_S 1 -/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture timer incrementing under APB_clk is enabled.*/ -#define MCPWM_CAP_TIMER_EN (BIT(0)) -#define MCPWM_CAP_TIMER_EN_M (BIT(0)) -#define MCPWM_CAP_TIMER_EN_V 0x1 -#define MCPWM_CAP_TIMER_EN_S 0 - -#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0x00ec) -/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Phase value for capture timer sync operation.*/ -#define MCPWM_CAP_PHASE 0xFFFFFFFF -#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S)) -#define MCPWM_CAP_PHASE_V 0xFFFFFFFF -#define MCPWM_CAP_PHASE_S 0 - -#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f0) -/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a software forced capture on channel 0*/ -#define MCPWM_CAP0_SW (BIT(12)) -#define MCPWM_CAP0_SW_M (BIT(12)) -#define MCPWM_CAP0_SW_V 0x1 -#define MCPWM_CAP0_SW_S 12 -/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: When set CAP0 form GPIO matrix is inverted before prescale*/ -#define MCPWM_CAP0_IN_INVERT (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_V 0x1 -#define MCPWM_CAP0_IN_INVERT_S 11 -/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: Value of prescale on possitive edge of CAP0. Prescale value = - PWM_CAP0_PRESCALE + 1*/ -#define MCPWM_CAP0_PRESCALE 0x000000FF -#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S)) -#define MCPWM_CAP0_PRESCALE_V 0xFF -#define MCPWM_CAP0_PRESCALE_S 3 -/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: Edge of capture on channel 0 after prescale. bit0: negedge cap - en bit1: posedge cap en*/ -#define MCPWM_CAP0_MODE 0x00000003 -#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S)) -#define MCPWM_CAP0_MODE_V 0x3 -#define MCPWM_CAP0_MODE_S 1 -/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture on channel 0 is enabled*/ -#define MCPWM_CAP0_EN (BIT(0)) -#define MCPWM_CAP0_EN_M (BIT(0)) -#define MCPWM_CAP0_EN_V 0x1 -#define MCPWM_CAP0_EN_S 0 - -#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f4) -/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a software forced capture on channel 1*/ -#define MCPWM_CAP1_SW (BIT(12)) -#define MCPWM_CAP1_SW_M (BIT(12)) -#define MCPWM_CAP1_SW_V 0x1 -#define MCPWM_CAP1_SW_S 12 -/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: When set CAP1 form GPIO matrix is inverted before prescale*/ -#define MCPWM_CAP1_IN_INVERT (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_V 0x1 -#define MCPWM_CAP1_IN_INVERT_S 11 -/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: Value of prescale on possitive edge of CAP1. Prescale value = - PWM_CAP1_PRESCALE + 1*/ -#define MCPWM_CAP1_PRESCALE 0x000000FF -#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S)) -#define MCPWM_CAP1_PRESCALE_V 0xFF -#define MCPWM_CAP1_PRESCALE_S 3 -/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: Edge of capture on channel 1 after prescale. bit0: negedge cap - en bit1: posedge cap en*/ -#define MCPWM_CAP1_MODE 0x00000003 -#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S)) -#define MCPWM_CAP1_MODE_V 0x3 -#define MCPWM_CAP1_MODE_S 1 -/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture on channel 1 is enabled*/ -#define MCPWM_CAP1_EN (BIT(0)) -#define MCPWM_CAP1_EN_M (BIT(0)) -#define MCPWM_CAP1_EN_V 0x1 -#define MCPWM_CAP1_EN_S 0 - -#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f8) -/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a software forced capture on channel 2*/ -#define MCPWM_CAP2_SW (BIT(12)) -#define MCPWM_CAP2_SW_M (BIT(12)) -#define MCPWM_CAP2_SW_V 0x1 -#define MCPWM_CAP2_SW_S 12 -/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: When set CAP2 form GPIO matrix is inverted before prescale*/ -#define MCPWM_CAP2_IN_INVERT (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_V 0x1 -#define MCPWM_CAP2_IN_INVERT_S 11 -/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: Value of prescale on possitive edge of CAP2. Prescale value = - PWM_CAP2_PRESCALE + 1*/ -#define MCPWM_CAP2_PRESCALE 0x000000FF -#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S)) -#define MCPWM_CAP2_PRESCALE_V 0xFF -#define MCPWM_CAP2_PRESCALE_S 3 -/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: Edge of capture on channel 2 after prescale. bit0: negedge cap - en bit1: posedge cap en*/ -#define MCPWM_CAP2_MODE 0x00000003 -#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S)) -#define MCPWM_CAP2_MODE_V 0x3 -#define MCPWM_CAP2_MODE_S 1 -/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: When set capture on channel 2 is enabled*/ -#define MCPWM_CAP2_EN (BIT(0)) -#define MCPWM_CAP2_EN_M (BIT(0)) -#define MCPWM_CAP2_EN_V 0x1 -#define MCPWM_CAP2_EN_S 0 - -#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0x00fc) -/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Value of last capture on channel 0*/ -#define MCPWM_CAP0_VALUE 0xFFFFFFFF -#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S)) -#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF -#define MCPWM_CAP0_VALUE_S 0 - -#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x0100) -/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Value of last capture on channel 1*/ -#define MCPWM_CAP1_VALUE 0xFFFFFFFF -#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S)) -#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF -#define MCPWM_CAP1_VALUE_S 0 - -#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x0104) -/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: Value of last capture on channel 2*/ -#define MCPWM_CAP2_VALUE 0xFFFFFFFF -#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S)) -#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF -#define MCPWM_CAP2_VALUE_S 0 - -#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0108) -/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */ -/*description: Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ -#define MCPWM_CAP2_EDGE (BIT(2)) -#define MCPWM_CAP2_EDGE_M (BIT(2)) -#define MCPWM_CAP2_EDGE_V 0x1 -#define MCPWM_CAP2_EDGE_S 2 -/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ -#define MCPWM_CAP1_EDGE (BIT(1)) -#define MCPWM_CAP1_EDGE_M (BIT(1)) -#define MCPWM_CAP1_EDGE_V 0x1 -#define MCPWM_CAP1_EDGE_S 1 -/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ -#define MCPWM_CAP0_EDGE (BIT(0)) -#define MCPWM_CAP0_EDGE_M (BIT(0)) -#define MCPWM_CAP0_EDGE_V 0x1 -#define MCPWM_CAP0_EDGE_S 0 - -#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x010c) -/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of active registers in PWM operator 2*/ -#define MCPWM_OP2_FORCE_UP (BIT(7)) -#define MCPWM_OP2_FORCE_UP_M (BIT(7)) -#define MCPWM_OP2_FORCE_UP_V 0x1 -#define MCPWM_OP2_FORCE_UP_S 7 -/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */ -/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers - in PWM operator 2 are enabled*/ -#define MCPWM_OP2_UP_EN (BIT(6)) -#define MCPWM_OP2_UP_EN_M (BIT(6)) -#define MCPWM_OP2_UP_EN_V 0x1 -#define MCPWM_OP2_UP_EN_S 6 -/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of active registers in PWM operator 1*/ -#define MCPWM_OP1_FORCE_UP (BIT(5)) -#define MCPWM_OP1_FORCE_UP_M (BIT(5)) -#define MCPWM_OP1_FORCE_UP_V 0x1 -#define MCPWM_OP1_FORCE_UP_S 5 -/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */ -/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers - in PWM operator 1 are enabled*/ -#define MCPWM_OP1_UP_EN (BIT(4)) -#define MCPWM_OP1_UP_EN_M (BIT(4)) -#define MCPWM_OP1_UP_EN_V 0x1 -#define MCPWM_OP1_UP_EN_S 4 -/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of active registers in PWM operator 0*/ -#define MCPWM_OP0_FORCE_UP (BIT(3)) -#define MCPWM_OP0_FORCE_UP_M (BIT(3)) -#define MCPWM_OP0_FORCE_UP_V 0x1 -#define MCPWM_OP0_FORCE_UP_S 3 -/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */ -/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers - in PWM operator 0 are enabled*/ -#define MCPWM_OP0_UP_EN (BIT(2)) -#define MCPWM_OP0_UP_EN_M (BIT(2)) -#define MCPWM_OP0_UP_EN_V 0x1 -#define MCPWM_OP0_UP_EN_S 2 -/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: A toggle (software negation of value of this bit) will trigger - a forced update of all active registers in MCPWM module*/ -#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_V 0x1 -#define MCPWM_GLOBAL_FORCE_UP_S 1 -/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: The global enable of update of all active registers in MCPWM module*/ -#define MCPWM_GLOBAL_UP_EN (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_V 0x1 -#define MCPWM_GLOBAL_UP_EN_S 0 - -#define MCMCPWM_INT_ENA_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0110) -/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_ENA (BIT(29)) -#define MCPWM_CAP2_INT_ENA_M (BIT(29)) -#define MCPWM_CAP2_INT_ENA_V 0x1 -#define MCPWM_CAP2_INT_ENA_S 29 -/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_ENA (BIT(28)) -#define MCPWM_CAP1_INT_ENA_M (BIT(28)) -#define MCPWM_CAP1_INT_ENA_V 0x1 -#define MCPWM_CAP1_INT_ENA_S 28 -/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_ENA (BIT(27)) -#define MCPWM_CAP0_INT_ENA_M (BIT(27)) -#define MCPWM_CAP0_INT_ENA_V 0x1 -#define MCPWM_CAP0_INT_ENA_S 27 -/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_ENA (BIT(26)) -#define MCPWM_FH2_OST_INT_ENA_M (BIT(26)) -#define MCPWM_FH2_OST_INT_ENA_V 0x1 -#define MCPWM_FH2_OST_INT_ENA_S 26 -/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_ENA (BIT(25)) -#define MCPWM_FH1_OST_INT_ENA_M (BIT(25)) -#define MCPWM_FH1_OST_INT_ENA_V 0x1 -#define MCPWM_FH1_OST_INT_ENA_S 25 -/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_ENA (BIT(24)) -#define MCPWM_FH0_OST_INT_ENA_M (BIT(24)) -#define MCPWM_FH0_OST_INT_ENA_V 0x1 -#define MCPWM_FH0_OST_INT_ENA_S 24 -/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_ENA (BIT(23)) -#define MCPWM_FH2_CBC_INT_ENA_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_ENA_V 0x1 -#define MCPWM_FH2_CBC_INT_ENA_S 23 -/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_ENA (BIT(22)) -#define MCPWM_FH1_CBC_INT_ENA_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_ENA_V 0x1 -#define MCPWM_FH1_CBC_INT_ENA_S 22 -/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_ENA (BIT(21)) -#define MCPWM_FH0_CBC_INT_ENA_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_ENA_V 0x1 -#define MCPWM_FH0_CBC_INT_ENA_S 21 -/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_ENA (BIT(20)) -#define MCPWM_OP2_TEB_INT_ENA_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_ENA_V 0x1 -#define MCPWM_OP2_TEB_INT_ENA_S 20 -/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_ENA (BIT(19)) -#define MCPWM_OP1_TEB_INT_ENA_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_ENA_V 0x1 -#define MCPWM_OP1_TEB_INT_ENA_S 19 -/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_ENA (BIT(18)) -#define MCPWM_OP0_TEB_INT_ENA_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_ENA_V 0x1 -#define MCPWM_OP0_TEB_INT_ENA_S 18 -/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_ENA (BIT(17)) -#define MCPWM_OP2_TEA_INT_ENA_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_ENA_V 0x1 -#define MCPWM_OP2_TEA_INT_ENA_S 17 -/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_ENA (BIT(16)) -#define MCPWM_OP1_TEA_INT_ENA_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_ENA_V 0x1 -#define MCPWM_OP1_TEA_INT_ENA_S 16 -/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_ENA (BIT(15)) -#define MCPWM_OP0_TEA_INT_ENA_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_ENA_V 0x1 -#define MCPWM_OP0_TEA_INT_ENA_S 15 -/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ENA_S 14 -/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ENA_S 13 -/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ENA_S 12 -/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_ENA (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_V 0x1 -#define MCPWM_FAULT2_INT_ENA_S 11 -/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_ENA (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_V 0x1 -#define MCPWM_FAULT1_INT_ENA_S 10 -/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: The enable bit for interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_ENA (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_V 0x1 -#define MCPWM_FAULT0_INT_ENA_S 9 -/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ENA_S 8 -/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ENA_S 7 -/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ENA_S 6 -/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 -/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 -/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 -/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ENA_S 2 -/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ENA_S 1 -/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The enable bit for interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER0_STOP_INT_ENA_S 0 - -#define MCMCPWM_INT_RAW_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0114) -/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_RAW (BIT(29)) -#define MCPWM_CAP2_INT_RAW_M (BIT(29)) -#define MCPWM_CAP2_INT_RAW_V 0x1 -#define MCPWM_CAP2_INT_RAW_S 29 -/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_RAW (BIT(28)) -#define MCPWM_CAP1_INT_RAW_M (BIT(28)) -#define MCPWM_CAP1_INT_RAW_V 0x1 -#define MCPWM_CAP1_INT_RAW_S 28 -/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_RAW (BIT(27)) -#define MCPWM_CAP0_INT_RAW_M (BIT(27)) -#define MCPWM_CAP0_INT_RAW_V 0x1 -#define MCPWM_CAP0_INT_RAW_S 27 -/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_RAW (BIT(26)) -#define MCPWM_FH2_OST_INT_RAW_M (BIT(26)) -#define MCPWM_FH2_OST_INT_RAW_V 0x1 -#define MCPWM_FH2_OST_INT_RAW_S 26 -/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_RAW (BIT(25)) -#define MCPWM_FH1_OST_INT_RAW_M (BIT(25)) -#define MCPWM_FH1_OST_INT_RAW_V 0x1 -#define MCPWM_FH1_OST_INT_RAW_S 25 -/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_RAW (BIT(24)) -#define MCPWM_FH0_OST_INT_RAW_M (BIT(24)) -#define MCPWM_FH0_OST_INT_RAW_V 0x1 -#define MCPWM_FH0_OST_INT_RAW_S 24 -/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_RAW (BIT(23)) -#define MCPWM_FH2_CBC_INT_RAW_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_RAW_V 0x1 -#define MCPWM_FH2_CBC_INT_RAW_S 23 -/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_RAW (BIT(22)) -#define MCPWM_FH1_CBC_INT_RAW_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_RAW_V 0x1 -#define MCPWM_FH1_CBC_INT_RAW_S 22 -/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_RAW (BIT(21)) -#define MCPWM_FH0_CBC_INT_RAW_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_RAW_V 0x1 -#define MCPWM_FH0_CBC_INT_RAW_S 21 -/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_RAW (BIT(20)) -#define MCPWM_OP2_TEB_INT_RAW_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_RAW_V 0x1 -#define MCPWM_OP2_TEB_INT_RAW_S 20 -/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_RAW (BIT(19)) -#define MCPWM_OP1_TEB_INT_RAW_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_RAW_V 0x1 -#define MCPWM_OP1_TEB_INT_RAW_S 19 -/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_RAW (BIT(18)) -#define MCPWM_OP0_TEB_INT_RAW_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_RAW_V 0x1 -#define MCPWM_OP0_TEB_INT_RAW_S 18 -/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_RAW (BIT(17)) -#define MCPWM_OP2_TEA_INT_RAW_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_RAW_V 0x1 -#define MCPWM_OP2_TEA_INT_RAW_S 17 -/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_RAW (BIT(16)) -#define MCPWM_OP1_TEA_INT_RAW_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_RAW_V 0x1 -#define MCPWM_OP1_TEA_INT_RAW_S 16 -/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_RAW (BIT(15)) -#define MCPWM_OP0_TEA_INT_RAW_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_RAW_V 0x1 -#define MCPWM_OP0_TEA_INT_RAW_S 15 -/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT2_CLR_INT_RAW_S 14 -/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT1_CLR_INT_RAW_S 13 -/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT0_CLR_INT_RAW_S 12 -/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_RAW (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_V 0x1 -#define MCPWM_FAULT2_INT_RAW_S 11 -/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_RAW (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_V 0x1 -#define MCPWM_FAULT1_INT_RAW_S 10 -/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: The raw status bit for interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_RAW (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_V 0x1 -#define MCPWM_FAULT0_INT_RAW_S 9 -/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEP_INT_RAW_S 8 -/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEP_INT_RAW_S 7 -/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEP_INT_RAW_S 6 -/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 -/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 -/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 -/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_STOP_INT_RAW_S 2 -/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_STOP_INT_RAW_S 1 -/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The raw status bit for interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER0_STOP_INT_RAW_S 0 - -#define MCMCPWM_INT_ST_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0118) -/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_ST (BIT(29)) -#define MCPWM_CAP2_INT_ST_M (BIT(29)) -#define MCPWM_CAP2_INT_ST_V 0x1 -#define MCPWM_CAP2_INT_ST_S 29 -/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_ST (BIT(28)) -#define MCPWM_CAP1_INT_ST_M (BIT(28)) -#define MCPWM_CAP1_INT_ST_V 0x1 -#define MCPWM_CAP1_INT_ST_S 28 -/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_ST (BIT(27)) -#define MCPWM_CAP0_INT_ST_M (BIT(27)) -#define MCPWM_CAP0_INT_ST_V 0x1 -#define MCPWM_CAP0_INT_ST_S 27 -/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_ST (BIT(26)) -#define MCPWM_FH2_OST_INT_ST_M (BIT(26)) -#define MCPWM_FH2_OST_INT_ST_V 0x1 -#define MCPWM_FH2_OST_INT_ST_S 26 -/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_ST (BIT(25)) -#define MCPWM_FH1_OST_INT_ST_M (BIT(25)) -#define MCPWM_FH1_OST_INT_ST_V 0x1 -#define MCPWM_FH1_OST_INT_ST_S 25 -/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_ST (BIT(24)) -#define MCPWM_FH0_OST_INT_ST_M (BIT(24)) -#define MCPWM_FH0_OST_INT_ST_V 0x1 -#define MCPWM_FH0_OST_INT_ST_S 24 -/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_ST (BIT(23)) -#define MCPWM_FH2_CBC_INT_ST_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_ST_V 0x1 -#define MCPWM_FH2_CBC_INT_ST_S 23 -/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_ST (BIT(22)) -#define MCPWM_FH1_CBC_INT_ST_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_ST_V 0x1 -#define MCPWM_FH1_CBC_INT_ST_S 22 -/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by an cycle-by-cycle - mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_ST (BIT(21)) -#define MCPWM_FH0_CBC_INT_ST_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_ST_V 0x1 -#define MCPWM_FH0_CBC_INT_ST_S 21 -/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_ST (BIT(20)) -#define MCPWM_OP2_TEB_INT_ST_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_ST_V 0x1 -#define MCPWM_OP2_TEB_INT_ST_S 20 -/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_ST (BIT(19)) -#define MCPWM_OP1_TEB_INT_ST_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_ST_V 0x1 -#define MCPWM_OP1_TEB_INT_ST_S 19 -/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_ST (BIT(18)) -#define MCPWM_OP0_TEB_INT_ST_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_ST_V 0x1 -#define MCPWM_OP0_TEB_INT_ST_S 18 -/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_ST (BIT(17)) -#define MCPWM_OP2_TEA_INT_ST_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_ST_V 0x1 -#define MCPWM_OP2_TEA_INT_ST_S 17 -/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_ST (BIT(16)) -#define MCPWM_OP1_TEA_INT_ST_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_ST_V 0x1 -#define MCPWM_OP1_TEA_INT_ST_S 16 -/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_ST (BIT(15)) -#define MCPWM_OP0_TEA_INT_ST_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_ST_V 0x1 -#define MCPWM_OP0_TEA_INT_ST_S 15 -/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ST_S 14 -/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ST_S 13 -/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ST_S 12 -/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_ST (BIT(11)) -#define MCPWM_FAULT2_INT_ST_M (BIT(11)) -#define MCPWM_FAULT2_INT_ST_V 0x1 -#define MCPWM_FAULT2_INT_ST_S 11 -/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_ST (BIT(10)) -#define MCPWM_FAULT1_INT_ST_M (BIT(10)) -#define MCPWM_FAULT1_INT_ST_V 0x1 -#define MCPWM_FAULT1_INT_ST_S 10 -/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: The masked status bit for interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_ST (BIT(9)) -#define MCPWM_FAULT0_INT_ST_M (BIT(9)) -#define MCPWM_FAULT0_INT_ST_V 0x1 -#define MCPWM_FAULT0_INT_ST_S 9 -/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ST_S 8 -/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ST_S 7 -/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ST_S 6 -/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ST_S 5 -/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ST_S 4 -/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ST_S 3 -/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ST_S 2 -/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ST_S 1 -/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The masked status bit for interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER0_STOP_INT_ST_S 0 - -#define MCMCPWM_INT_CLR_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x011c) -/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by captureon channel 2*/ -#define MCPWM_CAP2_INT_CLR (BIT(29)) -#define MCPWM_CAP2_INT_CLR_M (BIT(29)) -#define MCPWM_CAP2_INT_CLR_V 0x1 -#define MCPWM_CAP2_INT_CLR_S 29 -/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by captureon channel 1*/ -#define MCPWM_CAP1_INT_CLR (BIT(28)) -#define MCPWM_CAP1_INT_CLR_M (BIT(28)) -#define MCPWM_CAP1_INT_CLR_V 0x1 -#define MCPWM_CAP1_INT_CLR_S 28 -/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by captureon channel 0*/ -#define MCPWM_CAP0_INT_CLR (BIT(27)) -#define MCPWM_CAP0_INT_CLR_M (BIT(27)) -#define MCPWM_CAP0_INT_CLR_V 0x1 -#define MCPWM_CAP0_INT_CLR_S 27 -/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/ -#define MCPWM_FH2_OST_INT_CLR (BIT(26)) -#define MCPWM_FH2_OST_INT_CLR_M (BIT(26)) -#define MCPWM_FH2_OST_INT_CLR_V 0x1 -#define MCPWM_FH2_OST_INT_CLR_S 26 -/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH1_OST_INT_CLR (BIT(25)) -#define MCPWM_FH1_OST_INT_CLR_M (BIT(25)) -#define MCPWM_FH1_OST_INT_CLR_V 0x1 -#define MCPWM_FH1_OST_INT_CLR_S 25 -/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ -#define MCPWM_FH0_OST_INT_CLR (BIT(24)) -#define MCPWM_FH0_OST_INT_CLR_M (BIT(24)) -#define MCPWM_FH0_OST_INT_CLR_V 0x1 -#define MCPWM_FH0_OST_INT_CLR_S 24 -/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle - mode action on PWM2*/ -#define MCPWM_FH2_CBC_INT_CLR (BIT(23)) -#define MCPWM_FH2_CBC_INT_CLR_M (BIT(23)) -#define MCPWM_FH2_CBC_INT_CLR_V 0x1 -#define MCPWM_FH2_CBC_INT_CLR_S 23 -/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle - mode action on PWM1*/ -#define MCPWM_FH1_CBC_INT_CLR (BIT(22)) -#define MCPWM_FH1_CBC_INT_CLR_M (BIT(22)) -#define MCPWM_FH1_CBC_INT_CLR_V 0x1 -#define MCPWM_FH1_CBC_INT_CLR_S 22 -/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle - mode action on PWM0*/ -#define MCPWM_FH0_CBC_INT_CLR (BIT(21)) -#define MCPWM_FH0_CBC_INT_CLR_M (BIT(21)) -#define MCPWM_FH0_CBC_INT_CLR_V 0x1 -#define MCPWM_FH0_CBC_INT_CLR_S 21 -/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/ -#define MCPWM_OP2_TEB_INT_CLR (BIT(20)) -#define MCPWM_OP2_TEB_INT_CLR_M (BIT(20)) -#define MCPWM_OP2_TEB_INT_CLR_V 0x1 -#define MCPWM_OP2_TEB_INT_CLR_S 20 -/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/ -#define MCPWM_OP1_TEB_INT_CLR (BIT(19)) -#define MCPWM_OP1_TEB_INT_CLR_M (BIT(19)) -#define MCPWM_OP1_TEB_INT_CLR_V 0x1 -#define MCPWM_OP1_TEB_INT_CLR_S 19 -/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/ -#define MCPWM_OP0_TEB_INT_CLR (BIT(18)) -#define MCPWM_OP0_TEB_INT_CLR_M (BIT(18)) -#define MCPWM_OP0_TEB_INT_CLR_V 0x1 -#define MCPWM_OP0_TEB_INT_CLR_S 18 -/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/ -#define MCPWM_OP2_TEA_INT_CLR (BIT(17)) -#define MCPWM_OP2_TEA_INT_CLR_M (BIT(17)) -#define MCPWM_OP2_TEA_INT_CLR_V 0x1 -#define MCPWM_OP2_TEA_INT_CLR_S 17 -/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/ -#define MCPWM_OP1_TEA_INT_CLR (BIT(16)) -#define MCPWM_OP1_TEA_INT_CLR_M (BIT(16)) -#define MCPWM_OP1_TEA_INT_CLR_V 0x1 -#define MCPWM_OP1_TEA_INT_CLR_S 16 -/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/ -#define MCPWM_OP0_TEA_INT_CLR (BIT(15)) -#define MCPWM_OP0_TEA_INT_CLR_M (BIT(15)) -#define MCPWM_OP0_TEA_INT_CLR_V 0x1 -#define MCPWM_OP0_TEA_INT_CLR_S 15 -/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f2 ends*/ -#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT2_CLR_INT_CLR_S 14 -/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f1 ends*/ -#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT1_CLR_INT_CLR_S 13 -/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f0 ends*/ -#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT0_CLR_INT_CLR_S 12 -/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f2 starts*/ -#define MCPWM_FAULT2_INT_CLR (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_V 0x1 -#define MCPWM_FAULT2_INT_CLR_S 11 -/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f1 starts*/ -#define MCPWM_FAULT1_INT_CLR (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_V 0x1 -#define MCPWM_FAULT1_INT_CLR_S 10 -/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: Set this bit to clear interrupt triggered when event_f0 starts*/ -#define MCPWM_FAULT0_INT_CLR (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_V 0x1 -#define MCPWM_FAULT0_INT_CLR_S 9 -/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/ -#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEP_INT_CLR_S 8 -/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/ -#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEP_INT_CLR_S 7 -/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/ -#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEP_INT_CLR_S 6 -/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/ -#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 -/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/ -#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 -/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/ -#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 -/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered when timer 2 stops*/ -#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_STOP_INT_CLR_S 2 -/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered when timer 1 stops*/ -#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_STOP_INT_CLR_S 1 -/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to clear interrupt triggered when timer 0 stops*/ -#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER0_STOP_INT_CLR_S 0 - -#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x0120) -/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Force clock on for this reg file*/ -#define MCPWM_CLK_EN (BIT(0)) -#define MCPWM_CLK_EN_M (BIT(0)) -#define MCPWM_CLK_EN_V 0x1 -#define MCPWM_CLK_EN_S 0 - -#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x0124) -/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */ -/*description: Version of this reg file*/ -#define MCPWM_DATE 0x0FFFFFFF -#define MCPWM_DATE_M ((MCPWM_DATE_V)<<(MCPWM_DATE_S)) -#define MCPWM_DATE_V 0xFFFFFFF -#define MCPWM_DATE_S 0 - - - - -#endif /*_SOC_MCPWM_REG_H_ */ - - diff --git a/components/soc/esp32s2beta/include/soc/mcpwm_struct.h b/components/soc/esp32s2beta/include/soc/mcpwm_struct.h deleted file mode 100644 index f41d40c644..0000000000 --- a/components/soc/esp32s2beta/include/soc/mcpwm_struct.h +++ /dev/null @@ -1,462 +0,0 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_MCPWM_STRUCT_H__ -#define _SOC_MCPWM_STRUCT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ - uint32_t reserved8: 24; - }; - uint32_t val; - }clk_cfg; - struct { - union { - struct { - uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ - uint32_t period: 16; /*period shadow reg of PWM timer0*/ - uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/ - uint32_t reserved26: 6; - }; - uint32_t val; - }period; - union { - struct { - uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ - uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/ - uint32_t reserved5: 27; - }; - uint32_t val; - }mode; - union { - struct { - uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/ - uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/ - uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ - uint32_t timer_phase: 17; /*phase for timer reload on sync event*/ - uint32_t reserved21: 11; - }; - uint32_t val; - }sync; - union { - struct { - uint32_t value: 16; /*current PWM timer0 counter value*/ - uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/ - uint32_t reserved17: 15; - }; - uint32_t val; - }status; - }timer[3]; - - - union { - struct { - uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ - uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ - uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ - uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/ - uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/ - uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/ - uint32_t reserved12: 20; - }; - uint32_t val; - }timer_synci_cfg; - union { - struct { - uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/ - uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/ - uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/ - uint32_t reserved6: 26; - }; - uint32_t val; - }timer_sel; - - - struct { - union { - struct { - uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ - uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ - uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ - uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ - uint32_t reserved10: 22; - }; - uint32_t val; - }cmpr_cfg; - union { - struct { - uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/ - uint32_t reserved16:16; - }; - uint32_t val; - }cmpr_value[2]; - union { - struct { - uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/ - uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ - uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ - uint32_t reserved10: 22; - }; - uint32_t val; - }gen_cfg0; - union { - struct { - uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/ - uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/ - uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/ - uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/ - uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/ - uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/ - uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/ - uint32_t reserved16: 16; - }; - uint32_t val; - }gen_force; - union { - struct { - uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/ - uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/ - uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/ - uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/ - uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/ - uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/ - uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/ - uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/ - uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/ - uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/ - uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/ - uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/ - uint32_t reserved24: 8; - }; - uint32_t val; - }generator[2]; - union { - struct { - uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ - uint32_t a_outswap: 1; /*S6 in documentation*/ - uint32_t b_outswap: 1; /*S7 in documentation*/ - uint32_t red_insel: 1; /*S4 in documentation*/ - uint32_t fed_insel: 1; /*S5 in documentation*/ - uint32_t red_outinvert: 1; /*S2 in documentation*/ - uint32_t fed_outinvert: 1; /*S3 in documentation*/ - uint32_t a_outbypass: 1; /*S1 in documentation*/ - uint32_t b_outbypass: 1; /*S0 in documentation*/ - uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/ - uint32_t reserved18: 14; - }; - uint32_t val; - }db_cfg; - union { - struct { - uint32_t fed: 16; /*Shadow reg for FED*/ - uint32_t reserved16:16; - }; - uint32_t val; - }db_fed_cfg; - union { - struct { - uint32_t red: 16; /*Shadow reg for RED*/ - uint32_t reserved16:16; - }; - uint32_t val; - }db_red_cfg; - union { - struct { - uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/ - uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ - uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ - uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/ - uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/ - uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/ - uint32_t reserved14: 18; - }; - uint32_t val; - }carrier_cfg; - union { - struct { - uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ - uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/ - uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t reserved24: 8; - }; - uint32_t val; - }tz_cfg0; - union { - struct { - uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/ - uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/ - uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/ - uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/ - uint32_t reserved5: 27; - }; - uint32_t val; - }tz_cfg1; - union { - struct { - uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/ - uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/ - uint32_t reserved2: 30; - }; - uint32_t val; - }tz_status; - }channel[3]; - - union { - struct { - uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/ - uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/ - uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/ - uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ - uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ - uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ - uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/ - uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/ - uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/ - uint32_t reserved9: 23; - }; - uint32_t val; - }fault_detect; - union { - struct { - uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/ - uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/ - uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ - uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/ - uint32_t reserved6: 26; - }; - uint32_t val; - }cap_timer_cfg; - uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/ - union { - struct { - uint32_t en: 1; /*When set capture on channel 0 is enabled*/ - uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/ - uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/ - uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/ - uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/ - uint32_t reserved13: 19; - }; - uint32_t val; - }cap_cfg_ch[3]; - uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/ - union { - struct { - uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ - uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ - uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ - uint32_t reserved3: 29; - }; - uint32_t val; - }cap_status; - union { - struct { - uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/ - uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/ - uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/ - uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/ - uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/ - uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/ - uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/ - uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/ - uint32_t reserved8: 24; - }; - uint32_t val; - }update_cfg; - union { - struct { - uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30: 2; - }; - uint32_t val; - }int_ena; - union { - struct { - uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30: 2; - }; - uint32_t val; - }int_raw; - union { - struct { - uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30: 2; - }; - uint32_t val; - }int_st; - union { - struct { - uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/ - uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/ - uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/ - uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ - uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ - uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ - uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ - uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ - uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ - uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/ - uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/ - uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/ - uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/ - uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/ - uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/ - uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ - uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ - uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ - uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ - uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ - uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ - uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ - uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ - uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ - uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ - uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/ - uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/ - uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/ - uint32_t reserved30: 2; - }; - uint32_t val; - }int_clr; - union { - struct { - uint32_t clk_en: 1; /*Force clock on for this reg file*/ - uint32_t reserved1: 31; - }; - uint32_t val; - }reg_clk; - union { - struct { - uint32_t date: 28; /*Version of this reg file*/ - uint32_t reserved28: 4; - }; - uint32_t val; - }version; -} mcpwm_dev_t; -extern mcpwm_dev_t MCPWM0; -extern mcpwm_dev_t MCPWM1; - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_MCPWM_STRUCT_H__ */ diff --git a/components/soc/esp32s2beta/include/soc/soc_caps.h b/components/soc/esp32s2beta/include/soc/soc_caps.h new file mode 100644 index 0000000000..fc6db81782 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/soc_caps.h @@ -0,0 +1,4 @@ +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// seperate these information into periph_caps.h for each peripheral and +// include them here. diff --git a/components/soc/include/soc/soc_memory_layout.h b/components/soc/include/soc/soc_memory_layout.h index 3f614a4535..75c8c7daa6 100644 --- a/components/soc/include/soc/soc_memory_layout.h +++ b/components/soc/include/soc/soc_memory_layout.h @@ -163,9 +163,12 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p) intptr_t ip = (intptr_t) p; bool r; r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH); -#if CONFIG_SPIRAM && CONFIG_SPIRAM_SIZE - // ToDo: Use SOC_EXTRAM_DATA_HIGH if CONFIG_SPIRAM_SIZE is -1 (ie max possible SPIRAM size) +#if CONFIG_SPIRAM +#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE)); +#else + r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_HIGH)); +#endif #endif return r; } diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index 63b19cd968..756ef6767d 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -4,7 +4,7 @@ if(BOOTLOADER_BUILD) # but on other platforms no source files are needed for bootloader set(srcs) else() - set(srcs + set(srcs "cache_utils.c" "flash_mmap.c" "flash_ops.c" @@ -27,7 +27,7 @@ else() set(priv_requires bootloader_support app_update soc) endif() -if(CONFIG_IDF_TARGET_ESP32) +if(IDF_TARGET STREQUAL "esp32") list(APPEND srcs "spi_flash_rom_patch.c") endif() diff --git a/components/spi_flash/test/CMakeLists.txt b/components/spi_flash/test/CMakeLists.txt index ae23154f2f..a9c011d315 100644 --- a/components/spi_flash/test/CMakeLists.txt +++ b/components/spi_flash/test/CMakeLists.txt @@ -1,3 +1,7 @@ -idf_component_register(SRC_DIRS "." +set(src_dirs ".") +if(IDF_TARGET STREQUAL "esp32") + list(APPEND src_dirs "esp32") +endif() +idf_component_register(SRC_DIRS ${src_dirs} INCLUDE_DIRS "." REQUIRES unity test_utils spi_flash bootloader_support app_update) \ No newline at end of file diff --git a/components/spi_flash/test/component.mk b/components/spi_flash/test/component.mk index 5dd172bdb7..b2b7d9048f 100644 --- a/components/spi_flash/test/component.mk +++ b/components/spi_flash/test/component.mk @@ -2,4 +2,5 @@ #Component Makefile # +COMPONENT_SRCDIRS += esp32 COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive diff --git a/components/spi_flash/test/test_esp_flash.c b/components/spi_flash/test/esp32/test_esp_flash.c similarity index 100% rename from components/spi_flash/test/test_esp_flash.c rename to components/spi_flash/test/esp32/test_esp_flash.c diff --git a/components/spi_flash/test/test_partition_ext.c b/components/spi_flash/test/esp32/test_partition_ext.c similarity index 100% rename from components/spi_flash/test/test_partition_ext.c rename to components/spi_flash/test/esp32/test_partition_ext.c diff --git a/components/spi_flash/test/test_mmap.c b/components/spi_flash/test/test_mmap.c index 52a5be1f3a..4b8841e960 100644 --- a/components/spi_flash/test/test_mmap.c +++ b/components/spi_flash/test/test_mmap.c @@ -75,7 +75,7 @@ static void setup_mmap_tests(void) } } -TEST_CASE("Can mmap into data address space", "[spi_flash]") +TEST_CASE_ESP32("Can mmap into data address space", "[spi_flash]") { setup_mmap_tests(); @@ -135,7 +135,7 @@ TEST_CASE("Can mmap into data address space", "[spi_flash]") TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA)); } -TEST_CASE("Can mmap into instruction address space", "[mmap]") +TEST_CASE_ESP32("Can mmap into instruction address space", "[mmap]") { setup_mmap_tests(); @@ -183,7 +183,7 @@ TEST_CASE("Can mmap into instruction address space", "[mmap]") } -TEST_CASE("Can mmap unordered pages into contiguous memory", "[spi_flash]") +TEST_CASE_ESP32("Can mmap unordered pages into contiguous memory", "[spi_flash]") { int nopages; int *pages; @@ -324,7 +324,7 @@ TEST_CASE("flash_mmap can mmap after get enough free MMU pages", "[spi_flash]") TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA)); } -TEST_CASE("phys2cache/cache2phys basic checks", "[spi_flash]") +TEST_CASE_ESP32("phys2cache/cache2phys basic checks", "[spi_flash]") { uint8_t buf[64]; @@ -401,7 +401,7 @@ TEST_CASE("munmap followed by mmap flushes cache", "[spi_flash]") TEST_ASSERT_NOT_EQUAL(0, memcmp(buf, data, sizeof(buf))); } -TEST_CASE("no stale data read post mmap and write partition", "[spi_flash]") +TEST_CASE_ESP32("no stale data read post mmap and write partition", "[spi_flash]") { const char buf[] = "Test buffer data for partition"; char read_data[sizeof(buf)]; diff --git a/components/spi_flash/test/test_read_write.c b/components/spi_flash/test/test_read_write.c index 09ed0073af..00732f1abd 100644 --- a/components/spi_flash/test/test_read_write.c +++ b/components/spi_flash/test/test_read_write.c @@ -167,7 +167,7 @@ static void IRAM_ATTR test_write(int dst_off, int src_off, int len) TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0); } -TEST_CASE("Test spi_flash_write", "[spi_flash][esp_flash]") +TEST_CASE_ESP32("Test spi_flash_write", "[spi_flash][esp_flash]") { setup_tests(); #if CONFIG_SPI_FLASH_MINIMAL_TEST diff --git a/components/ulp/test/CMakeLists.txt b/components/ulp/test/CMakeLists.txt index 27311f9530..bbcb38f156 100644 --- a/components/ulp/test/CMakeLists.txt +++ b/components/ulp/test/CMakeLists.txt @@ -1,8 +1,10 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - REQUIRES unity ulp soc esp_common) +if(IDF_TARGET STREQUAL "esp32") + idf_component_register(SRC_DIRS esp32 + INCLUDE_DIRS . + REQUIRES unity ulp soc esp_common) -set(ulp_app_name ulp_test_app) -set(ulp_s_sources "ulp/test_jumps.S") -set(ulp_exp_dep_srcs "test_ulp_as.c") -ulp_embed_binary(${ulp_app_name} ${ulp_s_sources} ${ulp_exp_dep_srcs}) + set(ulp_app_name ulp_test_app) + set(ulp_s_sources "ulp/test_jumps_esp32.S") + set(ulp_exp_dep_srcs "esp32/test_ulp_as.c") + ulp_embed_binary(${ulp_app_name} ${ulp_s_sources} ${ulp_exp_dep_srcs}) +endif() diff --git a/components/ulp/test/component.mk b/components/ulp/test/component.mk index 84d7727d7e..7cd2406dec 100644 --- a/components/ulp/test/component.mk +++ b/components/ulp/test/component.mk @@ -1,11 +1,13 @@ ULP_APP_NAME = ulp_test_app +COMPONENT_SRCDIRS += esp32 + ULP_S_SOURCES = $(addprefix $(COMPONENT_PATH)/ulp/, \ - test_jumps.S \ + test_jumps_esp32.S \ ) -ULP_EXP_DEP_OBJECTS := test_ulp_as.o - +ULP_EXP_DEP_OBJECTS := esp32/test_ulp_as.o + include $(IDF_PATH)/components/ulp/component_ulp_common.mk COMPONENT_ADD_LDFLAGS += -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive diff --git a/components/ulp/test/test_ulp.c b/components/ulp/test/esp32/test_ulp.c similarity index 100% rename from components/ulp/test/test_ulp.c rename to components/ulp/test/esp32/test_ulp.c diff --git a/components/ulp/test/test_ulp_as.c b/components/ulp/test/esp32/test_ulp_as.c similarity index 100% rename from components/ulp/test/test_ulp_as.c rename to components/ulp/test/esp32/test_ulp_as.c diff --git a/components/ulp/test/ulp/test_jumps.S b/components/ulp/test/ulp/test_jumps_esp32.S similarity index 100% rename from components/ulp/test/ulp/test_jumps.S rename to components/ulp/test/ulp/test_jumps_esp32.S diff --git a/components/unity/include/unity_test_runner.h b/components/unity/include/unity_test_runner.h index e9e46ebd43..8e8b5a3dae 100644 --- a/components/unity/include/unity_test_runner.h +++ b/components/unity/include/unity_test_runner.h @@ -130,6 +130,8 @@ void unity_testcase_register(test_desc_t* desc); unity_testcase_register( & UNITY_TEST_UID(test_desc_) ); \ } + + /* * First argument is a free-form description, * second argument is (by convention) a list of identifiers, each one in square brackets. @@ -172,3 +174,14 @@ void unity_run_all_tests(void); void unity_run_menu(void); +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32 +#define TEST_CASE_ESP32(...) TEST_CASE(__VA_ARGS__) +#define TEST_CASE_MULTIPLE_STAGES_ESP32(...) TEST_CASE_MULTIPLE_STAGES(__VA_ARGS__) +#define TEST_CASE_MULTIPLE_DEVICES_ESP32(...) TEST_CASE_MULTIPLE_DEVICES(__VA_ARGS__) +#else +#define TEST_CASE_ESP32(...) __attribute__((unused)) static void UNITY_TEST_UID(test_func_) (void) +#define TEST_CASE_MULTIPLE_STAGES_ESP32(_, __, ...) __attribute__((unused)) static test_func UNITY_TEST_UID(test_functions)[] = {__VA_ARGS__}; +#define TEST_CASE_MULTIPLE_DEVICES_ESP32(_, __, ...) __attribute__((unused)) static test_func UNITY_TEST_UID(test_functions)[] = {__VA_ARGS__}; + +#endif diff --git a/components/vfs/test/CMakeLists.txt b/components/vfs/test/CMakeLists.txt index f0a24edd9f..2e15ead8db 100644 --- a/components/vfs/test/CMakeLists.txt +++ b/components/vfs/test/CMakeLists.txt @@ -1,4 +1,10 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - REQUIRES unity test_utils vfs fatfs spiffs - LDFRAGMENTS linker.lf) \ No newline at end of file +set(srcdirs ".") +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcdirs "esp32") +endif() + +idf_component_register(SRC_DIRS ${srcdirs} + INCLUDE_DIRS . + REQUIRES unity test_utils vfs fatfs spiffs + LDFRAGMENTS linker.lf + ) diff --git a/components/vfs/test/component.mk b/components/vfs/test/component.mk index 5650ced1ee..5ad4f756e5 100644 --- a/components/vfs/test/component.mk +++ b/components/vfs/test/component.mk @@ -1,3 +1,4 @@ COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive +COMPONENT_SRCDIRS += esp32 COMPONENT_ADD_LDFRAGMENTS += linker.lf diff --git a/components/vfs/test/test_vfs_uart.c b/components/vfs/test/esp32/test_vfs_uart.c similarity index 100% rename from components/vfs/test/test_vfs_uart.c rename to components/vfs/test/esp32/test_vfs_uart.c diff --git a/components/vfs/test/test_vfs_fd.c b/components/vfs/test/test_vfs_fd.c index 75be13a654..d3b242a561 100644 --- a/components/vfs/test/test_vfs_fd.c +++ b/components/vfs/test/test_vfs_fd.c @@ -232,7 +232,7 @@ static int time_test_vfs_write(int fd, const void *data, size_t size) return size; } -TEST_CASE("Open & write & close through VFS passes performance test", "[vfs]") +TEST_CASE_ESP32("Open & write & close through VFS passes performance test", "[vfs]") { esp_vfs_t desc = { .flags = ESP_VFS_FLAG_DEFAULT, diff --git a/components/wear_levelling/test/CMakeLists.txt b/components/wear_levelling/test/CMakeLists.txt index a81bf5a8e5..684960dac3 100644 --- a/components/wear_levelling/test/CMakeLists.txt +++ b/components/wear_levelling/test/CMakeLists.txt @@ -1,4 +1,11 @@ -idf_component_register(SRC_DIRS "." - INCLUDE_DIRS "." - REQUIRES unity test_utils wear_levelling - EMBED_FILES test_partition_v1.bin) \ No newline at end of file +set(srcdirs .) +if(IDF_TARGET STREQUAL "esp32") + list(APPEND srcdirs esp32) +endif() + + +idf_component_register(SRC_DIRS ${srcdirs} + INCLUDE_DIRS . + REQUIRES unity test_utils wear_levelling + EMBED_FILES test_partition_v1.bin + ) diff --git a/components/wear_levelling/test/component.mk b/components/wear_levelling/test/component.mk index 47bab96485..002a9f6b7c 100644 --- a/components/wear_levelling/test/component.mk +++ b/components/wear_levelling/test/component.mk @@ -1,2 +1,3 @@ COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_EMBED_FILES := test_partition_v1.bin +COMPONENT_SRCDIRS += esp32 diff --git a/components/wear_levelling/test/esp32/test_wl.c b/components/wear_levelling/test/esp32/test_wl.c new file mode 100644 index 0000000000..4ea0b3f2b3 --- /dev/null +++ b/components/wear_levelling/test/esp32/test_wl.c @@ -0,0 +1,88 @@ +#include +#include "unity.h" +#include "wear_levelling.h" +#include "test_utils.h" +#include "freertos/FreeRTOS.h" +#include "freertos/portable.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "soc/cpu.h" + +#include "esp32/clk.h" + + +#define TEST_SECTORS_COUNT 8 + +static void check_mem_data(wl_handle_t handle, uint32_t init_val, uint32_t* buff) +{ + size_t sector_size = wl_sector_size(handle); + + for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) { + TEST_ESP_OK(wl_read(handle, sector_size * m, buff, sector_size)); + for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) { + uint32_t compare_val = init_val + i + m*sector_size; + TEST_ASSERT_EQUAL( buff[i], compare_val); + } + } +} + + +// We write complete memory with defined data +// And then write one sector many times. +// A data in other secors should be the same. +// We do this also with unmount +TEST_CASE("multiple write is correct", "[wear_levelling]") +{ + const esp_partition_t *partition = get_test_data_partition(); + esp_partition_t fake_partition; + memcpy(&fake_partition, partition, sizeof(fake_partition)); + + fake_partition.size = SPI_FLASH_SEC_SIZE*(4 + TEST_SECTORS_COUNT); + + wl_handle_t handle; + TEST_ESP_OK(wl_mount(&fake_partition, &handle)); + + size_t sector_size = wl_sector_size(handle); + // Erase 8 sectors + TEST_ESP_OK(wl_erase_range(handle, 0, sector_size * TEST_SECTORS_COUNT)); + // Write data to all sectors + printf("Check 1 sector_size=0x%08x\n", sector_size); + // Set initial random value + uint32_t init_val = rand(); + + uint32_t* buff = (uint32_t*)malloc(sector_size); + for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) { + for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) { + buff[i] = init_val + i + m*sector_size; + } + TEST_ESP_OK(wl_erase_range(handle, sector_size*m, sector_size)); + TEST_ESP_OK(wl_write(handle, sector_size*m, buff, sector_size)); + } + + check_mem_data(handle, init_val, buff); + + uint32_t start; + RSR(CCOUNT, start); + + + for (int m=0 ; m< 100000 ; m++) { + uint32_t sector = m % TEST_SECTORS_COUNT; + for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) { + buff[i] = init_val + i + sector*sector_size; + } + TEST_ESP_OK(wl_erase_range(handle, sector_size*sector, sector_size)); + TEST_ESP_OK(wl_write(handle, sector_size*sector, buff, sector_size)); + check_mem_data(handle, init_val, buff); + + uint32_t end; + RSR(CCOUNT, end); + uint32_t ms = (end - start) / (esp_clk_cpu_freq() / 1000); + printf("loop %4i pass, time= %ims\n", m, ms); + if (ms > 10000) { + break; + } + } + + free(buff); + wl_unmount(handle); +} \ No newline at end of file diff --git a/components/wear_levelling/test/test_wl.c b/components/wear_levelling/test/test_wl.c index 09ef23bfec..c0abe88acc 100644 --- a/components/wear_levelling/test/test_wl.c +++ b/components/wear_levelling/test/test_wl.c @@ -6,7 +6,6 @@ #include "freertos/portable.h" #include "freertos/task.h" #include "freertos/semphr.h" -#include "esp32/clk.h" #include "soc/cpu.h" TEST_CASE("wl_unmount doesn't leak memory", "[wear_levelling]") @@ -23,7 +22,7 @@ TEST_CASE("wl_unmount doesn't leak memory", "[wear_levelling]") // Original code: //TEST_ASSERT_EQUAL_HEX32(size_before, size_after); // Workaround for problem with heap size calculation: - ptrdiff_t stack_diff = size_before - size_after; + ptrdiff_t stack_diff = size_before - size_after; stack_diff = abs(stack_diff); if (stack_diff > 8) TEST_ASSERT_EQUAL(0, stack_diff); } @@ -49,7 +48,7 @@ TEST_CASE("wl_mount check partition parameters", "[wear_levelling][ignore]") // Original code: //TEST_ASSERT_EQUAL_HEX32(size_before, size_after); // Workaround for problem with heap size calculation: - ptrdiff_t stack_diff = size_before - size_after; + ptrdiff_t stack_diff = size_before - size_after; stack_diff = abs(stack_diff); if (stack_diff > 8) TEST_ASSERT_EQUAL(0, stack_diff); } @@ -65,7 +64,7 @@ TEST_CASE("wl_mount check partition parameters", "[wear_levelling][ignore]") // Original code: //TEST_ASSERT_EQUAL_HEX32(size_before, size_after); // Workaround for problem with heap size calculation: - ptrdiff_t stack_diff = size_before - size_after; + ptrdiff_t stack_diff = size_before - size_after; stack_diff = abs(stack_diff); if (stack_diff > 8) TEST_ASSERT_EQUAL(0, stack_diff); } @@ -177,81 +176,6 @@ TEST_CASE("multiple tasks can access wl handle simultaneously", "[wear_levelling wl_unmount(handle); } -#define TEST_SECTORS_COUNT 8 - -static void check_mem_data(wl_handle_t handle, uint32_t init_val, uint32_t* buff) -{ - size_t sector_size = wl_sector_size(handle); - - for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) { - TEST_ESP_OK(wl_read(handle, sector_size * m, buff, sector_size)); - for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) { - uint32_t compare_val = init_val + i + m*sector_size; - TEST_ASSERT_EQUAL( buff[i], compare_val); - } - } -} - - -// We write complete memory with defined data -// And then write one sector many times. -// A data in other secors should be the same. -// We do this also with unmount -TEST_CASE("multiple write is correct", "[wear_levelling]") -{ - const esp_partition_t *partition = get_test_data_partition(); - esp_partition_t fake_partition; - memcpy(&fake_partition, partition, sizeof(fake_partition)); - - fake_partition.size = SPI_FLASH_SEC_SIZE*(4 + TEST_SECTORS_COUNT); - - wl_handle_t handle; - TEST_ESP_OK(wl_mount(&fake_partition, &handle)); - - size_t sector_size = wl_sector_size(handle); - // Erase 8 sectors - TEST_ESP_OK(wl_erase_range(handle, 0, sector_size * TEST_SECTORS_COUNT)); - // Write data to all sectors - printf("Check 1 sector_size=0x%08x\n", sector_size); - // Set initial random value - uint32_t init_val = rand(); - - uint32_t* buff = (uint32_t*)malloc(sector_size); - for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) { - for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) { - buff[i] = init_val + i + m*sector_size; - } - TEST_ESP_OK(wl_erase_range(handle, sector_size*m, sector_size)); - TEST_ESP_OK(wl_write(handle, sector_size*m, buff, sector_size)); - } - - check_mem_data(handle, init_val, buff); - - uint32_t start; - RSR(CCOUNT, start); - - - for (int m=0 ; m< 100000 ; m++) { - uint32_t sector = m % TEST_SECTORS_COUNT; - for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) { - buff[i] = init_val + i + sector*sector_size; - } - TEST_ESP_OK(wl_erase_range(handle, sector_size*sector, sector_size)); - TEST_ESP_OK(wl_write(handle, sector_size*sector, buff, sector_size)); - check_mem_data(handle, init_val, buff); - - uint32_t end; - RSR(CCOUNT, end); - uint32_t ms = (end - start) / (esp_clk_cpu_freq() / 1000); - printf("loop %4i pass, time= %ims\n", m, ms); - if (ms > 10000) { - break; - } - } - - free(buff); - wl_unmount(handle); -} extern const uint8_t test_partition_v1_bin_start[] asm("_binary_test_partition_v1_bin_start"); extern const uint8_t test_partition_v1_bin_end[] asm("_binary_test_partition_v1_bin_end"); @@ -259,7 +183,7 @@ extern const uint8_t test_partition_v1_bin_end[] asm("_binary_test_partition_v #define COMPARE_START_CONST 0x12340000 // We write to partition prepared image with V1 -// Then we convert image to new version and verifying the data +// Then we convert image to new version and verifying the data TEST_CASE("Version update test", "[wear_levelling]") { @@ -269,7 +193,7 @@ TEST_CASE("Version update test", "[wear_levelling]") if (partition->encrypted) { - printf("Update from V1 to V2 will not work.\n"); + printf("Update from V1 to V2 will not work.\n"); return; } fake_partition.size = (size_t)(test_partition_v1_bin_end - test_partition_v1_bin_start); diff --git a/components/wpa_supplicant/test/test_crypto.c b/components/wpa_supplicant/test/test_crypto.c index e8f8d05a5f..344c9daf6b 100644 --- a/components/wpa_supplicant/test/test_crypto.c +++ b/components/wpa_supplicant/test/test_crypto.c @@ -23,7 +23,7 @@ #include "mbedtls/ecp.h" typedef struct crypto_bignum crypto_bignum; -TEST_CASE("Test crypto lib bignum apis", "[wpa_crypto]") +TEST_CASE_ESP32("Test crypto lib bignum apis", "[wpa_crypto]") { { diff --git a/components/xtensa/CMakeLists.txt b/components/xtensa/CMakeLists.txt index ce33679c27..5c335ffddc 100644 --- a/components/xtensa/CMakeLists.txt +++ b/components/xtensa/CMakeLists.txt @@ -6,9 +6,12 @@ else() set(srcs "debug_helpers.c" "debug_helpers_asm.S" "eri.c" - "stdatomic.c") + ) - if(CONFIG_IDF_TARGET_ESP32) + if(IDF_TARGET STREQUAL "esp32s2beta") + list(APPEND srcs "stdatomic.c") + endif() + if(IDF_TARGET STREQUAL "esp32") list(APPEND srcs "trax.c") endif() endif() diff --git a/examples/bluetooth/nimble/blecent/blecent_test_noci.py b/examples/bluetooth/nimble/blecent/blecent_test_noci.py index d1d79298c4..a305797355 100644 --- a/examples/bluetooth/nimble/blecent/blecent_test_noci.py +++ b/examples/bluetooth/nimble/blecent/blecent_test_noci.py @@ -27,6 +27,7 @@ try: if test_fw_path and test_fw_path not in sys.path: sys.path.insert(0, test_fw_path) import IDF + from IDF.IDFDUT import ESP32DUT except ImportError as e: print(e) print("\nCheck your IDF_PATH\nOR") @@ -65,7 +66,7 @@ def test_example_app_ble_central(env, extra_data): adv_uuid = '1811' # Acquire DUT - dut = env.get_dut("blecent", "examples/bluetooth/nimble/blecent") + dut = env.get_dut("blecent", "examples/bluetooth/nimble/blecent", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut.app.binary_path, "blecent.bin") diff --git a/examples/bluetooth/nimble/blehr/blehr_test_noci.py b/examples/bluetooth/nimble/blehr/blehr_test_noci.py index 81f21ee92b..76cf2d4020 100644 --- a/examples/bluetooth/nimble/blehr/blehr_test_noci.py +++ b/examples/bluetooth/nimble/blehr/blehr_test_noci.py @@ -27,6 +27,7 @@ try: if test_fw_path and test_fw_path not in sys.path: sys.path.insert(0, test_fw_path) import IDF + from IDF.IDFDUT import ESP32DUT except ImportError as e: print(e) print("\nCheck your IDF_PATH\nOR") @@ -113,7 +114,7 @@ def test_example_app_ble_hr(env, extra_data): """ try: # Acquire DUT - dut = env.get_dut("blehr", "examples/bluetooth/nimble/blehr") + dut = env.get_dut("blehr", "examples/bluetooth/nimble/blehr", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut.app.binary_path, "blehr.bin") diff --git a/examples/bluetooth/nimble/bleprph/bleprph_test_noci.py b/examples/bluetooth/nimble/bleprph/bleprph_test_noci.py index 3e29f668c2..0a1a1aa62d 100644 --- a/examples/bluetooth/nimble/bleprph/bleprph_test_noci.py +++ b/examples/bluetooth/nimble/bleprph/bleprph_test_noci.py @@ -27,6 +27,7 @@ try: if test_fw_path and test_fw_path not in sys.path: sys.path.insert(0, test_fw_path) import IDF + from IDF.IDFDUT import ESP32DUT except ImportError as e: print(e) print("Try `export TEST_FW_PATH=$IDF_PATH/tools/tiny-test-fw` for resolving the issue") @@ -136,7 +137,7 @@ def test_example_app_ble_peripheral(env, extra_data): try: # Acquire DUT - dut = env.get_dut("bleprph", "examples/bluetooth/nimble/bleprph") + dut = env.get_dut("bleprph", "examples/bluetooth/nimble/bleprph", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut.app.binary_path, "bleprph.bin") diff --git a/examples/get-started/blink/example_test.py b/examples/get-started/blink/example_test.py index 91b0f9bc0e..fbe274beab 100644 --- a/examples/get-started/blink/example_test.py +++ b/examples/get-started/blink/example_test.py @@ -10,6 +10,7 @@ import hashlib try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # This environment variable is expected on the host machine test_fw_path = os.getenv("TEST_FW_PATH") @@ -40,7 +41,7 @@ def verify_elf_sha256_embedding(dut): @IDF.idf_example_test(env_tag="Example_WIFI") def test_examples_blink(env, extra_data): - dut = env.get_dut("blink", "examples/get-started/blink") + dut = env.get_dut("blink", "examples/get-started/blink", dut_class=ESP32DUT) binary_file = os.path.join(dut.app.binary_path, "blink.bin") bin_size = os.path.getsize(binary_file) IDF.log_performance("blink_bin_size", "{}KB".format(bin_size // 1024)) diff --git a/examples/peripherals/can/can_alert_and_recovery/example_test.py b/examples/peripherals/can/can_alert_and_recovery/example_test.py index 21341ed4c1..47b5ef7a8f 100644 --- a/examples/peripherals/can/can_alert_and_recovery/example_test.py +++ b/examples/peripherals/can/can_alert_and_recovery/example_test.py @@ -6,6 +6,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # The test cause is dependent on the Tiny Test Framework. Ensure the # `TEST_FW_PATH` environment variable is set to `$IDF_PATH/tools/tiny-test-fw` @@ -22,7 +23,7 @@ EXPECT_TIMEOUT = 20 @IDF.idf_example_test(env_tag='Example_CAN') def test_can_alert_and_recovery_example(env, extra_data): # Get device under test, flash and start example. "dut4" must be defined in EnvConfig - dut = env.get_dut('dut4', 'examples/peripherals/can/can_alert_and_recovery') + dut = env.get_dut('dut4', 'examples/peripherals/can/can_alert_and_recovery', dut_class=ESP32DUT) dut.start_app() for string in STR_EXPECT: diff --git a/examples/peripherals/can/can_network/example_test.py b/examples/peripherals/can/can_network/example_test.py index d8f249bc5f..2be9b6648f 100644 --- a/examples/peripherals/can/can_network/example_test.py +++ b/examples/peripherals/can/can_network/example_test.py @@ -6,6 +6,7 @@ import sys from threading import Thread try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # The test cause is dependent on the Tiny Test Framework. Ensure the # `TEST_FW_PATH` environment variable is set to `$IDF_PATH/tools/tiny-test-fw` @@ -40,9 +41,9 @@ def dut_thread_callback(**kwargs): def test_can_network_example(env, extra_data): # Get device under test. "dut1", "dut2", and "dut3" must be properly defined in EnvConfig - dut_master = env.get_dut("dut1", "examples/peripherals/can/can_network/can_network_master") - dut_slave = env.get_dut("dut2", "examples/peripherals/can/can_network/can_network_slave") - dut_listen_only = env.get_dut("dut3", "examples/peripherals/can/can_network/can_network_listen_only") + dut_master = env.get_dut("dut1", "examples/peripherals/can/can_network/can_network_master", dut_class=ESP32DUT) + dut_slave = env.get_dut("dut2", "examples/peripherals/can/can_network/can_network_slave", dut_class=ESP32DUT) + dut_listen_only = env.get_dut("dut3", "examples/peripherals/can/can_network/can_network_listen_only", dut_class=ESP32DUT) # Flash app onto each DUT, each DUT is reset again at the start of each thread dut_master.start_app() diff --git a/examples/peripherals/can/can_self_test/example_test.py b/examples/peripherals/can/can_self_test/example_test.py index 28b1f4eb8b..cea1b881ee 100644 --- a/examples/peripherals/can/can_self_test/example_test.py +++ b/examples/peripherals/can/can_self_test/example_test.py @@ -5,6 +5,7 @@ import os import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # The test cause is dependent on the Tiny Test Framework. Ensure the # `TEST_FW_PATH` environment variable is set to `$IDF_PATH/tools/tiny-test-fw` @@ -22,7 +23,7 @@ EXPECT_TIMEOUT = 20 @IDF.idf_example_test(env_tag='Example_CAN') def test_can_self_test_example(env, extra_data): # Get device under test, flash and start example. "dut4" must be defined in EnvConfig - dut = env.get_dut('dut4', 'examples/peripherals/can/can_self_test') + dut = env.get_dut('dut4', 'examples/peripherals/can/can_self_test', dut_class=ESP32DUT) dut.start_app() for string in STR_EXPECT: diff --git a/examples/peripherals/i2c/i2c_tools/example_test.py b/examples/peripherals/i2c/i2c_tools/example_test.py index a42a0f0740..0f0c2271d5 100644 --- a/examples/peripherals/i2c/i2c_tools/example_test.py +++ b/examples/peripherals/i2c/i2c_tools/example_test.py @@ -6,6 +6,7 @@ EXPECT_TIMEOUT = 20 try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv("TEST_FW_PATH") if test_fw_path and test_fw_path not in sys.path: @@ -16,7 +17,7 @@ except ImportError: @IDF.idf_example_test(env_tag='Example_I2C_CCS811_SENSOR') def test_i2ctools_example(env, extra_data): # Get device under test, flash and start example. "i2ctool" must be defined in EnvConfig - dut = env.get_dut('i2ctools', 'examples/peripherals/i2c/i2c_tools') + dut = env.get_dut('i2ctools', 'examples/peripherals/i2c/i2c_tools', dut_class=ESP32DUT) dut.start_app() dut.expect("esp32>", timeout=EXPECT_TIMEOUT) # Get i2c address diff --git a/examples/peripherals/sdio/sdio_test.py b/examples/peripherals/sdio/sdio_test.py index 8361dc3c86..0fa8b2979f 100644 --- a/examples/peripherals/sdio/sdio_test.py +++ b/examples/peripherals/sdio/sdio_test.py @@ -27,6 +27,7 @@ except ImportError: import TinyFW import IDF +from IDF.IDFDUT import ESP32DUT @IDF.idf_example_test(env_tag="Example_SDIO", ignore=True) @@ -49,8 +50,8 @@ def test_example_sdio_communication(env, extra_data): or use sdio test board, which has two wrover modules connect to a same FT3232 Assume that first dut is host and second is slave """ - dut1 = env.get_dut("sdio_host", "examples/peripherals/sdio/host") - dut2 = env.get_dut("sdio_slave", "examples/peripherals/sdio/slave") + dut1 = env.get_dut("sdio_host", "examples/peripherals/sdio/host", dut_class=ESP32DUT) + dut2 = env.get_dut("sdio_slave", "examples/peripherals/sdio/slave", dut_class=ESP32DUT) dut1.start_app() # wait until the master is ready to setup the slave dut1.expect("host ready, start initializing slave...") diff --git a/examples/peripherals/spi_master/main/CMakeLists.txt b/examples/peripherals/spi_master/main/CMakeLists.txt index 36f8332d05..d0f93ab576 100644 --- a/examples/peripherals/spi_master/main/CMakeLists.txt +++ b/examples/peripherals/spi_master/main/CMakeLists.txt @@ -3,7 +3,7 @@ set(srcs "pretty_effect.c" ) # Only ESP32 has enough memory to do jpeg decoding -if (CONFIG_IDF_TARGET_ESP32) +if(IDF_TARGET STREQUAL "esp32") list(APPEND srcs "decode_image.c") endif() diff --git a/examples/protocols/asio/chat_client/asio_chat_client_test.py b/examples/protocols/asio/chat_client/asio_chat_client_test.py index 3b141c7d17..f5581796d1 100644 --- a/examples/protocols/asio/chat_client/asio_chat_client_test.py +++ b/examples/protocols/asio/chat_client/asio_chat_client_test.py @@ -7,6 +7,7 @@ import time try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -69,7 +70,7 @@ def test_examples_protocol_asio_chat_client(env, extra_data): global g_client_response global g_msg_to_client test_msg = "ABC" - dut1 = env.get_dut("chat_client", "examples/protocols/asio/chat_client") + dut1 = env.get_dut("chat_client", "examples/protocols/asio/chat_client", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "asio_chat_client.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/asio/chat_server/asio_chat_server_test.py b/examples/protocols/asio/chat_server/asio_chat_server_test.py index ea4702c4e8..5d53a89467 100644 --- a/examples/protocols/asio/chat_server/asio_chat_server_test.py +++ b/examples/protocols/asio/chat_server/asio_chat_server_test.py @@ -6,6 +6,7 @@ import socket try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -27,7 +28,7 @@ def test_examples_protocol_asio_chat_server(env, extra_data): 4. Test evaluates received test message from server """ test_msg = b" 4ABC\n" - dut1 = env.get_dut("chat_server", "examples/protocols/asio/chat_server") + dut1 = env.get_dut("chat_server", "examples/protocols/asio/chat_server", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "asio_chat_server.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/asio/tcp_echo_server/asio_tcp_server_test.py b/examples/protocols/asio/tcp_echo_server/asio_tcp_server_test.py index 2cdfd45aee..aeb7faced5 100644 --- a/examples/protocols/asio/tcp_echo_server/asio_tcp_server_test.py +++ b/examples/protocols/asio/tcp_echo_server/asio_tcp_server_test.py @@ -6,6 +6,7 @@ import socket try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -29,7 +30,7 @@ def test_examples_protocol_asio_tcp_server(env, extra_data): 5. Test evaluates received test message on server stdout """ test_msg = b"echo message from client to server" - dut1 = env.get_dut("tcp_echo_server", "examples/protocols/asio/tcp_echo_server") + dut1 = env.get_dut("tcp_echo_server", "examples/protocols/asio/tcp_echo_server", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "asio_tcp_echo_server.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/asio/udp_echo_server/asio_udp_server_test.py b/examples/protocols/asio/udp_echo_server/asio_udp_server_test.py index dc2cc78a80..dac320068f 100644 --- a/examples/protocols/asio/udp_echo_server/asio_udp_server_test.py +++ b/examples/protocols/asio/udp_echo_server/asio_udp_server_test.py @@ -6,6 +6,7 @@ import socket try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -29,7 +30,7 @@ def test_examples_protocol_asio_udp_server(env, extra_data): 5. Test evaluates received test message on server stdout """ test_msg = b"echo message from client to server" - dut1 = env.get_dut("udp_echo_server", "examples/protocols/asio/udp_echo_server") + dut1 = env.get_dut("udp_echo_server", "examples/protocols/asio/udp_echo_server", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "asio_udp_echo_server.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/esp_http_client/esp_http_client_test.py b/examples/protocols/esp_http_client/esp_http_client_test.py index 1c9c1d5701..cdd0888c47 100644 --- a/examples/protocols/esp_http_client/esp_http_client_test.py +++ b/examples/protocols/esp_http_client/esp_http_client_test.py @@ -4,6 +4,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -23,7 +24,7 @@ def test_examples_protocol_esp_http_client(env, extra_data): 1. join AP 2. Send HTTP request to httpbin.org """ - dut1 = env.get_dut("esp_http_client", "examples/protocols/esp_http_client") + dut1 = env.get_dut("esp_http_client", "examples/protocols/esp_http_client", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "esp-http-client-example.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/http_server/advanced_tests/http_server_advanced_test.py b/examples/protocols/http_server/advanced_tests/http_server_advanced_test.py index a27ad5ee02..6e053a9984 100644 --- a/examples/protocols/http_server/advanced_tests/http_server_advanced_test.py +++ b/examples/protocols/http_server/advanced_tests/http_server_advanced_test.py @@ -23,6 +23,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # This environment variable is expected on the host machine test_fw_path = os.getenv("TEST_FW_PATH") @@ -52,7 +53,7 @@ client = Utility.load_source("client", expath + "/scripts/test.py") @IDF.idf_example_test(env_tag="Example_WIFI") def test_examples_protocol_http_server_advanced(env, extra_data): # Acquire DUT - dut1 = env.get_dut("http_server", "examples/protocols/http_server/advanced_tests") + dut1 = env.get_dut("http_server", "examples/protocols/http_server/advanced_tests", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut1.app.binary_path, "tests.bin") diff --git a/examples/protocols/http_server/persistent_sockets/http_server_persistence_test.py b/examples/protocols/http_server/persistent_sockets/http_server_persistence_test.py index 43174bc52c..f10a984857 100644 --- a/examples/protocols/http_server/persistent_sockets/http_server_persistence_test.py +++ b/examples/protocols/http_server/persistent_sockets/http_server_persistence_test.py @@ -26,6 +26,7 @@ import random try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # This environment variable is expected on the host machine test_fw_path = os.getenv("TEST_FW_PATH") @@ -48,7 +49,7 @@ client = Utility.load_source("client", expath + "/scripts/adder.py") @IDF.idf_example_test(env_tag="Example_WIFI") def test_examples_protocol_http_server_persistence(env, extra_data): # Acquire DUT - dut1 = env.get_dut("http_server", "examples/protocols/http_server/persistent_sockets") + dut1 = env.get_dut("http_server", "examples/protocols/http_server/persistent_sockets", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut1.app.binary_path, "persistent_sockets.bin") diff --git a/examples/protocols/http_server/restful_server/CMakeLists.txt b/examples/protocols/http_server/restful_server/CMakeLists.txt index cb143ac640..67e91b8877 100644 --- a/examples/protocols/http_server/restful_server/CMakeLists.txt +++ b/examples/protocols/http_server/restful_server/CMakeLists.txt @@ -4,4 +4,5 @@ cmake_minimum_required(VERSION 3.5) set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/common_components/protocol_examples_common) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(SUPPORTED_TARGETS esp32) project(restful_server) diff --git a/examples/protocols/http_server/simple/http_server_simple_test.py b/examples/protocols/http_server/simple/http_server_simple_test.py index 4cd344db83..75f5f4f262 100644 --- a/examples/protocols/http_server/simple/http_server_simple_test.py +++ b/examples/protocols/http_server/simple/http_server_simple_test.py @@ -26,6 +26,7 @@ import random try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # This environment variable is expected on the host machine test_fw_path = os.getenv("TEST_FW_PATH") @@ -49,7 +50,7 @@ client = Utility.load_source("client", expath + "/scripts/client.py") @IDF.idf_example_test(env_tag="Example_WIFI") def test_examples_protocol_http_server_simple(env, extra_data): # Acquire DUT - dut1 = env.get_dut("http_server", "examples/protocols/http_server/simple") + dut1 = env.get_dut("http_server", "examples/protocols/http_server/simple", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut1.app.binary_path, "simple.bin") diff --git a/examples/protocols/https_request/example_test.py b/examples/protocols/https_request/example_test.py index ce8453edb4..543edc3da2 100644 --- a/examples/protocols/https_request/example_test.py +++ b/examples/protocols/https_request/example_test.py @@ -4,6 +4,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -23,7 +24,7 @@ def test_examples_protocol_https_request(env, extra_data): 2. connect to www.howsmyssl.com:443 3. send http request """ - dut1 = env.get_dut("https_request", "examples/protocols/https_request") + dut1 = env.get_dut("https_request", "examples/protocols/https_request", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "https_request.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/mdns/mdns_example_test.py b/examples/protocols/mdns/mdns_example_test.py index cb527989a5..4f5aa5f441 100644 --- a/examples/protocols/mdns/mdns_example_test.py +++ b/examples/protocols/mdns/mdns_example_test.py @@ -16,6 +16,7 @@ from threading import Thread try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv("TEST_FW_PATH") if test_fw_path and test_fw_path not in sys.path: @@ -86,7 +87,7 @@ def test_examples_protocol_mdns(env, extra_data): 3. check the mdns name is accessible 4. check DUT output if mdns advertized host is resolved """ - dut1 = env.get_dut("mdns-test", "examples/protocols/mdns") + dut1 = env.get_dut("mdns-test", "examples/protocols/mdns", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "mdns-test.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py b/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py index 7e66482533..87931e83d1 100644 --- a/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py +++ b/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py @@ -11,6 +11,7 @@ from threading import Thread, Event try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -64,7 +65,7 @@ def test_examples_protocol_mqtt_ssl(env, extra_data): 3. Test evaluates python client received correct qos0 message 4. Test ESP32 client received correct qos0 message """ - dut1 = env.get_dut("mqtt_ssl", "examples/protocols/mqtt/ssl") + dut1 = env.get_dut("mqtt_ssl", "examples/protocols/mqtt/ssl", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "mqtt_ssl.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/mqtt/tcp/mqtt_tcp_example_test.py b/examples/protocols/mqtt/tcp/mqtt_tcp_example_test.py index 05e51420ed..4e39705643 100644 --- a/examples/protocols/mqtt/tcp/mqtt_tcp_example_test.py +++ b/examples/protocols/mqtt/tcp/mqtt_tcp_example_test.py @@ -9,6 +9,7 @@ import time try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -75,7 +76,7 @@ def test_examples_protocol_mqtt_qos1(env, extra_data): 3. Test evaluates that qos1 message is queued and removed from queued after ACK received 4. Test the broker received the same message id evaluated in step 3 """ - dut1 = env.get_dut("mqtt_tcp", "examples/protocols/mqtt/tcp") + dut1 = env.get_dut("mqtt_tcp", "examples/protocols/mqtt/tcp", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "mqtt_tcp.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/mqtt/ws/mqtt_ws_example_test.py b/examples/protocols/mqtt/ws/mqtt_ws_example_test.py index 0578876e2c..85074c2441 100644 --- a/examples/protocols/mqtt/ws/mqtt_ws_example_test.py +++ b/examples/protocols/mqtt/ws/mqtt_ws_example_test.py @@ -10,6 +10,7 @@ from threading import Thread, Event try: import IDF + from IDF.IDFDUT import ESP32DUT except Exception: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -62,7 +63,7 @@ def test_examples_protocol_mqtt_ws(env, extra_data): 3. Test evaluates it received correct qos0 message 4. Test ESP32 client received correct qos0 message """ - dut1 = env.get_dut("mqtt_websocket", "examples/protocols/mqtt/ws") + dut1 = env.get_dut("mqtt_websocket", "examples/protocols/mqtt/ws", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "mqtt_websocket.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/mqtt/wss/mqtt_wss_example_test.py b/examples/protocols/mqtt/wss/mqtt_wss_example_test.py index 58ce56036d..5e0e143651 100644 --- a/examples/protocols/mqtt/wss/mqtt_wss_example_test.py +++ b/examples/protocols/mqtt/wss/mqtt_wss_example_test.py @@ -11,6 +11,7 @@ from threading import Thread, Event try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -63,7 +64,7 @@ def test_examples_protocol_mqtt_wss(env, extra_data): 3. Test evaluates it received correct qos0 message 4. Test ESP32 client received correct qos0 message """ - dut1 = env.get_dut("mqtt_websocket_secure", "examples/protocols/mqtt/wss") + dut1 = env.get_dut("mqtt_websocket_secure", "examples/protocols/mqtt/wss", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "mqtt_websocket_secure.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/protocols/websocket/example_test.py b/examples/protocols/websocket/example_test.py index ef0c3b2f2b..4ca10b2043 100644 --- a/examples/protocols/websocket/example_test.py +++ b/examples/protocols/websocket/example_test.py @@ -2,6 +2,7 @@ import re import os import sys import IDF +from IDF.IDFDUT import ESP32DUT # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -20,7 +21,7 @@ def test_examples_protocol_websocket(env, extra_data): 2. connect to ws://echo.websocket.org 3. send and receive data """ - dut1 = env.get_dut("websocket", "examples/protocols/websocket") + dut1 = env.get_dut("websocket", "examples/protocols/websocket", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "websocket-example.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/provisioning/ble_prov/ble_prov_test.py b/examples/provisioning/ble_prov/ble_prov_test.py index 01277117ed..760756a439 100644 --- a/examples/provisioning/ble_prov/ble_prov_test.py +++ b/examples/provisioning/ble_prov/ble_prov_test.py @@ -22,6 +22,7 @@ import time try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv("TEST_FW_PATH") if test_fw_path and test_fw_path not in sys.path: @@ -43,7 +44,7 @@ esp_prov.config_throw_except = True @IDF.idf_example_test(env_tag="Example_WIFI_BT") def test_examples_provisioning_ble(env, extra_data): # Acquire DUT - dut1 = env.get_dut("ble_prov", "examples/provisioning/ble_prov") + dut1 = env.get_dut("ble_prov", "examples/provisioning/ble_prov", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut1.app.binary_path, "ble_prov.bin") diff --git a/examples/provisioning/manager/wifi_prov_mgr_test.py b/examples/provisioning/manager/wifi_prov_mgr_test.py index ea7172dc4d..600bb66d0c 100644 --- a/examples/provisioning/manager/wifi_prov_mgr_test.py +++ b/examples/provisioning/manager/wifi_prov_mgr_test.py @@ -22,6 +22,7 @@ import time try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv("TEST_FW_PATH") if test_fw_path and test_fw_path not in sys.path: @@ -43,7 +44,7 @@ esp_prov.config_throw_except = True @IDF.idf_example_test(env_tag="Example_WIFI_BT") def test_examples_wifi_prov_mgr(env, extra_data): # Acquire DUT - dut1 = env.get_dut("wifi_prov_mgr", "examples/provisioning/manager") + dut1 = env.get_dut("wifi_prov_mgr", "examples/provisioning/manager", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut1.app.binary_path, "wifi_prov_mgr.bin") diff --git a/examples/provisioning/softap_prov/softap_prov_test.py b/examples/provisioning/softap_prov/softap_prov_test.py index 6f67f47c8e..73d3a51815 100644 --- a/examples/provisioning/softap_prov/softap_prov_test.py +++ b/examples/provisioning/softap_prov/softap_prov_test.py @@ -22,6 +22,7 @@ import time try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv("TEST_FW_PATH") if test_fw_path and test_fw_path not in sys.path: @@ -51,7 +52,7 @@ esp_prov.config_throw_except = True @IDF.idf_example_test(env_tag="Example_WIFI_BT") def test_examples_provisioning_softap(env, extra_data): # Acquire DUT - dut1 = env.get_dut("softap_prov", "examples/provisioning/softap_prov") + dut1 = env.get_dut("softap_prov", "examples/provisioning/softap_prov", dut_class=ESP32DUT) # Get binary file binary_file = os.path.join(dut1.app.binary_path, "softap_prov.bin") diff --git a/examples/storage/parttool/example_test.py b/examples/storage/parttool/example_test.py index 6ba90c1756..8b9d37775b 100644 --- a/examples/storage/parttool/example_test.py +++ b/examples/storage/parttool/example_test.py @@ -5,6 +5,7 @@ import subprocess try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv('TEST_FW_PATH') if test_fw_path and test_fw_path not in sys.path: @@ -14,7 +15,7 @@ except ImportError: @IDF.idf_example_test(env_tag='Example_WIFI') def test_examples_parttool(env, extra_data): - dut = env.get_dut('parttool', 'examples/storage/parttool') + dut = env.get_dut('parttool', 'examples/storage/parttool', dut_class=ESP32DUT) dut.start_app(False) # Verify factory firmware diff --git a/examples/storage/spiffsgen/example_test.py b/examples/storage/spiffsgen/example_test.py index 636d69c7db..a2ad4304a4 100644 --- a/examples/storage/spiffsgen/example_test.py +++ b/examples/storage/spiffsgen/example_test.py @@ -5,6 +5,7 @@ import hashlib try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv('TEST_FW_PATH') if test_fw_path and test_fw_path not in sys.path: @@ -15,7 +16,7 @@ except ImportError: @IDF.idf_example_test(env_tag='Example_WIFI') def test_examples_spiffsgen(env, extra_data): # Test with default build configurations - dut = env.get_dut('spiffsgen', 'examples/storage/spiffsgen') + dut = env.get_dut('spiffsgen', 'examples/storage/spiffsgen', dut_class=ESP32DUT) dut.start_app() base_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)), 'spiffs_image') diff --git a/examples/system/cpp_exceptions/example_test.py b/examples/system/cpp_exceptions/example_test.py index 7b4c004ec5..2101458361 100644 --- a/examples/system/cpp_exceptions/example_test.py +++ b/examples/system/cpp_exceptions/example_test.py @@ -4,6 +4,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv('TEST_FW_PATH') if test_fw_path and test_fw_path not in sys.path: @@ -13,7 +14,7 @@ except ImportError: @IDF.idf_example_test(env_tag='Example_WIFI') def test_examples_system_cpp_exceptions(env, extra_data): - dut = env.get_dut('cpp_exceptions_example', 'examples/system/cpp_exceptions') + dut = env.get_dut('cpp_exceptions_example', 'examples/system/cpp_exceptions', dut_class=ESP32DUT) # start test dut.start_app() lines = ['app_main starting', diff --git a/examples/system/esp_event/default_event_loop/example_test.py b/examples/system/esp_event/default_event_loop/example_test.py index 002c35eddf..0befaecc9e 100644 --- a/examples/system/esp_event/default_event_loop/example_test.py +++ b/examples/system/esp_event/default_event_loop/example_test.py @@ -4,6 +4,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -93,7 +94,7 @@ def _test_iteration_events(dut): @IDF.idf_example_test(env_tag='Example_WIFI') def test_default_event_loop_example(env, extra_data): - dut = env.get_dut('default_event_loop', 'examples/system/esp_event/default_event_loop') + dut = env.get_dut('default_event_loop', 'examples/system/esp_event/default_event_loop', dut_class=ESP32DUT) _test_iteration_events(dut) _test_timer_events(dut) diff --git a/examples/system/esp_event/user_event_loops/example_test.py b/examples/system/esp_event/user_event_loops/example_test.py index ccd8eeab95..212597d42c 100644 --- a/examples/system/esp_event/user_event_loops/example_test.py +++ b/examples/system/esp_event/user_event_loops/example_test.py @@ -4,6 +4,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -22,7 +23,7 @@ TASK_ITERATION_HANDLING = "handling TASK_EVENTS:TASK_ITERATION_EVENT from {}, it @IDF.idf_example_test(env_tag='Example_WIFI') def test_user_event_loops_example(env, extra_data): - dut = env.get_dut('user_event_loops', 'examples/system/esp_event/user_event_loops') + dut = env.get_dut('user_event_loops', 'examples/system/esp_event/user_event_loops', dut_class=ESP32DUT) dut.start_app() diff --git a/examples/system/esp_timer/example_test.py b/examples/system/esp_timer/example_test.py index 474df5e0fa..325088abea 100644 --- a/examples/system/esp_timer/example_test.py +++ b/examples/system/esp_timer/example_test.py @@ -5,6 +5,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -39,7 +40,7 @@ ONE_SHOT_TIMER_PERIOD = 5000000 @IDF.idf_example_test(env_tag='Example_WIFI') def test_examples_system_esp_timer(env, extra_data): - dut = env.get_dut('esp_timer_example', 'examples/system/esp_timer') + dut = env.get_dut('esp_timer_example', 'examples/system/esp_timer', dut_class=ESP32DUT) # start test dut.start_app() groups = dut.expect(STARTING_TIMERS_REGEX, timeout=30) diff --git a/examples/system/freertos/real_time_stats/example_test.py b/examples/system/freertos/real_time_stats/example_test.py index f5ae64c3e4..2d2d2cc0bc 100644 --- a/examples/system/freertos/real_time_stats/example_test.py +++ b/examples/system/freertos/real_time_stats/example_test.py @@ -4,6 +4,7 @@ import sys try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -20,7 +21,7 @@ STATS_TASK_EXPECT = "Real time stats obtained" @IDF.idf_example_test(env_tag='Example_WIFI') def test_real_time_stats_example(env, extra_data): - dut = env.get_dut('real_time_stats', 'examples/system/freertos/real_time_stats') + dut = env.get_dut('real_time_stats', 'examples/system/freertos/real_time_stats', dut_class=ESP32DUT) dut.start_app() for iteration in range(0, STATS_TASK_ITERS): diff --git a/examples/system/light_sleep/example_test.py b/examples/system/light_sleep/example_test.py index a3ddd97a16..a29b5dcc8b 100644 --- a/examples/system/light_sleep/example_test.py +++ b/examples/system/light_sleep/example_test.py @@ -6,6 +6,7 @@ import time try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: test_fw_path = os.getenv('TEST_FW_PATH') if test_fw_path and test_fw_path not in sys.path: @@ -21,7 +22,7 @@ WAKEUP_INTERVAL_MS = 2000 @IDF.idf_example_test(env_tag='Example_WIFI') def test_examples_system_light_sleep(env, extra_data): - dut = env.get_dut('light_sleep_example', 'examples/system/light_sleep') + dut = env.get_dut('light_sleep_example', 'examples/system/light_sleep', dut_class=ESP32DUT) dut.start_app() # Ensure DTR and RTS are de-asserted for proper control of GPIO0 diff --git a/examples/system/ota/otatool/example_test.py b/examples/system/ota/otatool/example_test.py index a22ebf5a89..cfbf06450d 100644 --- a/examples/system/ota/otatool/example_test.py +++ b/examples/system/ota/otatool/example_test.py @@ -5,6 +5,7 @@ import subprocess try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -18,7 +19,7 @@ except ImportError: @IDF.idf_example_test(env_tag='Example_WIFI') def test_otatool_example(env, extra_data): - dut = env.get_dut('otatool', 'examples/system/ota/otatool') + dut = env.get_dut('otatool', 'examples/system/ota/otatool', dut_class=ESP32DUT) # Verify factory firmware dut.start_app() diff --git a/examples/system/ota/simple_ota_example/example_test.py b/examples/system/ota/simple_ota_example/example_test.py index 7c732a5425..0b79b68b59 100644 --- a/examples/system/ota/simple_ota_example/example_test.py +++ b/examples/system/ota/simple_ota_example/example_test.py @@ -9,6 +9,7 @@ import ssl try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -115,7 +116,7 @@ def test_examples_protocol_simple_ota_example(env, extra_data): 2. Fetch OTA image over HTTPS 3. Reboot with the new OTA image """ - dut1 = env.get_dut("simple_ota_example", "examples/system/ota/simple_ota_example") + dut1 = env.get_dut("simple_ota_example", "examples/system/ota/simple_ota_example", dut_class=ESP32DUT) # check and log bin size binary_file = os.path.join(dut1.app.binary_path, "simple_ota.bin") bin_size = os.path.getsize(binary_file) diff --git a/examples/wifi/iperf/iperf_test.py b/examples/wifi/iperf/iperf_test.py index 35538cae7c..bc67e240fe 100644 --- a/examples/wifi/iperf/iperf_test.py +++ b/examples/wifi/iperf/iperf_test.py @@ -32,6 +32,7 @@ import subprocess try: import IDF + from IDF.IDFDUT import ESP32DUT except ImportError: # this is a test case write with tiny-test-fw. # to run test cases outside tiny-test-fw, @@ -517,7 +518,7 @@ def test_wifi_throughput_with_different_configs(env, extra_data): "sdkconfig.{}".format(config_name)) # 2. get DUT and download - dut = env.get_dut("iperf", "examples/wifi/iperf") + dut = env.get_dut("iperf", "examples/wifi/iperf", dut_class=ESP32DUT) dut.start_app() dut.expect("esp32>") @@ -575,7 +576,7 @@ def test_wifi_throughput_vs_rssi(env, extra_data): build_iperf_with_config(BEST_PERFORMANCE_CONFIG) # 2. get DUT and download - dut = env.get_dut("iperf", "examples/wifi/iperf") + dut = env.get_dut("iperf", "examples/wifi/iperf", dut_class=ESP32DUT) dut.start_app() dut.expect("esp32>") @@ -624,7 +625,7 @@ def test_wifi_throughput_basic(env, extra_data): build_iperf_with_config(BEST_PERFORMANCE_CONFIG) # 2. get DUT - dut = env.get_dut("iperf", "examples/wifi/iperf") + dut = env.get_dut("iperf", "examples/wifi/iperf", dut_class=ESP32DUT) dut.start_app() dut.expect("esp32>") diff --git a/tools/ci/config/assign-test.yml b/tools/ci/config/assign-test.yml index 92dc8cad2c..40826ef7f2 100644 --- a/tools/ci/config/assign-test.yml +++ b/tools/ci/config/assign-test.yml @@ -13,6 +13,7 @@ assign_test: variables: TEST_FW_PATH: "$CI_PROJECT_DIR/tools/tiny-test-fw" EXAMPLE_CONFIG_OUTPUT_PATH: "$CI_PROJECT_DIR/examples/test_configs" + UNIT_TEST_CASE_FILE: "${CI_PROJECT_DIR}/components/idf_test/unit_test/TestCaseAll.yml" artifacts: paths: - components/idf_test/*/CIConfigs @@ -29,7 +30,7 @@ assign_test: # assign example tests - python $TEST_FW_PATH/CIAssignExampleTest.py $IDF_PATH/examples $CI_TARGET_TEST_CONFIG_FILE $EXAMPLE_CONFIG_OUTPUT_PATH # assign unit test cases - - python $TEST_FW_PATH/CIAssignUnitTest.py $IDF_PATH/components/idf_test/unit_test/TestCaseAll.yml $CI_TARGET_TEST_CONFIG_FILE $IDF_PATH/components/idf_test/unit_test/CIConfigs + - python $TEST_FW_PATH/CIAssignUnitTest.py $UNIT_TEST_CASE_FILE $CI_TARGET_TEST_CONFIG_FILE $IDF_PATH/components/idf_test/unit_test/CIConfigs # clone test script to assign tests - git clone $TEST_SCRIPT_REPOSITORY - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script diff --git a/tools/ci/config/build.yml b/tools/ci/config/build.yml index 64cc1846bc..afeba1692d 100644 --- a/tools/ci/config/build.yml +++ b/tools/ci/config/build.yml @@ -91,6 +91,7 @@ build_esp_idf_tests_make: script: - export EXTRA_CFLAGS=${PEDANTIC_CFLAGS} - export EXTRA_CXXFLAGS=${PEDANTIC_CXXFLAGS} + - export IDF_TARGET=esp32 - cd $CI_PROJECT_DIR/tools/unit-test-app - MAKEFLAGS= make help # make sure kconfig tools are built in single process - make ut-clean-all-configs @@ -131,6 +132,7 @@ build_examples_make: - build_examples/*/*/*/build/*.map - build_examples/*/*/*/build/download.config - build_examples/*/*/*/build/bootloader/*.bin + - build_examples/*/*/*/*/build/partition_table/*.bin - $LOG_PATH expire_in: 3 days variables: @@ -160,6 +162,10 @@ build_examples_make: # build some of examples - mkdir -p ${LOG_PATH} - ${IDF_PATH}/tools/ci/build_examples.sh + # Check if the tests demand Make built binaries. If not, delete them + - if [ "$EXAMPLE_TEST_BUILD_SYSTEM" == "make" ]; then exit 0; fi + - cd .. + - rm -rf build_examples # same as above, but for CMake .build_examples_cmake: &build_examples_cmake @@ -168,12 +174,13 @@ build_examples_make: artifacts: when: always paths: - - build_examples_cmake/*/*/*/*/build/*.bin - - build_examples_cmake/*/*/*/*/sdkconfig - - build_examples_cmake/*/*/*/*/build/*.elf - - build_examples_cmake/*/*/*/*/build/*.map - - build_examples_cmake/*/*/*/*/build/flasher_args.json - - build_examples_cmake/*/*/*/*/build/bootloader/*.bin + - build_examples/*/*/*/*/build/*.bin + - build_examples/*/*/*/*/sdkconfig + - build_examples/*/*/*/*/build/*.elf + - build_examples/*/*/*/*/build/*.map + - build_examples/*/*/*/*/build/flasher_args.json + - build_examples/*/*/*/*/build/bootloader/*.bin + - build_examples/*/*/*/*/build/partition_table/*.bin - $LOG_PATH expire_in: 3 days variables: @@ -188,12 +195,16 @@ build_examples_make: script: # it's not possible to build 100% out-of-tree and have the "artifacts" # mechanism work, but this is the next best thing - - rm -rf build_examples_cmake - - mkdir build_examples_cmake - - cd build_examples_cmake + - rm -rf build_examples + - mkdir build_examples + - cd build_examples # build some of examples - mkdir -p ${LOG_PATH} - ${IDF_PATH}/tools/ci/build_examples_cmake.sh + # Check if the tests demand CMake built binaries. If not, delete them + - if [ "$EXAMPLE_TEST_BUILD_SYSTEM" == "cmake" ]; then exit 0; fi + - cd .. + - rm -rf build_examples build_examples_cmake_esp32: extends: .build_examples_cmake diff --git a/tools/ci/config/target-test.yml b/tools/ci/config/target-test.yml index 6aa25316ea..cafed02acd 100644 --- a/tools/ci/config/target-test.yml +++ b/tools/ci/config/target-test.yml @@ -3,8 +3,8 @@ # we need to convert to pattern "job_name_index.yml" .define_config_file_name: &define_config_file_name | JOB_NAME_PREFIX=$(echo ${CI_JOB_NAME} | awk '{print $1}') - JOG_FULL_NAME="${JOB_NAME_PREFIX}_${CI_NODE_INDEX}" - CONFIG_FILE="${CONFIG_FILE_PATH}/${JOG_FULL_NAME}.yml" + JOB_FULL_NAME="${JOB_NAME_PREFIX}_${CI_NODE_INDEX}" + CONFIG_FILE="${CONFIG_FILE_PATH}/${JOB_FULL_NAME}.yml" .example_test_template: stage: target_test @@ -23,6 +23,7 @@ - assign_test - build_examples_make - build_examples_cmake_esp32 + - build_examples_cmake_esp32s2 artifacts: when: always paths: @@ -113,7 +114,7 @@ - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script - cd auto_test_script # run test - - python CIRunner.py -l "$LOG_PATH/$JOG_FULL_NAME" -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH + - python CIRunner.py -l "$LOG_PATH/$JOB_FULL_NAME" -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH test_weekend_mqtt: extends: .example_test_template @@ -412,6 +413,13 @@ UT_030: - ESP32_IDF - UT_T1_1 +UT_031: + extends: .unit_test_template + parallel: 28 + tags: + - 7.2.2 + - UT_T1_1 + nvs_compatible_test: extends: .test_template artifacts: @@ -437,7 +445,7 @@ nvs_compatible_test: # prepare nvs bins - ./Tools/prepare_nvs_bin.sh # run test - - python CIRunner.py -l "$LOG_PATH/$JOG_FULL_NAME" -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH + - python CIRunner.py -l "$LOG_PATH/$JOB_FULL_NAME" -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH IT_001: extends: .test_template diff --git a/tools/ci/executable-list.txt b/tools/ci/executable-list.txt index bcc257b3d4..6c259a10d3 100644 --- a/tools/ci/executable-list.txt +++ b/tools/ci/executable-list.txt @@ -79,6 +79,7 @@ tools/test_check_kconfigs.py tools/test_idf_monitor/run_test_idf_monitor.py tools/test_idf_size/test.sh tools/test_idf_tools/test_idf_tools.py +tools/unit-test-app/tools/get_available_configs.sh tools/unit-test-app/unit_test.py tools/windows/eclipse_make.sh tools/windows/tool_setup/build_installer.sh diff --git a/tools/ci/test_build_system_cmake.sh b/tools/ci/test_build_system_cmake.sh index bbe299b92f..47e1ae23ee 100755 --- a/tools/ci/test_build_system_cmake.sh +++ b/tools/ci/test_build_system_cmake.sh @@ -306,6 +306,15 @@ function run_tests() grep "CONFIG_IDF_TARGET=\"${fake_target}\"" sdkconfig || failure "Project not configured correctly using idf.py reconfigure -D" grep "IDF_TARGET:STRING=${fake_target}" build/CMakeCache.txt || failure "IDF_TARGET not set in CMakeCache.txt using idf.py reconfigure -D" + # TODO Change the real target to other value than esp32 when we have + real_target=esp32 + print_status "Can set target using idf.py set-target" + clean_build_dir + rm sdkconfig + idf.py set-target esp32 || failure "Failed to set target via idf.py set-target" + grep "CONFIG_IDF_TARGET=\"${real_target}\"" sdkconfig || failure "Project not configured correctly using idf.py set-target" + grep "IDF_TARGET:STRING=${real_target}" build/CMakeCache.txt || failure "IDF_TARGET not set in CMakeCache.txt using idf.py set-target" + # Clean up modifications for the fake target mv CMakeLists.txt.bak CMakeLists.txt rm -rf components diff --git a/tools/idf.py b/tools/idf.py index 0cad1edb15..c11704e78e 100755 --- a/tools/idf.py +++ b/tools/idf.py @@ -81,6 +81,8 @@ GENERATORS = [ GENERATOR_CMDS = dict((a[0], a[1]) for a in GENERATORS) GENERATOR_VERBOSE = dict((a[0], a[3]) for a in GENERATORS) +SUPPORTED_TARGETS = ["esp32", "esp32s2beta"] + def _run_tool(tool_name, args, cwd): def quote_arg(arg): @@ -220,7 +222,6 @@ def _ensure_build_directory(args, always_run_cmake=False): os.makedirs(build_dir) cache_path = os.path.join(build_dir, "CMakeCache.txt") - args.define_cache_entry = list(args.define_cache_entry) args.define_cache_entry.append("CCACHE_ENABLE=%d" % args.ccache) if always_run_cmake or _new_cmakecache_entries(cache_path, args.define_cache_entry): @@ -408,6 +409,17 @@ def clean(action, ctx, args): build_target("clean", ctx, args) +def set_target(action, ctx, args, idf_target): + args.define_cache_entry.append("IDF_TARGET=" + idf_target) + sdkconfig_path = os.path.join(args.project_dir, 'sdkconfig') + sdkconfig_old = sdkconfig_path + ".old" + if os.path.exists(sdkconfig_old): + os.remove(sdkconfig_old) + if os.path.exists(sdkconfig_path): + os.rename(sdkconfig_path, sdkconfig_old) + print("Set Target to: %s, new sdkconfig created. Existing sdkconfig renamed to sdkconfig.old." % idf_target) + + def reconfigure(action, ctx, args): _ensure_build_directory(args, True) @@ -830,24 +842,21 @@ def init_cli(): for action_callback in ctx.command.global_action_callbacks: action_callback(ctx, global_args, tasks) - # very simple dependency management - completed_tasks = set() - if not tasks: print(ctx.get_help()) ctx.exit() - while tasks: - task = tasks[0] - tasks_dict = dict([(t.name, t) for t in tasks]) + # Make sure that define_cache_entry is list + global_args.define_cache_entry = list(global_args.define_cache_entry) - name_with_aliases = task.name - if task.aliases: - name_with_aliases += " (aliases: %s)" % ", ".join(task.aliases) - - ready_to_run = True + # Go through the task and create depended but missing tasks + all_tasks = [t.name for t in tasks] + tasks, tasks_to_handle = [], tasks + while tasks_to_handle: + task = tasks_to_handle.pop() + tasks.append(task) for dep in task.dependencies: - if dep not in completed_tasks: + if dep not in all_tasks: print( 'Adding %s\'s dependency "%s" to list of actions' % (task.name, dep) @@ -860,8 +869,20 @@ def init_cli(): if option and (option.scope.is_global or option.scope.is_shared): dep_task.action_args.pop(key) - tasks.insert(0, dep_task) - ready_to_run = False + tasks_to_handle.append(dep_task) + all_tasks.append(dep_task.name) + + # very simple dependency management + completed_tasks = set() + while tasks: + task = tasks[0] + tasks_dict = dict([(t.name, t) for t in tasks]) + + name_with_aliases = task.name + if task.aliases: + name_with_aliases += " (aliases: %s)" % ", ".join(task.aliases) + + ready_to_run = True for dep in task.order_dependencies: if dep in tasks_dict.keys() and dep not in completed_tasks: @@ -1082,7 +1103,22 @@ def init_cli(): + "For example, \"idf.py -DNAME='VALUE' reconfigure\" " + 'can be used to set variable "NAME" in CMake cache to value "VALUE".', "options": global_options, - "order_dependencies": ["menuconfig"], + "order_dependencies": ["menuconfig", "set-target", "fullclean"], + }, + "set-target": { + "callback": set_target, + "short_help": "Set the chip target to build.", + "help": "Set the chip target to build. This will remove the " + + "existing sdkconfig file and corresponding CMakeCache and " + + "create new ones according to the new target.\nFor example, " + + "\"idf.py set-target esp32\" will select esp32 as the new chip " + + "target.", + "arguments": [{ + "names": ["idf-target"], + "nargs": 1, + "type": click.Choice(SUPPORTED_TARGETS), + }], + "dependencies": ["fullclean", "reconfigure"], }, "clean": { "callback": clean, diff --git a/tools/tiny-test-fw/CIAssignUnitTest.py b/tools/tiny-test-fw/CIAssignUnitTest.py index 2ea32e53d8..c6ec2a0ade 100644 --- a/tools/tiny-test-fw/CIAssignUnitTest.py +++ b/tools/tiny-test-fw/CIAssignUnitTest.py @@ -19,13 +19,12 @@ except ImportError: class Group(CIAssignTest.Group): - SORT_KEYS = ["config", "SDK", "test environment", "multi_device", "multi_stage", "tags"] + SORT_KEYS = ["config", "test environment", "multi_device", "multi_stage", "tags", "chip_target"] MAX_CASE = 30 ATTR_CONVERT_TABLE = { "execution_time": "execution time" } - # when IDF support multiple chips, SDK will be moved into tags, we can remove it - CI_JOB_MATCH_KEYS = ["test environment", "SDK"] + CI_JOB_MATCH_KEYS = ["test environment"] def __init__(self, case): super(Group, self).__init__(case) @@ -84,6 +83,7 @@ class Group(CIAssignTest.Group): :return: {"Filter": case filter, "CaseConfig": list of case configs for cases in this group} """ test_function = self._map_test_function() + output_data = { # we don't need filter for test function, as UT uses a few test functions for all cases "CaseConfig": [ @@ -91,8 +91,26 @@ class Group(CIAssignTest.Group): "name": test_function, "extra_data": self._create_extra_data(test_function), } - ] + ], } + + target = self._get_case_attr(self.case_list[0], "chip_target") + if target is not None: + target_dut = { + "esp32": "ESP32DUT", + "esp32s2beta": "ESP32S2DUT", + "esp8266": "ESP8266DUT", + }[target] + output_data.update({ + "Filter": { + "overwrite": { + "dut": { + "path": "IDF/IDFDUT.py", + "class": target_dut, + } + } + } + }) return output_data diff --git a/tools/tiny-test-fw/Env.py b/tools/tiny-test-fw/Env.py index 3622ba3824..389e87b335 100644 --- a/tools/tiny-test-fw/Env.py +++ b/tools/tiny-test-fw/Env.py @@ -99,10 +99,10 @@ class Env(object): except ValueError: dut_config = dict() dut_config.update(dut_init_args) - dut = self.default_dut_cls(dut_name, port, - os.path.join(self.log_path, dut_name + ".log"), - app_inst, - **dut_config) + dut = dut_class(dut_name, port, + os.path.join(self.log_path, dut_name + ".log"), + app_inst, + **dut_config) self.allocated_duts[dut_name] = {"port": port, "dut": dut} else: raise ValueError("Failed to get DUT") diff --git a/tools/tiny-test-fw/IDF/IDFDUT.py b/tools/tiny-test-fw/IDF/IDFDUT.py index c8ee24f236..e44a230d95 100644 --- a/tools/tiny-test-fw/IDF/IDFDUT.py +++ b/tools/tiny-test-fw/IDF/IDFDUT.py @@ -122,7 +122,7 @@ def _uses_esptool(func): settings = self.port_inst.get_settings() try: - rom = esptool.ESP32ROM(self.port_inst) + rom = self._get_rom()(self.port_inst) rom.connect('hard_reset') esp = rom.run_stub() @@ -159,6 +159,10 @@ class IDFDUT(DUT.SerialDUT): self.exceptions = _queue.Queue() self.performance_items = _queue.Queue() + @classmethod + def _get_rom(cls): + raise NotImplementedError("This is an abstraction class, method not defined.") + @classmethod def get_mac(cls, app, port): """ @@ -169,7 +173,7 @@ class IDFDUT(DUT.SerialDUT): :return: MAC address or None """ try: - esp = esptool.ESP32ROM(port) + esp = cls._get_rom()(port) esp.connect() return esp.read_mac() except RuntimeError: @@ -181,7 +185,18 @@ class IDFDUT(DUT.SerialDUT): @classmethod def confirm_dut(cls, port, app, **kwargs): - return cls.get_mac(app, port) is not None + try: + # TODO: check whether 8266 works with this logic + # Otherwise overwrite it in ESP8266DUT + inst = esptool.ESPLoader.detect_chip(port) + if type(inst) != cls._get_rom(): + raise RuntimeError("Target not expected") + return inst.read_mac() is not None + except(esptool.FatalError, RuntimeError): + return False + finally: + if inst: + inst._port.close() @_uses_esptool def _try_flash(self, esp, erase_nvs, baud_rate): @@ -389,3 +404,21 @@ class IDFDUT(DUT.SerialDUT): if not self.allow_dut_exception and self.get_exceptions(): Utility.console_log("DUT exception detected on {}".format(self), color="red") raise IDFDUTException() + + +class ESP32DUT(IDFDUT): + @classmethod + def _get_rom(cls): + return esptool.ESP32ROM + + +class ESP32S2DUT(IDFDUT): + @classmethod + def _get_rom(cls): + return esptool.ESP32S2ROM + + +class ESP8266DUT(IDFDUT): + @classmethod + def _get_rom(cls): + return esptool.ESP8266ROM diff --git a/tools/tiny-test-fw/Utility/CIAssignTest.py b/tools/tiny-test-fw/Utility/CIAssignTest.py index 6a93f9a885..a936428cb0 100644 --- a/tools/tiny-test-fw/Utility/CIAssignTest.py +++ b/tools/tiny-test-fw/Utility/CIAssignTest.py @@ -233,7 +233,7 @@ class AssignTest(object): else: failed_to_assign.append(group) if failed_to_assign: - console_log("Too many test cases vs jobs to run. Please add the following jobs to .gitlab-ci.yml with specific tags:", "R") + console_log("Too many test cases vs jobs to run. Please add the following jobs to tools/ci/config/target-test.yml with specific tags:", "R") for group in failed_to_assign: console_log("* Add job with: " + ",".join(group.ci_job_match_keys), "R") raise RuntimeError("Failed to assign test case to CI jobs") diff --git a/tools/tiny-test-fw/example.py b/tools/tiny-test-fw/example.py index 2cdd04b403..c4348bf346 100644 --- a/tools/tiny-test-fw/example.py +++ b/tools/tiny-test-fw/example.py @@ -28,6 +28,7 @@ except ImportError: import TinyFW import IDF +from IDF.IDFDUT import ESP32DUT @IDF.idf_example_test(env_tag="Example_WIFI") @@ -38,7 +39,7 @@ def test_examples_protocol_https_request(env, extra_data): 2. connect to www.howsmyssl.com:443 3. send http request """ - dut1 = env.get_dut("https_request", "examples/protocols/https_request") + dut1 = env.get_dut("https_request", "examples/protocols/https_request", dut_class=ESP32DUT) dut1.start_app() dut1.expect(re.compile(r"Connecting to www.howsmyssl.com:443"), timeout=30) dut1.expect("Performing the SSL/TLS handshake") diff --git a/tools/unit-test-app/Makefile b/tools/unit-test-app/Makefile index 006bf9753e..5aef4f9538 100644 --- a/tools/unit-test-app/Makefile +++ b/tools/unit-test-app/Makefile @@ -15,7 +15,7 @@ all: # Each file in configs/ directory defines a configuration. The format is the # same as sdkconfig file. Configuration is applied on top of sdkconfig.defaults # file from the project directory -CONFIG_NAMES := $(notdir $(wildcard configs/*)) +CONFIG_NAMES := $(shell ${IDF_PATH}/tools/unit-test-app/tools/get_available_configs.sh esp32) # Per-config targets CONFIG_BUILD_TARGETS := $(addprefix ut-build-,$(CONFIG_NAMES)) diff --git a/tools/unit-test-app/components/test_utils/CMakeLists.txt b/tools/unit-test-app/components/test_utils/CMakeLists.txt index f6174b15a7..c099725c1d 100644 --- a/tools/unit-test-app/components/test_utils/CMakeLists.txt +++ b/tools/unit-test-app/components/test_utils/CMakeLists.txt @@ -1,4 +1,4 @@ -idf_component_register(SRCS "ref_clock_${CONFIG_IDF_TARGET}.c" +idf_component_register(SRCS "ref_clock.c" "test_runner.c" "test_utils.c" INCLUDE_DIRS include diff --git a/tools/unit-test-app/components/test_utils/component.mk b/tools/unit-test-app/components/test_utils/component.mk index 0123566204..e69de29bb2 100644 --- a/tools/unit-test-app/components/test_utils/component.mk +++ b/tools/unit-test-app/components/test_utils/component.mk @@ -1 +0,0 @@ -COMPONENT_OBJEXCLUDE := ref_clock_esp32s2beta.o diff --git a/tools/unit-test-app/components/test_utils/ref_clock_esp32.c b/tools/unit-test-app/components/test_utils/ref_clock.c similarity index 94% rename from tools/unit-test-app/components/test_utils/ref_clock_esp32.c rename to tools/unit-test-app/components/test_utils/ref_clock.c index ef7545f750..a0ecd887b6 100644 --- a/tools/unit-test-app/components/test_utils/ref_clock_esp32.c +++ b/tools/unit-test-app/components/test_utils/ref_clock.c @@ -39,9 +39,9 @@ #include "freertos/FreeRTOS.h" #include "driver/periph_ctrl.h" #include "esp32/rom/gpio.h" +#include "sdkconfig.h" /* Select which RMT and PCNT channels, and GPIO to use */ -#define REF_CLOCK_RMT_CHANNEL 7 #define REF_CLOCK_PCNT_UNIT 0 #define REF_CLOCK_GPIO 21 @@ -53,7 +53,25 @@ static intr_handle_t s_intr_handle; static portMUX_TYPE s_lock = portMUX_INITIALIZER_UNLOCKED; static volatile uint32_t s_milliseconds; -void ref_clock_init(void) +#if CONFIG_IDF_TARGET_ESP32 +#define REF_CLOCK_RMT_CHANNEL 7 + +static int get_pcnt_sig(void) +{ + return (REF_CLOCK_PCNT_UNIT < 5) ? + PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT : + PCNT_SIG_CH0_IN5_IDX + 4 * (REF_CLOCK_PCNT_UNIT - 5); +} +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#define REF_CLOCK_RMT_CHANNEL 3 + +static int get_pcnt_sig(void) +{ + return PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT; +} +#endif + +void ref_clock_init() { assert(s_intr_handle == NULL && "already initialized"); @@ -87,9 +105,7 @@ void ref_clock_init(void) RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_start = 1; // Route signal to PCNT - int pcnt_sig_idx = (REF_CLOCK_PCNT_UNIT < 5) ? - PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT : - PCNT_SIG_CH0_IN5_IDX + 4 * (REF_CLOCK_PCNT_UNIT - 5); + int pcnt_sig_idx = get_pcnt_sig(); gpio_matrix_in(REF_CLOCK_GPIO, pcnt_sig_idx, false); if (REF_CLOCK_GPIO != 20) { PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[REF_CLOCK_GPIO]); @@ -133,7 +149,7 @@ static void IRAM_ATTR pcnt_isr(void* arg) portEXIT_CRITICAL_ISR(&s_lock); } -void ref_clock_deinit(void) +void ref_clock_deinit() { assert(s_intr_handle && "deinit called without init"); @@ -152,7 +168,7 @@ void ref_clock_deinit(void) periph_module_disable(PERIPH_PCNT_MODULE); } -uint64_t ref_clock_get(void) +uint64_t ref_clock_get() { portENTER_CRITICAL(&s_lock); uint32_t microseconds = PCNT.cnt_unit[REF_CLOCK_PCNT_UNIT].cnt_val; diff --git a/tools/unit-test-app/components/test_utils/ref_clock_esp32s2beta.c b/tools/unit-test-app/components/test_utils/ref_clock_esp32s2beta.c deleted file mode 100644 index deaef88af4..0000000000 --- a/tools/unit-test-app/components/test_utils/ref_clock_esp32s2beta.c +++ /dev/null @@ -1 +0,0 @@ -#warning "unit_test_app ref_clock not implemented for esp32s2beta" diff --git a/tools/unit-test-app/configs/aes_no_hw_s2 b/tools/unit-test-app/configs/aes_no_hw_s2 new file mode 100644 index 0000000000..69071c5451 --- /dev/null +++ b/tools/unit-test-app/configs/aes_no_hw_s2 @@ -0,0 +1,4 @@ +TEST_EXCLUDE_COMPONENTS=libsodium bt app_update +TEST_COMPONENTS=mbedtls +CONFIG_MBEDTLS_HARDWARE_AES=n +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/configs/default_2_s2 b/tools/unit-test-app/configs/default_2_s2 new file mode 100644 index 0000000000..c07c0833cf --- /dev/null +++ b/tools/unit-test-app/configs/default_2_s2 @@ -0,0 +1,2 @@ +TEST_EXCLUDE_COMPONENTS=libsodium bt app_update freertos esp32s2beta driver heap pthread soc spi_flash vfs +CONFIG_IDF_TARGET="esp32s2beta" \ No newline at end of file diff --git a/tools/unit-test-app/configs/default_s2 b/tools/unit-test-app/configs/default_s2 new file mode 100644 index 0000000000..e55c68be0a --- /dev/null +++ b/tools/unit-test-app/configs/default_s2 @@ -0,0 +1,2 @@ +TEST_COMPONENTS=freertos esp32s2beta driver heap pthread soc spi_flash vfs +CONFIG_IDF_TARGET="esp32s2beta" \ No newline at end of file diff --git a/tools/unit-test-app/configs/freertos_compliance_s2 b/tools/unit-test-app/configs/freertos_compliance_s2 new file mode 100644 index 0000000000..e94fa8863b --- /dev/null +++ b/tools/unit-test-app/configs/freertos_compliance_s2 @@ -0,0 +1,3 @@ +TEST_COMPONENTS=driver esp32s2beta spi_flash +CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/configs/libsodium_s2 b/tools/unit-test-app/configs/libsodium_s2 new file mode 100644 index 0000000000..9485da494f --- /dev/null +++ b/tools/unit-test-app/configs/libsodium_s2 @@ -0,0 +1,4 @@ +TEST_COMPONENTS=libsodium +TEST_EXCLUDE_COMPONENTS=bt app_update +CONFIG_UNITY_FREERTOS_STACK_SIZE=12288 +CONFIG_IDF_TARGET="esp32s2beta" \ No newline at end of file diff --git a/tools/unit-test-app/configs/release_2_s2 b/tools/unit-test-app/configs/release_2_s2 new file mode 100644 index 0000000000..b392e48fd2 --- /dev/null +++ b/tools/unit-test-app/configs/release_2_s2 @@ -0,0 +1,4 @@ +TEST_EXCLUDE_COMPONENTS=libsodium bt app_update freertos esp32s2beta driver heap pthread soc spi_flash vfs +CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/configs/release_s2 b/tools/unit-test-app/configs/release_s2 new file mode 100644 index 0000000000..aaa50b0ce4 --- /dev/null +++ b/tools/unit-test-app/configs/release_s2 @@ -0,0 +1,4 @@ +TEST_COMPONENTS=freertos esp32s2beta driver heap pthread soc spi_flash vfs +CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/configs/single_core_2_s2 b/tools/unit-test-app/configs/single_core_2_s2 new file mode 100644 index 0000000000..b9bbf882da --- /dev/null +++ b/tools/unit-test-app/configs/single_core_2_s2 @@ -0,0 +1,5 @@ +TEST_EXCLUDE_COMPONENTS=libsodium bt app_update freertos esp32s2beta driver heap pthread soc spi_flash vfs +CONFIG_MEMMAP_SMP=n +CONFIG_FREERTOS_UNICORE=y +CONFIG_ESP32_RTCDATA_IN_FAST_MEM=y +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/configs/single_core_s2 b/tools/unit-test-app/configs/single_core_s2 new file mode 100644 index 0000000000..e7353a4994 --- /dev/null +++ b/tools/unit-test-app/configs/single_core_s2 @@ -0,0 +1,5 @@ +TEST_COMPONENTS=freertos esp32s2beta driver heap pthread soc spi_flash vfs +CONFIG_MEMMAP_SMP=n +CONFIG_FREERTOS_UNICORE=y +CONFIG_ESP32_RTCDATA_IN_FAST_MEM=y +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/disabled_configs/app_update_s2 b/tools/unit-test-app/disabled_configs/app_update_s2 new file mode 100644 index 0000000000..9a714628db --- /dev/null +++ b/tools/unit-test-app/disabled_configs/app_update_s2 @@ -0,0 +1,14 @@ +TEST_COMPONENTS=app_update +TEST_EXCLUDE_COMPONENTS=libsodium bt +CONFIG_UNITY_FREERTOS_STACK_SIZE=12288 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_unit_test_two_ota.csv" +CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_two_ota.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x18000 +CONFIG_BOOTLOADER_FACTORY_RESET=y +CONFIG_BOOTLOADER_APP_TEST=y +CONFIG_BOOTLOADER_HOLD_TIME_GPIO=2 +CONFIG_BOOTLOADER_OTA_DATA_ERASE=y +CONFIG_BOOTLOADER_NUM_PIN_FACTORY_RESET=4 +CONFIG_BOOTLOADER_NUM_PIN_APP_TEST=32 +CONFIG_IDF_TARGET="esp32s2beta" \ No newline at end of file diff --git a/tools/unit-test-app/disabled_configs/psram_2_s2 b/tools/unit-test-app/disabled_configs/psram_2_s2 new file mode 100644 index 0000000000..69bb6ff1bb --- /dev/null +++ b/tools/unit-test-app/disabled_configs/psram_2_s2 @@ -0,0 +1,3 @@ +TEST_COMPONENTS=driver esp32s2beta spi_flash +CONFIG_ESP32S2_SPIRAM_SUPPORT=y +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/disabled_configs/psram_8m_s2 b/tools/unit-test-app/disabled_configs/psram_8m_s2 new file mode 100644 index 0000000000..68661d877f --- /dev/null +++ b/tools/unit-test-app/disabled_configs/psram_8m_s2 @@ -0,0 +1,5 @@ +TEST_COMPONENTS=esp32s2beta +CONFIG_ESP32S2_SPIRAM_SUPPORT=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/disabled_configs/psram_s2 b/tools/unit-test-app/disabled_configs/psram_s2 new file mode 100644 index 0000000000..be364cff75 --- /dev/null +++ b/tools/unit-test-app/disabled_configs/psram_s2 @@ -0,0 +1,3 @@ +TEST_EXCLUDE_COMPONENTS=libsodium bt app_update driver esp32s2beta spi_flash +CONFIG_ESP32S2_SPIRAM_SUPPORT=y +CONFIG_IDF_TARGET="esp32s2beta" diff --git a/tools/unit-test-app/idf_ext.py b/tools/unit-test-app/idf_ext.py index 9fea430466..d2bcc5fc4f 100644 --- a/tools/unit-test-app/idf_ext.py +++ b/tools/unit-test-app/idf_ext.py @@ -66,12 +66,19 @@ def action_extensions(base_actions, project_path=os.getcwd()): config_path = os.path.join(project_path, "configs", config_name) config = parse_config(config_path) + target = config.get("CONFIG_IDF_TARGET", "esp32").strip("'").strip('"') + + print("Reconfigure: config %s, target %s" % (config_name, target)) + + # Clean up and set idf-target + base_actions["actions"]["set-target"]["callback"]("set-target", ctx, args, target) + new_cache_values["EXCLUDE_COMPONENTS"] = config.get("EXCLUDE_COMPONENTS", "''") new_cache_values["TEST_EXCLUDE_COMPONENTS"] = config.get("TEST_EXCLUDE_COMPONENTS", "''") new_cache_values["TEST_COMPONENTS"] = config.get("TEST_COMPONENTS", "''") new_cache_values["TESTS_ALL"] = int(new_cache_values["TEST_COMPONENTS"] == "''") - - with tempfile.NamedTemporaryFile() as sdkconfig_temp: + # When delete=True, the file is invisible to kconfiglib on Windows + with tempfile.NamedTemporaryFile(delete=False) as sdkconfig_temp: # Use values from the combined defaults and the values from # config folder to build config sdkconfig_default = os.path.join(project_path, "sdkconfig.defaults") @@ -89,8 +96,8 @@ def action_extensions(base_actions, project_path=os.getcwd()): args.define_cache_entry.extend(["%s=%s" % (k, v) for k, v in new_cache_values.items()]) - reconfigure = base_actions["actions"]["reconfigure"]["callback"] - reconfigure(None, ctx, args) + base_actions["actions"]["fullclean"]["callback"]("fullclean", ctx, args) + base_actions["actions"]["reconfigure"]["callback"](None, ctx, args) # This target builds the configuration. It does not currently track dependencies, # but is good enough for CI builds if used together with clean-all-configs. diff --git a/tools/unit-test-app/tools/ConfigDependency.yml b/tools/unit-test-app/tools/ConfigDependency.yml index 2e720089a8..c9b2d46903 100644 --- a/tools/unit-test-app/tools/ConfigDependency.yml +++ b/tools/unit-test-app/tools/ConfigDependency.yml @@ -1,2 +1,4 @@ "psram": '{CONFIG_ESP32_SPIRAM_SUPPORT=y} and not {CONFIG_SPIRAM_BANKSWITCH_ENABLE=y}' "8Mpsram": "CONFIG_SPIRAM_BANKSWITCH_ENABLE=y" +"ESP32_IDF": "CONFIG_IDF_TARGET_ESP32=y" +"7.2.2": "CONFIG_IDF_TARGET_ESP32S2BETA=y" \ No newline at end of file diff --git a/tools/unit-test-app/tools/UnitTestParser.py b/tools/unit-test-app/tools/UnitTestParser.py index cf94eb0ae1..f82715768f 100644 --- a/tools/unit-test-app/tools/UnitTestParser.py +++ b/tools/unit-test-app/tools/UnitTestParser.py @@ -10,7 +10,7 @@ import CreateSectionTable TEST_CASE_PATTERN = { "initial condition": "UTINIT1", - "SDK": "ESP32_IDF", + "chip_target": "esp32", "level": "Unit", "execution time": 0, "auto test": "Yes", @@ -73,6 +73,7 @@ class Parser(object): table = CreateSectionTable.SectionTable("section_table.tmp") tags = self.parse_tags(os.path.join(config_output_folder, self.SDKCONFIG_FILE)) + print("Tags of config %s: %s" % (config_name, tags)) test_cases = [] # we could split cases of same config into multiple binaries as we have limited rom space @@ -94,7 +95,17 @@ class Parser(object): name = table.get_string("any", name_addr) desc = table.get_string("any", desc_addr) file_name = table.get_string("any", file_name_addr) - tc = self.parse_one_test_case(name, desc, file_name, config_name, stripped_config_name, tags) + + # Search in tags to set the target + target_tag_dict = {"ESP32_IDF": "esp32", "7.2.2": "esp32s2beta"} + for tag in target_tag_dict: + if tag in tags: + target = target_tag_dict[tag] + break + else: + target = "esp32" + + tc = self.parse_one_test_case(name, desc, file_name, config_name, stripped_config_name, tags, target) # check if duplicated case names # we need to use it to select case, @@ -233,7 +244,7 @@ class Parser(object): return match.group(1).split(' ') return None - def parse_one_test_case(self, name, description, file_name, config_name, stripped_config_name, tags): + def parse_one_test_case(self, name, description, file_name, config_name, stripped_config_name, tags, target): """ parse one test case :param name: test case name (summary) @@ -261,7 +272,8 @@ class Parser(object): "multi_device": prop["multi_device"], "multi_stage": prop["multi_stage"], "timeout": int(prop["timeout"]), - "tags": tags}) + "tags": tags, + "chip_target": target}) return test_case def dump_test_cases(self, test_cases): diff --git a/tools/unit-test-app/tools/get_available_configs.sh b/tools/unit-test-app/tools/get_available_configs.sh new file mode 100755 index 0000000000..c5161bd295 --- /dev/null +++ b/tools/unit-test-app/tools/get_available_configs.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +cd ${IDF_PATH}/tools/unit-test-app + +AVAL_CONFIGS="" +CONFIGS=$(ls configs) +if [ $1 == "esp32" ]; then + #echo 'Searching for configs for target "'$1'"' + for FILE in $CONFIGS + do + grep 'CONFIG_IDF_TARGET' /dev/null + if [ $? -ne 0 ]; then + # If CONFIG_IDF_TARGET not found, implies ESP32 + AVAL_CONFIGS="$AVAL_CONFIGS $FILE" + fi + grep -E '^CONFIG_IDF_TARGET="?'$1'"?$' /dev/null + if [ $? -eq 0 ]; then + AVAL_CONFIGS="$AVAL_CONFIGS $FILE" + fi + done +else + #echo 'Searching for configs for target "'$1'"' + for FILE in $CONFIGS + do + grep -E '^CONFIG_IDF_TARGET="?'$1'"?$' /dev/null + if [ $? -eq 0 ]; then + AVAL_CONFIGS="$AVAL_CONFIGS $FILE" + fi + done +fi + +echo $AVAL_CONFIGS