From 38b1fe9b11c5fd6889afe78eeb2d59499539649d Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Thu, 11 Jul 2024 17:35:50 +0800 Subject: [PATCH] feat(glitch_filter): add support for esp32c5 --- .../gpio_extensions/main/test_gpio_filter.c | 2 + .../gpio_extensions/pytest_gpio_extensions.py | 1 + .../include/hal/gpio_glitch_filter_ll.h | 66 +++++++++++++++++++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 8 +++ .../soc/esp32c5/include/soc/clk_tree_defs.h | 2 +- .../soc/esp32c5/include/soc/gpio_ext_struct.h | 23 ++++--- components/soc/esp32c5/include/soc/soc_caps.h | 6 +- .../soc/esp32c5/ld/esp32c5.peripherals.ld | 1 + 8 files changed, 96 insertions(+), 13 deletions(-) create mode 100644 components/hal/esp32c5/include/hal/gpio_glitch_filter_ll.h diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c index 6826cd15db..081d9ab2ec 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c @@ -16,6 +16,8 @@ #if CONFIG_IDF_TARGET_ESP32P4 #define TEST_FILTER_GPIO 20 +#elif CONFIG_IDF_TARGET_ESP32C5 +#define TEST_FILTER_GPIO 0 #else #define TEST_FILTER_GPIO 2 #endif diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py b/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py index 58c95c8f3a..6988a92595 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py @@ -11,6 +11,7 @@ CONFIGS = [ @pytest.mark.esp32c2 @pytest.mark.esp32c3 +@pytest.mark.esp32c5 @pytest.mark.esp32c6 @pytest.mark.esp32h2 @pytest.mark.esp32s2 diff --git a/components/hal/esp32c5/include/hal/gpio_glitch_filter_ll.h b/components/hal/esp32c5/include/hal/gpio_glitch_filter_ll.h new file mode 100644 index 0000000000..f1f5622dfc --- /dev/null +++ b/components/hal/esp32c5/include/hal/gpio_glitch_filter_ll.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include "hal/assert.h" +#include "soc/gpio_ext_struct.h" + +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable GPIO glitch filter + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_glitch_filter_enable(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, bool enable) +{ + hw->glitch_filter_chn[filter_idx].filter_chn_en = enable; +} + +/** + * @brief Set the input GPIO for the glitch filter + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param gpio_num GPIO number + */ +static inline void gpio_ll_glitch_filter_set_gpio(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t gpio_num) +{ + hw->glitch_filter_chn[filter_idx].filter_chn_input_io_num = gpio_num; +} + +/** + * @brief Set the coefficient of the glitch filter window + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param window_width Window width, in IOMUX clock ticks + * @param window_threshold Window threshold, in IOMUX clock ticks + */ +static inline void gpio_ll_glitch_filter_set_window_coeff(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t window_width, uint32_t window_thres) +{ + HAL_ASSERT(window_thres <= window_width); + hw->glitch_filter_chn[filter_idx].filter_chn_window_width = window_width - 1; + hw->glitch_filter_chn[filter_idx].filter_chn_window_thres = window_thres - 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 466607e158..91e6ffe6ed 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -399,6 +399,14 @@ config SOC_GPIO_PIN_COUNT int default 29 +config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER + bool + default y + +config SOC_GPIO_FLEX_GLITCH_FILTER_NUM + int + default 8 + config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 083b4c69a8..6c50e48480 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -402,7 +402,7 @@ typedef enum { * @brief Glitch filter clock source */ -typedef enum { // TODO: [ESP32C5] IDF-8718 (inherit from C6) +typedef enum { GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ diff --git a/components/soc/esp32c5/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/include/soc/gpio_ext_struct.h index 56aa2ecdd9..adf51ea44a 100644 --- a/components/soc/esp32c5/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32c5/include/soc/gpio_ext_struct.h @@ -142,13 +142,13 @@ typedef union { */ typedef union { struct { - /** filter_ch0_en : R/W; bitpos: [0]; default: 0; + /** filter_chn_en : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable channel n of Glitch Filter.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t filter_ch0_en:1; - /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; + uint32_t filter_chn_en:1; + /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0; * Configures to select the input GPIO for Glitch Filter. \\ * 0: Select GPIO0\\ * 1: Select GPIO1\\ @@ -157,20 +157,20 @@ typedef union { * 28: Select GPIO28\\ * 29 ~ 63: Reserved\\ */ - uint32_t filter_ch0_input_io_num:6; + uint32_t filter_chn_input_io_num:6; uint32_t reserved_7:1; - /** filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0; + /** filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be * less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.\\ %see DOC-4768\\ * Measurement unit: IO MUX operating clock cycle\\ */ - uint32_t filter_ch0_window_thres:6; - /** filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0; + uint32_t filter_chn_window_thres:6; + /** filter_chn_window_width : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width * is 0 ~ 63. \\ * Measurement unit: IO MUX operating clock cycle\\ */ - uint32_t filter_ch0_window_width:6; + uint32_t filter_chn_window_width:6; uint32_t reserved_20:12; }; uint32_t val; @@ -454,13 +454,17 @@ typedef struct gpio_etm_dev_t { volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[6]; } gpio_etm_dev_t; +typedef struct { + volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8]; +} gpio_glitch_filter_dev_t; + typedef struct { volatile gpio_sd_dev_t sigma_delta; uint32_t reserved_018[16]; volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0; volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0; uint32_t reserved_060[30]; - volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8]; + volatile gpio_glitch_filter_dev_t glitch_filter; uint32_t reserved_0f8[8]; volatile gpio_etm_dev_t etm; uint32_t reserved_170[24]; @@ -474,6 +478,7 @@ typedef struct { } gpio_ext_dev_t; extern gpio_sd_dev_t SDM; +extern gpio_glitch_filter_dev_t GLITCH_FILTER; extern gpio_etm_dev_t GPIO_ETM; extern gpio_ext_dev_t GPIO_EXT; diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 6e02acdff0..56cadf63a7 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -188,9 +188,9 @@ // ESP32-C5 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 29 -// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 -#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 +#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 +#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension #define SOC_GPIO_SUPPORT_ETM 1 diff --git a/components/soc/esp32c5/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld index 31097118a3..e1f8c4a005 100644 --- a/components/soc/esp32c5/ld/esp32c5.peripherals.ld +++ b/components/soc/esp32c5/ld/esp32c5.peripherals.ld @@ -44,6 +44,7 @@ PROVIDE ( IO_MUX = 0x60090000 ); PROVIDE ( GPIO = 0x60091000 ); PROVIDE ( GPIO_EXT = 0x60091e00 ); PROVIDE ( SDM = 0x60091e00 ); +PROVIDE ( GLITCH_FILTER = 0x60091ed8 ); PROVIDE ( GPIO_ETM = 0x60091f18 ); PROVIDE ( MEM_MONITOR = 0x60092000 ); PROVIDE ( PAU = 0x60093000 );