From 4c267ef0a6f83712b200fcb035856da6e6e7e484 Mon Sep 17 00:00:00 2001
From: songruojing <songruojing@espressif.com>
Date: Thu, 10 Feb 2022 20:59:27 +0800
Subject: [PATCH] gpio: Fix some gpio pin num errors on esp32s2

---
 components/driver/test/test_gpio.c                 | 4 ++--
 components/soc/soc/esp32s2/gpio_periph.c           | 2 --
 components/soc/soc/esp32s2/include/soc/gpio_caps.h | 4 ++--
 components/soc/soc/esp32s2/rtc_io_periph.c         | 1 -
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c
index e7c6964a51..d0bf3b1e6c 100644
--- a/components/driver/test/test_gpio.c
+++ b/components/driver/test/test_gpio.c
@@ -728,11 +728,11 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
 {
     const int test_io18 = GPIO_NUM_18;
     const int test_io19 = GPIO_NUM_19;
-    static gpio_isr_param_t io18_param = {
+    gpio_isr_param_t io18_param = {
         .gpio_num =  GPIO_NUM_18,
         .isr_cnt = 0,
     };
-    static gpio_isr_param_t io19_param = {
+    gpio_isr_param_t io19_param = {
         .gpio_num =  GPIO_NUM_19,
         .isr_cnt = 0,
     };
diff --git a/components/soc/soc/esp32s2/gpio_periph.c b/components/soc/soc/esp32s2/gpio_periph.c
index 03ef9143b1..af749a16a7 100644
--- a/components/soc/soc/esp32s2/gpio_periph.c
+++ b/components/soc/soc/esp32s2/gpio_periph.c
@@ -62,7 +62,6 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
     IO_MUX_GPIO44_REG,
     IO_MUX_GPIO45_REG,
     IO_MUX_GPIO46_REG,
-    0,
 };
 
 const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
@@ -113,5 +112,4 @@ const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
     BIT(23),
     BIT(24),
     BIT(25),
-    BIT(26),
 };
diff --git a/components/soc/soc/esp32s2/include/soc/gpio_caps.h b/components/soc/soc/esp32s2/include/soc/gpio_caps.h
index 8039602a7f..f063b953da 100644
--- a/components/soc/soc/esp32s2/include/soc/gpio_caps.h
+++ b/components/soc/soc/esp32s2/include/soc/gpio_caps.h
@@ -20,9 +20,9 @@ extern "C" {
 
 // ESP32-S2 has 1 GPIO peripheral
 #define SOC_GPIO_PORT           (1)
-#define GPIO_PIN_COUNT          (48)
+#define GPIO_PIN_COUNT          (47)
 
-// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. 
+// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register.
 // On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
 #define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
 // Force hold is a new function of ESP32-S2
diff --git a/components/soc/soc/esp32s2/rtc_io_periph.c b/components/soc/soc/esp32s2/rtc_io_periph.c
index 92326be96a..5d797bb6f7 100644
--- a/components/soc/soc/esp32s2/rtc_io_periph.c
+++ b/components/soc/soc/esp32s2/rtc_io_periph.c
@@ -62,7 +62,6 @@ const int rtc_io_num_map[GPIO_PIN_COUNT] = {
     -1,//GPIO44
     -1,//GPIO45
     -1,//GPIO46
-    -1,//GPIO47
 };
 
 //Reg,Mux,Fun,IE,Up,Down,Rtc_number