diff --git a/components/efuse/.build-test-rules.yml b/components/efuse/.build-test-rules.yml
index 15f8e3233d..498c17a761 100644
--- a/components/efuse/.build-test-rules.yml
+++ b/components/efuse/.build-test-rules.yml
@@ -2,6 +2,6 @@
 
 components/efuse/test_apps:
   disable_test:
-    - if: IDF_TARGET in ["esp32s2", "esp32s3", "esp32h2"]
+    - if: IDF_TARGET in ["esp32s2", "esp32s3"]
       temporary: true
-      reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3. H2 fails IDF-6897
+      reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3.
diff --git a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
index df4950f1c6..30aa478ff3 100644
--- a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
+++ b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
@@ -69,6 +69,9 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
 #ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
+#endif
+#if SOC_ECDSA_SUPPORTED
+            purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
 #endif
             purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL ||
             purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG ||
@@ -121,7 +124,10 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]")
     TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_efuse_write_key(EFUSE_BLK_KEY0, tmp_purpose, &rd_key, 33));
     TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_efuse_write_key(EFUSE_BLK10, tmp_purpose, &rd_key, sizeof(rd_key)));
 
-    for (esp_efuse_purpose_t purpose = ESP_EFUSE_KEY_PURPOSE_RESERVED; purpose < ESP_EFUSE_KEY_PURPOSE_MAX; ++purpose) {
+    for (esp_efuse_purpose_t purpose = ESP_EFUSE_KEY_PURPOSE_USER; purpose < ESP_EFUSE_KEY_PURPOSE_MAX; ++purpose) {
+        if (purpose == ESP_EFUSE_KEY_PURPOSE_USER) {
+            continue;
+        }
         esp_efuse_utility_reset();
 #ifdef CONFIG_EFUSE_FPGA_TEST
         esp_efuse_utility_update_virt_blocks();
@@ -160,7 +166,11 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]")
 
     esp_efuse_purpose_t purpose [] = {
         ESP_EFUSE_KEY_PURPOSE_USER,
+#if SOC_ECDSA_SUPPORTED
+        ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY,
+#else
         ESP_EFUSE_KEY_PURPOSE_RESERVED,
+#endif
 #ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256
         ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1,
         ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2,
diff --git a/components/efuse/test_apps/pytest_efuse.py b/components/efuse/test_apps/pytest_efuse.py
index 02211ea97a..692452b4d0 100644
--- a/components/efuse/test_apps/pytest_efuse.py
+++ b/components/efuse/test_apps/pytest_efuse.py
@@ -11,7 +11,7 @@ from pytest_embedded import Dut
 @pytest.mark.esp32c2
 @pytest.mark.esp32c3
 @pytest.mark.esp32c6
-# @pytest.mark.esp32h2  IDF-6897
+@pytest.mark.esp32h2
 @pytest.mark.generic
 def test_efuse(dut: Dut) -> None:
     dut.run_all_single_board_cases()