diff --git a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c index e2c7a370dd..7374d0589c 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c +++ b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c @@ -247,9 +247,9 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]") printf("Testing memcpy by AHB GDMA\r\n"); TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver)); test_memcpy_with_dest_addr_unaligned(driver, false, false); -#if SOC_AHB_GDMA_SUPPORT_PSRAM +#if SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED test_memcpy_with_dest_addr_unaligned(driver, true, true); -#endif // SOC_AHB_GDMA_SUPPORT_PSRAM +#endif // SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED TEST_ESP_OK(esp_async_memcpy_uninstall(driver)); #endif // SOC_AHB_GDMA_SUPPORTED @@ -257,9 +257,9 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]") printf("Testing memcpy by AXI GDMA\r\n"); TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&driver_config, &driver)); test_memcpy_with_dest_addr_unaligned(driver, false, false); -#if SOC_AXI_GDMA_SUPPORT_PSRAM +#if SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED test_memcpy_with_dest_addr_unaligned(driver, true, true); -#endif // SOC_AXI_GDMA_SUPPORT_PSRAM +#endif // SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED TEST_ESP_OK(esp_async_memcpy_uninstall(driver)); #endif // SOC_AXI_GDMA_SUPPORTED } diff --git a/components/soc/esp32h4/gdma_periph.c b/components/soc/esp32h4/gdma_periph.c index 38ba63f7b2..0fed9b87c2 100644 --- a/components/soc/esp32h4/gdma_periph.c +++ b/components/soc/esp32h4/gdma_periph.c @@ -35,3 +35,272 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; + +#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG + AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG + AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG + AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG + AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 19 +#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) +#define G0P0_RETENTION_REGS_CNT_1 4 +#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c}; +static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG + + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG + AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG + AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG + AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG + AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ + +#define G0P1_RETENTION_REGS_CNT_0 3 +#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) +#define G0P1_RETENTION_REGS_CNT_1 16 +#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200) +#define G0P1_RETENTION_REGS_CNT_2 4 +#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ + G0P1_RETENTION_REGS_CNT_2, 0, 0, \ + g0p1_regs_map2[0], g0p1_regs_map2[1], \ + g0p1_regs_map2[2], g0p1_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG + + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG + AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG + AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG + AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG + AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 3 +#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) +#define G0P2_RETENTION_REGS_CNT_1 16 +#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300) +#define G0P2_RETENTION_REGS_CNT_2 4 +#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ + G0P2_RETENTION_REGS_CNT_2, 0, 0, \ + g0p2_regs_map2[0], g0p2_regs_map2[1], \ + g0p2_regs_map2[2], g0p2_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair3) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG + + AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG + AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG + AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG + AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG + AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG + AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P3_RETENTION_REGS_CNT_0 3 +#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38) +#define G0P3_RETENTION_REGS_CNT_1 16 +#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400) +#define G0P3_RETENTION_REGS_CNT_2 4 +#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p3_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ + G0P3_RETENTION_REGS_CNT_0, 0, 0, \ + g0p3_regs_map0[0], g0p3_regs_map0[1], \ + g0p3_regs_map0[2], g0p3_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ + G0P3_RETENTION_REGS_CNT_1, 0, 0, \ + g0p3_regs_map1[0], g0p3_regs_map1[1], \ + g0p3_regs_map1[2], g0p3_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ + G0P3_RETENTION_REGS_CNT_2, 0, 0, \ + g0p3_regs_map2[0], g0p3_regs_map2[1], \ + g0p3_regs_map2[2], g0p3_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair4) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG + + AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG + AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG + AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG + AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG + AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P4_RETENTION_REGS_CNT_0 3 +#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48) +#define G0P4_RETENTION_REGS_CNT_1 20 +#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500) +static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x8, 0x0, 0x0}; +static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; +static const regdma_entries_config_t gdma_g0p4_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ + G0P4_RETENTION_REGS_CNT_0, 0, 0, \ + g0p4_regs_map0[0], g0p4_regs_map0[1], \ + g0p4_regs_map0[2], g0p4_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ + G0P4_RETENTION_REGS_CNT_1, 0, 0, \ + g0p4_regs_map1[0], g0p4_regs_map1[1], \ + g0p4_regs_map1[2], g0p4_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + }, + [3] = { + gdma_g0p3_regs_retention, + ARRAY_SIZE(gdma_g0p3_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH3, + }, + [4] = { + gdma_g0p4_regs_retention, + ARRAY_SIZE(gdma_g0p4_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH4, + }, + } +}; +#endif // SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 86de4dcd6d..4c75f8b563 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -163,6 +163,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 5 +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_AHB_GDMA_SUPPORT_PSRAM bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index a9d0b6e918..4733464237 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -184,7 +184,7 @@ #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 5 // #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: [ESP32H4] IDF-12383 -// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12384 +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 #define SOC_AHB_GDMA_SUPPORT_PSRAM 1 /*-------------------------- ETM CAPS --------------------------------------*/