From ac6101bf4eac5bf88aefe22c939c50b6601c0698 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Fri, 7 Jun 2024 21:29:44 +0800 Subject: [PATCH] feat(clk): support ESP32C5 XTAL 40M/48M selection --- .../src/bootloader_console.c | 10 ---- components/esp_hw_support/Kconfig | 46 +------------------ .../esp_hw_support/port/esp32/Kconfig.xtal | 30 ++++++++++++ .../esp_hw_support/port/esp32c2/Kconfig.xtal | 19 ++++++++ .../esp_hw_support/port/esp32c3/Kconfig.xtal | 16 +++++++ .../esp_hw_support/port/esp32c5/Kconfig.xtal | 30 ++++++++++++ .../port/esp32c5/esp_clk_tree.c | 4 +- .../port/esp32c5/include/soc/rtc.h | 14 ++---- .../esp_hw_support/port/esp32c5/rtc_clk.c | 19 ++++---- .../port/esp32c5/rtc_clk_init.c | 4 ++ .../esp_hw_support/port/esp32c5/systimer.c | 19 ++++++++ .../esp_hw_support/port/esp32c6/Kconfig.xtal | 16 +++++++ .../esp_hw_support/port/esp32c61/Kconfig.xtal | 16 +++++++ .../esp_hw_support/port/esp32h2/Kconfig.xtal | 16 +++++++ .../esp_hw_support/port/esp32p4/Kconfig.xtal | 16 +++++++ .../esp_hw_support/port/esp32s2/Kconfig.xtal | 16 +++++++ .../esp_hw_support/port/esp32s3/Kconfig.xtal | 16 +++++++ components/esp_system/Kconfig | 5 +- components/esp_system/port/soc/esp32c5/clk.c | 4 +- components/hal/CMakeLists.txt | 2 +- components/hal/esp32c5/clk_tree_hal.c | 13 +++++- .../hal/esp32c5/include/hal/clk_tree_ll.h | 16 +++++++ components/hal/esp32c5/include/hal/i2s_ll.h | 4 +- components/soc/esp32/include/soc/soc_caps.h | 2 +- .../mp/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32c5/mp/include/soc/soc.h | 5 -- .../soc/esp32c5/mp/include/soc/soc_caps.h | 1 + docs/en/get-started/start-project.rst | 3 +- docs/zh_CN/get-started/start-project.rst | 3 +- 29 files changed, 270 insertions(+), 99 deletions(-) create mode 100644 components/esp_hw_support/port/esp32/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32c2/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32c3/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32c5/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32c6/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32c61/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32h2/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32p4/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32s2/Kconfig.xtal create mode 100644 components/esp_hw_support/port/esp32s3/Kconfig.xtal diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 66ee195a3b..2001bb52a1 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -25,9 +25,6 @@ #include "esp_rom_uart.h" #include "esp_rom_sys.h" #include "esp_rom_caps.h" -#if CONFIG_IDF_TARGET_ESP32C5 -#include "soc/pcr_reg.h" -#endif #ifdef CONFIG_ESP_CONSOLE_NONE void bootloader_console_init(void) @@ -88,13 +85,6 @@ void bootloader_console_init(void) #if ESP_ROM_UART_CLK_IS_XTAL clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM #endif -#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION -#if CONFIG_IDF_ENV_FPGA - clock_hz = CONFIG_XTAL_FREQ * MHZ; -#else - clock_hz = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_CLK_XTAL_FREQ) * MHZ; -#endif // CONFIG_IDF_ENV_FPGA -#endif // CONFIG_IDF_TARGET_ESP32C5_MP_VERSION esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); } #endif // CONFIG_ESP_CONSOLE_UART diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index b6b44bac40..48c66d1137 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -240,51 +240,7 @@ menu "Hardware Settings" rsource "./dma/Kconfig.dma" menu "Main XTAL Config" - # TODO: IDF-8943 - choice XTAL_FREQ_SEL - prompt "Main XTAL frequency" - default XTAL_FREQ_48 if SOC_XTAL_SUPPORT_48M - default XTAL_FREQ_40 if (SOC_XTAL_SUPPORT_40M && !SOC_XTAL_SUPPORT_48M) - help - This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. - The selected value MUST reflect the frequency of the given hardware. - - Note: The XTAL_FREQ_AUTO option allows the ESP target to automatically estimating XTAL clock's - operating frequency. However, this feature is only supported on the ESP32. The ESP32 uses the - internal 8MHZ as a reference when estimating. Due to the internal oscillator's frequency being - temperature dependent, usage of the XTAL_FREQ_AUTO is not recommended in applications that operate - in high ambient temperatures or use high-temperature qualified chips and modules. - - config XTAL_FREQ_24 - depends on SOC_XTAL_SUPPORT_24M - bool "24 MHz" - config XTAL_FREQ_26 - depends on SOC_XTAL_SUPPORT_26M - bool "26 MHz" - config XTAL_FREQ_32 - depends on SOC_XTAL_SUPPORT_32M - bool "32 MHz" - config XTAL_FREQ_40 - depends on SOC_XTAL_SUPPORT_40M - bool "40 MHz" - config XTAL_FREQ_48 - depends on SOC_XTAL_SUPPORT_48M - bool "48 MHz" - config XTAL_FREQ_AUTO - depends on SOC_XTAL_SUPPORT_AUTO_DETECT - bool "Autodetect" - endchoice - - # soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported - # SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported - config XTAL_FREQ - int - default 24 if XTAL_FREQ_24 - default 26 if XTAL_FREQ_26 - default 32 if XTAL_FREQ_32 - default 40 if XTAL_FREQ_40 - default 48 if XTAL_FREQ_48 - default 0 if XTAL_FREQ_AUTO + orsource "./port/$IDF_TARGET/Kconfig.xtal" endmenu menu "Crypto DPA Protection" diff --git a/components/esp_hw_support/port/esp32/Kconfig.xtal b/components/esp_hw_support/port/esp32/Kconfig.xtal new file mode 100644 index 0000000000..a4b9217674 --- /dev/null +++ b/components/esp_hw_support/port/esp32/Kconfig.xtal @@ -0,0 +1,30 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + Note: On ESP32, the XTAL_FREQ_AUTO option allows the ESP target to automatically estimating XTAL clock's + operating frequency. The ESP32 uses the internal 8MHZ as a reference when estimating. Due to the internal + oscillator's frequency being temperature dependent, usage of the XTAL_FREQ_AUTO is not recommended in + applications that operate in high ambient temperatures or use high-temperature qualified chips and modules. + + config XTAL_FREQ_26 + bool "26 MHz" + config XTAL_FREQ_32 + bool "32 MHz" + config XTAL_FREQ_40 + bool "40 MHz" + config XTAL_FREQ_AUTO + bool "Autodetect" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 26 if XTAL_FREQ_26 + default 32 if XTAL_FREQ_32 + default 40 if XTAL_FREQ_40 + default 0 if XTAL_FREQ_AUTO diff --git a/components/esp_hw_support/port/esp32c2/Kconfig.xtal b/components/esp_hw_support/port/esp32c2/Kconfig.xtal new file mode 100644 index 0000000000..fff229474f --- /dev/null +++ b/components/esp_hw_support/port/esp32c2/Kconfig.xtal @@ -0,0 +1,19 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_26 + bool "26 MHz" + config XTAL_FREQ_40 + bool "40 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 26 if XTAL_FREQ_26 + default 40 if XTAL_FREQ_40 diff --git a/components/esp_hw_support/port/esp32c3/Kconfig.xtal b/components/esp_hw_support/port/esp32c3/Kconfig.xtal new file mode 100644 index 0000000000..64e10afc9a --- /dev/null +++ b/components/esp_hw_support/port/esp32c3/Kconfig.xtal @@ -0,0 +1,16 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_40 + bool "40 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 40 if XTAL_FREQ_40 diff --git a/components/esp_hw_support/port/esp32c5/Kconfig.xtal b/components/esp_hw_support/port/esp32c5/Kconfig.xtal new file mode 100644 index 0000000000..d56aa63cd9 --- /dev/null +++ b/components/esp_hw_support/port/esp32c5/Kconfig.xtal @@ -0,0 +1,30 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_48 if IDF_TARGET_ESP32C5_BETA3_VERSION + default XTAL_FREQ_AUTO + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + Note: ESP32C5 supports crystal frequencies of 40 MHz and 48 MHz. With XTAL_FREQ_AUTO option, boot + mode together with MTMS pin, EFUSE_XTAL_48M_SEL, and EFUSE_XTAL_48M_SEL_MODE collectively control + the crystal frequency, and record to PCR_CLK_XTAL_FREQ register field. + + config XTAL_FREQ_AUTO + depends on IDF_TARGET_ESP32C5_MP_VERSION + bool "Autodetect" + config XTAL_FREQ_40 + depends on IDF_TARGET_ESP32C5_BETA3_VERSION + bool "40 MHz" + config XTAL_FREQ_48 + depends on IDF_TARGET_ESP32C5_BETA3_VERSION + bool "48 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 0 if XTAL_FREQ_AUTO + default 40 if XTAL_FREQ_40 + default 48 if XTAL_FREQ_48 diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c index 0d34304800..b1071191ad 100644 --- a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c @@ -27,7 +27,7 @@ uint32_t *freq_value) uint32_t clk_src_freq = 0; switch (clk_src) { case SOC_MOD_CLK_XTAL: - clk_src_freq = CONFIG_XTAL_FREQ * MHZ; + clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ; break; case SOC_MOD_CLK_PLL_F80M: clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ; @@ -51,7 +51,7 @@ uint32_t *freq_value) clk_src_freq = SOC_CLK_RC_FAST_FREQ_APPROX; break; case SOC_MOD_CLK_XTAL_D2: - clk_src_freq = (CONFIG_XTAL_FREQ * MHZ) >> 1; + clk_src_freq = (clk_hal_xtal_get_freq_mhz() * MHZ) >> 1; break; default: break; diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index b066b5032a..fbfa69a616 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -10,6 +10,7 @@ #include #include "soc/soc.h" #include "soc/clk_tree_defs.h" +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { @@ -186,6 +187,7 @@ void rtc_clk_init(rtc_clk_config_t cfg); */ soc_xtal_freq_t rtc_clk_xtal_freq_get(void); +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION /** * @brief Update XTAL frequency * @@ -195,6 +197,7 @@ soc_xtal_freq_t rtc_clk_xtal_freq_get(void); * @param xtal_freq New frequency value */ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq); +#endif /** * @brief Enable or disable 32 kHz XTAL oscillator @@ -452,17 +455,6 @@ bool rtc_dig_8m_enabled(void); */ uint32_t rtc_clk_freq_cal(uint32_t cal_val); - -// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- -// **WARNING**: The following are only for backwards compatibility. -// Please use the declarations in soc/clk_tree_defs.h instead. -/** - * @brief Possible main XTAL frequency values. TODO: To be removed! - */ -typedef soc_xtal_freq_t rtc_xtal_freq_t; -#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL -#define RTC_XTAL_FREQ_48M SOC_XTAL_FREQ_48M //!< 48 MHz XTAL - #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index c44ccb9b31..c451899685 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -477,21 +477,25 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) soc_xtal_freq_t rtc_clk_xtal_freq_get(void) { #if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION - return CONFIG_XTAL_FREQ; -#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz(); if (xtal_freq_mhz == 0) { - ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); - return RTC_XTAL_FREQ_40M; + ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 48MHz"); + return SOC_XTAL_FREQ_48M; } return (soc_xtal_freq_t)xtal_freq_mhz; +#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + uint32_t xtal_freq_mhz = clk_ll_xtal_get_freq_mhz(); + assert(xtal_freq_mhz == SOC_XTAL_FREQ_48M || xtal_freq_mhz == SOC_XTAL_FREQ_40M); + return (soc_xtal_freq_t)xtal_freq_mhz; #endif } +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq) { clk_ll_xtal_store_freq_mhz(xtal_freq); } +#endif static uint32_t rtc_clk_ahb_freq_get(void) { @@ -561,10 +565,3 @@ bool rtc_dig_8m_enabled(void) { return clk_ll_rc_fast_digi_is_enabled(); } - -#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION -/* Name used in libphy.a:phy_chip_v7.o - * TODO: update the library to use rtc_clk_xtal_freq_get - */ -rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get"))); -#endif diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c index dfbce0b2ce..c06d879455 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c @@ -84,9 +84,13 @@ void rtc_clk_init(rtc_clk_config_t cfg) clk_ll_rc_fast_tick_conf(); // TODO: IDF-8642 Unnecessary or not? +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION soc_xtal_freq_t xtal_freq = cfg.xtal_freq; esp_rom_output_tx_wait_idle(0); rtc_clk_xtal_freq_update(xtal_freq); +#else + // XTAL freq determined by efuse, and can be directly informed from register field PCR_CLK_XTAL_FREQ +#endif /* Set CPU frequency */ rtc_clk_cpu_freq_get_config(&old_config); diff --git a/components/esp_hw_support/port/esp32c5/systimer.c b/components/esp_hw_support/port/esp32c5/systimer.c index f217295de2..6b367ec2cc 100644 --- a/components/esp_hw_support/port/esp32c5/systimer.c +++ b/components/esp_hw_support/port/esp32c5/systimer.c @@ -6,7 +6,9 @@ #include "sdkconfig.h" #include "esp_private/systimer.h" +#include "hal/clk_tree_ll.h" +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION #if CONFIG_XTAL_FREQ_40 /** * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5). @@ -35,3 +37,20 @@ uint64_t systimer_us_to_ticks(uint64_t us) #else #error "Unsupported XTAL frequency by systimer" #endif // CONFIG_XTAL_FREQ_xx + +#else // !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION +/** + * @brief systimer's clock source is fixed to XTAL, the fixed fractional divider is changed according to + * EFUSE_XTAL_48M_SEL. No matter 48MHz or 40MHz XTAL, the resolution of the systimer is always 16MHz. + */ + +uint64_t systimer_ticks_to_us(uint64_t ticks) +{ + return ticks / 16; +} + +uint64_t systimer_us_to_ticks(uint64_t us) +{ + return us * 16; +} +#endif diff --git a/components/esp_hw_support/port/esp32c6/Kconfig.xtal b/components/esp_hw_support/port/esp32c6/Kconfig.xtal new file mode 100644 index 0000000000..64e10afc9a --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/Kconfig.xtal @@ -0,0 +1,16 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_40 + bool "40 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 40 if XTAL_FREQ_40 diff --git a/components/esp_hw_support/port/esp32c61/Kconfig.xtal b/components/esp_hw_support/port/esp32c61/Kconfig.xtal new file mode 100644 index 0000000000..64e10afc9a --- /dev/null +++ b/components/esp_hw_support/port/esp32c61/Kconfig.xtal @@ -0,0 +1,16 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_40 + bool "40 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 40 if XTAL_FREQ_40 diff --git a/components/esp_hw_support/port/esp32h2/Kconfig.xtal b/components/esp_hw_support/port/esp32h2/Kconfig.xtal new file mode 100644 index 0000000000..e9aa20e3b5 --- /dev/null +++ b/components/esp_hw_support/port/esp32h2/Kconfig.xtal @@ -0,0 +1,16 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_32 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_32 + bool "32 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 32 if XTAL_FREQ_32 diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.xtal b/components/esp_hw_support/port/esp32p4/Kconfig.xtal new file mode 100644 index 0000000000..64e10afc9a --- /dev/null +++ b/components/esp_hw_support/port/esp32p4/Kconfig.xtal @@ -0,0 +1,16 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_40 + bool "40 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 40 if XTAL_FREQ_40 diff --git a/components/esp_hw_support/port/esp32s2/Kconfig.xtal b/components/esp_hw_support/port/esp32s2/Kconfig.xtal new file mode 100644 index 0000000000..64e10afc9a --- /dev/null +++ b/components/esp_hw_support/port/esp32s2/Kconfig.xtal @@ -0,0 +1,16 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_40 + bool "40 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 40 if XTAL_FREQ_40 diff --git a/components/esp_hw_support/port/esp32s3/Kconfig.xtal b/components/esp_hw_support/port/esp32s3/Kconfig.xtal new file mode 100644 index 0000000000..64e10afc9a --- /dev/null +++ b/components/esp_hw_support/port/esp32s3/Kconfig.xtal @@ -0,0 +1,16 @@ +choice XTAL_FREQ + prompt "Main XTAL frequency" + default XTAL_FREQ_40 + help + This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. + The selected value MUST reflect the frequency of the given hardware. + + config XTAL_FREQ_40 + bool "40 MHz" +endchoice + +# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported +# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported +config XTAL_FREQ + int + default 40 if XTAL_FREQ_40 diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index c5f33787ed..8a5addc5a2 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -360,8 +360,7 @@ menu "ESP System Settings" prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM depends on ESP_CONSOLE_UART default 74880 if (IDF_TARGET_ESP32C2 && XTAL_FREQ_26) - # TODO: IDF-8651 Check if need update - default 138240 if (IDF_TARGET_ESP32C5 && XTAL_FREQ_48) + default 138240 if (IDF_TARGET_ESP32C5_BETA3_VERSION && XTAL_FREQ_48) default 115200 range 1200 4000000 if !PM_ENABLE range 1200 1000000 if PM_ENABLE @@ -411,7 +410,7 @@ menu "ESP System Settings" default 800 if (SPIRAM && IDF_TARGET_ESP32) range 10 10000 help - The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate. + The timeout of the watchdog, in milliseconds. Make this higher than the FreeRTOS tick rate. config ESP_INT_WDT_CHECK_CPU1 bool "Also watch CPU1 tick interrupt" diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 38aa5f9a6c..ab78ffd86f 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -60,14 +60,14 @@ __attribute__((weak)) void esp_clk_init(void) #endif rtc_clk_8m_enable(true); rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); -#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION +#else #if !CONFIG_IDF_ENV_FPGA pmu_init(); if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) { esp_ocode_calib_init(); } - assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M); + assert((rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_48M) || (rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M)); rtc_clk_8m_enable(true); rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 7e9c0fe2c4..ac66ab026c 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -62,7 +62,7 @@ if(NOT BOOTLOADER_BUILD) endif() endif() - if(CONFIG_SOC_CLK_TREE_SUPPORTED) + if(CONFIG_SOC_CLK_TREE_SUPPORTED OR CONFIG_IDF_TARGET_ESP32C5) # TODO: IDF-8642 list(APPEND srcs "${target}/clk_tree_hal.c") endif() diff --git a/components/hal/esp32c5/clk_tree_hal.c b/components/hal/esp32c5/clk_tree_hal.c index d68db76ccd..2b5ba166cd 100644 --- a/components/hal/esp32c5/clk_tree_hal.c +++ b/components/hal/esp32c5/clk_tree_hal.c @@ -10,8 +10,11 @@ #include "hal/clk_tree_ll.h" #include "hal/gpio_ll.h" #include "hal/log.h" +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION static const char *CLK_HAL_TAG = "clk_hal"; +#endif uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) { @@ -85,12 +88,18 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void) uint32_t clk_hal_xtal_get_freq_mhz(void) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION uint32_t freq = clk_ll_xtal_load_freq_mhz(); if (freq == 0) { - HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); - return (uint32_t)SOC_XTAL_FREQ_40M; + HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 48MHz"); + return (uint32_t)SOC_XTAL_FREQ_48M; } return freq; +#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + uint32_t freq = clk_ll_xtal_get_freq_mhz(); + HAL_ASSERT(freq == SOC_XTAL_FREQ_48M || freq == SOC_XTAL_FREQ_40M); + return freq; +#endif } void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) diff --git a/components/hal/esp32c5/include/hal/clk_tree_ll.h b/components/hal/esp32c5/include/hal/clk_tree_ll.h index dcfe9aa417..57e6d62257 100644 --- a/components/hal/esp32c5/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c5/include/hal/clk_tree_ll.h @@ -266,6 +266,20 @@ static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(v return LP_CLKRST.clk_to_hp.icg_hp_osc32k; } +#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION +/** + * @brief Get XTAL_CLK frequency + * + * PCR_CLK_XTAL_FREQ updates its value based on EFUSE_XTAL_48M_SEL. + * + * @return Main XTAL clock frequency, in MHz. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void) +{ + return PCR.sysclk_conf.clk_xtal_freq; +} +#endif + /** * @brief Get PLL_CLK frequency * @@ -910,6 +924,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uin } /************************** LP STORAGE REGISTER STORE/LOAD **************************/ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION /** * @brief Store XTAL_CLK frequency in RTC storage register * @@ -950,6 +965,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz( // If the format in reg is invalid return 0; } +#endif /** * @brief Store RTC_SLOW_CLK calibration value in RTC storage register diff --git a/components/hal/esp32c5/include/hal/i2s_ll.h b/components/hal/esp32c5/include/hal/i2s_ll.h index c14a4bf4ae..0ea81b3b27 100644 --- a/components/hal/esp32c5/include/hal/i2s_ll.h +++ b/components/hal/esp32c5/include/hal/i2s_ll.h @@ -35,8 +35,8 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width -#define I2S_LL_XTAL_CLK_FREQ (CONFIG_XTAL_FREQ * 1000000) // XTAL_CLK: 40MHz or 48MHz -#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source on P4, use XTAL as default +#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz +#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT /** * @brief Enable the bus clock for I2S module diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 97b1c6e930..004e2de7cc 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -114,7 +114,7 @@ /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_26M 1 #define SOC_XTAL_SUPPORT_40M 1 -#define SOC_XTAL_SUPPORT_AUTO_DETECT 1 +#define SOC_XTAL_SUPPORT_AUTO_DETECT 1 // Measure XTAL freq with an internal RC clock /*-------------------------- ADC CAPS ----------------------------------------*/ /*!< SAR ADC Module*/ diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in index e36ec0f749..b303da8a7d 100644 --- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in @@ -127,6 +127,10 @@ config SOC_XTAL_SUPPORT_48M bool default y +config SOC_XTAL_SUPPORT_EFUSE_SEL + bool + default y + config SOC_AES_SUPPORT_DMA bool default y diff --git a/components/soc/esp32c5/mp/include/soc/soc.h b/components/soc/esp32c5/mp/include/soc/soc.h index 5c3ac9c8e9..8185b1fccc 100644 --- a/components/soc/esp32c5/mp/include/soc/soc.h +++ b/components/soc/esp32c5/mp/include/soc/soc.h @@ -134,15 +134,10 @@ //}} //Periheral Clock {{ -#define APB_CLK_FREQ_ROM ( 40*1000000 ) -#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration -#define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 40*1000000 ) #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define XTAL_CLK_FREQ (40*1000000) #define GPIO_MATRIX_DELAY_NS 0 //}} diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index 9f2762b069..98d5ebd93e 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -78,6 +78,7 @@ /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 #define SOC_XTAL_SUPPORT_48M 1 +#define SOC_XTAL_SUPPORT_EFUSE_SEL 1 // XTAL freq in runtime determined through EFUSE_XTAL_48M_SEL /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) diff --git a/docs/en/get-started/start-project.rst b/docs/en/get-started/start-project.rst index 9826f7130c..6f4b5ebc06 100644 --- a/docs/en/get-started/start-project.rst +++ b/docs/en/get-started/start-project.rst @@ -115,14 +115,13 @@ To exit IDF monitor use the shortcut ``Ctrl+]``. 1. Exit the monitor. 2. Go back to ``menuconfig``. - 3. Go to ``Component config`` --> ``Hardware Settings`` --> ``Main XTAL Config`` --> ``Main XTAL frequency``, then change :ref:`CONFIG_XTAL_FREQ_SEL` to 26 MHz. + 3. Go to ``Component config`` --> ``Hardware Settings`` --> ``Main XTAL Config`` --> ``Main XTAL frequency``, then change :ref:`CONFIG_XTAL_FREQ` to 26 MHz. 4. After that, ``build and flash`` the application again. In the current version of ESP-IDF, main XTAL frequencies supported by {IDF_TARGET_NAME} are as follows: .. list:: - :SOC_XTAL_SUPPORT_24M: - 24 MHz :SOC_XTAL_SUPPORT_26M: - 26 MHz :SOC_XTAL_SUPPORT_32M: - 32 MHz :SOC_XTAL_SUPPORT_40M: - 40 MHz diff --git a/docs/zh_CN/get-started/start-project.rst b/docs/zh_CN/get-started/start-project.rst index 982e78deca..e8462c1b83 100644 --- a/docs/zh_CN/get-started/start-project.rst +++ b/docs/zh_CN/get-started/start-project.rst @@ -115,14 +115,13 @@ 1. 退出监视器。 2. 返回 ``menuconfig``。 - 3. 进入 ``Component config`` --> ``Hardware Settings`` --> ``Main XTAL Config`` --> ``Main XTAL frequency`` 进行配置，将 :ref:`CONFIG_XTAL_FREQ_SEL` 设置为 26 MHz。 + 3. 进入 ``Component config`` --> ``Hardware Settings`` --> ``Main XTAL Config`` --> ``Main XTAL frequency`` 进行配置，将 :ref:`CONFIG_XTAL_FREQ` 设置为 26 MHz。 4. 重新 ``编译和烧录`` 应用程序。 在当前的 ESP-IDF 版本中，{IDF_TARGET_NAME} 支持的主晶振频率如下： .. list:: - :SOC_XTAL_SUPPORT_24M: - 24 MHz :SOC_XTAL_SUPPORT_26M: - 26 MHz :SOC_XTAL_SUPPORT_32M: - 32 MHz :SOC_XTAL_SUPPORT_40M: - 40 MHz