diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index b112109005..8fbf4444c4 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -424,7 +424,7 @@ static void IRAM_ATTR flush_uarts(void)
 #ifdef CONFIG_IDF_TARGET_ESP32
         esp_rom_uart_tx_wait_idle(i);
 #else
-        if (periph_ll_uart_enabled(i)) {
+        if (uart_ll_is_enabled(i)) {
             esp_rom_uart_tx_wait_idle(i);
         }
 #endif
@@ -442,7 +442,7 @@ FORCE_INLINE_ATTR void suspend_uarts(void)
     s_suspended_uarts_bmap = 0;
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
 #ifndef CONFIG_IDF_TARGET_ESP32
-        if (!periph_ll_uart_enabled(i)) {
+        if (!uart_ll_is_enabled(i)) {
             continue;
         }
 #endif
diff --git a/components/hal/esp32/include/hal/clk_gate_ll.h b/components/hal/esp32/include/hal/clk_gate_ll.h
index 6455a04431..4ab3a9aceb 100644
--- a/components/hal/esp32/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32/include/hal/clk_gate_ll.h
@@ -266,19 +266,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
-                            (uart_num == 1) ? DPORT_UART1_RST :
-                            (uart_num == 2) ? DPORT_UART2_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
-                            (uart_num == 1) ? DPORT_UART1_CLK_EN :
-                            (uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h
index fbd970c9f2..45ce8b8e9c 100644
--- a/components/hal/esp32/include/hal/uart_ll.h
+++ b/components/hal/esp32/include/hal/uart_ll.h
@@ -11,6 +11,7 @@
 #pragma once
 
 #include <stdlib.h>
+#include "hal/assert.h"
 #include "hal/misc.h"
 #include "esp_attr.h"
 #include "soc/uart_reg.h"
@@ -56,6 +57,26 @@ typedef enum {
     UART_INTR_CMD_CHAR_DET     = (0x1<<18),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
+                            (uart_num == 1) ? DPORT_UART1_RST :
+                            (uart_num == 2) ? DPORT_UART2_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
+                            (uart_num == 1) ? DPORT_UART1_CLK_EN :
+                            (uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
+}
+
 /**
  * @brief Enable the bus clock for uart
  * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
diff --git a/components/hal/esp32c2/include/hal/clk_gate_ll.h b/components/hal/esp32c2/include/hal/clk_gate_ll.h
index 69355f34f5..a832b86c9c 100644
--- a/components/hal/esp32c2/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c2/include/hal/clk_gate_ll.h
@@ -216,17 +216,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
-                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
-                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h
index 46bea10726..4b65f064f7 100644
--- a/components/hal/esp32c2/include/hal/uart_ll.h
+++ b/components/hal/esp32c2/include/hal/uart_ll.h
@@ -12,10 +12,13 @@
 #include <stdlib.h>
 #include "hal/uart_types.h"
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
 #include "soc/clk_tree_defs.h"
 #include "soc/system_struct.h"
+#include "soc/system_reg.h"
+#include "soc/dport_access.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -57,6 +60,24 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
+                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
+                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
+}
+
 /**
  * @brief  Configure the UART core reset.
  *
diff --git a/components/hal/esp32c3/include/hal/clk_gate_ll.h b/components/hal/esp32c3/include/hal/clk_gate_ll.h
index 3222449055..b76993c048 100644
--- a/components/hal/esp32c3/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c3/include/hal/clk_gate_ll.h
@@ -265,17 +265,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
-                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
-                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h
index 3a19a9a6da..03217562f4 100644
--- a/components/hal/esp32c3/include/hal/uart_ll.h
+++ b/components/hal/esp32c3/include/hal/uart_ll.h
@@ -11,11 +11,14 @@
 #pragma once
 
 #include <stdlib.h>
+#include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
 #include "soc/system_struct.h"
+#include "soc/system_reg.h"
+#include "soc/dport_access.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -57,6 +60,24 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
+                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
+                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
+}
+
 /**
  * @brief  Configure the UART core reset.
  *
diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h
index 3df27b2616..237c10d645 100644
--- a/components/hal/esp32c6/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h
@@ -330,19 +330,6 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
            REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
-                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
-                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
-                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
-    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
-        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h
index b990cf7df5..1927bbae1b 100644
--- a/components/hal/esp32c6/include/hal/uart_ll.h
+++ b/components/hal/esp32c6/include/hal/uart_ll.h
@@ -16,6 +16,7 @@
 #include "soc/uart_struct.h"
 #include "soc/lp_uart_reg.h"
 #include "soc/pcr_struct.h"
+#include "soc/pcr_reg.h"
 #include "soc/lp_clkrst_struct.h"
 #include "soc/lpperi_struct.h"
 #include "hal/assert.h"
@@ -161,6 +162,27 @@ static inline void lp_uart_ll_reset_register(int hw_id)
 #define lp_uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_reset_register(__VA_ARGS__)
 
 /*************************************** General LL functions ******************************************/
+
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
+                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
+                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
+                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
+    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
+        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
+}
+
 /**
  * @brief Sync the update to UART core clock domain
  *
diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h
index 19ba4c2aff..c0549ffdab 100644
--- a/components/hal/esp32h2/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h
@@ -394,19 +394,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
-                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
-                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
-                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
-    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
-        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h
index b25782d952..dce5c6be1d 100644
--- a/components/hal/esp32h2/include/hal/uart_ll.h
+++ b/components/hal/esp32h2/include/hal/uart_ll.h
@@ -12,11 +12,13 @@
 
 #include <stdlib.h>
 #include "esp_attr.h"
+#include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
 #include "soc/pcr_struct.h"
+#include "soc/pcr_reg.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -80,6 +82,26 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
+                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
+                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
+                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
+    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
+        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
+}
+
 /**
  * @brief Sync the update to UART core clock domain
  *
diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h
index 4a7c68f360..ae9418991a 100644
--- a/components/hal/esp32p4/include/hal/uart_ll.h
+++ b/components/hal/esp32p4/include/hal/uart_ll.h
@@ -153,6 +153,52 @@ FORCE_INLINE_ATTR void lp_uart_ll_reset_register(int hw_id)
 
 /*************************************** General LL functions ******************************************/
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    bool uart_rst_en = false;
+    bool uart_apb_en = false;
+    bool uart_sys_en = false;
+    switch (uart_num)
+    {
+    case 0:
+        uart_rst_en = HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart0_apb;
+        uart_apb_en = HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart0_apb_clk_en;
+        uart_sys_en = HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart0_sys_clk_en;
+        break;
+    case 1:
+        uart_rst_en = HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart1_apb;
+        uart_apb_en = HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart1_apb_clk_en;
+        uart_sys_en = HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart1_sys_clk_en;
+        break;
+    case 2:
+        uart_rst_en = HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart2_apb;
+        uart_apb_en = HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart2_apb_clk_en;
+        uart_sys_en = HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart2_sys_clk_en;
+        break;
+    case 3:
+        uart_rst_en = HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart3_apb;
+        uart_apb_en = HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart3_apb_clk_en;
+        uart_sys_en = HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart3_sys_clk_en;
+        break;
+    case 4:
+        uart_rst_en = HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_apb;
+        uart_apb_en = HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart4_apb_clk_en;
+        uart_sys_en = HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart4_sys_clk_en;
+        break;
+    default:
+        break;
+    }
+    return (!uart_rst_en && uart_apb_en && uart_sys_en);
+}
+
 /**
  * @brief Sync the update to UART core clock domain
  *
@@ -176,7 +222,6 @@ FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
 {
-
     if ((hw) == &UART0) {
         HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart0_core = core_rst_en;
     } else if ((hw) == &UART1) {
@@ -188,8 +233,7 @@ FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
     } else if ((hw) == &UART4) {
         HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_core = core_rst_en;
     } else {
-        // LP_UART reset shares the same register with other LP peripherals
-        // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
+        // Not going to implement LP_UART reset in this function, it will have its own LL function
         abort();
     }
 }
@@ -217,8 +261,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
     } else if ((hw) == &UART4) {
         HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_en = 1;
     } else {
-        // LP_UART reset shares the same register with other LP peripherals
-        // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
+        // Not going to implement LP_UART reset in this function, it will have its own LL function
         abort();
     }
 }
@@ -245,8 +288,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
     } else if ((hw) == &UART4) {
         HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_en = 0;
     } else {
-        // LP_UART reset shares the same register with other LP peripherals
-        // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
+        // Not going to implement LP_UART reset in this function, it will have its own LL function
         abort();
     }
 }
@@ -282,8 +324,10 @@ FORCE_INLINE_ATTR void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enabl
         HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart4_apb_clk_en = enable;
         HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart4_sys_clk_en = enable;
         break;
+    case 5:
+        // LP_UART port having its own enable_bus_clock function: lp_uart_ll_enable_bus_clock
+        break;;
     default:
-        // LP_UART
         abort();
         break;
     }
@@ -319,8 +363,10 @@ FORCE_INLINE_ATTR void uart_ll_reset_register(uart_port_t uart_num)
         HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_apb = 1;
         HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_apb = 0;
         break;
+    case 5:
+        // LP_UART port having its own enable_bus_clock function: lp_uart_ll_reset_register
+        break;;
     default:
-        // LP_UART
         abort();
         break;
     }
@@ -365,6 +411,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
     } else if ((hw) == &UART4) {
         HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_src_sel = sel_value;
     } else {
+        // LP_UART port having its own enable_bus_clock function: lp_uart_ll_set_source_clk
         abort();
     }
 }
@@ -424,7 +471,9 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
 {
 #define DIV_UP(a, b)    (((a) + (b) - 1) / (b))
     const uint32_t max_div = BIT(12) - 1;   // UART divider integer part only has 12 bits
-    int sclk_div = DIV_UP(sclk_freq, max_div * baud);
+    uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
+    if (sclk_div == 0) abort();
+
     uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
     // The baud rate configuration register is divided into
     // an integer part and a fractional part.
@@ -477,7 +526,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
     } else if ((hw) == &UART4) {
         sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num) + 1;
     } else {
-        return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag));
+        sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
     }
     return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * sclk_div);
 }
diff --git a/components/hal/esp32s2/include/hal/clk_gate_ll.h b/components/hal/esp32s2/include/hal/clk_gate_ll.h
index 28c9787f13..32ee2c457b 100644
--- a/components/hal/esp32s2/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32s2/include/hal/clk_gate_ll.h
@@ -279,17 +279,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
-                            (uart_num == 1) ? DPORT_UART1_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
-                            (uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h
index ef707f0b3f..ab7d4941be 100644
--- a/components/hal/esp32s2/include/hal/uart_ll.h
+++ b/components/hal/esp32s2/include/hal/uart_ll.h
@@ -11,6 +11,7 @@
 #pragma once
 
 #include <stdlib.h>
+#include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_reg.h"
@@ -55,6 +56,24 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
+                            (uart_num == 1) ? DPORT_UART1_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
+                            (uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
+}
+
 /**
  * @brief Enable the bus clock for uart
  * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
diff --git a/components/hal/esp32s3/include/hal/clk_gate_ll.h b/components/hal/esp32s3/include/hal/clk_gate_ll.h
index 0d2a2b1872..dfc15c868b 100644
--- a/components/hal/esp32s3/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32s3/include/hal/clk_gate_ll.h
@@ -300,19 +300,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
-                            (uart_num == 1) ? SYSTEM_UART1_RST :
-                            (uart_num == 2) ? SYSTEM_UART2_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
-                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN :
-                            (uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h
index 363f5471ab..324f88f6e3 100644
--- a/components/hal/esp32s3/include/hal/uart_ll.h
+++ b/components/hal/esp32s3/include/hal/uart_ll.h
@@ -11,11 +11,14 @@
 #pragma once
 
 #include <stdlib.h>
+#include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
 #include "soc/system_struct.h"
+#include "soc/system_reg.h"
+#include "soc/dport_access.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -57,6 +60,26 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
+                            (uart_num == 1) ? SYSTEM_UART1_RST :
+                            (uart_num == 2) ? SYSTEM_UART2_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
+                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN :
+                            (uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
+}
+
 /**
  * @brief  Configure the UART core reset.
  *
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index a3d1d0a665..628b0ba9ac 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -472,9 +472,10 @@
 
 /*-------------------------- UART CAPS ---------------------------------------*/
 // ESP32-P4 has 6 UARTs (5 HP UART, and 1 LP UART)
-// The RTC GPIO and sigmap is not supported yet, so make SOC_UART_NUM->5 to avoid lp-uart build errors
 #define SOC_UART_NUM                    (5)
 #define SOC_UART_HP_NUM                 (5)
+// TODO: 7815
+// The RTC GPIO and sigmap is not supported yet, so make SOC_UART_NUM->5 to avoid lp-uart build errors
 // #define SOC_UART_LP_NUM                 (1U)
 #define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
 #define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
diff --git a/components/soc/esp32p4/include/soc/uart_struct.h b/components/soc/esp32p4/include/soc/uart_struct.h
index 0756a2ad85..b23e6db930 100644
--- a/components/soc/esp32p4/include/soc/uart_struct.h
+++ b/components/soc/esp32p4/include/soc/uart_struct.h
@@ -883,17 +883,16 @@ typedef union {
         /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
          *  The  denominator of the frequency divider factor.
          */
-        uint32_t sclk_div_b:6;
+        uint32_t sclk_div_b:6;      //HP UART's sclk_div_b is in hp_sys_clkrst_struct.h
         /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
          *  The numerator of the frequency divider factor.
          */
-        uint32_t sclk_div_a:6;
+        uint32_t sclk_div_a:6;      //HP UART's sclk_div_a is in hp_sys_clkrst_struct.h
         /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
          *  The integral part of the frequency divider factor.
          *  It is only used by LP UART
-         *  HP UART's sclk_div_num is in hp_sys_clkrst_struct.h
          */
-        uint32_t sclk_div_num:8;
+        uint32_t sclk_div_num:8;    //HP UART's sclk_div_num is in hp_sys_clkrst_struct.h
         uint32_t reserved_20:4;
         /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
          *  Set this bit to enable UART Tx clock.
diff --git a/components/ulp/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core_uart.c
index 9fee3a0907..94e22e85d6 100644
--- a/components/ulp/lp_core/lp_core_uart.c
+++ b/components/ulp/lp_core/lp_core_uart.c
@@ -53,7 +53,7 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
     }
 
     /* Override protocol parameters from the configuration */
-    UART_CLK_ATOMIC() {
+    UART_SCLK_ATOMIC() {
         uart_hal_set_baudrate(&hal, cfg->uart_proto_cfg.baud_rate, sclk_freq);
     }
     uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);