diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
index 2ac9b2d0e1..8766a908a5 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
@@ -22,7 +22,7 @@
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 
-void bootloader_flash_update_id()
+void IRAM_ATTR bootloader_flash_update_id()
 {
     esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
     chip->device_id = bootloader_read_flash_id();
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 9e5320fa32..e1ec30482f 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -90,6 +90,7 @@
 
 #include "esp_private/spi_flash_os.h"
 #include "esp_private/mspi_timing_tuning.h"
+#include "esp_private/esp_gpio_reserve.h"
 #include "bootloader_flash_config.h"
 #include "bootloader_flash.h"
 #include "esp_private/crosscore_int.h"
@@ -576,6 +577,20 @@ void IRAM_ATTR call_start_cpu0(void)
 #endif
     }
 #endif
+
+    //----------------------------------Separator-----------------------------//
+    /**
+     * @note
+     * After this stage, you can place non-internal ram code
+     */
+
+    /* Reserve the GPIO pins */
+    uint64_t reserve_pin_mask = 0;
+    for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
+        reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
+    }
+    esp_gpio_reserve_pins(reserve_pin_mask);
+
 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 
 #if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c
index 0dd92a7810..f99fcfe4df 100644
--- a/components/spi_flash/flash_ops.c
+++ b/components/spi_flash/flash_ops.c
@@ -24,7 +24,6 @@
 #include "esp_private/system_internal.h"
 #include "esp_private/spi_flash_os.h"
 #include "esp_private/esp_clk.h"
-#include "esp_private/esp_gpio_reserve.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/cache.h"
 #include "esp32/rom/spi_flash.h"
@@ -150,12 +149,6 @@ void IRAM_ATTR esp_mspi_pin_init(void)
     }
     //Set F4R4 board pin drive strength. TODO: IDF-3663
 #endif
-    /* Reserve the GPIO pins */
-    uint64_t reserve_pin_mask = 0;
-    for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
-        reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
-    }
-    esp_gpio_reserve(reserve_pin_mask);
 }
 
 esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)