From d3c6c9ccb8d8d5d02e6aeaf722f03f0ee0af003b Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 1 Aug 2024 16:28:21 +0800 Subject: [PATCH 1/2] fix(ci): enable gpio, uart, ledc target tests on esp32p4 --- .../esp_driver_gpio/test_apps/.build-test-rules.yml | 4 ---- .../esp_driver_gpio/test_apps/gpio/main/test_rtcio.h | 8 ++++---- .../esp_driver_gpio/test_apps/gpio/pytest_gpio.py | 2 +- .../esp_driver_ledc/test_apps/.build-test-rules.yml | 4 ---- .../esp_driver_ledc/test_apps/ledc/pytest_ledc.py | 2 +- .../esp_driver_uart/test_apps/.build-test-rules.yml | 4 ---- .../esp_driver_uart/test_apps/uart/main/test_uart.c | 11 +++++++++++ .../esp_driver_uart/test_apps/uart/pytest_uart.py | 2 +- 8 files changed, 18 insertions(+), 19 deletions(-) diff --git a/components/esp_driver_gpio/test_apps/.build-test-rules.yml b/components/esp_driver_gpio/test_apps/.build-test-rules.yml index f0eb84e6e2..d9694c7aef 100644 --- a/components/esp_driver_gpio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_gpio/test_apps/.build-test-rules.yml @@ -1,10 +1,6 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps components/esp_driver_gpio/test_apps: - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: test not pass, should be re-enable # TODO: IDF-8968 depends_components: - esp_driver_gpio diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h index e2eb1f00d3..ca9a9cbca6 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -122,7 +122,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { #elif CONFIG_IDF_TARGET_ESP32P4 // Has no input-only rtcio pins, all pins support pull-up/down #define RTCIO_SUPPORT_PU_PD(num) 1 -#define TEST_GPIO_PIN_COUNT 16 +#define TEST_GPIO_PIN_COUNT 14 const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_0, //GPIO0 GPIO_NUM_1, //GPIO1 @@ -131,8 +131,8 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_4, //GPIO4 GPIO_NUM_5, //GPIO5 GPIO_NUM_6, //GPIO6 - GPIO_NUM_7, //GPIO7 - GPIO_NUM_8, //GPIO8 + // GPIO_NUM_7, //GPIO7 // Workaround: IO7 is pullup outside on ESP32P4 Core Board Runner + // GPIO_NUM_8, //GPIO8 // Workaround: IO8 is pullup outside on ESP32P4 Core Board Runner GPIO_NUM_9, //GPIO9 GPIO_NUM_10, //GPIO10 GPIO_NUM_11, //GPIO11 diff --git a/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py b/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py index 2af5378174..09cba42044 100644 --- a/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py +++ b/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py @@ -10,7 +10,6 @@ CONFIGS = [ ] -@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD') @pytest.mark.supported_targets @pytest.mark.generic @pytest.mark.parametrize('config', CONFIGS, indirect=True) @@ -23,6 +22,7 @@ def test_gpio(dut: IdfDut) -> None: @pytest.mark.esp32s3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32p4 @pytest.mark.generic @pytest.mark.parametrize('config', CONFIGS, indirect=True) def test_rtc_io(dut: IdfDut) -> None: diff --git a/components/esp_driver_ledc/test_apps/.build-test-rules.yml b/components/esp_driver_ledc/test_apps/.build-test-rules.yml index b18d676013..926f54a037 100644 --- a/components/esp_driver_ledc/test_apps/.build-test-rules.yml +++ b/components/esp_driver_ledc/test_apps/.build-test-rules.yml @@ -6,9 +6,5 @@ components/esp_driver_ledc/test_apps/ledc: - if: IDF_TARGET == "esp32c5" temporary: true reason: build failed. track in IDFCI-2204 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: test not pass, should be re-enable # TODO: IDF-8969 depends_components: - esp_driver_ledc diff --git a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py index c93955b3a9..5d4daa5beb 100644 --- a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py +++ b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py @@ -6,7 +6,7 @@ from pytest_embedded_idf import IdfDut @pytest.mark.supported_targets -@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4'], reason='skip due to duplication with test_ledc_psram, p4 TBD') # TODO: IDF-8969 +@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='skip due to duplication with test_ledc_psram') @pytest.mark.generic @pytest.mark.parametrize( 'config', diff --git a/components/esp_driver_uart/test_apps/.build-test-rules.yml b/components/esp_driver_uart/test_apps/.build-test-rules.yml index 403036b446..1e0bdf7afb 100644 --- a/components/esp_driver_uart/test_apps/.build-test-rules.yml +++ b/components/esp_driver_uart/test_apps/.build-test-rules.yml @@ -14,10 +14,6 @@ components/esp_driver_uart/test_apps/rs485: components/esp_driver_uart/test_apps/uart: disable: - if: SOC_UART_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: test not pass, should be re-enable # TODO: IDF-8971 depends_components: - esp_driver_uart - esp_driver_gpio diff --git a/components/esp_driver_uart/test_apps/uart/main/test_uart.c b/components/esp_driver_uart/test_apps/uart/main/test_uart.c index 76f6f93df4..2840e833d9 100644 --- a/components/esp_driver_uart/test_apps/uart/main/test_uart.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_uart.c @@ -10,7 +10,11 @@ #include "driver/uart.h" #include "esp_log.h" #include "esp_rom_gpio.h" +#if SOC_LP_GPIO_MATRIX_SUPPORTED #include "driver/lp_io.h" +#include "driver/rtc_io.h" +#include "hal/rtc_io_ll.h" +#endif #include "soc/uart_periph.h" #include "soc/uart_pins.h" #include "soc/soc_caps.h" @@ -469,6 +473,13 @@ TEST_CASE("uart int state restored after flush", "[uart]") } else { // LP_UART #if SOC_LP_GPIO_MATRIX_SUPPORTED + // Need to route TX signal to RX signal with the help of LP_GPIO matrix, TX signal connect to the RX IO directly + // This means RX IO should also only use LP_GPIO matrix to connect the RX signal + // In case the selected RX IO is the LP UART IOMUX IO, and the IO has been configured to IOMUX function in the driver + // Do the following: + TEST_ESP_OK(rtc_gpio_iomux_func_sel(uart_rx, RTCIO_LL_PIN_FUNC)); + const int uart_rx_signal = uart_periph_signal[uart_num].pins[SOC_UART_RX_PIN_IDX].signal; + TEST_ESP_OK(lp_gpio_connect_in_signal(uart_rx, uart_rx_signal, false)); TEST_ESP_OK(lp_gpio_connect_out_signal(uart_rx, uart_tx_signal, false, false)); #else // The only way is to use loop back feature diff --git a/components/esp_driver_uart/test_apps/uart/pytest_uart.py b/components/esp_driver_uart/test_apps/uart/pytest_uart.py index e1be06ea5f..b154e64421 100644 --- a/components/esp_driver_uart/test_apps/uart/pytest_uart.py +++ b/components/esp_driver_uart/test_apps/uart/pytest_uart.py @@ -15,7 +15,7 @@ input_argv = { @pytest.mark.supported_targets -@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4'], reason='skip due to duplication with test_uart_single_dev_psram, p4 TBD') # TODO: IDF-8971 +@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='skip due to duplication with test_uart_single_dev_psram') @pytest.mark.generic @pytest.mark.parametrize( 'config', From 16476a7a591909463b208bc2b1dc2bb8a2f4cce4 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Mon, 5 Aug 2024 21:00:37 +0800 Subject: [PATCH 2/2] fix(gpio): esp32p4 IOs cannot keep being held in the entire deep sleep process --- .../esp_driver_gpio/include/driver/gpio.h | 10 +++- components/esp_driver_gpio/src/gpio.c | 4 +- .../test_apps/gpio/main/test_gpio.c | 60 +++++++++++++++++++ .../test_apps/gpio/main/test_gpio.h | 12 +++- .../test_apps/gpio/main/test_rtcio.c | 6 +- .../test_apps/gpio/pytest_gpio.py | 1 - .../test_apps/ledc/pytest_ledc.py | 1 - .../include/esp_private/esp_sleep_internal.h | 2 +- components/esp_hw_support/sleep_gpio.c | 4 +- components/esp_hw_support/sleep_modes.c | 2 +- components/hal/esp32p4/include/hal/gpio_ll.h | 5 ++ components/hal/include/hal/gpio_hal.h | 10 ++-- .../soc/esp32/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32/include/soc/soc_caps.h | 3 + .../esp32c2/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32c2/include/soc/soc_caps.h | 3 + .../esp32c3/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32c3/include/soc/soc_caps.h | 3 + .../beta3/include/soc/Kconfig.soc_caps.in | 4 ++ .../soc/esp32c5/beta3/include/soc/soc_caps.h | 2 + .../mp/include/soc/Kconfig.soc_caps.in | 4 ++ .../soc/esp32c5/mp/include/soc/soc_caps.h | 2 + .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32c6/include/soc/soc_caps.h | 2 + .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 ++ .../soc/esp32c61/include/soc/soc_caps.h | 2 + .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32h2/include/soc/soc_caps.h | 2 + .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32p4/include/soc/soc_caps.h | 2 - .../esp32s2/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32s2/include/soc/soc_caps.h | 2 + .../esp32s3/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32s3/include/soc/soc_caps.h | 3 + 34 files changed, 161 insertions(+), 26 deletions(-) diff --git a/components/esp_driver_gpio/include/driver/gpio.h b/components/esp_driver_gpio/include/driver/gpio.h index 70307f7116..30081a1771 100644 --- a/components/esp_driver_gpio/include/driver/gpio.h +++ b/components/esp_driver_gpio/include/driver/gpio.h @@ -376,7 +376,11 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren * in output mode: the output level of the GPIO will be locked and can not be changed. * in input mode: the input read value can still reflect the changes of the input signal. * - * However, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep. + * Please be aware that, + * + * On ESP32P4, the states of IOs can not be hold after waking up from Deep-sleep. + * + * Additionally, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep. * Even if this function is enabled, the digital GPIO will be reset to its default state when the chip wakes up from * Deep-sleep. If you want to hold the state of a digital GPIO during Deep-sleep, please call `gpio_deep_sleep_hold_en`. * @@ -409,7 +413,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num); */ esp_err_t gpio_hold_dis(gpio_num_t gpio_num); -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Enable all digital gpio pads hold function during Deep-sleep. * @@ -428,7 +432,7 @@ void gpio_deep_sleep_hold_en(void); * @brief Disable all digital gpio pads hold function during Deep-sleep. */ void gpio_deep_sleep_hold_dis(void); -#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Set pad input to a peripheral signal through the IOMUX. diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 5e878b7e7d..5357cb99ff 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -753,7 +753,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num) return ret; } -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP void gpio_deep_sleep_hold_en(void) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); @@ -767,7 +767,7 @@ void gpio_deep_sleep_hold_dis(void) gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP #if SOC_GPIO_SUPPORT_FORCE_HOLD esp_err_t IRAM_ATTR gpio_force_hold_all() diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c index 177c65862f..cb14746784 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c @@ -879,3 +879,63 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]") TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO); } #endif + +#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +// Pick one digital IO for each target to test is enough +static void gpio_deep_sleep_hold_test_first_stage(void) +{ + printf("configure a digital pin to hold during deep sleep"); + int io_num = TEST_GPIO_DEEP_SLEEP_HOLD_PIN; + TEST_ASSERT(GPIO_IS_VALID_DIGITAL_IO_PAD(io_num)); + + TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2000000)); + + gpio_config_t io_conf = { + .intr_type = GPIO_INTR_DISABLE, + .mode = GPIO_MODE_INPUT_OUTPUT, + .pin_bit_mask = (1ULL << io_num), + .pull_down_en = 0, + .pull_up_en = 0, + }; + TEST_ESP_OK(gpio_config(&io_conf)); + TEST_ESP_OK(gpio_set_level(io_num, 0)); + + // Enable global persistence + TEST_ESP_OK(gpio_hold_en(io_num)); +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + // On such target, digital IOs cannot be held individually in Deep-sleep + // Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep + gpio_deep_sleep_hold_en(); +#endif + + esp_deep_sleep_start(); +} + +static void gpio_deep_sleep_hold_test_second_stage(void) +{ + int io_num = TEST_GPIO_DEEP_SLEEP_HOLD_PIN; + // Check reset reason is waking up from deepsleep + TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason()); + + // Pin should stay at low level after the deep sleep + TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num)); + // Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held) + TEST_ESP_OK(gpio_set_level(io_num, 1)); + TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num)); + +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + gpio_deep_sleep_hold_dis(); +#endif + TEST_ESP_OK(gpio_hold_dis(io_num)); +} + +/* + * Test digital IOs hold function during deep sleep. + * This test case can only check the hold state after waking up from deep sleep + * If you want to check that the digital IO hold function works properly during deep sleep, + * please use logic analyzer or oscilloscope + */ +TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]", + gpio_deep_sleep_hold_test_first_stage, + gpio_deep_sleep_hold_test_second_stage) +#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h index 971b3fb4c4..2000b19520 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,27 +20,37 @@ extern "C" { #define TEST_GPIO_INPUT_ONLY_PIN (34) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (4) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC224_IDX) +#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (5) #elif CONFIG_IDF_TARGET_ESP32S2 #define TEST_GPIO_EXT_OUT_IO (17) #define TEST_GPIO_EXT_IN_IO (21) #define TEST_GPIO_INPUT_ONLY_PIN (46) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC223_IDX) +#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (45) #elif CONFIG_IDF_TARGET_ESP32S3 #define TEST_GPIO_EXT_OUT_IO (17) #define TEST_GPIO_EXT_IN_IO (21) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC208_IDX) +#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (45) #elif CONFIG_IDF_TARGET_ESP32P4 #define TEST_GPIO_EXT_OUT_IO (2) #define TEST_GPIO_EXT_IN_IO (3) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX) +#elif CONFIG_IDF_TARGET_ESP32H2 +#define TEST_GPIO_EXT_OUT_IO (2) +#define TEST_GPIO_EXT_IN_IO (3) +#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) +#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX) +#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (25) #else #define TEST_GPIO_EXT_OUT_IO (2) #define TEST_GPIO_EXT_IN_IO (3) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX) +#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (9) #endif #ifdef __cplusplus diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c index 44d93165a9..1ce7ae438f 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -235,7 +235,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]") #endif //SOC_RTCIO_HOLD_SUPPORTED #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED -#if SOC_DEEP_SLEEP_SUPPORTED +#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP // It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep // Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin // (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12) these pads' default configuration is low level @@ -284,4 +284,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void) TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]", rtcio_deep_sleep_hold_test_first_stage, rtcio_deep_sleep_hold_test_second_stage) -#endif // SOC_DEEP_SLEEP_SUPPORTED +#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP diff --git a/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py b/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py index 09cba42044..1f61e4a7c3 100644 --- a/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py +++ b/components/esp_driver_gpio/test_apps/gpio/pytest_gpio.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded_idf import IdfDut diff --git a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py index 5d4daa5beb..7d3dd1898e 100644 --- a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py +++ b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded_idf import IdfDut diff --git a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h index e71e0928bb..09cd05f3cd 100644 --- a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h +++ b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h @@ -39,7 +39,7 @@ void esp_sleep_set_sleep_context(esp_sleep_context_t *sleep_ctx); */ void esp_sleep_enable_adc_tsens_monitor(bool enable); -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Isolate all digital IOs except those that are held during deep sleep * diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index 8c23325e9b..5c75c44bfb 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -112,7 +112,7 @@ void esp_sleep_enable_gpio_switch(bool enable) } } -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP IRAM_ATTR void esp_sleep_isolate_digital_gpio(void) { gpio_hal_context_t gpio_hal = { @@ -150,7 +150,7 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void) } } } -#endif // !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP void esp_deep_sleep_wakeup_io_reset(void) { diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 2e2b812b9b..cf2aafb1de 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -955,7 +955,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m } #endif if (deep_sleep) { -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP esp_sleep_isolate_digital_gpio(); #endif diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index f4111b3f7d..fe01d9eb21 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -467,6 +467,11 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu *strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv); } +// On ESP32P4, all digital GPIO pads can be held together during Deep-sleep through PMU.hp_sys[PMU_MODE_HP_SLEEP].syscntl.hp_pad_hold_all = 1 +// However, since the hold register for digital IOs is in TOP domain (HP_SYSTEM.gpio_o_hold_ctrlx), it gets powered down in Deep-sleep. +// Therefore, after waking up from Deep-sleep, the register has been reset, it is not able to hold at that time. +// In all, the users can not achieve the purpose of being hold all the time. So this feature is considered not usable on P4. + /** * @brief Enable gpio pad hold function. * diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index 11a15a71da..534683a3e9 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -291,7 +291,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); * e.g. * If you hold gpio18 high during Deep-sleep, after the chip is woken up and `gpio_hold_dis` is called, * gpio18 will output low level(because gpio18 is input mode by default). If you don't want this behavior, - * you should configure gpio18 as output mode and set it to hight level before calling `gpio_hold_dis`. + * you should configure gpio18 as output mode and set it to high level before calling `gpio_hold_dis`. * * @param hal Context of the HAL layer * @param gpio_num GPIO number, only support output GPIOs @@ -299,7 +299,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); #define gpio_hal_hold_dis(hal, gpio_num) gpio_ll_hold_dis((hal)->dev, gpio_num) /** - * @brief Get wether digital gpio pad is held + * @brief Get whether digital gpio pad is held * * @param hal Context of the HAL layer * @param gpio_num GPIO number, only support output GPIOs @@ -314,7 +314,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); */ #define gpio_hal_is_digital_io_hold(hal, gpio_num) gpio_ll_is_digital_io_hold((hal)->dev, gpio_num) -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Enable all digital gpio pad hold function during Deep-sleep. * @@ -345,7 +345,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); * - false deep sleep hold is disabled */ #define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev) -#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Set pad input to a peripheral signal through the IOMUX. diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 7837f082aa..54613e95c7 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -359,6 +359,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 0b988de2f1..8b81cff3f2 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -193,6 +193,9 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) +// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) + /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32 has 2 I2C #define SOC_I2C_NUM (2U) diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 2e71155117..9dd7fe452c 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -327,6 +327,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 9ee2f14fed..b2097fd6ec 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -144,6 +144,9 @@ #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) +// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) + /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 95dff02b45..88a5471a3a 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -419,6 +419,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index e51177a051..2480280d64 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -182,6 +182,9 @@ #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) +// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) + /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in index fdfe6872e2..a79ab56d1f 100644 --- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -279,6 +279,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h index de79e2fbad..4406377a86 100644 --- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -214,6 +214,8 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in index 8b61d088e9..5a9fbe47f3 100644 --- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in @@ -179,6 +179,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index b49d69e530..8771d4671c 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -208,6 +208,8 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 73b9b913df..83b4279927 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -515,6 +515,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index f4d5a4c3fd..445da2aff8 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -211,6 +211,8 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 3585115350..0f09c495a7 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -187,6 +187,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 802b85fa28..896c4c4143 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -208,6 +208,8 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 344914ca47..0b8bf6777e 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -515,6 +515,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index ec15e3e793..5ae75321f7 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -214,6 +214,8 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 022dd58197..812f34c210 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -655,10 +655,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP - bool - default y - config SOC_RTCIO_PIN_COUNT int default 16 diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index a8b567d41d..d7ff8efdf1 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -258,8 +258,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// Support to hold a single digital I/O when the digital domain is powered off -#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 16 diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index fd0d99840e..6708df2216 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -407,6 +407,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index e18f5ee245..5200212381 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -182,6 +182,8 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) +// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index d0f8945995..42aa62bb99 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -491,6 +491,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 +config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP + bool + default y + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 25bbf3d8bb..6de9d7e3a3 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -192,6 +192,9 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) +// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up +#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) + /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */