diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
index e4877e39a3..231e4b17a1 100644
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -565,7 +565,7 @@ config SOC_UART_FIFO_LEN
 
 config SOC_UART_BITRATE_MAX
     int
-    default 5000000
+    default 2500000
 
 config SOC_UART_SUPPORT_WAKEUP_INT
     bool
diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h
index 4aaf76d103..b95a68cdca 100644
--- a/components/soc/esp32c2/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h
@@ -185,9 +185,6 @@ typedef enum {
     UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F40M,  /*!< UART source clock default choice is PLL_F40M */
 } soc_periph_uart_clk_src_legacy_t;
 
-/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
-
-
 /////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
 
 /**
@@ -204,6 +201,8 @@ typedef enum {
     SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,            /*!< Select XTAL as SPI source clock */
 } soc_periph_spi_clk_src_t;
 
+/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
+
 /**
  * @brief Array initializer for all supported clock sources of I2C
  */
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index 04428c8dae..578bc8e874 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -269,7 +269,7 @@
 // ESP32-C2 has 2 UARTs
 #define SOC_UART_NUM                (2)
 #define SOC_UART_FIFO_LEN           (128)      /*!< The UART hardware FIFO length */
-#define SOC_UART_BITRATE_MAX        (5000000)  /*!< Max bit rate supported by UART */
+#define SOC_UART_BITRATE_MAX        (2500000)  /*!< Max bit rate supported by UART */
 #define SOC_UART_SUPPORT_WAKEUP_INT (1)         /*!< Support UART wakeup interrupt */
 #define SOC_UART_SUPPORT_PLL_F40M_CLK (1)   /*!< Support APB as the clock source */
 #define SOC_UART_SUPPORT_RTC_CLK    (1)     /*!< Support RTC clock as the clock source */