From 40bce1334850951388bd2d14a25a422cb9a69d1c Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Thu, 30 Nov 2023 17:43:01 +0800 Subject: [PATCH] feat(esp32c5): update reg headers for multiple instances module (part3) --- .../soc/esp32c5/include/soc/pcnt_struct.h | 86 +------ .../soc/esp32c5/include/soc/timer_group_reg.h | 52 ++-- .../soc/esp32c5/include/soc/twai_struct.h | 236 ++---------------- components/soc/esp32c5/include/soc/uart_reg.h | 76 +++--- 4 files changed, 102 insertions(+), 348 deletions(-) diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/include/soc/pcnt_struct.h index 65de09bb12..ce929f709e 100644 --- a/components/soc/esp32c5/include/soc/pcnt_struct.h +++ b/components/soc/esp32c5/include/soc/pcnt_struct.h @@ -213,74 +213,22 @@ typedef union { uint32_t val; } pcnt_ctrl_reg_t; -/** Type of u3_change_conf register +/** Type of change_conf register * Configuration register for unit $n's step value. */ typedef union { struct { - /** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0; + /** cnt_step : R/W; bitpos: [15:0]; default: 0; * Configures the step value for unit 3. */ - uint32_t cnt_step_u3:16; - /** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0; + uint32_t cnt_step:16; + /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0; * Configures the step limit value for unit 3. */ - uint32_t cnt_step_lim_u3:16; + uint32_t cnt_step_lim:16; }; uint32_t val; -} pcnt_u3_change_conf_reg_t; - -/** Type of u2_change_conf register - * Configuration register for unit $n's step value. - */ -typedef union { - struct { - /** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0; - * Configures the step value for unit 2. - */ - uint32_t cnt_step_u2:16; - /** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0; - * Configures the step limit value for unit 2. - */ - uint32_t cnt_step_lim_u2:16; - }; - uint32_t val; -} pcnt_u2_change_conf_reg_t; - -/** Type of u1_change_conf register - * Configuration register for unit $n's step value. - */ -typedef union { - struct { - /** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0; - * Configures the step value for unit 1. - */ - uint32_t cnt_step_u1:16; - /** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0; - * Configures the step limit value for unit 1. - */ - uint32_t cnt_step_lim_u1:16; - }; - uint32_t val; -} pcnt_u1_change_conf_reg_t; - -/** Type of u0_change_conf register - * Configuration register for unit $n's step value. - */ -typedef union { - struct { - /** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0; - * Configures the step value for unit 0. - */ - uint32_t cnt_step_u0:16; - /** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0; - * Configures the step limit value for unit 0. - */ - uint32_t cnt_step_lim_u0:16; - }; - uint32_t val; -} pcnt_u0_change_conf_reg_t; - +} pcnt_un_change_conf_reg_t; /** Group: Status Register */ /** Type of un_cnt register @@ -466,18 +414,11 @@ typedef union { typedef struct pcnt_dev_t { - volatile pcnt_un_conf0_reg_t u0_conf0; - volatile pcnt_un_conf1_reg_t u0_conf1; - volatile pcnt_un_conf2_reg_t u0_conf2; - volatile pcnt_un_conf0_reg_t u1_conf0; - volatile pcnt_un_conf1_reg_t u1_conf1; - volatile pcnt_un_conf2_reg_t u1_conf2; - volatile pcnt_un_conf0_reg_t u2_conf0; - volatile pcnt_un_conf1_reg_t u2_conf1; - volatile pcnt_un_conf2_reg_t u2_conf2; - volatile pcnt_un_conf0_reg_t u3_conf0; - volatile pcnt_un_conf1_reg_t u3_conf1; - volatile pcnt_un_conf2_reg_t u3_conf2; + volatile struct { + pcnt_un_conf0_reg_t conf0; + pcnt_un_conf1_reg_t conf1; + pcnt_un_conf2_reg_t conf2; + } conf_unit[4]; volatile pcnt_un_cnt_reg_t un_cnt[4]; volatile pcnt_int_raw_reg_t int_raw; volatile pcnt_int_st_reg_t int_st; @@ -485,10 +426,7 @@ typedef struct pcnt_dev_t { volatile pcnt_int_clr_reg_t int_clr; volatile pcnt_un_status_reg_t un_status[4]; volatile pcnt_ctrl_reg_t ctrl; - volatile pcnt_u3_change_conf_reg_t u3_change_conf; - volatile pcnt_u2_change_conf_reg_t u2_change_conf; - volatile pcnt_u1_change_conf_reg_t u1_change_conf; - volatile pcnt_u0_change_conf_reg_t u0_change_conf; + volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210 uint32_t reserved_074[34]; volatile pcnt_date_reg_t date; } pcnt_dev_t; diff --git a/components/soc/esp32c5/include/soc/timer_group_reg.h b/components/soc/esp32c5/include/soc/timer_group_reg.h index 4d3f13661b..97a10ff9f0 100644 --- a/components/soc/esp32c5/include/soc/timer_group_reg.h +++ b/components/soc/esp32c5/include/soc/timer_group_reg.h @@ -14,7 +14,7 @@ extern "C" { /** TIMG_T0CONFIG_REG register * Timer 0 configuration register */ -#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0) +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) /** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; * When set, the alarm is enabled. This bit is automatically cleared once an * alarm occurs. @@ -63,7 +63,7 @@ extern "C" { /** TIMG_T0LO_REG register * Timer 0 current value, low 32 bits */ -#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4) +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter * of timer 0 can be read here. @@ -76,7 +76,7 @@ extern "C" { /** TIMG_T0HI_REG register * Timer 0 current value, high 22 bits */ -#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8) +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter * of timer 0 can be read here. @@ -89,7 +89,7 @@ extern "C" { /** TIMG_T0UPDATE_REG register * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG */ -#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc) +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. */ @@ -101,7 +101,7 @@ extern "C" { /** TIMG_T0ALARMLO_REG register * Timer 0 alarm value, low 32 bits */ -#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10) +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; * Timer 0 alarm trigger time-base counter value, low 32 bits. */ @@ -113,7 +113,7 @@ extern "C" { /** TIMG_T0ALARMHI_REG register * Timer 0 alarm value, high bits */ -#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14) +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; * Timer 0 alarm trigger time-base counter value, high 22 bits. */ @@ -125,7 +125,7 @@ extern "C" { /** TIMG_T0LOADLO_REG register * Timer 0 reload value, low 32 bits */ -#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18) +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; * Low 32 bits of the value that a reload will load onto timer 0 time-base * Counter. @@ -138,7 +138,7 @@ extern "C" { /** TIMG_T0LOADHI_REG register * Timer 0 reload value, high 22 bits */ -#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c) +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; * High 22 bits of the value that a reload will load onto timer 0 time-base * counter. @@ -151,7 +151,7 @@ extern "C" { /** TIMG_T0LOAD_REG register * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG */ -#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20) +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) /** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; * * Write any value to trigger a timer 0 time-base counter reload. @@ -164,7 +164,7 @@ extern "C" { /** TIMG_WDTCONFIG0_REG register * Watchdog timer configuration register */ -#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48) +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; * WDT reset CPU enable. */ @@ -248,7 +248,7 @@ extern "C" { /** TIMG_WDTCONFIG1_REG register * Watchdog timer prescaler register */ -#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c) +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; * When set, WDT 's clock divider counter will be reset. */ @@ -268,7 +268,7 @@ extern "C" { /** TIMG_WDTCONFIG2_REG register * Watchdog timer stage 0 timeout value */ -#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50) +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; * Stage 0 timeout value, in MWDT clock cycles. */ @@ -280,7 +280,7 @@ extern "C" { /** TIMG_WDTCONFIG3_REG register * Watchdog timer stage 1 timeout value */ -#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54) +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; * Stage 1 timeout value, in MWDT clock cycles. */ @@ -292,7 +292,7 @@ extern "C" { /** TIMG_WDTCONFIG4_REG register * Watchdog timer stage 2 timeout value */ -#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58) +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; * Stage 2 timeout value, in MWDT clock cycles. */ @@ -304,7 +304,7 @@ extern "C" { /** TIMG_WDTCONFIG5_REG register * Watchdog timer stage 3 timeout value */ -#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c) +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; * Stage 3 timeout value, in MWDT clock cycles. */ @@ -316,7 +316,7 @@ extern "C" { /** TIMG_WDTFEED_REG register * Write to feed the watchdog timer */ -#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60) +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) /** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; * Write any value to feed the MWDT. (WO) */ @@ -328,7 +328,7 @@ extern "C" { /** TIMG_WDTWPROTECT_REG register * Watchdog write protect register */ -#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64) +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; * If the register contains a different value than its reset value, write * protection is enabled. @@ -341,7 +341,7 @@ extern "C" { /** TIMG_RTCCALICFG_REG register * RTC calibration configure register */ -#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68) +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) /** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; * 0: one-shot frequency calculation,1: periodic frequency calculation, */ @@ -381,7 +381,7 @@ extern "C" { /** TIMG_RTCCALICFG1_REG register * RTC calibration configure1 register */ -#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c) +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) /** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; * indicate periodic frequency calculation is done. */ @@ -401,7 +401,7 @@ extern "C" { /** TIMG_INT_ENA_TIMERS_REG register * Interrupt enable bits */ -#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70) +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the TIMG_T$x_INT interrupt. */ @@ -420,7 +420,7 @@ extern "C" { /** TIMG_INT_RAW_TIMERS_REG register * Raw interrupt status */ -#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74) +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) /** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; * The raw interrupt status bit for the TIMG_T$x_INT interrupt. */ @@ -439,7 +439,7 @@ extern "C" { /** TIMG_INT_ST_TIMERS_REG register * Masked interrupt status */ -#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78) +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status bit for the TIMG_T$x_INT interrupt. */ @@ -458,7 +458,7 @@ extern "C" { /** TIMG_INT_CLR_TIMERS_REG register * Interrupt clear bits */ -#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c) +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c) /** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the TIMG_T$x_INT interrupt. */ @@ -477,7 +477,7 @@ extern "C" { /** TIMG_RTCCALICFG2_REG register * Timer group calibration register */ -#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80) +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) /** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; * RTC calibration timeout indicator */ @@ -504,7 +504,7 @@ extern "C" { /** TIMG_NTIMERS_DATE_REG register * Timer version control register */ -#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8) +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8) /** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; * Timer version control register */ @@ -516,7 +516,7 @@ extern "C" { /** TIMG_REGCLK_REG register * Timer group clock gate register */ -#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc) +#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) /** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; * enable timer's etm task and event */ diff --git a/components/soc/esp32c5/include/soc/twai_struct.h b/components/soc/esp32c5/include/soc/twai_struct.h index e89df67922..bc3be7f3f4 100644 --- a/components/soc/esp32c5/include/soc/twai_struct.h +++ b/components/soc/esp32c5/include/soc/twai_struct.h @@ -493,213 +493,21 @@ typedef union { /** Group: Data Registers */ -/** Type of data_0 register - * Data register 0. +/** Type of tx_rx_buffer register + * Data register. */ typedef union { struct { - /** data_0 : R/W; bitpos: [7:0]; default: 0; + /** byte : R/W; bitpos: [7:0]; default: 0; * In reset mode, it is acceptance code register 0 with R/W Permission. In operation * mode, when software initiate write operation, it is tx data register 0 and when * software initiate read operation, it is rx data register 0. */ - uint32_t data_0:8; + uint32_t byte:8; uint32_t reserved_8:24; }; uint32_t val; -} twai_data_0_reg_t; - -/** Type of data_1 register - * Data register 1. - */ -typedef union { - struct { - /** data_1 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance code register 1 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 1 and when - * software initiate read operation, it is rx data register 1. - */ - uint32_t data_1:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_1_reg_t; - -/** Type of data_2 register - * Data register 2. - */ -typedef union { - struct { - /** data_2 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance code register 2 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 2 and when - * software initiate read operation, it is rx data register 2. - */ - uint32_t data_2:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_2_reg_t; - -/** Type of data_3 register - * Data register 3. - */ -typedef union { - struct { - /** data_3 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance code register 3 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 3 and when - * software initiate read operation, it is rx data register 3. - */ - uint32_t data_3:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_3_reg_t; - -/** Type of data_4 register - * Data register 4. - */ -typedef union { - struct { - /** data_4 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 4 and when - * software initiate read operation, it is rx data register 4. - */ - uint32_t data_4:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_4_reg_t; - -/** Type of data_5 register - * Data register 5. - */ -typedef union { - struct { - /** data_5 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 5 and when - * software initiate read operation, it is rx data register 5. - */ - uint32_t data_5:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_5_reg_t; - -/** Type of data_6 register - * Data register 6. - */ -typedef union { - struct { - /** data_6 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 6 and when - * software initiate read operation, it is rx data register 6. - */ - uint32_t data_6:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_6_reg_t; - -/** Type of data_7 register - * Data register 7. - */ -typedef union { - struct { - /** data_7 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation - * mode, when software initiate write operation, it is tx data register 7 and when - * software initiate read operation, it is rx data register 7. - */ - uint32_t data_7:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_7_reg_t; - -/** Type of data_8 register - * Data register 8. - */ -typedef union { - struct { - /** data_8 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 8 and when software initiate read operation, it - * is rx data register 8. - */ - uint32_t data_8:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_8_reg_t; - -/** Type of data_9 register - * Data register 9. - */ -typedef union { - struct { - /** data_9 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 9 and when software initiate read operation, it - * is rx data register 9. - */ - uint32_t data_9:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_9_reg_t; - -/** Type of data_10 register - * Data register 10. - */ -typedef union { - struct { - /** data_10 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 10 and when software initiate read operation, it - * is rx data register 10. - */ - uint32_t data_10:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_10_reg_t; - -/** Type of data_11 register - * Data register 11. - */ -typedef union { - struct { - /** data_11 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 11 and when software initiate read operation, it - * is rx data register 11. - */ - uint32_t data_11:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_11_reg_t; - -/** Type of data_12 register - * Data register 12. - */ -typedef union { - struct { - /** data_12 : R/W; bitpos: [7:0]; default: 0; - * In reset mode, reserved with RO. In operation mode, when software initiate write - * operation, it is tx data register 12 and when software initiate read operation, it - * is rx data register 12. - */ - uint32_t data_12:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} twai_data_12_reg_t; +} twai_tx_rx_buffer_reg_t; /** Group: Timestamp Register */ @@ -744,6 +552,23 @@ typedef union { uint32_t val; } twai_timestamp_cfg_reg_t; +typedef struct { + union { + struct { + uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } acr[4]; + union { + struct { + uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } amr[4]; + uint32_t reserved_60[5]; +} acceptance_filter_reg_t; typedef struct twai_dev_t { volatile twai_mode_reg_t mode; @@ -760,19 +585,10 @@ typedef struct twai_dev_t { volatile twai_err_warning_limit_reg_t err_warning_limit; volatile twai_rx_err_cnt_reg_t rx_err_cnt; volatile twai_tx_err_cnt_reg_t tx_err_cnt; - volatile twai_data_0_reg_t data_0; - volatile twai_data_1_reg_t data_1; - volatile twai_data_2_reg_t data_2; - volatile twai_data_3_reg_t data_3; - volatile twai_data_4_reg_t data_4; - volatile twai_data_5_reg_t data_5; - volatile twai_data_6_reg_t data_6; - volatile twai_data_7_reg_t data_7; - volatile twai_data_8_reg_t data_8; - volatile twai_data_9_reg_t data_9; - volatile twai_data_10_reg_t data_10; - volatile twai_data_11_reg_t data_11; - volatile twai_data_12_reg_t data_12; + volatile union { + acceptance_filter_reg_t acceptance_filter; + twai_tx_rx_buffer_reg_t tx_rx_buffer[13]; + }; volatile twai_rx_message_counter_reg_t rx_message_counter; uint32_t reserved_078; volatile twai_clock_divider_reg_t clock_divider; diff --git a/components/soc/esp32c5/include/soc/uart_reg.h b/components/soc/esp32c5/include/soc/uart_reg.h index 1be6cb107f..ac864940d8 100644 --- a/components/soc/esp32c5/include/soc/uart_reg.h +++ b/components/soc/esp32c5/include/soc/uart_reg.h @@ -14,7 +14,7 @@ extern "C" { /** UART_FIFO_REG register * FIFO data register */ -#define UART_FIFO_REG (DR_REG_UART_BASE + 0x0) +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) /** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; * UART $n accesses FIFO via this register. */ @@ -26,7 +26,7 @@ extern "C" { /** UART_INT_RAW_REG register * Raw interrupt status */ -#define UART_INT_RAW_REG (DR_REG_UART_BASE + 0x4) +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) /** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * This interrupt raw bit turns to high level when receiver receives more data than * what rxfifo_full_thrhd specifies. @@ -191,7 +191,7 @@ extern "C" { /** UART_INT_ST_REG register * Masked interrupt status */ -#define UART_INT_ST_REG (DR_REG_UART_BASE + 0x8) +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) /** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. */ @@ -341,7 +341,7 @@ extern "C" { /** UART_INT_ENA_REG register * Interrupt enable bits */ -#define UART_INT_ENA_REG (DR_REG_UART_BASE + 0xc) +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) /** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; * This is the enable bit for rxfifo_full_int_st register. */ @@ -486,7 +486,7 @@ extern "C" { /** UART_INT_CLR_REG register * Interrupt clear bits */ -#define UART_INT_CLR_REG (DR_REG_UART_BASE + 0x10) +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) /** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the rxfifo_full_int_raw interrupt. */ @@ -631,7 +631,7 @@ extern "C" { /** UART_CLKDIV_SYNC_REG register * Clock divider configuration */ -#define UART_CLKDIV_SYNC_REG (DR_REG_UART_BASE + 0x14) +#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) /** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; * The integral part of the frequency divider factor. */ @@ -650,7 +650,7 @@ extern "C" { /** UART_RX_FILT_REG register * Rx Filter configuration */ -#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18) +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) /** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; * when input pulse width is lower than this value the pulse is ignored. */ @@ -669,7 +669,7 @@ extern "C" { /** UART_STATUS_REG register * UART status register */ -#define UART_STATUS_REG (DR_REG_UART_BASE + 0x1c) +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) /** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; * Stores the byte number of valid data in Rx-FIFO. */ @@ -730,7 +730,7 @@ extern "C" { /** UART_CONF0_SYNC_REG register * a */ -#define UART_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x20) +#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) /** UART_PARITY : R/W; bitpos: [0]; default: 0; * This register is used to configure the parity check mode. */ @@ -893,7 +893,7 @@ extern "C" { /** UART_CONF1_REG register * Configuration register 1 */ -#define UART_CONF1_REG (DR_REG_UART_BASE + 0x24) +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; * It will produce rxfifo_full_int interrupt when receiver receives more data than * this register value. @@ -958,7 +958,7 @@ extern "C" { /** UART_HWFC_CONF_SYNC_REG register * Hardware flow-control configuration */ -#define UART_HWFC_CONF_SYNC_REG (DR_REG_UART_BASE + 0x2c) +#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) /** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; * This register is used to configure the maximum amount of data that can be received * when hardware flow control works. @@ -978,7 +978,7 @@ extern "C" { /** UART_SLEEP_CONF0_REG register * UART sleep configure register 0 */ -#define UART_SLEEP_CONF0_REG (DR_REG_UART_BASE + 0x30) +#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) /** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; * This register restores the specified wake up char1 to wake up */ @@ -1011,7 +1011,7 @@ extern "C" { /** UART_SLEEP_CONF1_REG register * UART sleep configure register 1 */ -#define UART_SLEEP_CONF1_REG (DR_REG_UART_BASE + 0x34) +#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) /** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; * This register restores the specified char0 to wake up */ @@ -1023,7 +1023,7 @@ extern "C" { /** UART_SLEEP_CONF2_REG register * UART sleep configure register 2 */ -#define UART_SLEEP_CONF2_REG (DR_REG_UART_BASE + 0x38) +#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) /** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; * The uart is activated from light sleeping mode when the input rxd edge changes more * times than this register value. @@ -1066,7 +1066,7 @@ extern "C" { /** UART_SWFC_CONF0_SYNC_REG register * Software flow-control character configuration */ -#define UART_SWFC_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x3c) +#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) /** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; * This register stores the Xon flow control char. */ @@ -1138,7 +1138,7 @@ extern "C" { /** UART_SWFC_CONF1_REG register * Software flow-control character configuration */ -#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40) +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) /** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; * When the data amount in Rx-FIFO is less than this register value with * uart_sw_flow_con_en set to 1 it will send a Xon char. @@ -1159,7 +1159,7 @@ extern "C" { /** UART_TXBRK_CONF_SYNC_REG register * Tx Break character configuration */ -#define UART_TXBRK_CONF_SYNC_REG (DR_REG_UART_BASE + 0x44) +#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) /** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; * This register is used to configure the number of 0 to be sent after the process of * sending data is done. It is active when txd_brk is set to 1. @@ -1172,7 +1172,7 @@ extern "C" { /** UART_IDLE_CONF_SYNC_REG register * Frame-end idle configuration */ -#define UART_IDLE_CONF_SYNC_REG (DR_REG_UART_BASE + 0x48) +#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) /** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; * It will produce frame end signal when receiver takes more time to receive one byte * data than this register value. @@ -1192,7 +1192,7 @@ extern "C" { /** UART_RS485_CONF_SYNC_REG register * RS485 mode configuration */ -#define UART_RS485_CONF_SYNC_REG (DR_REG_UART_BASE + 0x4c) +#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) /** UART_RS485_EN : R/W; bitpos: [0]; default: 0; * Set this bit to choose the rs485 mode. */ @@ -1247,7 +1247,7 @@ extern "C" { /** UART_AT_CMD_PRECNT_SYNC_REG register * Pre-sequence timing configuration */ -#define UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_UART_BASE + 0x50) +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) /** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the idle duration time before the first at_cmd * is received by receiver. @@ -1260,7 +1260,7 @@ extern "C" { /** UART_AT_CMD_POSTCNT_SYNC_REG register * Post-sequence timing configuration */ -#define UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_UART_BASE + 0x54) +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) /** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the duration time between the last at_cmd and * the next data. @@ -1273,7 +1273,7 @@ extern "C" { /** UART_AT_CMD_GAPTOUT_SYNC_REG register * Timeout configuration */ -#define UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_UART_BASE + 0x58) +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) /** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; * This register is used to configure the duration time between the at_cmd chars. */ @@ -1285,7 +1285,7 @@ extern "C" { /** UART_AT_CMD_CHAR_SYNC_REG register * AT escape sequence detection configuration */ -#define UART_AT_CMD_CHAR_SYNC_REG (DR_REG_UART_BASE + 0x5c) +#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) /** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; * This register is used to configure the content of at_cmd char. */ @@ -1305,7 +1305,7 @@ extern "C" { /** UART_MEM_CONF_REG register * UART memory power configuration */ -#define UART_MEM_CONF_REG (DR_REG_UART_BASE + 0x60) +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) /** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; * Set this bit to force power down UART memory. */ @@ -1324,7 +1324,7 @@ extern "C" { /** UART_TOUT_CONF_SYNC_REG register * UART threshold and allocation configuration */ -#define UART_TOUT_CONF_SYNC_REG (DR_REG_UART_BASE + 0x64) +#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; * This is the enble bit for uart receiver's timeout function. */ @@ -1352,7 +1352,7 @@ extern "C" { /** UART_MEM_TX_STATUS_REG register * Tx-SRAM write and read offset address. */ -#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x68) +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) /** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; * This register stores the offset write address in Tx-SRAM. */ @@ -1371,7 +1371,7 @@ extern "C" { /** UART_MEM_RX_STATUS_REG register * Rx-SRAM write and read offset address. */ -#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x6c) +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) /** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; * This register stores the offset read address in RX-SRAM. */ @@ -1390,7 +1390,7 @@ extern "C" { /** UART_FSM_STATUS_REG register * UART transmit and receive status. */ -#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x70) +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) /** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; * This is the status register of receiver. */ @@ -1409,7 +1409,7 @@ extern "C" { /** UART_POSPULSE_REG register * Autobaud high pulse register */ -#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x74) +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) /** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two positive edges. It * is used in boudrate-detect process. @@ -1422,7 +1422,7 @@ extern "C" { /** UART_NEGPULSE_REG register * Autobaud low pulse register */ -#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x78) +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) /** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two negative edges. It * is used in boudrate-detect process. @@ -1435,7 +1435,7 @@ extern "C" { /** UART_LOWPULSE_REG register * Autobaud minimum low pulse duration register */ -#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x7c) +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) /** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the minimum duration time of the low level pulse. * It is used in baud rate-detect process. @@ -1448,7 +1448,7 @@ extern "C" { /** UART_HIGHPULSE_REG register * Autobaud minimum high pulse duration register */ -#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x80) +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the maxinum duration time for the high level * pulse. It is used in baud rate-detect process. @@ -1461,7 +1461,7 @@ extern "C" { /** UART_RXD_CNT_REG register * Autobaud edge change count register */ -#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x84) +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) /** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; * This register stores the count of rxd edge change. It is used in baud rate-detect * process. @@ -1474,7 +1474,7 @@ extern "C" { /** UART_CLK_CONF_REG register * UART core clock configuration */ -#define UART_CLK_CONF_REG (DR_REG_UART_BASE + 0x88) +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) /** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; * Set this bit to enable UART Tx clock. */ @@ -1507,7 +1507,7 @@ extern "C" { /** UART_DATE_REG register * UART Version register */ -#define UART_DATE_REG (DR_REG_UART_BASE + 0x8c) +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) /** UART_DATE : R/W; bitpos: [31:0]; default: 35680848; * This is the version register. */ @@ -1519,7 +1519,7 @@ extern "C" { /** UART_AFIFO_STATUS_REG register * UART AFIFO Status */ -#define UART_AFIFO_STATUS_REG (DR_REG_UART_BASE + 0x90) +#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) /** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; * Full signal of APB TX AFIFO. */ @@ -1552,7 +1552,7 @@ extern "C" { /** UART_REG_UPDATE_REG register * UART Registers Configuration Update register */ -#define UART_REG_UPDATE_REG (DR_REG_UART_BASE + 0x98) +#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) /** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; * Software write 1 would synchronize registers into UART Core clock domain and would * be cleared by hardware after synchronization is done. @@ -1565,7 +1565,7 @@ extern "C" { /** UART_ID_REG register * UART ID register */ -#define UART_ID_REG (DR_REG_UART_BASE + 0x9c) +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) /** UART_ID : R/W; bitpos: [31:0]; default: 1280; * This register is used to configure the uart_id. */