diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h index 5527ee1eb7..013238142b 100644 --- a/components/hal/esp32c3/include/hal/spi_ll.h +++ b/components/hal/esp32c3/include/hal/spi_ll.h @@ -1005,7 +1005,7 @@ static inline void spi_ll_set_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) static inline void spi_ll_clear_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) { -#define CLR_INTR(intr_bit, _, __, clr_op) if (intr_mask & (intr_bit)) hw->clr_op; +#define CLR_INTR(intr_bit, _, __, clr_reg) if (intr_mask & (intr_bit)) hw->clr_reg; FOR_EACH_ITEM(CLR_INTR, INTR_LIST); #undef CLR_INTR } diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index d11fbcd98a..5ede97d958 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -995,7 +995,7 @@ static inline void spi_ll_set_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) static inline void spi_ll_clear_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) { -#define CLR_INTR(intr_bit, _, __, clr_op) if (intr_mask & (intr_bit)) hw->clr_op; +#define CLR_INTR(intr_bit, _, __, clr_reg) if (intr_mask & (intr_bit)) hw->clr_reg; FOR_EACH_ITEM(CLR_INTR, INTR_LIST); #undef CLR_INTR } diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h index 8c040e20ef..27693ca12d 100644 --- a/components/hal/esp32s3/include/hal/spi_ll.h +++ b/components/hal/esp32s3/include/hal/spi_ll.h @@ -979,16 +979,16 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) //helper macros to generate code for each interrupts #define FOR_EACH_ITEM(op, list) do { list(op) } while(0) #define INTR_LIST(item) \ - item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done=1) \ - item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done=1) \ - item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done=1) \ - item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done=1) \ - item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done=1) \ - item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done=1) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1) + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done, dma_int_set.rd_buf_done_int_set) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done, dma_int_set.wr_buf_done_int_set) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done, dma_int_set.rd_dma_done_int_set) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done, dma_int_set.wr_dma_done_int_set) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7, dma_int_set.cmd7_int_set) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8, dma_int_set.cmd8_int_set) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9, dma_int_set.cmd9_int_set) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda, dma_int_set.cmda_int_set) static inline void spi_ll_enable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) @@ -1007,21 +1007,21 @@ static inline void spi_ll_disable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) static inline void spi_ll_set_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) { -#define SET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit)) hw->st_reg = 1; +#define SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; FOR_EACH_ITEM(SET_INTR, INTR_LIST); #undef SET_INTR } static inline void spi_ll_clear_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) { -#define CLR_INTR(intr_bit, _, __, clr_op) if (intr_mask & (intr_bit)) hw->clr_op; +#define CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; FOR_EACH_ITEM(CLR_INTR, INTR_LIST); #undef CLR_INTR } static inline bool spi_ll_get_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) { -#define GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; +#define GET_INTR(intr_bit, _, raw_reg, ...) if (intr_mask & (intr_bit) && hw->raw_reg) return true; FOR_EACH_ITEM(GET_INTR, INTR_LIST); return false; #undef GET_INTR @@ -1047,7 +1047,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw) */ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) { - hw->dma_int_raw.trans_done = 0; + hw->dma_int_clr.trans_done = 1; } /** @@ -1057,7 +1057,7 @@ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) */ static inline void spi_ll_set_int_stat(spi_dev_t *hw) { - hw->dma_int_raw.trans_done = 1; + hw->dma_int_set.trans_done_int_set = 1; } /** diff --git a/components/soc/esp32c3/include/soc/spi_struct.h b/components/soc/esp32c3/include/soc/spi_struct.h index 24844d58ba..cc22595dd0 100644 --- a/components/soc/esp32c3/include/soc/spi_struct.h +++ b/components/soc/esp32c3/include/soc/spi_struct.h @@ -18,7 +18,6 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" typedef volatile struct { union { diff --git a/components/soc/esp32s3/include/soc/spi_caps.h b/components/soc/esp32s3/include/soc/spi_caps.h index 3976153e1e..deab59b23a 100644 --- a/components/soc/esp32s3/include/soc/spi_caps.h +++ b/components/soc/esp32s3/include/soc/spi_caps.h @@ -35,4 +35,4 @@ #define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 8192 +#define SOC_SPI_MAX_PRE_DIVIDER 16 diff --git a/components/soc/esp32s3/include/soc/spi_reg.h b/components/soc/esp32s3/include/soc/spi_reg.h index 7f6a157760..712b32f38b 100644 --- a/components/soc/esp32s3/include/soc/spi_reg.h +++ b/components/soc/esp32s3/include/soc/spi_reg.h @@ -52,20 +52,20 @@ clock domain, which is only used in SPI master mode..*/ #define SPI_USR_ADDR_VALUE_S 0 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) -/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */ +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ /*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con figured in CONF state..*/ -#define SPI_WR_BIT_ORDER 0x00000003 -#define SPI_WR_BIT_ORDER_M ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S)) -#define SPI_WR_BIT_ORDER_V 0x3 -#define SPI_WR_BIT_ORDER_S 25 -/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */ +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ /*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s tate..*/ -#define SPI_RD_BIT_ORDER 0x00000003 -#define SPI_RD_BIT_ORDER_M ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S)) -#define SPI_RD_BIT_ORDER_V 0x3 -#define SPI_RD_BIT_ORDER_S 23 +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 /* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */ /*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. C an be configured in CONF state..*/ @@ -813,20 +813,6 @@ _vld is cleared by spi_trans_done..*/ #define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) #define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 #define SPI_DMA_SLV_SEG_TRANS_EN_S 18 -/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat -a. 0: DMA RX FIFO is ready for receiving data..*/ -#define SPI_DMA_INFIFO_FULL (BIT(1)) -#define SPI_DMA_INFIFO_FULL_M (BIT(1)) -#define SPI_DMA_INFIFO_FULL_V 0x1 -#define SPI_DMA_INFIFO_FULL_S 1 -/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. - 0: DMA TX FIFO is ready for sending data..*/ -#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) -#define SPI_DMA_OUTFIFO_EMPTY_M (BIT(0)) -#define SPI_DMA_OUTFIFO_EMPTY_V 0x1 -#define SPI_DMA_OUTFIFO_EMPTY_S 0 #define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34) /* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ @@ -1740,7 +1726,7 @@ M. 0: XTAL CLK..*/ #define SPI_CLK_EN_S 0 #define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xF0) -/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012290 ; */ +/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010110 ; */ /*description: SPI register version..*/ #define SPI_DATE 0x0FFFFFFF #define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) diff --git a/components/soc/esp32s3/include/soc/spi_struct.h b/components/soc/esp32s3/include/soc/spi_struct.h index 799ef15149..95d252cdab 100644 --- a/components/soc/esp32s3/include/soc/spi_struct.h +++ b/components/soc/esp32s3/include/soc/spi_struct.h @@ -13,6 +13,7 @@ // limitations under the License. #ifndef _SOC_SPI_STRUCT_H_ #define _SOC_SPI_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif @@ -49,9 +50,9 @@ typedef volatile struct { uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/ uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t reserved22 : 1; /*reserved*/ - uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ - uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ + uint32_t reserved22 : 3; /*reserved*/ + uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ + uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ uint32_t reserved27 : 5; /*reserved*/ }; uint32_t val; @@ -195,9 +196,7 @@ typedef volatile struct { } dout_mode; union { struct { - uint32_t outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/ - uint32_t infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/ - uint32_t reserved2 : 16; /*reserved*/ + uint32_t reserved0 : 18; /*reserved*/ uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ @@ -366,7 +365,7 @@ typedef volatile struct { uint32_t reserved_8c; uint32_t reserved_90; uint32_t reserved_94; - uint32_t data_buf[16]; /*SPI CPU-controlled buffer0*/ + uint32_t data_buf[16]; uint32_t reserved_d8; uint32_t reserved_dc; union { @@ -420,4 +419,4 @@ extern spi_dev_t GPSPI3; } #endif -#endif /* _SOC_SPI_STRUCT_H_ */ +#endif /*_SOC_SPI_STRUCT_H_ */