diff --git a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
index b63d83a311..f79cefbdbd 100644
--- a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
+++ b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
@@ -28,12 +28,10 @@ esp_err_t bootloader_init_spi_flash(void);
 void bootloader_flash_hardware_init(void);
 #endif
 
-#if SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
 /**
- * @brief Initialise flash core clock
+ * @brief Initialise mspi core clock
  */
-void bootloader_flash_init_core_clock(void);
-#endif  //SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
+void bootloader_init_mspi_clock(void);
 
 #ifdef __cplusplus
 }
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
index 92d259b3e9..a876c04173 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
@@ -48,8 +48,18 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
     SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
 }
 
+void IRAM_ATTR bootloader_init_mspi_clock(void)
+{
+    // Set source mspi pll clock as 80M in bootloader stage.
+    // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
+    // in this stage, set divider as 6
+    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
+    mspi_ll_fast_set_hs_divider(6);
+}
+
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
+    bootloader_init_mspi_clock();
     uint32_t spi_clk_div = 0;
     switch (pfhdr->spi_speed) {
     case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -204,11 +214,7 @@ static void bootloader_spi_flash_resume(void)
 
 esp_err_t bootloader_init_spi_flash(void)
 {
-    // Set source mspi pll clock as 80M in bootloader stage.
-    // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
-    // in this stage, set divider as 6
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
-    mspi_ll_fast_set_hs_divider(6);
+    bootloader_init_mspi_clock();
 
     bootloader_init_flash_configure();
     bootloader_spi_flash_resume();
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
index c38157840c..78a53b4a6c 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
@@ -42,7 +42,7 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
     SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
 }
 
-void IRAM_ATTR bootloader_flash_init_core_clock(void)
+void IRAM_ATTR bootloader_init_mspi_clock(void)
 {
     _spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
     _spimem_ctrlr_ll_set_core_clock(0, 6);
@@ -50,7 +50,7 @@ void IRAM_ATTR bootloader_flash_init_core_clock(void)
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
-    bootloader_flash_init_core_clock();
+    bootloader_init_mspi_clock();
 
     uint32_t spi_clk_div = 0;
     switch (pfhdr->spi_speed) {
diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
index 950bb1fbd6..9b70bf6817 100644
--- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@@ -112,7 +112,7 @@ static inline void bootloader_hardware_init(void)
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
     // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.
     if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {
-        bootloader_flash_init_core_clock();
+        bootloader_init_mspi_clock();
     }
 #endif
 }