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change(soc): re-generate ahb_dma header file for esp32c61

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This commit is contained in:
wanlei
2024-07-17 09:59:57 +08:00
committed by morris
parent a262df7c31
commit 4313f22a1e
2 changed files with 1723 additions and 1679 deletions
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3160
components/soc/esp32c61/include/soc/ahb_dma_reg.h
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242
components/soc/esp32c61/include/soc/ahb_dma_struct.h
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@@ -47,7 +47,7 @@ typedef union {
uint32_t reserved_7:25; uint32_t reserved_7:25;
}; };
uint32_t val; uint32_t val;
} gdma_in_int_raw_chn_reg_t; } ahb_dma_in_int_raw_chn_reg_t;
/** Type of in_int_st_chn register /** Type of in_int_st_chn register
* Masked interrupt status of RX channel 0 * Masked interrupt status of RX channel 0
@@ -85,7 +85,7 @@ typedef union {
uint32_t reserved_7:25; uint32_t reserved_7:25;
}; };
uint32_t val; uint32_t val;
} gdma_in_int_st_chn_reg_t; } ahb_dma_in_int_st_chn_reg_t;
/** Type of in_int_ena_chn register /** Type of in_int_ena_chn register
* Interrupt enable bits of RX channel 0 * Interrupt enable bits of RX channel 0
@@ -123,7 +123,7 @@ typedef union {
uint32_t reserved_7:25; uint32_t reserved_7:25;
}; };
uint32_t val; uint32_t val;
} gdma_in_int_ena_chn_reg_t; } ahb_dma_in_int_ena_chn_reg_t;
/** Type of in_int_clr_chn register /** Type of in_int_clr_chn register
* Interrupt clear bits of RX channel 0 * Interrupt clear bits of RX channel 0
@@ -161,7 +161,7 @@ typedef union {
uint32_t reserved_7:25; uint32_t reserved_7:25;
}; };
uint32_t val; uint32_t val;
} gdma_in_int_clr_chn_reg_t; } ahb_dma_in_int_clr_chn_reg_t;
/** Type of out_int_raw_chn register /** Type of out_int_raw_chn register
* Raw interrupt status of TX channel 0 * Raw interrupt status of TX channel 0
@@ -195,7 +195,7 @@ typedef union {
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} gdma_out_int_raw_chn_reg_t; } ahb_dma_out_int_raw_chn_reg_t;
/** Type of out_int_st_chn register /** Type of out_int_st_chn register
* Masked interrupt status of TX channel 0 * Masked interrupt status of TX channel 0
@@ -229,7 +229,7 @@ typedef union {
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} gdma_out_int_st_chn_reg_t; } ahb_dma_out_int_st_chn_reg_t;
/** Type of out_int_ena_chn register /** Type of out_int_ena_chn register
* Interrupt enable bits of TX channel 0 * Interrupt enable bits of TX channel 0
@@ -263,7 +263,7 @@ typedef union {
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} gdma_out_int_ena_chn_reg_t; } ahb_dma_out_int_ena_chn_reg_t;
/** Type of out_int_clr_chn register /** Type of out_int_clr_chn register
* Interrupt clear bits of TX channel 0 * Interrupt clear bits of TX channel 0
@@ -297,7 +297,7 @@ typedef union {
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} gdma_out_int_clr_chn_reg_t; } ahb_dma_out_int_clr_chn_reg_t;
/** Group: Debug Registers */ /** Group: Debug Registers */
@@ -318,7 +318,7 @@ typedef union {
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} gdma_ahb_test_reg_t; } ahb_dma_ahb_test_reg_t;
/** Group: Configuration Registers */ /** Group: Configuration Registers */
@@ -345,7 +345,7 @@ typedef union {
uint32_t reserved_4:28; uint32_t reserved_4:28;
}; };
uint32_t val; uint32_t val;
} gdma_misc_conf_reg_t; } ahb_dma_misc_conf_reg_t;
/** Type of in_conf0_chn register /** Type of in_conf0_chn register
* Configuration register 0 of RX channel 0 * Configuration register 0 of RX channel 0
@@ -384,7 +384,7 @@ typedef union {
uint32_t reserved_8:24; uint32_t reserved_8:24;
}; };
uint32_t val; uint32_t val;
} gdma_in_conf0_chn_reg_t; } ahb_dma_in_conf0_chn_reg_t;
/** Type of in_conf1_chn register /** Type of in_conf1_chn register
* Configuration register 1 of RX channel 0 * Configuration register 1 of RX channel 0
@@ -400,7 +400,7 @@ typedef union {
uint32_t reserved_13:19; uint32_t reserved_13:19;
}; };
uint32_t val; uint32_t val;
} gdma_in_conf1_chn_reg_t; } ahb_dma_in_conf1_chn_reg_t;
/** Type of in_pop_chn register /** Type of in_pop_chn register
* Pop control register of RX channel 0 * Pop control register of RX channel 0
@@ -419,7 +419,7 @@ typedef union {
uint32_t reserved_13:19; uint32_t reserved_13:19;
}; };
uint32_t val; uint32_t val;
} gdma_in_pop_chn_reg_t; } ahb_dma_in_pop_chn_reg_t;
/** Type of in_link_chn register /** Type of in_link_chn register
* Linked list descriptor configuration and control register of RX channel 0 * Linked list descriptor configuration and control register of RX channel 0
@@ -453,8 +453,55 @@ typedef union {
uint32_t reserved_5:27; uint32_t reserved_5:27;
}; };
uint32_t val; uint32_t val;
} gdma_in_link_chn_reg_t; } ahb_dma_in_link_chn_reg_t;
/** Type of out_conf0_ch0 register
* Configuration register 0 of TX channel 0
*/
typedef union {
struct {
/** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
* Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0:
* Release reset\\1: Reset\\
*/
uint32_t out_rst_ch0:1;
/** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
* Reserved.
*/
uint32_t out_loop_test_ch0:1;
/** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable automatic outlink write-back when all the data
* in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\
*/
uint32_t out_auto_wrback_ch0:1;
/** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
* Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated
* when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for
* TX channel 0 is generated when data to be transmitted has been popped from FIFO in
* AHB_DMA.\\
*/
uint32_t out_eof_mode_ch0:1;
/** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable INCR burst transfer for TX channel 0 reading
* descriptors.\\0: Disable\\1: Enable\\
*/
uint32_t outdscr_burst_en_ch0:1;
uint32_t reserved_5:1;
/** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0;
* Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1:
* Enable\\
*/
uint32_t out_etm_en_ch0:1;
uint32_t reserved_7:1;
/** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
*/
uint32_t out_data_burst_mode_sel_ch0:2;
uint32_t reserved_10:22;
};
uint32_t val;
} ahb_dma_out_conf0_ch0_reg_t;
/** Type of out_conf1_chn register /** Type of out_conf1_chn register
* Configuration register 1 of TX channel 0 * Configuration register 1 of TX channel 0
@@ -470,7 +517,7 @@ typedef union {
uint32_t reserved_13:19; uint32_t reserved_13:19;
}; };
uint32_t val; uint32_t val;
} gdma_out_conf1_chn_reg_t; } ahb_dma_out_conf1_chn_reg_t;
/** Type of out_push_chn register /** Type of out_push_chn register
* Push control register of TX channel 0 * Push control register of TX channel 0
@@ -489,7 +536,7 @@ typedef union {
uint32_t reserved_10:22; uint32_t reserved_10:22;
}; };
uint32_t val; uint32_t val;
} gdma_out_push_chn_reg_t; } ahb_dma_out_push_chn_reg_t;
/** Type of out_link_chn register /** Type of out_link_chn register
* Linked list descriptor configuration and control register of TX channel 0 * Linked list descriptor configuration and control register of TX channel 0
@@ -518,7 +565,7 @@ typedef union {
uint32_t reserved_4:28; uint32_t reserved_4:28;
}; };
uint32_t val; uint32_t val;
} gdma_out_link_chn_reg_t; } ahb_dma_out_link_chn_reg_t;
/** Type of out_conf0_chn register /** Type of out_conf0_chn register
* Configuration register 0 of TX channel 1 * Configuration register 0 of TX channel 1
@@ -566,7 +613,7 @@ typedef union {
uint32_t reserved_10:22; uint32_t reserved_10:22;
}; };
uint32_t val; uint32_t val;
} gdma_out_conf0_chn_reg_t; } ahb_dma_out_conf0_chn_reg_t;
/** Type of tx_ch_arb_weigh_chn register /** Type of tx_ch_arb_weigh_chn register
* TX channel 0 arbitration weight configuration register * TX channel 0 arbitration weight configuration register
@@ -661,7 +708,7 @@ typedef union {
uint32_t access_intr_mem_start_addr:32; uint32_t access_intr_mem_start_addr:32;
}; };
uint32_t val; uint32_t val;
} gdma_intr_mem_start_addr_reg_t; } ahb_dma_intr_mem_start_addr_reg_t;
/** Type of intr_mem_end_addr register /** Type of intr_mem_end_addr register
* Accessible address space end address configuration register * Accessible address space end address configuration register
@@ -674,7 +721,7 @@ typedef union {
uint32_t access_intr_mem_end_addr:32; uint32_t access_intr_mem_end_addr:32;
}; };
uint32_t val; uint32_t val;
} gdma_intr_mem_end_addr_reg_t; } ahb_dma_intr_mem_end_addr_reg_t;
/** Type of arb_timeout_tx register /** Type of arb_timeout_tx register
* TX arbitration timeout configuration register * TX arbitration timeout configuration register
@@ -688,7 +735,7 @@ typedef union {
uint32_t reserved_16:16; uint32_t reserved_16:16;
}; };
uint32_t val; uint32_t val;
} gdma_arb_timeout_tx_reg_t; } ahb_dma_arb_timeout_tx_reg_t;
/** Type of arb_timeout_rx register /** Type of arb_timeout_rx register
* RX arbitration timeout configuration register * RX arbitration timeout configuration register
@@ -702,7 +749,7 @@ typedef union {
uint32_t reserved_16:16; uint32_t reserved_16:16;
}; };
uint32_t val; uint32_t val;
} gdma_arb_timeout_rx_reg_t; } ahb_dma_arb_timeout_rx_reg_t;
/** Type of weight_en_tx register /** Type of weight_en_tx register
* TX weight arbitration enable register * TX weight arbitration enable register
@@ -716,7 +763,7 @@ typedef union {
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} gdma_weight_en_tx_reg_t; } ahb_dma_weight_en_tx_reg_t;
/** Type of weight_en_rx register /** Type of weight_en_rx register
* RX weight arbitration enable register * RX weight arbitration enable register
@@ -730,7 +777,7 @@ typedef union {
uint32_t reserved_1:31; uint32_t reserved_1:31;
}; };
uint32_t val; uint32_t val;
} gdma_weight_en_rx_reg_t; } ahb_dma_weight_en_rx_reg_t;
/** Group: Version Registers */ /** Group: Version Registers */
@@ -745,7 +792,7 @@ typedef union {
uint32_t date:32; uint32_t date:32;
}; };
uint32_t val; uint32_t val;
} gdma_date_reg_t; } ahb_dma_date_reg_t;
/** Group: Status Registers */ /** Group: Status Registers */
@@ -856,7 +903,7 @@ typedef union {
uint32_t inlink_dscr_chn:32; uint32_t inlink_dscr_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_in_dscr_chn_reg_t; } ahb_dma_in_dscr_chn_reg_t;
/** Type of in_dscr_bf0_chn register /** Type of in_dscr_bf0_chn register
* The last receive descriptor address of RX channel 0 * The last receive descriptor address of RX channel 0
@@ -870,7 +917,7 @@ typedef union {
uint32_t inlink_dscr_bf0_chn:32; uint32_t inlink_dscr_bf0_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_in_dscr_bf0_chn_reg_t; } ahb_dma_in_dscr_bf0_chn_reg_t;
/** Type of in_dscr_bf1_chn register /** Type of in_dscr_bf1_chn register
* The second-to-last receive descriptor address of RX channel 0 * The second-to-last receive descriptor address of RX channel 0
@@ -884,7 +931,7 @@ typedef union {
uint32_t inlink_dscr_bf1_chn:32; uint32_t inlink_dscr_bf1_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_in_dscr_bf1_chn_reg_t; } ahb_dma_in_dscr_bf1_chn_reg_t;
/** Type of in_done_des_addr_chn register /** Type of in_done_des_addr_chn register
* RX_done Inlink descriptor address of RX channel 0 * RX_done Inlink descriptor address of RX channel 0
@@ -897,7 +944,7 @@ typedef union {
uint32_t in_done_des_addr_chn:32; uint32_t in_done_des_addr_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_in_done_des_addr_chn_reg_t; } ahb_dma_in_done_des_addr_chn_reg_t;
/** Type of outfifo_status_chn register /** Type of outfifo_status_chn register
* Transmit FIFO status of TX channel 0 * Transmit FIFO status of TX channel 0
@@ -937,7 +984,7 @@ typedef union {
uint32_t reserved_27:5; uint32_t reserved_27:5;
}; };
uint32_t val; uint32_t val;
} gdma_outfifo_status_chn_reg_t; } ahb_dma_outfifo_status_chn_reg_t;
/** Type of out_state_chn register /** Type of out_state_chn register
* Transmit status of TX channel 0 * Transmit status of TX channel 0
@@ -960,7 +1007,7 @@ typedef union {
uint32_t reserved_23:9; uint32_t reserved_23:9;
}; };
uint32_t val; uint32_t val;
} gdma_out_state_chn_reg_t; } ahb_dma_out_state_chn_reg_t;
/** Type of out_eof_des_addr_chn register /** Type of out_eof_des_addr_chn register
* Transmit descriptor address when EOF occurs on TX channel 0 * Transmit descriptor address when EOF occurs on TX channel 0
@@ -974,7 +1021,7 @@ typedef union {
uint32_t out_eof_des_addr_chn:32; uint32_t out_eof_des_addr_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_out_eof_des_addr_chn_reg_t; } ahb_dma_out_eof_des_addr_chn_reg_t;
/** Type of out_eof_bfr_des_addr_chn register /** Type of out_eof_bfr_des_addr_chn register
* The last transmit descriptor address when EOF occurs on TX channel 0 * The last transmit descriptor address when EOF occurs on TX channel 0
@@ -988,7 +1035,7 @@ typedef union {
uint32_t out_eof_bfr_des_addr_chn:32; uint32_t out_eof_bfr_des_addr_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_out_eof_bfr_des_addr_chn_reg_t; } ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
/** Type of out_dscr_chn register /** Type of out_dscr_chn register
* Current transmit descriptor address of TX channel 0 * Current transmit descriptor address of TX channel 0
@@ -1002,7 +1049,7 @@ typedef union {
uint32_t outlink_dscr_chn:32; uint32_t outlink_dscr_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_out_dscr_chn_reg_t; } ahb_dma_out_dscr_chn_reg_t;
/** Type of out_dscr_bf0_chn register /** Type of out_dscr_bf0_chn register
* The last transmit descriptor address of TX channel 0 * The last transmit descriptor address of TX channel 0
@@ -1016,7 +1063,7 @@ typedef union {
uint32_t outlink_dscr_bf0_chn:32; uint32_t outlink_dscr_bf0_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_out_dscr_bf0_chn_reg_t; } ahb_dma_out_dscr_bf0_chn_reg_t;
/** Type of out_dscr_bf1_chn register /** Type of out_dscr_bf1_chn register
* The second-to-last transmit descriptor address of TX channel 0 * The second-to-last transmit descriptor address of TX channel 0
@@ -1030,7 +1077,7 @@ typedef union {
uint32_t outlink_dscr_bf1_chn:32; uint32_t outlink_dscr_bf1_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_out_dscr_bf1_chn_reg_t; } ahb_dma_out_dscr_bf1_chn_reg_t;
/** Type of out_done_des_addr_chn register /** Type of out_done_des_addr_chn register
* TX done outlink descriptor address of TX channel 0 * TX done outlink descriptor address of TX channel 0
@@ -1043,7 +1090,7 @@ typedef union {
uint32_t out_done_des_addr_chn:32; uint32_t out_done_des_addr_chn:32;
}; };
uint32_t val; uint32_t val;
} gdma_out_done_des_addr_chn_reg_t; } ahb_dma_out_done_des_addr_chn_reg_t;
/** Group: Priority Registers */ /** Group: Priority Registers */
@@ -1060,7 +1107,7 @@ typedef union {
uint32_t reserved_4:28; uint32_t reserved_4:28;
}; };
uint32_t val; uint32_t val;
} gdma_in_pri_chn_reg_t; } ahb_dma_in_pri_chn_reg_t;
/** Type of out_pri_chn register /** Type of out_pri_chn register
* Priority register of TX channel 0 * Priority register of TX channel 0
@@ -1075,7 +1122,7 @@ typedef union {
uint32_t reserved_4:28; uint32_t reserved_4:28;
}; };
uint32_t val; uint32_t val;
} gdma_out_pri_chn_reg_t; } ahb_dma_out_pri_chn_reg_t;
/** Group: Peripheral Select Registers */ /** Group: Peripheral Select Registers */
@@ -1093,7 +1140,7 @@ typedef union {
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} gdma_in_peri_sel_chn_reg_t; } ahb_dma_in_peri_sel_chn_reg_t;
/** Type of out_peri_sel_chn register /** Type of out_peri_sel_chn register
* Peripheral selection register of TX channel 0 * Peripheral selection register of TX channel 0
@@ -1109,68 +1156,65 @@ typedef union {
uint32_t reserved_6:26; uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} gdma_out_peri_sel_chn_reg_t; } ahb_dma_out_peri_sel_chn_reg_t;
typedef struct { typedef struct {
volatile gdma_in_int_raw_chn_reg_t raw; volatile ahb_dma_in_int_raw_chn_reg_t raw;
volatile gdma_in_int_st_chn_reg_t st; volatile ahb_dma_in_int_st_chn_reg_t st;
volatile gdma_in_int_ena_chn_reg_t ena; volatile ahb_dma_in_int_ena_chn_reg_t ena;
volatile gdma_in_int_clr_chn_reg_t clr; volatile ahb_dma_in_int_clr_chn_reg_t clr;
} gdma_in_int_chn_reg_t; } ahb_dma_in_int_chn_reg_t;
typedef struct { typedef struct {
volatile gdma_out_int_raw_chn_reg_t raw; volatile ahb_dma_out_int_raw_chn_reg_t raw;
volatile gdma_out_int_st_chn_reg_t st; volatile ahb_dma_out_int_st_chn_reg_t st;
volatile gdma_out_int_ena_chn_reg_t ena; volatile ahb_dma_out_int_ena_chn_reg_t ena;
volatile gdma_out_int_clr_chn_reg_t clr; volatile ahb_dma_out_int_clr_chn_reg_t clr;
} gdma_out_int_chn_reg_t; } ahb_dma_out_int_chn_reg_t;
typedef struct { typedef struct {
volatile gdma_in_conf0_chn_reg_t in_conf0; volatile ahb_dma_in_conf0_chn_reg_t in_conf0;
volatile gdma_in_conf1_chn_reg_t in_conf1; volatile ahb_dma_in_conf1_chn_reg_t in_conf1;
volatile ahb_dma_infifo_status_chn_reg_t infifo_status; volatile ahb_dma_infifo_status_chn_reg_t infifo_status;
volatile gdma_in_pop_chn_reg_t in_pop; volatile ahb_dma_in_pop_chn_reg_t in_pop;
volatile gdma_in_link_chn_reg_t in_link; volatile ahb_dma_in_link_chn_reg_t in_link;
volatile ahb_dma_in_state_chn_reg_t in_state; volatile ahb_dma_in_state_chn_reg_t in_state;
volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile gdma_in_dscr_chn_reg_t in_dscr; volatile ahb_dma_in_dscr_chn_reg_t in_dscr;
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0; volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1; volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile gdma_in_pri_chn_reg_t in_pri; volatile ahb_dma_in_pri_chn_reg_t in_pri;
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel; volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel;
} gdma_in_chn_reg_t; } ahb_dma_in_chn_reg_t;
typedef struct { typedef struct {
volatile gdma_out_conf0_chn_reg_t out_conf0; volatile ahb_dma_out_conf0_chn_reg_t out_conf0;
volatile gdma_out_conf1_chn_reg_t out_conf1; volatile ahb_dma_out_conf1_chn_reg_t out_conf1;
volatile gdma_outfifo_status_chn_reg_t outfifo_status; volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status;
volatile gdma_out_push_chn_reg_t out_push; volatile ahb_dma_out_push_chn_reg_t out_push;
volatile gdma_out_link_chn_reg_t out_link; volatile ahb_dma_out_link_chn_reg_t out_link;
volatile gdma_out_state_chn_reg_t out_state; volatile ahb_dma_out_state_chn_reg_t out_state;
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr; volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr; volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
volatile gdma_out_dscr_chn_reg_t out_dscr; volatile ahb_dma_out_dscr_chn_reg_t out_dscr;
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0; volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1; volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
volatile gdma_out_pri_chn_reg_t out_pri; volatile ahb_dma_out_pri_chn_reg_t out_pri;
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel; volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel;
} gdma_out_chn_reg_t; } ahb_dma_out_chn_reg_t;
typedef struct { typedef struct {
volatile gdma_in_chn_reg_t in; volatile ahb_dma_in_chn_reg_t in;
// uint32_t reserved_in[11]; // volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0; uint32_t reserved_0a4[3];
uint32_t reserved_in1[3]; volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0;
volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_chn; uint32_t reserved_0b4[7];
uint32_t reserved_in2[7]; volatile ahb_dma_out_chn_reg_t out;
volatile gdma_out_chn_reg_t out; uint32_t reserved_104[3];
// uint32_t reserved_out[11]; // volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0; volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0;
uint32_t reserved_out1[3]; uint32_t reserved_114[7];
volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_chn; } ahb_dma_chn_reg_t;
uint32_t reserved_out2[7];
} gdma_chn_reg_t;
typedef struct { typedef struct {
uint32_t reserved[8]; uint32_t reserved[8];
@@ -1185,15 +1229,15 @@ typedef struct {
} ahb_dma_in_crc_arb_chn_reg_t; } ahb_dma_in_crc_arb_chn_reg_t;
typedef struct { typedef struct {
volatile gdma_in_int_chn_reg_t in_intr[2]; volatile ahb_dma_in_int_chn_reg_t in_intr[2];
uint32_t reserved_020[4]; uint32_t reserved_020[4];
volatile gdma_out_int_chn_reg_t out_intr[2]; volatile ahb_dma_out_int_chn_reg_t out_intr[2];
uint32_t reserved_050[4]; uint32_t reserved_050[4];
volatile gdma_ahb_test_reg_t ahb_test; volatile ahb_dma_ahb_test_reg_t ahb_test;
volatile gdma_misc_conf_reg_t misc_conf; volatile ahb_dma_misc_conf_reg_t misc_conf;
volatile gdma_date_reg_t date; volatile ahb_dma_date_reg_t date;
uint32_t reserved_06c; uint32_t reserved_06c;
volatile gdma_chn_reg_t channel[2]; volatile ahb_dma_chn_reg_t channel[2];
uint32_t reserved_1d4[51]; uint32_t reserved_1d4[51];
volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[2]; volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[2];
uint32_t reserved_30c[10]; uint32_t reserved_30c[10];
@@ -1203,12 +1247,12 @@ typedef struct {
uint32_t reserved_3b4; uint32_t reserved_3b4;
volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[2]; volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[2];
uint32_t reserved_3c0; uint32_t reserved_3c0;
volatile gdma_intr_mem_start_addr_reg_t intr_mem_start_addr; volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
volatile gdma_intr_mem_end_addr_reg_t intr_mem_end_addr; volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
volatile gdma_arb_timeout_tx_reg_t arb_timeout_tx; volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
volatile gdma_arb_timeout_rx_reg_t arb_timeout_rx; volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx;
volatile gdma_weight_en_tx_reg_t weight_en_tx; volatile ahb_dma_weight_en_tx_reg_t weight_en_tx;
volatile gdma_weight_en_rx_reg_t weight_en_rx; volatile ahb_dma_weight_en_rx_reg_t weight_en_rx;
} ahb_dma_dev_t; } ahb_dma_dev_t;
extern ahb_dma_dev_t AHB_DMA; extern ahb_dma_dev_t AHB_DMA;