diff --git a/components/bootloader/subproject/main/ld/esp32/bootloader.ld b/components/bootloader/subproject/main/ld/esp32/bootloader.ld index 6af138c9d9..255a2de665 100644 --- a/components/bootloader/subproject/main/ld/esp32/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32/bootloader.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* Linker file used to link the bootloader. */ @@ -44,7 +49,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random) - *libbootloader_support.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -60,6 +65,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld index 863b9ab090..3bd9c809d0 100644 --- a/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld @@ -36,7 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libbootloader_support.a:bootloader_efuse_esp32c2.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -52,6 +52,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld index c9b2da7612..4681666917 100644 --- a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /** Simplified memory map for the bootloader. * Make sure the bootloader can load into main memory without overwriting itself. * We put 2nd bootloader in the high address space (before ROM stack/data/bss). @@ -31,7 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libbootloader_support.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -47,6 +52,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld index c5648b815e..de0b940443 100644 --- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /** Simplified memory map for the bootloader. * Make sure the bootloader can load into main memory without overwriting itself. * We put 2nd bootloader in the high address space (before ROM stack/data/bss). @@ -31,7 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libbootloader_support.a:bootloader_efuse_esp32h2.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -45,6 +50,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld index 92e0126cf0..0277a7d7a9 100644 --- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* Simplified memory map for the bootloader. * Make sure the bootloader can load into main memory without overwriting itself. */ @@ -31,7 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random) - *libbootloader_support.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -47,6 +52,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld index b35d247e3a..75de59055c 100644 --- a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /** Simplified memory map for the bootloader. * Make sure the bootloader can load into main memory without overwriting itself. * We put 2nd bootloader in the high address space (before ROM stack/data/bss). @@ -31,7 +36,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random) - *libbootloader_support.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -47,6 +52,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index 585106991c..6b958067a3 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -13,7 +13,7 @@ set(srcs "src/flash_partitions.c" "bootloader_flash/src/flash_qio_mode.c" "bootloader_flash/src/bootloader_flash_config_${IDF_TARGET}.c" - "src/bootloader_efuse_${IDF_TARGET}.c" + "src/bootloader_efuse.c" ) if(BOOTLOADER_BUILD) diff --git a/components/bootloader_support/include/bootloader_clock.h b/components/bootloader_support/include/bootloader_clock.h index 6b71f68f38..3264651598 100644 --- a/components/bootloader_support/include/bootloader_clock.h +++ b/components/bootloader_support/include/bootloader_clock.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/bootloader_support/include/esp_flash_encrypt.h b/components/bootloader_support/include/esp_flash_encrypt.h index fc939f6b8d..403db028de 100644 --- a/components/bootloader_support/include/esp_flash_encrypt.h +++ b/components/bootloader_support/include/esp_flash_encrypt.h @@ -11,7 +11,7 @@ #ifndef BOOTLOADER_BUILD #include "esp_spi_flash.h" #endif -#include "soc/efuse_periph.h" +#include "hal/efuse_ll.h" #include "sdkconfig.h" #ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH @@ -47,22 +47,14 @@ typedef enum { static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_enabled(void) { uint32_t flash_crypt_cnt = 0; -#if CONFIG_IDF_TARGET_ESP32 - #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); - #else - esp_efuse_read_field_blob(ESP_EFUSE_FLASH_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_FLASH_CRYPT_CNT[0]->bit_count); - #endif +#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + flash_crypt_cnt = efuse_ll_get_flash_crypt_cnt(); #else - #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - #if CONFIG_IDF_TARGET_ESP32C2 - // IDF-3899 - #else - flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT); - #endif - #else - esp_efuse_read_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_SPI_BOOT_CRYPT_CNT[0]->bit_count); - #endif +#if CONFIG_IDF_TARGET_ESP32 + esp_efuse_read_field_blob(ESP_EFUSE_FLASH_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_FLASH_CRYPT_CNT[0]->bit_count); +#else + esp_efuse_read_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_SPI_BOOT_CRYPT_CNT[0]->bit_count); +#endif #endif /* __builtin_parity is in flash, so we calculate parity inline */ bool enabled = false; diff --git a/components/bootloader_support/include/esp_secure_boot.h b/components/bootloader_support/include/esp_secure_boot.h index 9b7269ee4c..d87c947110 100644 --- a/components/bootloader_support/include/esp_secure_boot.h +++ b/components/bootloader_support/include/esp_secure_boot.h @@ -12,6 +12,7 @@ #include "esp_rom_efuse.h" #include "sdkconfig.h" #include "esp_rom_crc.h" +#include "hal/efuse_ll.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/efuse.h" @@ -67,20 +68,20 @@ static inline bool esp_secure_boot_enabled(void) #if CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_SECURE_BOOT_V1_ENABLED #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - return REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_RD_ABS_DONE_0; + return efuse_ll_get_secure_boot_v1_en(); #else return esp_efuse_read_field_bit(ESP_EFUSE_ABS_DONE_0); #endif #elif CONFIG_SECURE_BOOT_V2_ENABLED #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - return ets_use_secure_boot_v2(); + return efuse_ll_get_secure_boot_v2_en(); #else return esp_efuse_read_field_bit(ESP_EFUSE_ABS_DONE_1); #endif #endif #else #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - return esp_rom_efuse_is_secure_boot_enabled(); + return efuse_ll_get_secure_boot_v2_en(); #else return esp_efuse_read_field_bit(ESP_EFUSE_SECURE_BOOT_EN); #endif diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index 50c3ad710e..336fb06c97 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "sdkconfig.h" #include "soc/soc.h" #include "soc/rtc.h" -#include "soc/efuse_periph.h" +#include "hal/efuse_hal.h" #include "soc/rtc_cntl_reg.h" #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" @@ -32,8 +32,7 @@ __attribute__((weak)) void bootloader_clock_configure(void) * document). For rev. 0, switch to 240 instead if it has been enabled * previously. */ - uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG); - if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 && + if (efuse_hal_get_chip_revision() == 0 && DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) { cpu_freq_mhz = 240; } diff --git a/components/bootloader_support/src/bootloader_efuse.c b/components/bootloader_support/src/bootloader_efuse.c new file mode 100644 index 0000000000..ac5f9f7f87 --- /dev/null +++ b/components/bootloader_support/src/bootloader_efuse.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "bootloader_common.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" + +uint8_t bootloader_common_get_chip_revision(void) +{ + return efuse_hal_get_chip_revision(); +} + +uint32_t bootloader_common_get_chip_ver_pkg(void) +{ + return efuse_ll_get_chip_ver_pkg(); +} + +int bootloader_clock_get_rated_freq_mhz(void) +{ +#ifdef CONFIG_IDF_TARGET_ESP32 + return efuse_hal_get_rated_freq_mhz(); + +#elif CONFIG_IDF_TARGET_ESP32C2 + return 120; + +#elif CONFIG_IDF_TARGET_ESP32C3 + return 160; + +#elif CONFIG_IDF_TARGET_ESP32H2 + return 96; + +#elif CONFIG_IDF_TARGET_ESP32S2 + return 240; + +#elif CONFIG_IDF_TARGET_ESP32S3 + return 240; + +#endif +} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32.c b/components/bootloader_support/src/bootloader_efuse_esp32.c deleted file mode 100644 index 2a89e63ce4..0000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "bootloader_common.h" -#include "bootloader_clock.h" -#include "soc/efuse_reg.h" -#include "soc/syscon_reg.h" - -uint8_t bootloader_common_get_chip_revision(void) -{ - uint8_t eco_bit0, eco_bit1, eco_bit2; - eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15; - eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20; - eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31; - uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; - uint8_t chip_ver = 0; - switch (combine_value) { - case 0: - chip_ver = 0; - break; - case 1: - chip_ver = 1; - break; - case 3: - chip_ver = 2; - break; -#if CONFIG_IDF_ENV_FPGA - case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */ - chip_ver = 3; - break; -#endif - case 7: - chip_ver = 3; - break; - default: - chip_ver = 0; - break; - } - return chip_ver; -} - -uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); - uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT); - return (pkg_version_4bit << 3) | pkg_version; -} - -int bootloader_clock_get_rated_freq_mhz() -{ - //Check if ESP32 is rated for a CPU frequency of 160MHz only - if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) && - REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) { - return 160; - } - return 240; -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32c2.c b/components/bootloader_support/src/bootloader_efuse_esp32c2.c deleted file mode 100644 index f5cf24704d..0000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32c2.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "soc/efuse_reg.h" - -uint8_t bootloader_common_get_chip_revision(void) -{ - // should return the same value as esp_efuse_get_chip_ver() - return REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_WAFER_VERSION); -} - -uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - // should return the same value as esp_efuse_get_pkg_ver() - return REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_PKG_VERSION); -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32c3.c b/components/bootloader_support/src/bootloader_efuse_esp32c3.c deleted file mode 100644 index aa59b5e60f..0000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32c3.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "soc/efuse_reg.h" - -uint8_t bootloader_common_get_chip_revision(void) -{ - // should return the same value as esp_efuse_get_chip_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); -} - -uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - // should return the same value as esp_efuse_get_pkg_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32h2.c b/components/bootloader_support/src/bootloader_efuse_esp32h2.c deleted file mode 100644 index ea38c22a6a..0000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32h2.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "soc/efuse_reg.h" - -uint8_t bootloader_common_get_chip_revision(void) -{ -#if IDF_TARGET_ESP32H2_BETA_VERSION_1 // TODO: IDF-4337 - // should return the same value as esp_efuse_get_chip_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); -#else - return 0; -#endif -} - -uint32_t bootloader_common_get_chip_ver_pkg(void) -{ -#if IDF_TARGET_ESP32H2_BETA_VERSION_1 // TODO: IDF-4337 - // should return the same value as esp_efuse_get_pkg_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); -#else - return 0; -#endif -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32s2.c b/components/bootloader_support/src/bootloader_efuse_esp32s2.c deleted file mode 100644 index 0ecabe7078..0000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32s2.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "sdkconfig.h" -#include "bootloader_clock.h" -#include "bootloader_common.h" -#include "soc/efuse_reg.h" - -uint8_t bootloader_common_get_chip_revision(void) -{ - // should return the same value as esp_efuse_get_chip_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); -} - -uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - // should return the same value as esp_efuse_get_pkg_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_4_REG, EFUSE_PKG_VERSION); -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32s3.c b/components/bootloader_support/src/bootloader_efuse_esp32s3.c deleted file mode 100644 index 61d179f697..0000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32s3.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -uint8_t bootloader_common_get_chip_revision(void) -{ - // should return the same value as esp_efuse_get_chip_ver() - /* No other revisions for ESP32-S3 */ - return 0; -} - -uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - // should return the same value as esp_efuse_get_pkg_ver() - return 0; -} diff --git a/components/efuse/esp32/esp_efuse_fields.c b/components/efuse/esp32/esp_efuse_fields.c index 7d45cfd68c..ece674b116 100644 --- a/components/efuse/esp32/esp_efuse_fields.c +++ b/components/efuse/esp32/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "esp_err.h" #include "esp_log.h" #include "soc/efuse_periph.h" +#include "hal/efuse_hal.h" #include "bootloader_random.h" #include "sys/param.h" #include "soc/syscon_reg.h" @@ -24,30 +25,7 @@ const static char *TAG = "efuse"; // Returns chip version from efuse uint8_t esp_efuse_get_chip_ver(void) { - uint8_t eco_bit0, eco_bit1, eco_bit2; - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1); - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1); - eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31; - uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; - uint8_t chip_ver = 0; - switch (combine_value) { - case 0: - chip_ver = 0; - break; - case 1: - chip_ver = 1; - break; - case 3: - chip_ver = 2; - break; - case 7: - chip_ver = 3; - break; - default: - chip_ver = 0; - break; - } - return chip_ver; + return efuse_hal_get_chip_revision(); } // Returns chip package from efuse @@ -92,32 +70,3 @@ esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) { return ESP_ERR_NOT_SUPPORTED; } - -void esp_efuse_write_random_key(uint32_t blk_wdata0_reg) -{ - uint32_t buf[8]; - uint8_t raw[24]; - - if (esp_efuse_get_coding_scheme(EFUSE_BLK2) == EFUSE_CODING_SCHEME_NONE) { - bootloader_fill_random(buf, sizeof(buf)); - } else { // 3/4 Coding Scheme - bootloader_fill_random(raw, sizeof(raw)); - esp_err_t r = esp_efuse_utility_apply_34_encoding(raw, buf, sizeof(raw)); - (void) r; - assert(r == ESP_OK); - } - - ESP_LOGV(TAG, "Writing random values to address 0x%08x", blk_wdata0_reg); - for (int i = 0; i < 8; i++) { - ESP_LOGV(TAG, "EFUSE_BLKx_WDATA%d_REG = 0x%08x", i, buf[i]); - REG_WRITE(blk_wdata0_reg + 4*i, buf[i]); - } - bzero(buf, sizeof(buf)); - bzero(raw, sizeof(raw)); -} - -// Permanently update values written to the efuse write registers -void esp_efuse_burn_new_values(void) -{ - esp_efuse_utility_burn_efuses(); -} diff --git a/components/efuse/esp32/esp_efuse_utility.c b/components/efuse/esp32/esp_efuse_utility.c index d289eaf3db..81dadbc92f 100644 --- a/components/efuse/esp32/esp_efuse_utility.c +++ b/components/efuse/esp32/esp_efuse_utility.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "esp_efuse_utility.h" #include "soc/efuse_periph.h" +#include "hal/efuse_hal.h" #include "esp_private/esp_clk.h" #include "esp_log.h" #include "assert.h" @@ -34,33 +35,12 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = { {EFUSE_BLK3_WDATA0_REG, EFUSE_BLK3_WDATA7_REG} // range address of EFUSE_BLK3 }; -#define EFUSE_CONF_WRITE 0x5A5A /* eFuse_pgm_op_ena, force no rd/wr disable. */ -#define EFUSE_CONF_READ 0x5AA5 /* eFuse_read_op_ena, release force. */ -#define EFUSE_CMD_PGM 0x02 /* Command to program. */ -#define EFUSE_CMD_READ 0x01 /* Command to read. */ - #ifndef CONFIG_EFUSE_VIRTUAL // Update Efuse timing configuration static esp_err_t esp_efuse_set_timing(void) { uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000; - uint32_t clk_sel0, clk_sel1, dac_clk_div; - if (apb_freq_mhz <= 26) { - clk_sel0 = 250; - clk_sel1 = 255; - dac_clk_div = 52; - } else if (apb_freq_mhz <= 40) { - clk_sel0 = 160; - clk_sel1 = 255; - dac_clk_div = 80; - } else { - clk_sel0 = 80; - clk_sel1 = 128; - dac_clk_div = 100; - } - REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div); - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0); - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1); + efuse_hal_set_timing(apb_freq_mhz); return ESP_OK; } #endif // ifndef CONFIG_EFUSE_VIRTUAL @@ -68,7 +48,7 @@ static esp_err_t esp_efuse_set_timing(void) // Efuse read operation: copies data from physical efuses to efuse read registers. void esp_efuse_utility_clear_program_registers(void) { - REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); + efuse_hal_clear_program_registers(); } // Burn values written to the efuse write registers @@ -104,12 +84,7 @@ void esp_efuse_utility_burn_chip(void) #else esp_efuse_set_timing(); // Permanently update values written to the efuse write registers - REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE); - REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_PGM); - while (REG_READ(EFUSE_CMD_REG) != 0) {}; - REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); - REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_READ); - while (REG_READ(EFUSE_CMD_REG) != 0) {}; + efuse_hal_program(0); #endif // CONFIG_EFUSE_VIRTUAL esp_efuse_utility_reset(); } diff --git a/components/efuse/esp32/include/esp_efuse.h b/components/efuse/esp32/include/esp_efuse.h index a28e2482f3..0c8f53eb0c 100644 --- a/components/efuse/esp32/include/esp_efuse.h +++ b/components/efuse/esp32/include/esp_efuse.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -54,61 +54,6 @@ typedef enum { ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE*/ } esp_efuse_purpose_t; - -/** - * @brief Permanently update values written to the efuse write registers - * - * After updating EFUSE_BLKx_WDATAx_REG registers with new values to - * write, call this function to permanently write them to efuse. - * - * @note Setting bits in efuse is permanent, they cannot be unset. - * - * @note Due to this restriction you don't need to copy values to - * Efuse write registers from the matching read registers, bits which - * are set in the read register but unset in the matching write - * register will be unchanged when new values are burned. - * - * @note This function is not threadsafe, if calling code updates - * efuse values from multiple tasks then this is caller's - * responsibility to serialise. - * - * @deprecated Use the batch mode instead of directly call the burn command. - * - * After burning new efuses, the read registers are updated to match - * the new efuse values. - */ -void esp_efuse_burn_new_values(void) __attribute__ ((deprecated)); - -/* @brief Write random data to efuse key block write registers - * - * @note Caller is responsible for ensuring efuse - * block is empty and not write protected, before calling. - * - * @note Behaviour depends on coding scheme: a 256-bit key is - * generated and written for Coding Scheme "None", a 192-bit key - * is generated, extended to 256-bits by the Coding Scheme, - * and then writtten for 3/4 Coding Scheme. - * - * @note This function does not burn the new values, caller should - * call esp_efuse_burn_new_values() when ready to do this. - * - * @deprecated Use the code below instead of this function: - * - * @code{c} - * uint32_t key[8]; - * size_t key_size = 256; - * if (coding_scheme == EFUSE_CODING_SCHEME_3_4) { - * key_size = 192; - * } - * bootloader_fill_random(key, key_size / 8); - * esp_efuse_write_block(EFUSE_BLK1, key, 0, key_size); - * @endcode - * - * @param blk_wdata0_reg Address of the first data write register - * in the block - */ -void esp_efuse_write_random_key(uint32_t blk_wdata0_reg) __attribute__ ((deprecated)); - #ifdef __cplusplus } #endif diff --git a/components/efuse/esp32c3/esp_efuse_utility.c b/components/efuse/esp32c3/esp_efuse_utility.c index 802337479d..43a1084062 100644 --- a/components/efuse/esp32c3/esp_efuse_utility.c +++ b/components/efuse/esp32c3/esp_efuse_utility.c @@ -10,8 +10,7 @@ #include "assert.h" #include "esp_efuse_utility.h" #include "soc/efuse_periph.h" -#include "esp_private/esp_clk.h" -#include "esp32c3/rom/efuse.h" +#include "hal/efuse_hal.h" static const char *TAG = "efuse"; @@ -51,45 +50,22 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = { {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, }; +#ifndef CONFIG_EFUSE_VIRTUAL // Update Efuse timing configuration static esp_err_t esp_efuse_set_timing(void) { - REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x190); + // efuse clock is fixed. + // An argument (0) is for compatibility and will be ignored. + efuse_hal_set_timing(0); return ESP_OK; } - -static void efuse_read(void) -{ - esp_efuse_set_timing(); - REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE); - REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD); - - while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } - /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ - while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } -} - -#ifndef CONFIG_EFUSE_VIRTUAL -static void efuse_program(esp_efuse_block_t block) -{ - esp_efuse_set_timing(); - - REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE); - - REG_WRITE(EFUSE_CMD_REG, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD); - - while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_PGM_CMD) != 0) { }; - - ets_efuse_clear_program_registers(); - efuse_read(); -} #endif // ifndef CONFIG_EFUSE_VIRTUAL // Efuse read operation: copies data from physical efuses to efuse read registers. void esp_efuse_utility_clear_program_registers(void) { - efuse_read(); - ets_efuse_clear_program_registers(); + efuse_hal_read(); + efuse_hal_clear_program_registers(); } // Burn values written to the efuse write registers @@ -117,12 +93,12 @@ void esp_efuse_utility_burn_chip(void) if (REG_READ(addr_wr_block) != 0) { if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { uint8_t block_rs[12]; - ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); } int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); - efuse_program(num_block); + efuse_hal_program(num_block); break; } } diff --git a/components/efuse/esp32h2/esp_efuse_utility.c b/components/efuse/esp32h2/esp_efuse_utility.c index 91cc15a49c..43a1084062 100644 --- a/components/efuse/esp32h2/esp_efuse_utility.c +++ b/components/efuse/esp32h2/esp_efuse_utility.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +10,7 @@ #include "assert.h" #include "esp_efuse_utility.h" #include "soc/efuse_periph.h" -#include "esp_private/esp_clk.h" -#include "esp32h2/rom/efuse.h" +#include "hal/efuse_hal.h" static const char *TAG = "efuse"; @@ -55,14 +54,9 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = { // Update Efuse timing configuration static esp_err_t esp_efuse_set_timing(void) { - // efuse clock is fixed in ESP32-C3, so the ets_efuse_set_timing() function - // takes an argument for compatibility with older ROM functions but it's ignored. - int res = ets_efuse_set_timing(0); - assert(res == 0); - (void)res; - - REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x60); - + // efuse clock is fixed. + // An argument (0) is for compatibility and will be ignored. + efuse_hal_set_timing(0); return ESP_OK; } #endif // ifndef CONFIG_EFUSE_VIRTUAL @@ -70,8 +64,8 @@ static esp_err_t esp_efuse_set_timing(void) // Efuse read operation: copies data from physical efuses to efuse read registers. void esp_efuse_utility_clear_program_registers(void) { - ets_efuse_read(); - ets_efuse_clear_program_registers(); + efuse_hal_read(); + efuse_hal_clear_program_registers(); } // Burn values written to the efuse write registers @@ -99,12 +93,12 @@ void esp_efuse_utility_burn_chip(void) if (REG_READ(addr_wr_block) != 0) { if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { uint8_t block_rs[12]; - ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); } int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); - ets_efuse_program(num_block); + efuse_hal_program(num_block); break; } } diff --git a/components/efuse/esp32s2/esp_efuse_utility.c b/components/efuse/esp32s2/esp_efuse_utility.c index bab6e61844..89f8439f67 100644 --- a/components/efuse/esp32s2/esp_efuse_utility.c +++ b/components/efuse/esp32s2/esp_efuse_utility.c @@ -1,17 +1,17 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "assert.h" #include "esp_efuse_utility.h" #include "soc/efuse_periph.h" #include "esp_private/esp_clk.h" -#include "esp_log.h" -#include "assert.h" -#include "sdkconfig.h" -#include -#include "esp32s2/rom/efuse.h" +#include "hal/efuse_hal.h" static const char *TAG = "efuse"; @@ -56,15 +56,16 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = { static esp_err_t esp_efuse_set_timing(void) { uint32_t clock_hz = esp_clk_apb_freq(); - return ets_efuse_set_timing(clock_hz) ? ESP_FAIL : ESP_OK; + efuse_hal_set_timing(clock_hz); + return ESP_OK; } #endif // ifndef CONFIG_EFUSE_VIRTUAL // Efuse read operation: copies data from physical efuses to efuse read registers. void esp_efuse_utility_clear_program_registers(void) { - ets_efuse_read(); - ets_efuse_clear_program_registers(); + efuse_hal_read(); + efuse_hal_clear_program_registers(); } // Burn values written to the efuse write registers @@ -92,12 +93,12 @@ void esp_efuse_utility_burn_chip(void) if (REG_READ(addr_wr_block) != 0) { if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { uint8_t block_rs[12]; - ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); } int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); - ets_efuse_program(num_block); + efuse_hal_program(num_block); break; } } diff --git a/components/efuse/esp32s3/esp_efuse_utility.c b/components/efuse/esp32s3/esp_efuse_utility.c index 7879cf4119..92fc8b2494 100644 --- a/components/efuse/esp32s3/esp_efuse_utility.c +++ b/components/efuse/esp32s3/esp_efuse_utility.c @@ -6,12 +6,11 @@ #include "esp_efuse_utility.h" #include "soc/efuse_periph.h" -#include "esp_private/esp_clk.h" +#include "hal/efuse_hal.h" #include "esp_log.h" #include "assert.h" #include "sdkconfig.h" #include -#include "esp32s3/rom/efuse.h" static const char *TAG = "efuse"; @@ -51,45 +50,22 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = { {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, }; +#ifndef CONFIG_EFUSE_VIRTUAL // Update Efuse timing configuration static esp_err_t esp_efuse_set_timing(void) { - REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x190); + // efuse clock is fixed. + // An argument (0) is for compatibility and will be ignored. + efuse_hal_set_timing(0); return ESP_OK; } - -static void efuse_read(void) -{ - esp_efuse_set_timing(); - REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE); - REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD); - - while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } - /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ - while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } -} - -#ifndef CONFIG_EFUSE_VIRTUAL -static void efuse_program(esp_efuse_block_t block) -{ - esp_efuse_set_timing(); - - REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE); - - REG_WRITE(EFUSE_CMD_REG, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD); - - while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_PGM_CMD) != 0) { }; - - ets_efuse_clear_program_registers(); - efuse_read(); -} #endif // ifndef CONFIG_EFUSE_VIRTUAL // Efuse read operation: copies data from physical efuses to efuse read registers. void esp_efuse_utility_clear_program_registers(void) { - efuse_read(); - ets_efuse_clear_program_registers(); + efuse_hal_read(); + efuse_hal_clear_program_registers(); } // Burn values written to the efuse write registers @@ -117,12 +93,12 @@ void esp_efuse_utility_burn_chip(void) if (REG_READ(addr_wr_block) != 0) { if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { uint8_t block_rs[12]; - ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); } int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); - efuse_program(num_block); + efuse_hal_program(num_block); break; } } diff --git a/components/efuse/src/efuse_controller/keys/without_key_purposes/three_key_blocks/esp_efuse_api_key.c b/components/efuse/src/efuse_controller/keys/without_key_purposes/three_key_blocks/esp_efuse_api_key.c index 57b3ff5a31..069a3b85b3 100644 --- a/components/efuse/src/efuse_controller/keys/without_key_purposes/three_key_blocks/esp_efuse_api_key.c +++ b/components/efuse/src/efuse_controller/keys/without_key_purposes/three_key_blocks/esp_efuse_api_key.c @@ -6,7 +6,7 @@ #include "esp_efuse.h" #include "esp_efuse_utility.h" -#include "soc/efuse_periph.h" +#include "hal/efuse_ll.h" #include "assert.h" #include "sdkconfig.h" #include "esp_efuse_table.h" @@ -62,7 +62,7 @@ esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk) if (blk == EFUSE_BLK0) { scheme = EFUSE_CODING_SCHEME_NONE; } else { - uint32_t coding_scheme = REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME); + uint32_t coding_scheme = efuse_ll_get_coding_scheme(); if (coding_scheme == EFUSE_CODING_SCHEME_VAL_NONE || coding_scheme == (EFUSE_CODING_SCHEME_VAL_34 | EFUSE_CODING_SCHEME_VAL_REPEAT)) { scheme = EFUSE_CODING_SCHEME_NONE; diff --git a/components/esp_adc_cal/esp32/esp_adc_cal.c b/components/esp_adc_cal/esp32/esp_adc_cal.c index 187a35c3ed..2a845a9ef3 100644 --- a/components/esp_adc_cal/esp32/esp_adc_cal.c +++ b/components/esp_adc_cal/esp32/esp_adc_cal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,7 @@ #include #include "esp_types.h" #include "driver/adc.h" -#include "soc/efuse_periph.h" +#include "hal/efuse_ll.h" #include "esp_err.h" #include "esp_check.h" #include "assert.h" @@ -45,14 +45,10 @@ #define VREF_FORMAT 0 /* ------------------------------ eFuse Access ----------------------------- */ -#define BLK3_RESERVED_REG EFUSE_BLK0_RDATA3_REG - -#define VREF_REG EFUSE_BLK0_RDATA4_REG #define VREF_MASK 0x1F #define VREF_STEP_SIZE 7 #define VREF_OFFSET 1100 -#define TP_REG EFUSE_BLK3_RDATA3_REG #define TP_LOW1_OFFSET 278 #define TP_LOW2_OFFSET 421 #define TP_LOW_MASK 0x7F @@ -100,24 +96,20 @@ static const uint32_t lut_adc2_high[LUT_POINTS] = {2657, 2698, 2738, 2774, 2807, static bool check_efuse_vref(void) { //Check if Vref is burned in eFuse - return (REG_GET_FIELD(VREF_REG, EFUSE_RD_ADC_VREF) != 0) ? true : false; + return (efuse_ll_get_adc_vref() != 0) ? true : false; } static bool check_efuse_tp(void) { //Check if Two Point values are burned in eFuse - if (CHECK_BLK3_FLAG && (REG_GET_FIELD(BLK3_RESERVED_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0)) { + if (CHECK_BLK3_FLAG && (efuse_ll_get_blk3_part_reserve() == 0)) { return false; } //All TP cal values must be non zero - if ((REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW) != 0) && - (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW) != 0) && - (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH) != 0) && - (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_HIGH) != 0)) { - return true; - } else { - return false; - } + return efuse_ll_get_adc1_tp_low() && + efuse_ll_get_adc2_tp_low() && + efuse_ll_get_adc1_tp_high() && + efuse_ll_get_adc2_tp_high(); } static inline int decode_bits(uint32_t bits, uint32_t mask, bool is_twos_compl) @@ -141,7 +133,7 @@ static uint32_t read_efuse_vref(void) { //eFuse stores deviation from ideal reference voltage uint32_t ret = VREF_OFFSET; //Ideal vref - uint32_t bits = REG_GET_FIELD(VREF_REG, EFUSE_ADC_VREF); + uint32_t bits = efuse_ll_get_adc_vref(); ret += decode_bits(bits, VREF_MASK, VREF_FORMAT) * VREF_STEP_SIZE; return ret; //ADC Vref in mV } @@ -154,10 +146,10 @@ static uint32_t read_efuse_tp_low(adc_unit_t adc_num) if (adc_num == ADC_UNIT_1) { ret = TP_LOW1_OFFSET; - bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW); + bits = efuse_ll_get_adc1_tp_low(); } else { ret = TP_LOW2_OFFSET; - bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW); + bits = efuse_ll_get_adc2_tp_low(); } ret += decode_bits(bits, TP_LOW_MASK, true) * TP_STEP_SIZE; return ret; //Reading of ADC at 150mV @@ -171,10 +163,10 @@ static uint32_t read_efuse_tp_high(adc_unit_t adc_num) if (adc_num == ADC_UNIT_1) { ret = TP_HIGH1_OFFSET; - bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH); + bits = efuse_ll_get_adc1_tp_high(); } else { ret = TP_HIGH2_OFFSET; - bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_HIGH); + bits = efuse_ll_get_adc2_tp_high(); } ret += decode_bits(bits, TP_HIGH_MASK, true) * TP_STEP_SIZE; return ret; //Reading of ADC at 850mV diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 51766f23f6..589f9feb4c 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -2,9 +2,6 @@ idf_build_get_property(target IDF_TARGET) set(requires soc) set(priv_requires efuse bootloader_support spi_flash) -if(${target} STREQUAL "esp32") - list(APPEND requires efuse) -endif() set(srcs "compare_set.c" "cpu_util.c") if(NOT BOOTLOADER_BUILD) diff --git a/components/esp_hw_support/port/esp32/chip_info.c b/components/esp_hw_support/port/esp32/chip_info.c index 231b8bb8d4..fed2dbde8c 100644 --- a/components/esp_hw_support/port/esp32/chip_info.c +++ b/components/esp_hw_support/port/esp32/chip_info.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2013-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,26 +8,26 @@ #include "esp_chip_info.h" #include "soc/soc.h" #include "soc/efuse_reg.h" -#include "esp_efuse.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" void esp_chip_info(esp_chip_info_t* out_info) { - uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG); memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32; - out_info->revision = esp_efuse_get_chip_ver(); + out_info->revision = efuse_hal_get_chip_revision(); - if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) { + if (efuse_ll_get_disable_app_cpu() == 0) { out_info->cores = 2; } else { out_info->cores = 1; } out_info->features = CHIP_FEATURE_WIFI_BGN; - if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) { + if (efuse_ll_get_disable_bt() == 0) { out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE; } - uint32_t package = esp_efuse_get_pkg_ver(); + uint32_t package = efuse_ll_get_chip_ver_pkg(); if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 || @@ -42,6 +42,6 @@ void esp_chip_info(esp_chip_info_t* out_info) #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX inline bool soc_has_cache_lock_bug(void) { - return (esp_efuse_get_chip_ver() == 3); + return (efuse_hal_get_chip_revision() == 3); } #endif diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index 4a28816ff0..977b6cf165 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,13 +11,13 @@ #include "esp32/rom/ets_sys.h" // for ets_update_cpu_frequency #include "esp32/rom/rtc.h" #include "esp_rom_gpio.h" -#include "esp_efuse.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" #include "soc/sens_periph.h" #include "soc/soc_caps.h" #include "soc/dport_reg.h" -#include "soc/efuse_periph.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" #include "soc/syscon_reg.h" #include "soc/gpio_struct.h" #include "hal/cpu_hal.h" @@ -83,7 +83,7 @@ * * There is a record in efuse which indicates the proper voltage for these two cases. */ -#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV))) +#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - efuse_ll_get_vol_level_hp_inv()) #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT #else @@ -123,7 +123,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias) REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias); #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_chip_revision(); // version0 and version1 need provide additional current to external XTAL. if(chip_ver == 0 || chip_ver == 1) { /* TOUCH sensor can provide additional current to external XTAL. @@ -139,7 +139,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias) SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M); } #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2 - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_chip_revision(); if(chip_ver == 0 || chip_ver == 1) { /* TOUCH sensor can provide additional current to external XTAL. In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */ @@ -173,13 +173,13 @@ void rtc_clk_32k_enable(bool enable) CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL); #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_chip_revision(); if(chip_ver == 0 || chip_ver == 1) { /* Power down TOUCH */ CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M); } #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2 - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_chip_revision(); if(chip_ver == 0 || chip_ver == 1) { /* Power down TOUCH */ CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M); @@ -344,7 +344,7 @@ uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) { uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1; - uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0); + uint32_t is_rev0 = (efuse_ll_get_chip_ver_rev1() == 0); if (is_rev0) { sdm0 = 0; sdm1 = 0; diff --git a/components/esp_hw_support/port/esp32/rtc_init.c b/components/esp_hw_support/port/esp32/rtc_init.c index e66a493b3d..4b9472ff97 100644 --- a/components/esp_hw_support/port/esp32/rtc_init.c +++ b/components/esp_hw_support/port/esp32/rtc_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ #include "soc/rtc.h" #include "soc/rtc_periph.h" #include "soc/dport_reg.h" -#include "soc/efuse_periph.h" +#include "hal/efuse_ll.h" #include "soc/gpio_periph.h" @@ -110,20 +110,19 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void) result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S; return result; } - uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG); - if (efuse_reg & EFUSE_RD_SDIO_FORCE) { + if (efuse_ll_get_sdio_force()) { // Get configuration from EFUSE result.force = 0; - result.enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S; - result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S; + result.enable = efuse_ll_get_xpd_sdio(); + result.tieh = efuse_ll_get_sdio_tieh(); //DREFH/M/L eFuse are used for EFUSE_ADC_VREF instead. Therefore tuning //will only be available on older chips that don't have EFUSE_ADC_VREF - if(REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG ,EFUSE_RD_BLK3_PART_RESERVE) == 0){ + if(efuse_ll_get_blk3_part_reserve() == 0){ //BLK3_PART_RESERVE indicates the presence of EFUSE_ADC_VREF // in this case, DREFH/M/L are also set from EFUSE - result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S; - result.drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) >> EFUSE_RD_SDIO_DREFM_S; - result.drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) >> EFUSE_RD_SDIO_DREFL_S; + result.drefh = efuse_ll_get_sdio_drefh(); + result.drefm = efuse_ll_get_sdio_drefm(); + result.drefl = efuse_ll_get_sdio_drefl(); } return result; } diff --git a/components/esp_hw_support/port/esp32c2/chip_info.c b/components/esp_hw_support/port/esp32c2/chip_info.c index cfedff172d..4ef87c5de7 100644 --- a/components/esp_hw_support/port/esp32c2/chip_info.c +++ b/components/esp_hw_support/port/esp32c2/chip_info.c @@ -6,13 +6,13 @@ #include #include "esp_chip_info.h" -#include "esp_efuse.h" +#include "hal/efuse_hal.h" void esp_chip_info(esp_chip_info_t *out_info) { memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32C2; - out_info->revision = esp_efuse_get_chip_ver(); + out_info->revision = efuse_hal_get_chip_revision(); out_info->cores = 1; out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE; } diff --git a/components/esp_hw_support/port/esp32c3/chip_info.c b/components/esp_hw_support/port/esp32c3/chip_info.c index bb178b47fa..b0e2506c53 100644 --- a/components/esp_hw_support/port/esp32c3/chip_info.c +++ b/components/esp_hw_support/port/esp32c3/chip_info.c @@ -6,13 +6,13 @@ #include #include "esp_chip_info.h" -#include "esp_efuse.h" +#include "hal/efuse_hal.h" void esp_chip_info(esp_chip_info_t *out_info) { memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32C3; - out_info->revision = esp_efuse_get_chip_ver(); + out_info->revision = efuse_hal_get_chip_revision(); out_info->cores = 1; out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE; } diff --git a/components/esp_hw_support/port/esp32h2/chip_info.c b/components/esp_hw_support/port/esp32h2/chip_info.c index 9d1105b599..ae81b5f265 100644 --- a/components/esp_hw_support/port/esp32h2/chip_info.c +++ b/components/esp_hw_support/port/esp32h2/chip_info.c @@ -6,13 +6,13 @@ #include #include "esp_chip_info.h" -#include "esp_efuse.h" +#include "hal/efuse_hal.h" void esp_chip_info(esp_chip_info_t *out_info) { memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32H2; - out_info->revision = esp_efuse_get_chip_ver(); + out_info->revision = efuse_hal_get_chip_revision(); out_info->cores = 1; out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE; } diff --git a/components/esp_hw_support/port/esp32s2/chip_info.c b/components/esp_hw_support/port/esp32s2/chip_info.c index d03c16cb6d..63231f53c4 100644 --- a/components/esp_hw_support/port/esp32s2/chip_info.c +++ b/components/esp_hw_support/port/esp32s2/chip_info.c @@ -6,11 +6,11 @@ #include #include "esp_chip_info.h" -#include "esp_efuse.h" +#include "hal/efuse_ll.h" void esp_chip_info(esp_chip_info_t *out_info) { - uint32_t pkg_ver = esp_efuse_get_pkg_ver(); + uint32_t pkg_ver = efuse_ll_get_chip_ver_pkg(); memset(out_info, 0, sizeof(*out_info)); diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c index b3fd093726..ae1c2949d6 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_init.c @@ -182,18 +182,12 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void) result.force = 0; } #if 0 // ToDo: re-enable the commented codes - uint32_t efuse_reg = REG_READ(EFUSE_RD_REPEAT_DATA1_REG); - if (efuse_reg & EFUSE_SDIO_FORCE) { - // Get configuration from EFUSE - result.enable = (efuse_reg & EFUSE_SDIO_XPD_M) >> EFUSE_SDIO_XPD_S; - result.tieh = (efuse_reg & EFUSE_SDIO_TIEH_M) >> EFUSE_SDIO_TIEH_S; - - result.drefm = (efuse_reg & EFUSE_SDIO_DREFM_M) >> EFUSE_SDIO_DREFM_S; - result.drefl = (efuse_reg & EFUSE_SDIO_DREFL_M) >> EFUSE_SDIO_DREFL_S; - - efuse_reg = REG_READ(EFUSE_RD_REPEAT_DATA0_REG); - result.drefh = (efuse_reg & EFUSE_SDIO_DREFH_M) >> EFUSE_SDIO_DREFH_S; - + if (efuse_ll_get_sdio_force()) { + result.enable = efuse_ll_get_sdio_xpd(); + result.tieh = efuse_ll_get_sdio_tieh(); + result.drefm = efuse_ll_get_sdio_drefm(); + result.drefl = efuse_ll_get_sdio_drefl(); + result.drefh = efuse_ll_get_sdio_drefh(); return result; } #endif diff --git a/components/esp_hw_support/port/esp32s2/rtc_wdt.c b/components/esp_hw_support/port/esp32s2/rtc_wdt.c index 10110275a5..5ef9ad6ddd 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_wdt.c +++ b/components/esp_hw_support/port/esp32s2/rtc_wdt.c @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "soc/rtc_wdt.h" #include "soc/rtc.h" -#include "soc/efuse_periph.h" +#include "hal/efuse_ll.h" bool rtc_wdt_get_protect_status(void) @@ -88,7 +88,7 @@ esp_err_t rtc_wdt_set_time(rtc_wdt_stage_t stage, unsigned int timeout_ms) } uint32_t timeout = (uint32_t) ((uint64_t) rtc_clk_slow_freq_get_hz() * timeout_ms / 1000); if (stage == RTC_WDT_STAGE0) { - timeout = timeout >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + timeout = timeout >> (1 + efuse_ll_get_wdt_delay_sel()); } WRITE_PERI_REG(get_addr_reg(stage), timeout); return ESP_OK; diff --git a/components/esp_rom/esp32s2/usb_descriptors.c b/components/esp_rom/esp32s2/usb_descriptors.c index a1098d11c4..cae0abdd9e 100644 --- a/components/esp_rom/esp32s2/usb_descriptors.c +++ b/components/esp_rom/esp32s2/usb_descriptors.c @@ -1,21 +1,13 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include #include "esp32s2/rom/usb/usb_common.h" #include "soc/soc.h" -#include "soc/efuse_reg.h" +#include "hal/efuse_hal.h" /* USB CDC descriptor. * Note that we aren't using the one in ROM since it doesn't @@ -54,13 +46,8 @@ static inline uint16_t nibble_to_hex_u16(uint8_t b) void rom_usb_cdc_set_descriptor_patch(void) { - /* Get the MAC address */ - const uint32_t mac0 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_MAC_0); - const uint32_t mac1 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_1_REG, EFUSE_MAC_1); uint8_t mac_bytes[6]; - memcpy(mac_bytes, &mac0, 4); - memcpy(mac_bytes + 4, &mac1, 2); - + efuse_hal_get_mac(mac_bytes); /* Convert to UTF16 string */ uint16_t* dst = s_str_serial_descr.bString; for (int i = 0; i < 6; ++i) { diff --git a/components/esp_rom/include/esp32c2/rom/efuse.h b/components/esp_rom/include/esp32c2/rom/efuse.h index d80d41a91e..c69ea0bc24 100644 --- a/components/esp_rom/include/esp32c2/rom/efuse.h +++ b/components/esp_rom/include/esp32c2/rom/efuse.h @@ -32,13 +32,9 @@ typedef enum { typedef enum { ETS_EFUSE_BLOCK0 = 0, - ETS_EFUSE_MAC_SPI_SYS_0 = 1, - ETS_EFUSE_BLOCK_SYS_DATA = 2, - ETS_EFUSE_BLOCK_USR_DATA = 3, - ETS_EFUSE_BLOCK_KEY0 = 4, - ETS_EFUSE_BLOCK_KEY1 = 5, - ETS_EFUSE_BLOCK_KEY2 = 6, - ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_SYS_DATA1 = 1, + ETS_EFUSE_BLOCK_SYS_DATA2 = 2, + ETS_EFUSE_BLOCK_KEY0 = 3, ETS_EFUSE_BLOCK_MAX, } ets_efuse_block_t; diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 23b68d5785..f3b3ae38c8 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -72,7 +72,7 @@ #include "hal/gpio_hal.h" #include "hal/wdt_hal.h" #include "soc/rtc.h" -#include "soc/efuse_reg.h" +#include "hal/efuse_ll.h" #include "soc/periph_defs.h" #include "esp_cpu.h" #include "soc/rtc.h" @@ -363,7 +363,7 @@ void IRAM_ATTR call_start_cpu0(void) #endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 #if CONFIG_ESPTOOLPY_OCT_FLASH - bool efuse_opflash_en = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA3_REG, EFUSE_FLASH_TYPE); + bool efuse_opflash_en = efuse_ll_get_flash_type(); if (!efuse_opflash_en) { ESP_EARLY_LOGE(TAG, "Octal Flash option selected, but EFUSE not configured!"); abort(); diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index a8eeedf9a3..95fb28a874 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -2,7 +2,9 @@ idf_build_get_property(target IDF_TARGET) set(srcs "wdt_hal_iram.c" "mpu_hal.c" - "cpu_hal.c") + "cpu_hal.c" + "efuse_hal.c" + "${target}/efuse_hal.c") set(includes "${target}/include" "include" "platform_port/include") @@ -158,7 +160,7 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} PRIV_INCLUDE_DIRS ${priv_include} - REQUIRES soc + REQUIRES soc esp_rom PRIV_REQUIRES ${target} LDFRAGMENTS linker.lf) diff --git a/components/hal/efuse_hal.c b/components/hal/efuse_hal.c new file mode 100644 index 0000000000..85fecc7f0c --- /dev/null +++ b/components/hal/efuse_hal.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" + + +void efuse_hal_get_mac(uint8_t *mac) +{ + *((uint32_t*)&mac[0]) = efuse_ll_get_mac0(); + *((uint16_t*)&mac[4]) = (uint16_t) efuse_ll_get_mac1(); +} diff --git a/components/hal/esp32/efuse_hal.c b/components/hal/esp32/efuse_hal.c new file mode 100644 index 0000000000..9a6ed6ab46 --- /dev/null +++ b/components/hal/esp32/efuse_hal.c @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "soc/syscon_reg.h" + + +uint32_t efuse_hal_get_chip_revision(void) +{ + uint8_t eco_bit0 = efuse_ll_get_chip_ver_rev1(); + uint8_t eco_bit1 = efuse_ll_get_chip_ver_rev2(); + uint8_t eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31; + uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; + uint32_t chip_ver = 0; + switch (combine_value) { + case 0: + chip_ver = 0; + break; + case 1: + chip_ver = 1; + break; + case 3: + chip_ver = 2; + break; +#if CONFIG_IDF_ENV_FPGA + case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */ + chip_ver = 3; + break; +#endif // CONFIG_IDF_ENV_FPGA + case 7: + chip_ver = 3; + break; + default: + chip_ver = 0; + break; + } + return chip_ver; +} + +uint32_t efuse_hal_get_rated_freq_mhz(void) +{ + //Check if ESP32 is rated for a CPU frequency of 160MHz only + if (efuse_ll_get_chip_cpu_freq_rated() && efuse_ll_get_chip_cpu_freq_low()) { + return 160; + } + return 240; +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_mhz) +{ + uint32_t clk_sel0; + uint32_t clk_sel1; + uint32_t dac_clk_div; + if (apb_freq_mhz <= 26) { + clk_sel0 = 250; + clk_sel1 = 255; + dac_clk_div = 52; + } else if (apb_freq_mhz <= 40) { + clk_sel0 = 160; + clk_sel1 = 255; + dac_clk_div = 80; + } else { + clk_sel0 = 80; + clk_sel1 = 128; + dac_clk_div = 100; + } + efuse_ll_set_dac_clk_div(dac_clk_div); + efuse_ll_set_dac_clk_sel0(clk_sel0); + efuse_ll_set_dac_clk_sel1(clk_sel1); +} + +void efuse_hal_read(void) +{ + efuse_ll_set_conf_read_op_code(); + efuse_ll_set_read_cmd(); + while (efuse_ll_get_cmd() != 0) { }; +} + +void efuse_hal_clear_program_registers(void) +{ + efuse_ll_set_conf_read_op_code(); +} + +void efuse_hal_program(uint32_t block) +{ + (void) block; + // Permanently update values written to the efuse write registers + efuse_ll_set_conf_write_op_code(); + efuse_ll_set_pgm_cmd(); + while (efuse_ll_get_cmd() != 0) { }; + + efuse_hal_read(); +} + +/******************* eFuse control functions *************************/ diff --git a/components/hal/esp32/include/hal/efuse_hal.h b/components/hal/esp32/include/hal/efuse_hal.h new file mode 100644 index 0000000000..021f510c5f --- /dev/null +++ b/components/hal/esp32/include/hal/efuse_hal.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief get rated frequency in MHz + */ +uint32_t efuse_hal_get_rated_freq_mhz(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_mhz APB frequency in MHz + */ +void efuse_hal_set_timing(uint32_t apb_freq_mhz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (all blocks at once) + * + * @param block not used + */ +void efuse_hal_program(uint32_t block); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32/include/hal/efuse_ll.h b/components/hal/esp32/include/hal/efuse_ll.h new file mode 100644 index 0000000000..7aa7adcd21 --- /dev/null +++ b/components/hal/esp32/include/hal/efuse_ll.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return REG_READ(EFUSE_BLK0_RDATA1_REG); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA2_REG, EFUSE_RD_WIFI_MAC_CRC_HIGH) & 0x0000FFFF; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v1_en(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_0); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_1); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_FORCE); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_xpd_sdio(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_XPD_SDIO_REG); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_TIEH); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFH); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFM); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFL); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_blk3_part_reserve(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_rated(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_low(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); + uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT); + return (pkg_version_4bit << 3) | pkg_version; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev1(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev2(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_coding_scheme(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_app_cpu(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_bt(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_BT); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_vol_level_hp_inv(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc_vref(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_ADC_VREF); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_low(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_LOW); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_low(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_LOW); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_high(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_HIGH); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_high(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_HIGH); +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_cmd(void) +{ + return REG_READ(EFUSE_CMD_REG); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(void) +{ + REG_WRITE(EFUSE_CMD_REG, EFUSE_PGM_CMD); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint32_t value) +{ + REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, value); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel0(uint32_t value) +{ + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, value); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value) +{ + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, value); +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c2/efuse_hal.c b/components/hal/esp32c2/efuse_hal.c new file mode 100644 index 0000000000..e805cd29ef --- /dev/null +++ b/components/hal/esp32c2/efuse_hal.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" + + +uint32_t efuse_hal_get_chip_revision(void) +{ + return efuse_ll_get_chip_revision(); +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_hz) +{ + (void) apb_freq_hz; + efuse_ll_set_pwr_off_num(0x190); +} + +void efuse_hal_read(void) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_read_op_code(); + efuse_ll_set_read_cmd(); + + while (efuse_ll_get_read_cmd() != 0) { } + /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ + while (efuse_ll_get_read_cmd() != 0) { } +} + +void efuse_hal_clear_program_registers(void) +{ + ets_efuse_clear_program_registers(); +} + +void efuse_hal_program(uint32_t block) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_write_op_code(); + efuse_ll_set_pgm_cmd(block); + + while (efuse_ll_get_pgm_cmd() != 0) { } + + efuse_hal_clear_program_registers(); + efuse_hal_read(); +} + +void efuse_hal_rs_calculate(const void *data, void *rs_values) +{ + ets_efuse_rs_calculate(data, rs_values); +} + +/******************* eFuse control functions *************************/ diff --git a/components/hal/esp32c2/include/hal/efuse_hal.h b/components/hal/esp32c2/include/hal/efuse_hal.h new file mode 100644 index 0000000000..a6aaae0a18 --- /dev/null +++ b/components/hal/esp32c2/include/hal/efuse_hal.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +void efuse_hal_set_timing(uint32_t apb_freq_hz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +void efuse_hal_program(uint32_t block); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void efuse_hal_rs_calculate(const void *data, void *rs_values); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c2/include/hal/efuse_ll.h b/components/hal/esp32c2/include/hal/efuse_ll.h new file mode 100644 index 0000000000..cdf2c1472a --- /dev/null +++ b/components/hal/esp32c2/include/hal/efuse_ll.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32c2/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data0.spi_boot_encrypt_decrypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data0.wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_blk2_data0.blk2_data0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_blk2_data1.mac_id_high; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data0.secure_boot_en; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void) +{ + return EFUSE.rd_blk2_data1.wafer_version; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return EFUSE.rd_blk2_data1.pkg_version; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c2/include/hal/rwdt_ll.h b/components/hal/esp32c2/include/hal/rwdt_ll.h index daa870d80c..e7823be3f6 100644 --- a/components/hal/esp32c2/include/hal/rwdt_ll.h +++ b/components/hal/esp32c2/include/hal/rwdt_ll.h @@ -17,7 +17,7 @@ extern "C" { #include #include "hal/wdt_types.h" #include "soc/rtc_cntl_periph.h" -#include "soc/efuse_reg.h" +#include "hal/efuse_ll.h" #include "esp_attr.h" //Type check wdt_stage_action_t @@ -94,7 +94,7 @@ FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stag case WDT_STAGE0: hw->wdt_config0.stg0 = behavior; //Account of implicty multiplier applied to stage 0 timeout tick config value - hw->wdt_config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG, EFUSE_WDT_DELAY_SEL)); + hw->wdt_config1 = timeout_ticks >> (1 + efuse_ll_get_wdt_delay_sel()); break; case WDT_STAGE1: hw->wdt_config0.stg1 = behavior; diff --git a/components/hal/esp32c3/efuse_hal.c b/components/hal/esp32c3/efuse_hal.c new file mode 100644 index 0000000000..e805cd29ef --- /dev/null +++ b/components/hal/esp32c3/efuse_hal.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" + + +uint32_t efuse_hal_get_chip_revision(void) +{ + return efuse_ll_get_chip_revision(); +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_hz) +{ + (void) apb_freq_hz; + efuse_ll_set_pwr_off_num(0x190); +} + +void efuse_hal_read(void) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_read_op_code(); + efuse_ll_set_read_cmd(); + + while (efuse_ll_get_read_cmd() != 0) { } + /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ + while (efuse_ll_get_read_cmd() != 0) { } +} + +void efuse_hal_clear_program_registers(void) +{ + ets_efuse_clear_program_registers(); +} + +void efuse_hal_program(uint32_t block) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_write_op_code(); + efuse_ll_set_pgm_cmd(block); + + while (efuse_ll_get_pgm_cmd() != 0) { } + + efuse_hal_clear_program_registers(); + efuse_hal_read(); +} + +void efuse_hal_rs_calculate(const void *data, void *rs_values) +{ + ets_efuse_rs_calculate(data, rs_values); +} + +/******************* eFuse control functions *************************/ diff --git a/components/hal/esp32c3/include/hal/efuse_hal.h b/components/hal/esp32c3/include/hal/efuse_hal.h new file mode 100644 index 0000000000..a6aaae0a18 --- /dev/null +++ b/components/hal/esp32c3/include/hal/efuse_hal.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +void efuse_hal_set_timing(uint32_t apb_freq_hz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +void efuse_hal_program(uint32_t block); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void efuse_hal_rs_calculate(const void *data, void *rs_values); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c3/include/hal/efuse_ll.h b/components/hal/esp32c3/include/hal/efuse_ll.h new file mode 100644 index 0000000000..8070067323 --- /dev/null +++ b/components/hal/esp32c3/include/hal/efuse_ll.h @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32c3/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void) +{ + return EFUSE.rd_repeat_data3.flash_type; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_sys_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_sys_1.mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.secure_boot_en; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void) +{ + return EFUSE.rd_mac_spi_sys_3.wafer_version; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return EFUSE.rd_mac_spi_sys_3.pkg_version; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c3/include/hal/rwdt_ll.h b/components/hal/esp32c3/include/hal/rwdt_ll.h index 0986ce3dec..1e97b531e6 100644 --- a/components/hal/esp32c3/include/hal/rwdt_ll.h +++ b/components/hal/esp32c3/include/hal/rwdt_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ // The LL layer for Timer Group register operations. // Note that most of the register operations in this layer are non-atomic operations. @@ -27,7 +19,7 @@ extern "C" { #include "hal/wdt_types.h" #include "soc/rtc_cntl_periph.h" #include "soc/rtc_cntl_struct.h" -#include "soc/efuse_reg.h" +#include "hal/efuse_ll.h" #include "esp_attr.h" //Type check wdt_stage_action_t @@ -104,7 +96,7 @@ FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stag case WDT_STAGE0: hw->wdt_config0.stg0 = behavior; //Account of implicty multiplier applied to stage 0 timeout tick config value - hw->wdt_config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + hw->wdt_config1 = timeout_ticks >> (1 + efuse_ll_get_wdt_delay_sel()); break; case WDT_STAGE1: hw->wdt_config0.stg1 = behavior; diff --git a/components/hal/esp32h2/efuse_hal.c b/components/hal/esp32h2/efuse_hal.c new file mode 100644 index 0000000000..e805cd29ef --- /dev/null +++ b/components/hal/esp32h2/efuse_hal.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" + + +uint32_t efuse_hal_get_chip_revision(void) +{ + return efuse_ll_get_chip_revision(); +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_hz) +{ + (void) apb_freq_hz; + efuse_ll_set_pwr_off_num(0x190); +} + +void efuse_hal_read(void) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_read_op_code(); + efuse_ll_set_read_cmd(); + + while (efuse_ll_get_read_cmd() != 0) { } + /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ + while (efuse_ll_get_read_cmd() != 0) { } +} + +void efuse_hal_clear_program_registers(void) +{ + ets_efuse_clear_program_registers(); +} + +void efuse_hal_program(uint32_t block) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_write_op_code(); + efuse_ll_set_pgm_cmd(block); + + while (efuse_ll_get_pgm_cmd() != 0) { } + + efuse_hal_clear_program_registers(); + efuse_hal_read(); +} + +void efuse_hal_rs_calculate(const void *data, void *rs_values) +{ + ets_efuse_rs_calculate(data, rs_values); +} + +/******************* eFuse control functions *************************/ diff --git a/components/hal/esp32h2/include/hal/efuse_hal.h b/components/hal/esp32h2/include/hal/efuse_hal.h new file mode 100644 index 0000000000..a6aaae0a18 --- /dev/null +++ b/components/hal/esp32h2/include/hal/efuse_hal.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +void efuse_hal_set_timing(uint32_t apb_freq_hz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +void efuse_hal_program(uint32_t block); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void efuse_hal_rs_calculate(const void *data, void *rs_values); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/efuse_ll.h b/components/hal/esp32h2/include/hal/efuse_ll.h new file mode 100644 index 0000000000..8070067323 --- /dev/null +++ b/components/hal/esp32h2/include/hal/efuse_ll.h @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32c3/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void) +{ + return EFUSE.rd_repeat_data3.flash_type; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_sys_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_sys_1.mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.secure_boot_en; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void) +{ + return EFUSE.rd_mac_spi_sys_3.wafer_version; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return EFUSE.rd_mac_spi_sys_3.pkg_version; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/rwdt_ll.h b/components/hal/esp32h2/include/hal/rwdt_ll.h index 92a17786fe..9cf8fac81a 100644 --- a/components/hal/esp32h2/include/hal/rwdt_ll.h +++ b/components/hal/esp32h2/include/hal/rwdt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,7 +16,7 @@ extern "C" { #include "hal/wdt_types.h" #include "soc/rtc_cntl_periph.h" #include "soc/rtc_cntl_struct.h" -#include "soc/efuse_reg.h" +#include "hal/efuse_ll.h" #include "esp_attr.h" //Type check wdt_stage_action_t @@ -93,7 +93,7 @@ FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stag case WDT_STAGE0: hw->wdt_config0.stg0 = behavior; //Account of implicty multiplier applied to stage 0 timeout tick config value - hw->wdt_config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + hw->wdt_config1 = timeout_ticks >> (1 + efuse_ll_get_wdt_delay_sel()); break; case WDT_STAGE1: hw->wdt_config0.stg1 = behavior; diff --git a/components/hal/esp32s2/efuse_hal.c b/components/hal/esp32s2/efuse_hal.c new file mode 100644 index 0000000000..eb39fff684 --- /dev/null +++ b/components/hal/esp32s2/efuse_hal.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" +#include "esp32s2/rom/efuse.h" + + +uint32_t efuse_hal_get_chip_revision(void) +{ + return efuse_ll_get_chip_revision(); +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_hz) +{ + ets_efuse_set_timing(apb_freq_hz); +} + +void efuse_hal_read(void) +{ + ets_efuse_read(); +} + +void efuse_hal_clear_program_registers(void) +{ + ets_efuse_clear_program_registers(); +} + +void efuse_hal_program(uint32_t block) +{ + ets_efuse_program(block); +} + +void efuse_hal_rs_calculate(const void *data, void *rs_values) +{ + ets_efuse_rs_calculate(data, rs_values); +} + +/******************* eFuse control functions *************************/ diff --git a/components/hal/esp32s2/include/hal/efuse_hal.h b/components/hal/esp32s2/include/hal/efuse_hal.h new file mode 100644 index 0000000000..d6b09949ee --- /dev/null +++ b/components/hal/esp32s2/include/hal/efuse_hal.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +void efuse_hal_set_timing(uint32_t apb_freq_hz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +void efuse_hal_program(uint32_t block); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void efuse_hal_rs_calculate(const void *data, void *rs_values); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s2/include/hal/efuse_ll.h b/components/hal/esp32s2/include/hal/efuse_ll.h new file mode 100644 index 0000000000..78e5ae5069 --- /dev/null +++ b/components/hal/esp32s2/include/hal/efuse_ll.h @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32s2/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_8m_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_8m_1.mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.secure_boot_en; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void) +{ + return EFUSE.rd_mac_spi_8m_3.wafer_version; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return EFUSE.rd_mac_spi_8m_4.pkg_version; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) +{ + return EFUSE.rd_repeat_data1.sdio_force; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) +{ + return EFUSE.rd_repeat_data1.sdio_tieh; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_xpd(void) +{ + return EFUSE.rd_repeat_data1.sdio_xpd; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) +{ + return EFUSE.rd_repeat_data1.sdio_drefl; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) +{ + return EFUSE.rd_repeat_data1.sdio_drefm; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) +{ + return EFUSE.rd_repeat_data0.sdio_drefh; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s2/include/hal/rwdt_ll.h b/components/hal/esp32s2/include/hal/rwdt_ll.h index f3cc3c0cc4..8d6d5841be 100644 --- a/components/hal/esp32s2/include/hal/rwdt_ll.h +++ b/components/hal/esp32s2/include/hal/rwdt_ll.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ // The LL layer for Timer Group register operations. // Note that most of the register operations in this layer are non-atomic operations. @@ -27,7 +19,7 @@ extern "C" { #include "hal/wdt_types.h" #include "soc/rtc_cntl_periph.h" #include "soc/rtc_cntl_struct.h" -#include "soc/efuse_reg.h" +#include "hal/efuse_ll.h" #include "esp_attr.h" //Type check wdt_stage_action_t @@ -104,7 +96,7 @@ FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stag case WDT_STAGE0: hw->wdt_config0.stg0 = behavior; //Account of implicty multiplier applied to stage 0 timeout tick config value - hw->wdt_config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + hw->wdt_config1 = timeout_ticks >> (1 + efuse_ll_get_wdt_delay_sel()); break; case WDT_STAGE1: hw->wdt_config0.stg1 = behavior; diff --git a/components/hal/esp32s3/efuse_hal.c b/components/hal/esp32s3/efuse_hal.c new file mode 100644 index 0000000000..5bda5261e0 --- /dev/null +++ b/components/hal/esp32s3/efuse_hal.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" +#include "esp32s3/rom/efuse.h" + +uint32_t efuse_hal_get_chip_revision(void) +{ + return efuse_ll_get_chip_revision(); +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_hz) +{ + (void) apb_freq_hz; + efuse_ll_set_pwr_off_num(0x190); +} + +void efuse_hal_read(void) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_read_op_code(); + efuse_ll_set_read_cmd(); + + while (efuse_ll_get_read_cmd() != 0) { } + /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ + while (efuse_ll_get_read_cmd() != 0) { } +} + +void efuse_hal_clear_program_registers(void) +{ + ets_efuse_clear_program_registers(); +} + +void efuse_hal_program(uint32_t block) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_write_op_code(); + efuse_ll_set_pgm_cmd(block); + + while (efuse_ll_get_pgm_cmd() != 0) { } + + efuse_hal_clear_program_registers(); + efuse_hal_read(); +} + +void efuse_hal_rs_calculate(const void *data, void *rs_values) +{ + ets_efuse_rs_calculate(data, rs_values); +} + +/******************* eFuse control functions *************************/ diff --git a/components/hal/esp32s3/include/hal/efuse_hal.h b/components/hal/esp32s3/include/hal/efuse_hal.h new file mode 100644 index 0000000000..a6aaae0a18 --- /dev/null +++ b/components/hal/esp32s3/include/hal/efuse_hal.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +void efuse_hal_set_timing(uint32_t apb_freq_hz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +void efuse_hal_program(uint32_t block); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void efuse_hal_rs_calculate(const void *data, void *rs_values); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s3/include/hal/efuse_ll.h b/components/hal/esp32s3/include/hal/efuse_ll.h new file mode 100644 index 0000000000..bfe6888f66 --- /dev/null +++ b/components/hal/esp32s3/include/hal/efuse_ll.h @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32s3/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.reg_wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void) +{ + return EFUSE.rd_repeat_data3.reg_flash_type; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_sys_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_sys_1.reg_mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.reg_secure_boot_en; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void) +{ + return 0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return 0; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/efuse_hal.h b/components/hal/include/hal/efuse_hal.h new file mode 100644 index 0000000000..4a0a155782 --- /dev/null +++ b/components/hal/include/hal/efuse_hal.h @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get factory mac address + */ +void efuse_hal_get_mac(uint8_t *mac); + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/efuse_reg.h b/components/soc/esp32/include/soc/efuse_reg.h index 77e3b8db96..58791d93e9 100644 --- a/components/soc/esp32/include/soc/efuse_reg.h +++ b/components/soc/esp32/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -216,12 +216,11 @@ #define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) #define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 #define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 -/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ -/* Deprecated */ -#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/ -#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/ -#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/ -#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/ +/* EFUSE_RD_CHIP_VER_REV2 : RO ;bitpos:[20] ;default: 8'b0 ; */ +#define EFUSE_RD_CHIP_VER_REV2 0x00000001 +#define EFUSE_RD_CHIP_VER_REV2_M ((EFUSE_RD_CHIP_VER_REV2_V)<<(EFUSE_RD_CHIP_VER_REV2_S)) +#define EFUSE_RD_CHIP_VER_REV2_V 0x1 +#define EFUSE_RD_CHIP_VER_REV2_S 20 /* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ /*description: read for SPI_pad_config_cs0*/ #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F @@ -1054,6 +1053,9 @@ #define EFUSE_CLK_SEL0_V 0xFF #define EFUSE_CLK_SEL0_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) /* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ /*description: */ diff --git a/components/soc/esp32/include/soc/efuse_struct.h b/components/soc/esp32/include/soc/efuse_struct.h new file mode 100644 index 0000000000..246572e40f --- /dev/null +++ b/components/soc/esp32/include/soc/efuse_struct.h @@ -0,0 +1,106 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_EFUSE_STRUCT_H_ +#define _SOC_EFUSE_STRUCT_H_ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct efuse_dev_s { + uint32_t blk0_rdata0; + uint32_t blk0_rdata1; + uint32_t blk0_rdata2; + uint32_t blk0_rdata3; + uint32_t blk0_rdata4; + uint32_t blk0_rdata5; + uint32_t blk0_rdata6; + + uint32_t blk0_wdata0; + uint32_t blk0_wdata1; + uint32_t blk0_wdata2; + uint32_t blk0_wdata3; + uint32_t blk0_wdata4; + uint32_t blk0_wdata5; + uint32_t blk0_wdata6; + + uint32_t blk1_rdata0; + uint32_t blk1_rdata1; + uint32_t blk1_rdata2; + uint32_t blk1_rdata3; + uint32_t blk1_rdata4; + uint32_t blk1_rdata5; + uint32_t blk1_rdata6; + uint32_t blk1_rdata7; + + uint32_t blk2_rdata0; + uint32_t blk2_rdata1; + uint32_t blk2_rdata2; + uint32_t blk2_rdata3; + uint32_t blk2_rdata4; + uint32_t blk2_rdata5; + uint32_t blk2_rdata6; + uint32_t blk2_rdata7; + + uint32_t blk3_rdata0; + uint32_t blk3_rdata1; + uint32_t blk3_rdata2; + uint32_t blk3_rdata3; + uint32_t blk3_rdata4; + uint32_t blk3_rdata5; + uint32_t blk3_rdata6; + uint32_t blk3_rdata7; + + uint32_t blk1_wdata0; + uint32_t blk1_wdata1; + uint32_t blk1_wdata2; + uint32_t blk1_wdata3; + uint32_t blk1_wdata4; + uint32_t blk1_wdata5; + uint32_t blk1_wdata6; + uint32_t blk1_wdata7; + + uint32_t blk2_wdata0; + uint32_t blk2_wdata1; + uint32_t blk2_wdata2; + uint32_t blk2_wdata3; + uint32_t blk2_wdata4; + uint32_t blk2_wdata5; + uint32_t blk2_wdata6; + uint32_t blk2_wdata7; + + uint32_t blk3_wdata0; + uint32_t blk3_wdata1; + uint32_t blk3_wdata2; + uint32_t blk3_wdata3; + uint32_t blk3_wdata4; + uint32_t blk3_wdata5; + uint32_t blk3_wdata6; + uint32_t blk3_wdata7; + + uint32_t clk; + uint32_t conf; + uint32_t status; + uint32_t cmd; + uint32_t int_raw; + uint32_t int_st; + uint32_t int_ena; + uint32_t int_clr; + uint32_t dac_conf; + uint32_t dec_status; + uint32_t reserve[55]; + uint32_t date; +} efuse_dev_t; + +extern efuse_dev_t EFUSE; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_EFUSE_STRUCT_H_ */ diff --git a/components/soc/esp32/ld/esp32.peripherals.ld b/components/soc/esp32/ld/esp32.peripherals.ld index e9154e764f..3d6a401748 100644 --- a/components/soc/esp32/ld/esp32.peripherals.ld +++ b/components/soc/esp32/ld/esp32.peripherals.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,6 +23,7 @@ PROVIDE ( RMTMEM = 0x3ff56800 ); PROVIDE ( PCNT = 0x3ff57000 ); PROVIDE ( SLC = 0x3ff58000 ); PROVIDE ( LEDC = 0x3ff59000 ); +PROVIDE ( EFUSE = 0x3ff5A000 ); PROVIDE ( MCPWM0 = 0x3ff5E000 ); PROVIDE ( TIMERG0 = 0x3ff5F000 ); PROVIDE ( TIMERG1 = 0x3ff60000 ); diff --git a/components/soc/esp32c2/include/soc/efuse_reg.h b/components/soc/esp32c2/include/soc/efuse_reg.h index 82de857ff5..ef8373fd8e 100644 --- a/components/soc/esp32c2/include/soc/efuse_reg.h +++ b/components/soc/esp32c2/include/soc/efuse_reg.h @@ -749,6 +749,9 @@ extern "C" { #define EFUSE_CLK_EN_V 0x00000001U #define EFUSE_CLK_EN_S 16 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + /** EFUSE_CONF_REG register * eFuse operation mode configuraiton register */ diff --git a/components/soc/esp32c2/include/soc/efuse_struct.h b/components/soc/esp32c2/include/soc/efuse_struct.h index 7fc768f6f7..ac73904247 100644 --- a/components/soc/esp32c2/include/soc/efuse_struct.h +++ b/components/soc/esp32c2/include/soc/efuse_struct.h @@ -992,6 +992,7 @@ typedef struct { volatile efuse_date_reg_t date; } efuse_dev_t; +extern efuse_dev_t EFUSE; #ifndef __cplusplus _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); diff --git a/components/soc/esp32c2/ld/esp32c2.peripherals.ld b/components/soc/esp32c2/ld/esp32c2.peripherals.ld index 374ee5f5d6..6f34ae6237 100644 --- a/components/soc/esp32c2/ld/esp32c2.peripherals.ld +++ b/components/soc/esp32c2/ld/esp32c2.peripherals.ld @@ -11,6 +11,7 @@ PROVIDE ( GPIO = 0x60004000 ); PROVIDE ( SIGMADELTA = 0x60004f00 ); PROVIDE ( RTCCNTL = 0x60008000 ); PROVIDE ( RTCIO = 0x60008400 ); +PROVIDE ( EFUSE = 0x60008800 ); PROVIDE ( HINF = 0x6000B000 ); PROVIDE ( I2C0 = 0x60013000 ); PROVIDE ( HOST = 0x60015000 ); diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/include/soc/efuse_reg.h index c2664a15d3..6ad90ea671 100644 --- a/components/soc/esp32c3/include/soc/efuse_reg.h +++ b/components/soc/esp32c3/include/soc/efuse_reg.h @@ -1851,6 +1851,9 @@ extern "C" { #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h index 24915ba810..9d4692a465 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/include/soc/efuse_struct.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_EFUSE_STRUCT_H_ #define _SOC_EFUSE_STRUCT_H_ #ifdef __cplusplus @@ -193,7 +185,9 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t sys_data_part0_0:14; /*Stores the fist 14 bits of the zeroth part of system data.*/ + uint32_t wafer_version: 3; + uint32_t pkg_version: 3; + uint32_t sys_data_part0_0: 8; /*Stores the fist 14 bits of the zeroth part of system data.*/ }; uint32_t val; } rd_mac_spi_sys_3; diff --git a/components/soc/esp32c3/ld/esp32c3.peripherals.ld b/components/soc/esp32c3/ld/esp32c3.peripherals.ld index 710ae9aeea..5366b062d0 100644 --- a/components/soc/esp32c3/ld/esp32c3.peripherals.ld +++ b/components/soc/esp32c3/ld/esp32c3.peripherals.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ PROVIDE ( UART0 = 0x60000000 ); PROVIDE ( UART1 = 0x60010000 ); PROVIDE ( SPIMEM1 = 0x60002000 ); @@ -6,6 +11,7 @@ PROVIDE ( GPIO = 0x60004000 ); PROVIDE ( SIGMADELTA = 0x60004f00 ); PROVIDE ( RTCCNTL = 0x60008000 ); PROVIDE ( RTCIO = 0x60008400 ); +PROVIDE ( EFUSE = 0x60008800 ); PROVIDE ( HINF = 0x6000B000 ); PROVIDE ( I2S0 = 0x6002d000 ); PROVIDE ( I2C0 = 0x60013000 ); diff --git a/components/soc/esp32h2/include/rev1/soc/efuse_reg.h b/components/soc/esp32h2/include/rev1/soc/efuse_reg.h index a2540c41fd..158e874421 100644 --- a/components/soc/esp32h2/include/rev1/soc/efuse_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/efuse_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1851,6 +1851,9 @@ extern "C" { #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ diff --git a/components/soc/esp32h2/include/rev1/soc/efuse_struct.h b/components/soc/esp32h2/include/rev1/soc/efuse_struct.h index 9365a46fa4..2c773ec00b 100644 --- a/components/soc/esp32h2/include/rev1/soc/efuse_struct.h +++ b/components/soc/esp32h2/include/rev1/soc/efuse_struct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -185,7 +185,9 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t sys_data_part0_0:14; /*Stores the fist 14 bits of the zeroth part of system data.*/ + uint32_t wafer_version: 3; + uint32_t pkg_version: 3; + uint32_t sys_data_part0_0: 8; /*Stores the fist 14 bits of the zeroth part of system data.*/ }; uint32_t val; } rd_mac_spi_sys_3; diff --git a/components/soc/esp32h2/include/rev2/soc/efuse_reg.h b/components/soc/esp32h2/include/rev2/soc/efuse_reg.h index 7a2226feb4..2a775d5fe0 100644 --- a/components/soc/esp32h2/include/rev2/soc/efuse_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -591,20 +591,30 @@ extern "C" { * BLOCK1 data register $n. */ #define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; - * Stores the second part of SPI_PAD_CONF. - */ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFFU -#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) -#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFFU +/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: Stores the fist 8 bits of the zeroth part of system data.*/ +#define EFUSE_SYS_DATA_PART0_0 0x000000FF +#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) +#define EFUSE_SYS_DATA_PART0_0_V 0xFF +#define EFUSE_SYS_DATA_PART0_0_S 25 +/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: Package version 0:ESP32-H2 */ +#define EFUSE_PKG_VERSION 0x00000007 +#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) +#define EFUSE_PKG_VERSION_V 0x7 +#define EFUSE_PKG_VERSION_S 21 +/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: WAFER version 0:A */ +#define EFUSE_WAFER_VERSION 0x00000007 +#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) +#define EFUSE_WAFER_VERSION_V 0x7 +#define EFUSE_WAFER_VERSION_S 18 +/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ +/*description: Stores the second part of SPI_PAD_CONF.*/ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) +#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF #define EFUSE_SPI_PAD_CONF_2_S 0 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the fist 14 bits of the zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 /** EFUSE_RD_MAC_SPI_SYS_4_REG register * BLOCK1 data register $n. @@ -2076,6 +2086,9 @@ extern "C" { #define EFUSE_CLK_EN_V 0x00000001U #define EFUSE_CLK_EN_S 16 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + /** EFUSE_CONF_REG register * eFuse operation mode configuraiton register */ diff --git a/components/soc/esp32h2/include/rev2/soc/efuse_struct.h b/components/soc/esp32h2/include/rev2/soc/efuse_struct.h index 5db82071d5..c9cac7f8a1 100644 --- a/components/soc/esp32h2/include/rev2/soc/efuse_struct.h +++ b/components/soc/esp32h2/include/rev2/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -475,10 +475,9 @@ typedef union { * Stores the second part of SPI_PAD_CONF. */ uint32_t spi_pad_conf_2:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the fist 14 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_0:14; + uint32_t wafer_version:3; + uint32_t pkg_version:3; + uint32_t sys_data_part0_0:8; }; uint32_t val; } efuse_rd_mac_spi_sys_3_reg_t; diff --git a/components/soc/esp32h2/ld/esp32h2.peripherals.ld b/components/soc/esp32h2/ld/esp32h2.peripherals.ld index ee3154ad43..098d285d01 100644 --- a/components/soc/esp32h2/ld/esp32h2.peripherals.ld +++ b/components/soc/esp32h2/ld/esp32h2.peripherals.ld @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ PROVIDE ( UART0 = 0x60000000 ); PROVIDE ( UART1 = 0x60010000 ); PROVIDE ( SPIMEM1 = 0x60002000 ); @@ -17,6 +22,7 @@ PROVIDE ( RMTMEM = 0x60016400 ); PROVIDE ( PCNT = 0x60017000 ); PROVIDE ( SLC = 0x60018000 ); PROVIDE ( LEDC = 0x60019000 ); +PROVIDE ( EFUSE = 0x6001A000 ); PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); PROVIDE ( SYSTIMER = 0x60023000 ); diff --git a/components/soc/esp32s2/include/soc/efuse_reg.h b/components/soc/esp32s2/include/soc/efuse_reg.h index f7be21c6ed..bb369fa740 100644 --- a/components/soc/esp32s2/include/soc/efuse_reg.h +++ b/components/soc/esp32s2/include/soc/efuse_reg.h @@ -1,16 +1,8 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_EFUSE_REG_H_ #define _SOC_EFUSE_REG_H_ @@ -2072,6 +2064,9 @@ extern "C" { #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: 0x5A5A: Operate programming command*/ diff --git a/components/soc/esp32s2/include/soc/efuse_struct.h b/components/soc/esp32s2/include/soc/efuse_struct.h index d2ef645494..f08712fce7 100644 --- a/components/soc/esp32s2/include/soc/efuse_struct.h +++ b/components/soc/esp32s2/include/soc/efuse_struct.h @@ -1,16 +1,8 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_EFUSE_STRUCT_H_ #define _SOC_EFUSE_STRUCT_H_ #ifdef __cplusplus @@ -206,8 +198,21 @@ typedef volatile struct efuse_dev_s { }; uint32_t val; } rd_mac_spi_8m_2; - uint32_t rd_mac_spi_8m_3; /**/ - uint32_t rd_mac_spi_8m_4; /**/ + union { + struct { + uint32_t spi_pad_conf_2: 18; + uint32_t wafer_version: 3; + uint32_t reserve: 11; + }; + uint32_t val; + } rd_mac_spi_8m_3; + union { + struct { + uint32_t pkg_version: 4; + uint32_t reserve: 28; + }; + uint32_t val; + } rd_mac_spi_8m_4; uint32_t rd_mac_spi_8m_5; /**/ uint32_t rd_sys_data0; /**/ uint32_t rd_sys_data1; /**/ diff --git a/components/soc/esp32s2/ld/esp32s2.peripherals.ld b/components/soc/esp32s2/ld/esp32s2.peripherals.ld index bd1d00c5b7..71edf058a8 100644 --- a/components/soc/esp32s2/ld/esp32s2.peripherals.ld +++ b/components/soc/esp32s2/ld/esp32s2.peripherals.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,6 +22,7 @@ PROVIDE ( RMTMEM = 0x3f416400 ); PROVIDE ( PCNT = 0x3f417000 ); PROVIDE ( SLC = 0x3f418000 ); PROVIDE ( LEDC = 0x3f419000 ); +PROVIDE ( EFUSE = 0x3f41A000 ); PROVIDE ( CP_DMA = 0x3f4c3000 ); PROVIDE ( TIMERG0 = 0x3f41F000 ); PROVIDE ( TIMERG1 = 0x3f420000 ); diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index b4d10f3f66..8cfde9a2c2 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -1732,6 +1732,9 @@ ing user data failed and the number of error bytes is over 6..*/ #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/ diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld index 27343e9dd9..90b06191d3 100644 --- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,7 @@ PROVIDE ( SPIMEM1 = 0x60002000 ); PROVIDE ( SPIMEM0 = 0x60003000 ); PROVIDE ( GPIO = 0x60004000 ); PROVIDE ( SIGMADELTA = 0x60004f00 ); +PROVIDE ( EFUSE = 0x60007000 ); PROVIDE ( RTCCNTL = 0x60008000 ); PROVIDE ( RTCIO = 0x60008400 ); PROVIDE ( SENS = 0x60008800 ); diff --git a/components/soc/include/soc/efuse_periph.h b/components/soc/include/soc/efuse_periph.h index 76a118e3b6..c386ecf2d9 100644 --- a/components/soc/include/soc/efuse_periph.h +++ b/components/soc/include/soc/efuse_periph.h @@ -1,16 +1,9 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include "soc/efuse_reg.h" +#include "soc/efuse_struct.h" diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index e95d15a877..b4ca804627 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1,14 +1,5 @@ components/bootloader/subproject/main/bootloader_hooks.h components/bootloader/subproject/main/bootloader_start.c -components/bootloader/subproject/main/ld/esp32/bootloader.ld -components/bootloader/subproject/main/ld/esp32/bootloader.rom.ld -components/bootloader/subproject/main/ld/esp32c3/bootloader.ld -components/bootloader/subproject/main/ld/esp32c3/bootloader.rom.ld -components/bootloader/subproject/main/ld/esp32h2/bootloader.ld -components/bootloader/subproject/main/ld/esp32s2/bootloader.ld -components/bootloader/subproject/main/ld/esp32s2/bootloader.rom.ld -components/bootloader/subproject/main/ld/esp32s3/bootloader.ld -components/bootloader/subproject/main/ld/esp32s3/bootloader.rom.ld components/bt/common/osi/alarm.c components/bt/common/osi/allocator.c components/bt/common/osi/buffer.c @@ -551,7 +542,6 @@ components/esp_rom/esp32s2/ld/esp32s2.rom.newlib-data.ld components/esp_rom/esp32s2/ld/esp32s2.rom.newlib-funcs.ld components/esp_rom/esp32s2/ld/esp32s2.rom.newlib-nano.ld components/esp_rom/esp32s2/ld/esp32s2.rom.spiflash.ld -components/esp_rom/esp32s2/usb_descriptors.c components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld components/esp_rom/esp32s3/ld/esp32s3.rom.ld components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld @@ -861,7 +851,6 @@ components/hal/esp32c3/include/hal/i2c_ll.h components/hal/esp32c3/include/hal/interrupt_controller_ll.h components/hal/esp32c3/include/hal/mpu_ll.h components/hal/esp32c3/include/hal/rtc_cntl_ll.h -components/hal/esp32c3/include/hal/rwdt_ll.h components/hal/esp32c3/include/hal/sha_ll.h components/hal/esp32c3/include/hal/sigmadelta_ll.h components/hal/esp32c3/include/hal/soc_ll.h @@ -919,7 +908,6 @@ components/hal/esp32s2/include/hal/mpu_ll.h components/hal/esp32s2/include/hal/pcnt_ll.h components/hal/esp32s2/include/hal/rtc_cntl_ll.h components/hal/esp32s2/include/hal/rtc_io_ll.h -components/hal/esp32s2/include/hal/rwdt_ll.h components/hal/esp32s2/include/hal/sha_ll.h components/hal/esp32s2/include/hal/sigmadelta_ll.h components/hal/esp32s2/include/hal/soc_ll.h @@ -1436,7 +1424,6 @@ components/soc/esp32c3/include/soc/bb_reg.h components/soc/esp32c3/include/soc/boot_mode.h components/soc/esp32c3/include/soc/clkout_channel.h components/soc/esp32c3/include/soc/dport_access.h -components/soc/esp32c3/include/soc/efuse_struct.h components/soc/esp32c3/include/soc/extmem_reg.h components/soc/esp32c3/include/soc/fe_reg.h components/soc/esp32c3/include/soc/gpio_pins.h @@ -1484,7 +1471,6 @@ components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h components/soc/esp32c3/include/soc/wdev_reg.h components/soc/esp32c3/interrupts.c -components/soc/esp32c3/ld/esp32c3.peripherals.ld components/soc/esp32c3/ledc_periph.c components/soc/esp32c3/rmt_periph.c components/soc/esp32c3/sigmadelta_periph.c @@ -1535,7 +1521,6 @@ components/soc/esp32h2/include/soc/uart_pins.h components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h components/soc/esp32h2/include/soc/wdev_reg.h -components/soc/esp32h2/ld/esp32h2.peripherals.ld components/soc/esp32h2/ledc_periph.c components/soc/esp32h2/rmt_periph.c components/soc/esp32h2/sigmadelta_periph.c @@ -1561,8 +1546,6 @@ components/soc/esp32s2/include/soc/dac_channel.h components/soc/esp32s2/include/soc/dedic_gpio_reg.h components/soc/esp32s2/include/soc/dedic_gpio_struct.h components/soc/esp32s2/include/soc/dport_access.h -components/soc/esp32s2/include/soc/efuse_reg.h -components/soc/esp32s2/include/soc/efuse_struct.h components/soc/esp32s2/include/soc/extmem_reg.h components/soc/esp32s2/include/soc/fe_reg.h components/soc/esp32s2/include/soc/gpio_pins.h @@ -1747,7 +1730,6 @@ components/soc/esp32s3/usb_periph.h components/soc/include/soc/adc_periph.h components/soc/include/soc/dac_periph.h components/soc/include/soc/dedic_gpio_periph.h -components/soc/include/soc/efuse_periph.h components/soc/include/soc/emac_periph.h components/soc/include/soc/gpio_periph.h components/soc/include/soc/hwcrypto_periph.h diff --git a/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c b/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c index 75328d9717..709d408df4 100644 --- a/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c +++ b/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c @@ -10,6 +10,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "soc/efuse_reg.h" +#include "hal/efuse_ll.h" #include "esp_efuse.h" #include "esp_system.h" #include "esp_spi_flash.h" @@ -51,14 +52,15 @@ static void example_print_chip_info(void) static void example_secure_boot_status(void) { - uint32_t efuse_block0 = REG_READ(EFUSE_BLK0_RDATA6_REG); - #ifdef CONFIG_ESP32_REV_MIN_3 uint8_t efuse_trusted_digest[DIGEST_LEN] = {0}, i; ESP_LOGI(TAG, "Checking for secure boot v2.."); - if(efuse_block0 & EFUSE_RD_ABS_DONE_1) { + if(efuse_ll_get_secure_boot_v2_en()) { ESP_LOGI(TAG, "ABS_DONE_1 is set. Secure Boot V2 enabled"); - memcpy(efuse_trusted_digest, (uint8_t *)EFUSE_BLK2_RDATA0_REG, DIGEST_LEN); + esp_err_t err = esp_efuse_read_block(EFUSE_BLK2, &efuse_trusted_digest, 0, DIGEST_LEN * 8); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Error (0x%x) while reading eFuse BLK2", err); + } ESP_LOGI(TAG, "Reading the public key digest from BLK2."); for (i = 0; i < DIGEST_LEN; i++) { ESP_LOGI(TAG, "%02x \t", efuse_trusted_digest[i]); @@ -70,21 +72,17 @@ static void example_secure_boot_status(void) #endif ESP_LOGI(TAG, "Checking for secure boot v1.."); - uint32_t dis_reg = REG_READ(EFUSE_BLK0_RDATA0_REG); - if (efuse_block0 & EFUSE_RD_ABS_DONE_0) { + if (efuse_ll_get_secure_boot_v1_en()) { ESP_LOGI(TAG, "ABS_DONE_0 is set. Secure Boot V1 enabled"); #ifdef CONFIG_ESP32_REV_MIN_3 - ESP_LOGW(TAG, "This chip version supports Secure Boot V2. It is recommended to use Secure Boot V2."); + ESP_LOGW(TAG, "This chip version supports Secure Boot V2. It is recommended to use Secure Boot V2."); #endif - bool efuse_key_read_protected = dis_reg & EFUSE_RD_DIS_BLK2; - bool efuse_key_write_protected = dis_reg & EFUSE_WR_DIS_BLK2; - ESP_LOGI(TAG, "Checking the integrityof the key in BLK2.."); - if (!efuse_key_read_protected) { + if (!esp_efuse_get_key_dis_read(EFUSE_BLK2)) { ESP_LOGE(TAG, "Key is not read protected. Refusing to blow secure boot efuse."); return; } - if (!efuse_key_write_protected) { + if (!esp_efuse_get_key_dis_write(EFUSE_BLK2)) { ESP_LOGE(TAG, "Key is not write protected. Refusing to blow secure boot efuse."); return; }