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Merge branch 'feature/move_target_kconfig_2' into 'master'

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system: move kconfig options out of target component

See merge request espressif/esp-idf!17321
This commit is contained in:
Marius Vikhammer
2022-04-24 13:29:43 +08:00
parent 5bb2379bac d2872095f9
commit 45c1d1cba2
174 changed files with 1455 additions and 1723 deletions
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components/esp_system/Kconfig
+3 -1
View File
@@ -1,5 +1,7 @@
menu "ESP System Settings"
# Insert chip-specific cpu config
rsource "./port/soc/$IDF_TARGET/Kconfig.cpu"
choice ESP_SYSTEM_PANIC
prompt "Panic handler behaviour"
@@ -48,7 +50,7 @@ menu "ESP System Settings"
config ESP_SYSTEM_RTC_EXT_XTAL
# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
# e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on
# e.g. It will be selected on when RTC_CLK_SRC_EXT_CRYS is on
bool
default n
components/esp_system/port/soc/esp32/Kconfig.cpu
+24
View File
@@ -0,0 +1,24 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_160
help
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_40
bool "40 MHz"
depends on IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_80
bool "80 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_160
bool "160 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_240
bool "240 MHz"
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80
default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160
default 240 if ESP_DEFAULT_CPU_FREQ_MHZ_240
components/esp_system/port/soc/esp32/clk.c
+7 -7
View File
@@ -29,10 +29,10 @@ static const char* TAG = "clk";
* Larger values increase startup delay. Smaller values may cause false positive
* detection (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32_RTC_CLK_CAL_CYCLES
#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#ifdef CONFIG_ESP32_RTC_XTAL_CAL_RETRY
#define RTC_XTAL_CAL_RETRY CONFIG_ESP32_RTC_XTAL_CAL_RETRY
#ifdef CONFIG_RTC_XTAL_CAL_RETRY
#define RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RETRY
#else
#define RTC_XTAL_CAL_RETRY 1
#endif
@@ -149,11 +149,11 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)
#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC)
#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256)
#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256);
#else
select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -172,7 +172,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
rtc_cpu_freq_config_t new_config;
rtc_clk_cpu_freq_get_config(&old_config);
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
assert(res);
components/esp_system/port/soc/esp32/highint_hdl.S
+6 -14
View File
@@ -1,16 +1,8 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/coreasm.h>
@@ -315,7 +307,7 @@ xt_highintx:
wsr a2, depc /* temp storage */
rsr.ccount a2
addmi a2, a2, (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ*50)
addmi a2, a2, (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ*50)
wsr a2, CCOMPARE2
/* Enable Integration Mode */
components/esp_system/port/soc/esp32c2/Kconfig.cpu
+21
View File
@@ -0,0 +1,21 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_120
help
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_40
bool "40 MHz"
depends on IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_80
bool "80 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_120
bool "120 MHz"
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80
default 120 if ESP_DEFAULT_CPU_FREQ_MHZ_120
components/esp_system/port/soc/esp32c2/clk.c
+4 -4
View File
@@ -32,7 +32,7 @@
* Larger values increase startup delay. Smaller values may cause false positive
* detection (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32C2_RTC_CLK_CAL_CYCLES
#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#define MHZ (1000000)
@@ -93,9 +93,9 @@ static const char *TAG = "clk";
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
#if defined(CONFIG_ESP32C2_RTC_CLK_SRC_EXT_OSC)
#if defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32C2_RTC_CLK_SRC_INT_8MD256)
#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256);
#else
select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -113,7 +113,7 @@ static const char *TAG = "clk";
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32C2_DEFAULT_CPU_FREQ_MHZ;
const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
assert(res);
components/esp_system/port/soc/esp32c3/Kconfig.cpu
+21
View File
@@ -0,0 +1,21 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_160
help
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_40
bool "40 MHz"
depends on IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_80
bool "80 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_160
bool "160 MHz"
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80
default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160
components/esp_system/port/soc/esp32c3/clk.c
+5 -5
View File
@@ -33,7 +33,7 @@
* Larger values increase startup delay. Smaller values may cause false positive
* detection (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES
#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#define MHZ (1000000)
@@ -94,11 +94,11 @@ static const char *TAG = "clk";
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
#if defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS)
#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC)
#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256)
#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256);
#else
select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -116,7 +116,7 @@ static const char *TAG = "clk";
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ;
const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
assert(res);
components/esp_system/port/soc/esp32h2/Kconfig.cpu
+27
View File
@@ -0,0 +1,27 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_64 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_96 if !IDF_ENV_FPGA
help
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_16
bool "16 MHz"
depends on IDF_ENV_FPGA #ESP32H2-TODO: IDF-3786
config ESP_DEFAULT_CPU_FREQ_MHZ_32
bool "32 MHz"
depends on IDF_ENV_FPGA #ESP32H2-TODO: IDF-3786
config ESP_DEFAULT_CPU_FREQ_MHZ_64
bool "64 MHz"
depends on IDF_ENV_FPGA #ESP32H2-TODO: IDF-3786
config ESP_DEFAULT_CPU_FREQ_MHZ_96
bool "96 MHz"
depends on !IDF_ENV_FPGA
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 16 if ESP_DEFAULT_CPU_FREQ_MHZ_16
default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32
default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96
components/esp_system/port/soc/esp32h2/clk.c
+5 -5
View File
@@ -33,7 +33,7 @@
* Larger values increase startup delay. Smaller values may cause false positive
* detection (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32H2_RTC_CLK_CAL_CYCLES
#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#define MHZ (1000000)
@@ -92,11 +92,11 @@ static const char *TAG = "clk";
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
#if defined(CONFIG_ESP32H2_RTC_CLK_SRC_EXT_CRYS)
#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_ESP32H2_RTC_CLK_SRC_EXT_OSC)
#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32H2_RTC_CLK_SRC_INT_8MD256)
#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256);
#else
select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -114,7 +114,7 @@ static const char *TAG = "clk";
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ;
const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
assert(res);
components/esp_system/port/soc/esp32s2/Kconfig.cpu
+24
View File
@@ -0,0 +1,24 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_160
help
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_40
bool "40 MHz"
depends on IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_80
bool "80 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_160
bool "160 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_240
bool "240 MHz"
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80
default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160
default 240 if ESP_DEFAULT_CPU_FREQ_MHZ_240
components/esp_system/port/soc/esp32s2/clk.c
+7 -7
View File
@@ -34,10 +34,10 @@ static const char *TAG = "clk";
* Larger values increase startup delay. Smaller values may cause false positive
* detection (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES
#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#ifdef CONFIG_ESP32S2_RTC_XTAL_CAL_RETRY
#define RTC_XTAL_CAL_RETRY CONFIG_ESP32S2_RTC_XTAL_CAL_RETRY
#ifdef CONFIG_RTC_XTAL_CAL_RETRY
#define RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RETRY
#else
#define RTC_XTAL_CAL_RETRY 1
#endif
@@ -91,11 +91,11 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
#if defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS)
#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC)
#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256)
#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256);
#else
select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -113,7 +113,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ;
const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
assert(res);
components/esp_system/port/soc/esp32s3/Kconfig.cpu
+24
View File
@@ -0,0 +1,24 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_160
help
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_40
bool "40 MHz"
depends on IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_80
bool "80 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_160
bool "160 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_240
bool "240 MHz"
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80
default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160
default 240 if ESP_DEFAULT_CPU_FREQ_MHZ_240
components/esp_system/port/soc/esp32s3/clk.c
+5 -5
View File
@@ -33,7 +33,7 @@ static const char *TAG = "clk";
* Larger values increase startup delay. Smaller values may cause false positive
* detection (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES
#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#define RTC_XTAL_CAL_RETRY 1
@@ -90,11 +90,11 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif
#if defined(CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS)
#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC)
#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256)
#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256);
#else
select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -112,7 +112,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ;
const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
assert(res);
components/esp_system/sdkconfig.rename.esp32
+7
View File
@@ -8,6 +8,7 @@ CONFIG_ESP32_PANIC_SILENT_REBOOT CONFIG_ESP_SYSTEM_PANIC_
CONFIG_ESP32_PANIC_GDBSTUB CONFIG_ESP_SYSTEM_PANIC_GDBSTUB
CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
CONFIG_ESP32_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE
CONFIG_ESP32_NO_BLOBS CONFIG_APP_NO_BLOBS
CONFIG_ESP32_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
CONFIG_ESP32_BROWNOUT_DET_LVL_SEL CONFIG_ESP_BROWNOUT_DET_LVL_SEL
@@ -20,3 +21,9 @@ CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 CONFIG_ESP_BROWNOUT_DET_
CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6
CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
CONFIG_ESP32_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
CONFIG_ESP32_DEFAULT_CPU_FREQ_40 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_40
CONFIG_ESP32_DEFAULT_CPU_FREQ_80 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80
CONFIG_ESP32_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
CONFIG_ESP32_DEFAULT_CPU_FREQ_240 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
components/esp_system/sdkconfig.rename.esp32c3
+5
View File
@@ -17,3 +17,8 @@ CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 CONFIG_ESP_BROWNOUT_DET_
CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6
CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
CONFIG_ESP32C3_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_40 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_40
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
components/esp_system/sdkconfig.rename.esp32h2
+6
View File
@@ -3,3 +3,9 @@
CONFIG_ESP32H2_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
CONFIG_ESP32H2_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
CONFIG_ESP32H2_DEFAULT_CPU_FREQ_16 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_16
CONFIG_ESP32H2_DEFAULT_CPU_FREQ_32 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_32
CONFIG_ESP32H2_DEFAULT_CPU_FREQ_64 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_64
CONFIG_ESP32H2_DEFAULT_CPU_FREQ_96 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_96
components/esp_system/sdkconfig.rename.esp32s2
+7
View File
@@ -10,6 +10,7 @@ CONFIG_ESP32S2_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPRO
CONFIG_ESP32S2_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
CONFIG_ESP32S2_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE
CONFIG_ESP32S2_NO_BLOBS CONFIG_APP_NO_BLOBS
CONFIG_ESP32S2_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
CONFIG_ESP32S2_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
@@ -23,3 +24,9 @@ CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 CONFIG_ESP_BROWNOUT_DET_
CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6
CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
CONFIG_ESP32S2_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
CONFIG_ESP32S2_DEFAULT_CPU_FREQ_40 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_40
CONFIG_ESP32S2_DEFAULT_CPU_FREQ_80 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80
CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
components/esp_system/sdkconfig.rename.esp32s3
+6
View File
@@ -15,3 +15,9 @@ CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 CONFIG_ESP_BROWNOUT_DET_
CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6
CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
CONFIG_ESP32S3_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_40 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_40
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240