feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

esp32s2: fix inconsistency between reg and struct headers

Browse Source 
test_mux register doesn't exist in RTCCNTL anymore, remove it from
struct header. Also remove adc_ll_vref_output implementation, which
depends on that register.
This commit is contained in:
Ivan Grokhotkov
2020-01-21 16:33:57 +01:00
parent c1ab87b580
commit 46035032cf
2 changed files with 6 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
components/soc/esp32s2/include/hal/adc_ll.h
View File

@@ -586,26 +586,5 @@ static inline void adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl
*/ */
static inline bool adc_ll_vref_output(int io) static inline bool adc_ll_vref_output(int io)
{ {
int channel; return false;
if (io == 25) {
channel = 8; //Channel 8 bit
} else if (io == 26) {
channel = 9; //Channel 9 bit
} else if (io == 27) {
channel = 7; //Channel 7 bit
} else {
return false;
}
RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode
//set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2)
RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels
//set ent
RTCCNTL.test_mux.ent_rtc = 1;
//set sar2_en_test
SENS.sar_meas2_ctrl1.sar2_en_test = 1;
//set sar2 en force
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW
//set en_pad for channels 7,8,9 (bits 0x380)
SENS.sar_meas2_ctrl2.sar2_en_pad = 1 << channel;
return true;
} }

15
components/soc/esp32s2/include/soc/rtc_cntl_struct.h
View File

@@ -13,6 +13,9 @@
// limitations under the License. // limitations under the License.
#ifndef _SOC_RTC_CNTL_STRUCT_H_ #ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_ #define _SOC_RTC_CNTL_STRUCT_H_
#include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@@ -554,15 +557,6 @@ typedef volatile struct {
uint32_t val; uint32_t val;
} swd_conf; } swd_conf;
uint32_t swd_wprotect; /*swd write protect*/ uint32_t swd_wprotect; /*swd write protect*/
union {
struct {
uint32_t reserved0: 28;
uint32_t ent_tsens: 1; /*ENT_TSENS*/
uint32_t ent_rtc: 1; /*ENT_RTC*/
uint32_t dtest_rtc: 2;
};
uint32_t val;
} test_mux;
union { union {
struct { struct {
uint32_t reserved0: 20; uint32_t reserved0: 20;
@@ -656,7 +650,8 @@ typedef volatile struct {
} ext_wakeup1_status; } ext_wakeup1_status;
union { union {
struct { struct {
uint32_t reserved0: 4; uint32_t out2_ena: 1; /*enable brown_out2 to start chip reset*/
uint32_t reserved1: 3;
uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ uint32_t int_wait: 10; /*brown out interrupt wait cycles*/
uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/
uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/