reset_reasons: EFUSE_RST is treated as POWERON_RST

ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.

components/bootloader_support/src/esp_image_format.c

@@ -256,7 +256,11 @@ esp_err_t bootloader_load_image(const esp_partition_pos_t *part, esp_image_metad
 #if CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS
     mode = ESP_IMAGE_LOAD_NO_VALIDATE;
 #elif CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON
-    if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) {
+    if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON
+#if SOC_EFUSE_HAS_EFUSE_RST_BUG
+        || esp_rom_get_reset_reason(0) == RESET_REASON_CORE_EFUSE_CRC
+#endif
+        ) {
         mode = ESP_IMAGE_LOAD_NO_VALIDATE;
     }
 #endif // CONFIG_BOOTLOADER_SKIP_...

components/esp_rom/include/esp32s2/rom/rtc.h

@@ -89,6 +89,7 @@ typedef enum {
     TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
     SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
     GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
+    EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -106,6 +107,7 @@ _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT,
 _Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
 _Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
+_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
 
 typedef enum {
     NO_SLEEP        = 0,

components/esp_system/port/soc/esp32c3/clk.c

@@ -68,7 +68,11 @@ static const char *TAG = "clk";
     rtc_config_t cfg = RTC_CONFIG_DEFAULT();
     soc_reset_reason_t rst_reas;
     rst_reas = esp_rom_get_reset_reason(0);
-    if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
+    if (rst_reas == RESET_REASON_CHIP_POWER_ON
+#if SOC_EFUSE_HAS_EFUSE_RST_BUG
+        || rst_reas == RESET_REASON_CORE_EFUSE_CRC
+#endif
+        ) {
         cfg.cali_ocode = 1;
     }
     rtc_init(cfg);

components/esp_system/port/soc/esp32c3/reset_reason.c

@@ -1,16 +1,8 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #include "esp_system.h"
 #include "esp_rom_sys.h"
@@ -26,6 +18,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
 {
     switch (rtc_reset_reason) {
     case RESET_REASON_CHIP_POWER_ON:
+#if SOC_EFUSE_HAS_EFUSE_RST_BUG
+    case RESET_REASON_CORE_EFUSE_CRC:
+#endif
         return ESP_RST_POWERON;
 
     case RESET_REASON_CPU0_SW:

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -55,6 +55,10 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
     bool
     default y
 
+config SOC_EFUSE_HAS_EFUSE_RST_BUG
+    bool
+    default y
+
 config SOC_RTC_FAST_MEM_SUPPORTED
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -38,6 +38,7 @@
 #define SOC_WIFI_SUPPORTED              1
 #define SOC_SUPPORTS_SECURE_DL_MODE     1
 #define SOC_EFUSE_KEY_PURPOSE_FIELD         1
+#define SOC_EFUSE_HAS_EFUSE_RST_BUG         1
 #define SOC_RTC_FAST_MEM_SUPPORTED        1
 #define SOC_I2S_SUPPORTED               1
 #define SOC_RMT_SUPPORTED               1

components/soc/esp32s2/include/soc/reset_reasons.h

@@ -1,16 +1,8 @@
-// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #pragma once
 
@@ -51,6 +43,7 @@ typedef enum {
     RESET_REASON_CPU0_MWDT1      = 0x11, // Main watch dog 1 resets CPU 0
     RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
     RESET_REASON_SYS_CLK_GLITCH  = 0x13, // Glitch on clock resets the digital core and rtc module
+    RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core
 } soc_reset_reason_t;
 
 #ifdef __cplusplus

tools/ci/check_copyright_ignore.txt

@@ -681,7 +681,6 @@ components/esp_system/port/soc/esp32/intr.c
 components/esp_system/port/soc/esp32/reset_reason.c
 components/esp_system/port/soc/esp32c3/apb_backup_dma.c
 components/esp_system/port/soc/esp32c3/cache_err_int.h
-components/esp_system/port/soc/esp32c3/reset_reason.c
 components/esp_system/port/soc/esp32h2/apb_backup_dma.c
 components/esp_system/port/soc/esp32h2/cache_err_int.h
 components/esp_system/port/soc/esp32h2/reset_reason.c
@@ -1357,7 +1356,6 @@ components/soc/esp32s2/include/soc/ledc_reg.h
 components/soc/esp32s2/include/soc/ledc_struct.h
 components/soc/esp32s2/include/soc/memprot_defs.h
 components/soc/esp32s2/include/soc/nrx_reg.h
-components/soc/esp32s2/include/soc/reset_reasons.h
 components/soc/esp32s2/include/soc/rtc_cntl_reg.h
 components/soc/esp32s2/include/soc/rtc_cntl_struct.h
 components/soc/esp32s2/include/soc/rtc_i2c_reg.h