From 4a10d24b485c1d58d71a2bc5ad950eef50859add Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Thu, 5 Sep 2024 17:07:18 +0800 Subject: [PATCH] fix(parlio_tx): fix error in first transfer and 1 byte transfer On p4, the clock was configured in the wrong order causing a dropped count on the first transmission. And gdma eof event fails to trigger parlio_tx eof event when transmitting single byte. --- components/driver/parlio/parlio_tx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/components/driver/parlio/parlio_tx.c b/components/driver/parlio/parlio_tx.c index 194f7f1be1..755a12738e 100644 --- a/components/driver/parlio/parlio_tx.c +++ b/components/driver/parlio/parlio_tx.c @@ -250,7 +250,8 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par ESP_RETURN_ON_ERROR(ret, TAG, "create NO_LIGHT_SLEEP lock failed"); } #endif - + // turn on the tx module clock to sync the register configuration to the module + parlio_ll_tx_enable_clock(hal->regs, true); parlio_ll_tx_set_clock_source(hal->regs, clk_src); // set clock division, round up uint32_t div = (periph_src_clk_hz + config->output_clk_freq_hz - 1) / config->output_clk_freq_hz;