diff --git a/components/soc/esp32p4/include/soc/ana_i2c_mst_reg.h b/components/soc/esp32p4/include/soc/ana_i2c_mst_reg.h deleted file mode 100644 index 8ae4236271..0000000000 --- a/components/soc/esp32p4/include/soc/ana_i2c_mst_reg.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** ANA_I2C_MST_I2C0_CTRL_REG register - * need des - */ -#define ANA_I2C_MST_I2C0_CTRL_REG (DR_REG_ANA_I2C_MST_BASE + 0x0) -/** ANA_I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C0_CTRL 0x01FFFFFFU -#define ANA_I2C_MST_I2C0_CTRL_M (ANA_I2C_MST_I2C0_CTRL_V << ANA_I2C_MST_I2C0_CTRL_S) -#define ANA_I2C_MST_I2C0_CTRL_V 0x01FFFFFFU -#define ANA_I2C_MST_I2C0_CTRL_S 0 -/** ANA_I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C0_BUSY (BIT(25)) -#define ANA_I2C_MST_I2C0_BUSY_M (ANA_I2C_MST_I2C0_BUSY_V << ANA_I2C_MST_I2C0_BUSY_S) -#define ANA_I2C_MST_I2C0_BUSY_V 0x00000001U -#define ANA_I2C_MST_I2C0_BUSY_S 25 - -/** ANA_I2C_MST_I2C1_CTRL_REG register - * need des - */ -#define ANA_I2C_MST_I2C1_CTRL_REG (DR_REG_ANA_I2C_MST_BASE + 0x4) -/** ANA_I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C1_CTRL 0x01FFFFFFU -#define ANA_I2C_MST_I2C1_CTRL_M (ANA_I2C_MST_I2C1_CTRL_V << ANA_I2C_MST_I2C1_CTRL_S) -#define ANA_I2C_MST_I2C1_CTRL_V 0x01FFFFFFU -#define ANA_I2C_MST_I2C1_CTRL_S 0 -/** ANA_I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C1_BUSY (BIT(25)) -#define ANA_I2C_MST_I2C1_BUSY_M (ANA_I2C_MST_I2C1_BUSY_V << ANA_I2C_MST_I2C1_BUSY_S) -#define ANA_I2C_MST_I2C1_BUSY_V 0x00000001U -#define ANA_I2C_MST_I2C1_BUSY_S 25 - -/** ANA_I2C_MST_I2C0_CONF_REG register - * need des - */ -#define ANA_I2C_MST_I2C0_CONF_REG (DR_REG_ANA_I2C_MST_BASE + 0x8) -/** ANA_I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C0_CONF 0x00FFFFFFU -#define ANA_I2C_MST_I2C0_CONF_M (ANA_I2C_MST_I2C0_CONF_V << ANA_I2C_MST_I2C0_CONF_S) -#define ANA_I2C_MST_I2C0_CONF_V 0x00FFFFFFU -#define ANA_I2C_MST_I2C0_CONF_S 0 -/** ANA_I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C0_STATUS 0x000000FFU -#define ANA_I2C_MST_I2C0_STATUS_M (ANA_I2C_MST_I2C0_STATUS_V << ANA_I2C_MST_I2C0_STATUS_S) -#define ANA_I2C_MST_I2C0_STATUS_V 0x000000FFU -#define ANA_I2C_MST_I2C0_STATUS_S 24 - -/** ANA_I2C_MST_I2C1_CONF_REG register - * need des - */ -#define ANA_I2C_MST_I2C1_CONF_REG (DR_REG_ANA_I2C_MST_BASE + 0xc) -/** ANA_I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C1_CONF 0x00FFFFFFU -#define ANA_I2C_MST_I2C1_CONF_M (ANA_I2C_MST_I2C1_CONF_V << ANA_I2C_MST_I2C1_CONF_S) -#define ANA_I2C_MST_I2C1_CONF_V 0x00FFFFFFU -#define ANA_I2C_MST_I2C1_CONF_S 0 -/** ANA_I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C1_STATUS 0x000000FFU -#define ANA_I2C_MST_I2C1_STATUS_M (ANA_I2C_MST_I2C1_STATUS_V << ANA_I2C_MST_I2C1_STATUS_S) -#define ANA_I2C_MST_I2C1_STATUS_V 0x000000FFU -#define ANA_I2C_MST_I2C1_STATUS_S 24 - -/** ANA_I2C_MST_I2C_BURST_CONF_REG register - * need des - */ -#define ANA_I2C_MST_I2C_BURST_CONF_REG (DR_REG_ANA_I2C_MST_BASE + 0x10) -/** ANA_I2C_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU -#define ANA_I2C_MST_I2C_MST_BURST_CTRL_M (ANA_I2C_MST_I2C_MST_BURST_CTRL_V << ANA_I2C_MST_I2C_MST_BURST_CTRL_S) -#define ANA_I2C_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU -#define ANA_I2C_MST_I2C_MST_BURST_CTRL_S 0 - -/** ANA_I2C_MST_I2C_BURST_STATUS_REG register - * need des - */ -#define ANA_I2C_MST_I2C_BURST_STATUS_REG (DR_REG_ANA_I2C_MST_BASE + 0x14) -/** ANA_I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C_MST_BURST_DONE (BIT(0)) -#define ANA_I2C_MST_I2C_MST_BURST_DONE_M (ANA_I2C_MST_I2C_MST_BURST_DONE_V << ANA_I2C_MST_I2C_MST_BURST_DONE_S) -#define ANA_I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U -#define ANA_I2C_MST_I2C_MST_BURST_DONE_S 0 -/** ANA_I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) -#define ANA_I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (ANA_I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << ANA_I2C_MST_I2C_MST0_BURST_ERR_FLAG_S) -#define ANA_I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U -#define ANA_I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1 -/** ANA_I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) -#define ANA_I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (ANA_I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << ANA_I2C_MST_I2C_MST1_BURST_ERR_FLAG_S) -#define ANA_I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U -#define ANA_I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2 -/** ANA_I2C_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024; - * need des - */ -#define ANA_I2C_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU -#define ANA_I2C_MST_I2C_MST_BURST_TIMEOUT_CNT_M (ANA_I2C_MST_I2C_MST_BURST_TIMEOUT_CNT_V << ANA_I2C_MST_I2C_MST_BURST_TIMEOUT_CNT_S) -#define ANA_I2C_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU -#define ANA_I2C_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20 - -/** ANA_I2C_MST_ANA_CONF0_REG register - * need des - */ -#define ANA_I2C_MST_ANA_CONF0_REG (DR_REG_ANA_I2C_MST_BASE + 0x18) -/** ANA_I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_ANA_CONF0 0x00FFFFFFU -#define ANA_I2C_MST_ANA_CONF0_M (ANA_I2C_MST_ANA_CONF0_V << ANA_I2C_MST_ANA_CONF0_S) -#define ANA_I2C_MST_ANA_CONF0_V 0x00FFFFFFU -#define ANA_I2C_MST_ANA_CONF0_S 0 -/** ANA_I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define ANA_I2C_MST_ANA_STATUS0 0x000000FFU -#define ANA_I2C_MST_ANA_STATUS0_M (ANA_I2C_MST_ANA_STATUS0_V << ANA_I2C_MST_ANA_STATUS0_S) -#define ANA_I2C_MST_ANA_STATUS0_V 0x000000FFU -#define ANA_I2C_MST_ANA_STATUS0_S 24 - -/** ANA_I2C_MST_ANA_CONF1_REG register - * need des - */ -#define ANA_I2C_MST_ANA_CONF1_REG (DR_REG_ANA_I2C_MST_BASE + 0x1c) -/** ANA_I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_ANA_CONF1 0x00FFFFFFU -#define ANA_I2C_MST_ANA_CONF1_M (ANA_I2C_MST_ANA_CONF1_V << ANA_I2C_MST_ANA_CONF1_S) -#define ANA_I2C_MST_ANA_CONF1_V 0x00FFFFFFU -#define ANA_I2C_MST_ANA_CONF1_S 0 -/** ANA_I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define ANA_I2C_MST_ANA_STATUS1 0x000000FFU -#define ANA_I2C_MST_ANA_STATUS1_M (ANA_I2C_MST_ANA_STATUS1_V << ANA_I2C_MST_ANA_STATUS1_S) -#define ANA_I2C_MST_ANA_STATUS1_V 0x000000FFU -#define ANA_I2C_MST_ANA_STATUS1_S 24 - -/** ANA_I2C_MST_ANA_CONF2_REG register - * need des - */ -#define ANA_I2C_MST_ANA_CONF2_REG (DR_REG_ANA_I2C_MST_BASE + 0x20) -/** ANA_I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_ANA_CONF2 0x00FFFFFFU -#define ANA_I2C_MST_ANA_CONF2_M (ANA_I2C_MST_ANA_CONF2_V << ANA_I2C_MST_ANA_CONF2_S) -#define ANA_I2C_MST_ANA_CONF2_V 0x00FFFFFFU -#define ANA_I2C_MST_ANA_CONF2_S 0 -/** ANA_I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0; - * need des - */ -#define ANA_I2C_MST_ANA_STATUS2 0x000000FFU -#define ANA_I2C_MST_ANA_STATUS2_M (ANA_I2C_MST_ANA_STATUS2_V << ANA_I2C_MST_ANA_STATUS2_S) -#define ANA_I2C_MST_ANA_STATUS2_V 0x000000FFU -#define ANA_I2C_MST_ANA_STATUS2_S 24 - -/** ANA_I2C_MST_I2C0_CTRL1_REG register - * need des - */ -#define ANA_I2C_MST_I2C0_CTRL1_REG (DR_REG_ANA_I2C_MST_BASE + 0x24) -/** ANA_I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define ANA_I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU -#define ANA_I2C_MST_I2C0_SCL_PULSE_DUR_M (ANA_I2C_MST_I2C0_SCL_PULSE_DUR_V << ANA_I2C_MST_I2C0_SCL_PULSE_DUR_S) -#define ANA_I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU -#define ANA_I2C_MST_I2C0_SCL_PULSE_DUR_S 0 -/** ANA_I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define ANA_I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU -#define ANA_I2C_MST_I2C0_SDA_SIDE_GUARD_M (ANA_I2C_MST_I2C0_SDA_SIDE_GUARD_V << ANA_I2C_MST_I2C0_SDA_SIDE_GUARD_S) -#define ANA_I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU -#define ANA_I2C_MST_I2C0_SDA_SIDE_GUARD_S 6 - -/** ANA_I2C_MST_I2C1_CTRL1_REG register - * need des - */ -#define ANA_I2C_MST_I2C1_CTRL1_REG (DR_REG_ANA_I2C_MST_BASE + 0x28) -/** ANA_I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define ANA_I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU -#define ANA_I2C_MST_I2C1_SCL_PULSE_DUR_M (ANA_I2C_MST_I2C1_SCL_PULSE_DUR_V << ANA_I2C_MST_I2C1_SCL_PULSE_DUR_S) -#define ANA_I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU -#define ANA_I2C_MST_I2C1_SCL_PULSE_DUR_S 0 -/** ANA_I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define ANA_I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU -#define ANA_I2C_MST_I2C1_SDA_SIDE_GUARD_M (ANA_I2C_MST_I2C1_SDA_SIDE_GUARD_V << ANA_I2C_MST_I2C1_SDA_SIDE_GUARD_S) -#define ANA_I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU -#define ANA_I2C_MST_I2C1_SDA_SIDE_GUARD_S 6 - -/** ANA_I2C_MST_HW_I2C_CTRL_REG register - * need des - */ -#define ANA_I2C_MST_HW_I2C_CTRL_REG (DR_REG_ANA_I2C_MST_BASE + 0x2c) -/** ANA_I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; - * need des - */ -#define ANA_I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU -#define ANA_I2C_MST_HW_I2C_SCL_PULSE_DUR_M (ANA_I2C_MST_HW_I2C_SCL_PULSE_DUR_V << ANA_I2C_MST_HW_I2C_SCL_PULSE_DUR_S) -#define ANA_I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU -#define ANA_I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0 -/** ANA_I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; - * need des - */ -#define ANA_I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU -#define ANA_I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (ANA_I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << ANA_I2C_MST_HW_I2C_SDA_SIDE_GUARD_S) -#define ANA_I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU -#define ANA_I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/** ANA_I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0; - * need des - */ -#define ANA_I2C_MST_ARBITER_DIS (BIT(11)) -#define ANA_I2C_MST_ARBITER_DIS_M (ANA_I2C_MST_ARBITER_DIS_V << ANA_I2C_MST_ARBITER_DIS_S) -#define ANA_I2C_MST_ARBITER_DIS_V 0x00000001U -#define ANA_I2C_MST_ARBITER_DIS_S 11 - -/** ANA_I2C_MST_NOUSE_REG register - * need des - */ -#define ANA_I2C_MST_NOUSE_REG (DR_REG_ANA_I2C_MST_BASE + 0x30) -/** ANA_I2C_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C_MST_NOUSE 0xFFFFFFFFU -#define ANA_I2C_MST_I2C_MST_NOUSE_M (ANA_I2C_MST_I2C_MST_NOUSE_V << ANA_I2C_MST_I2C_MST_NOUSE_S) -#define ANA_I2C_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU -#define ANA_I2C_MST_I2C_MST_NOUSE_S 0 - -/** ANA_I2C_MST_CLK160M_REG register - * need des - */ -#define ANA_I2C_MST_CLK160M_REG (DR_REG_ANA_I2C_MST_BASE + 0x34) -/** ANA_I2C_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; - * need des - */ -#define ANA_I2C_MST_CLK_I2C_MST_SEL_160M (BIT(0)) -#define ANA_I2C_MST_CLK_I2C_MST_SEL_160M_M (ANA_I2C_MST_CLK_I2C_MST_SEL_160M_V << ANA_I2C_MST_CLK_I2C_MST_SEL_160M_S) -#define ANA_I2C_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U -#define ANA_I2C_MST_CLK_I2C_MST_SEL_160M_S 0 - -/** ANA_I2C_MST_DATE_REG register - * need des - */ -#define ANA_I2C_MST_DATE_REG (DR_REG_ANA_I2C_MST_BASE + 0x38) -/** ANA_I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448; - * need des - */ -#define ANA_I2C_MST_DATE 0x0FFFFFFFU -#define ANA_I2C_MST_DATE_M (ANA_I2C_MST_DATE_V << ANA_I2C_MST_DATE_S) -#define ANA_I2C_MST_DATE_V 0x0FFFFFFFU -#define ANA_I2C_MST_DATE_S 0 -/** ANA_I2C_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0; - * need des - */ -#define ANA_I2C_MST_I2C_MST_CLK_EN (BIT(28)) -#define ANA_I2C_MST_I2C_MST_CLK_EN_M (ANA_I2C_MST_I2C_MST_CLK_EN_V << ANA_I2C_MST_I2C_MST_CLK_EN_S) -#define ANA_I2C_MST_I2C_MST_CLK_EN_V 0x00000001U -#define ANA_I2C_MST_I2C_MST_CLK_EN_S 28 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h new file mode 100644 index 0000000000..78a8a6fc43 --- /dev/null +++ b/components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h @@ -0,0 +1,301 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2C_ANA_MST_I2C0_CTRL_REG register + * need des + */ +#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) +/** I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU +#define I2C_ANA_MST_I2C0_CTRL_M (I2C_ANA_MST_I2C0_CTRL_V << I2C_ANA_MST_I2C0_CTRL_S) +#define I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU +#define I2C_ANA_MST_I2C0_CTRL_S 0 +/** I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_M (I2C_ANA_MST_I2C0_BUSY_V << I2C_ANA_MST_I2C0_BUSY_S) +#define I2C_ANA_MST_I2C0_BUSY_V 0x00000001U +#define I2C_ANA_MST_I2C0_BUSY_S 25 + +/** I2C_ANA_MST_I2C1_CTRL_REG register + * need des + */ +#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) +/** I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFFU +#define I2C_ANA_MST_I2C1_CTRL_M (I2C_ANA_MST_I2C1_CTRL_V << I2C_ANA_MST_I2C1_CTRL_S) +#define I2C_ANA_MST_I2C1_CTRL_V 0x01FFFFFFU +#define I2C_ANA_MST_I2C1_CTRL_S 0 +/** I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C1_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_M (I2C_ANA_MST_I2C1_BUSY_V << I2C_ANA_MST_I2C1_BUSY_S) +#define I2C_ANA_MST_I2C1_BUSY_V 0x00000001U +#define I2C_ANA_MST_I2C1_BUSY_S 25 + +/** I2C_ANA_MST_I2C0_CONF_REG register + * need des + */ +#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) +/** I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU +#define I2C_ANA_MST_I2C0_CONF_M (I2C_ANA_MST_I2C0_CONF_V << I2C_ANA_MST_I2C0_CONF_S) +#define I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU +#define I2C_ANA_MST_I2C0_CONF_S 0 +/** I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C0_STATUS 0x000000FFU +#define I2C_ANA_MST_I2C0_STATUS_M (I2C_ANA_MST_I2C0_STATUS_V << I2C_ANA_MST_I2C0_STATUS_S) +#define I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU +#define I2C_ANA_MST_I2C0_STATUS_S 24 + +/** I2C_ANA_MST_I2C1_CONF_REG register + * need des + */ +#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc) +/** I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFFU +#define I2C_ANA_MST_I2C1_CONF_M (I2C_ANA_MST_I2C1_CONF_V << I2C_ANA_MST_I2C1_CONF_S) +#define I2C_ANA_MST_I2C1_CONF_V 0x00FFFFFFU +#define I2C_ANA_MST_I2C1_CONF_S 0 +/** I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C1_STATUS 0x000000FFU +#define I2C_ANA_MST_I2C1_STATUS_M (I2C_ANA_MST_I2C1_STATUS_V << I2C_ANA_MST_I2C1_STATUS_S) +#define I2C_ANA_MST_I2C1_STATUS_V 0x000000FFU +#define I2C_ANA_MST_I2C1_STATUS_S 24 + +/** I2C_ANA_MST_I2C_BURST_CONF_REG register + * need des + */ +#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) +/** I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU +#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M (I2C_ANA_MST_I2C_MST_BURST_CTRL_V << I2C_ANA_MST_I2C_MST_BURST_CTRL_S) +#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU +#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0 + +/** I2C_ANA_MST_I2C_BURST_STATUS_REG register + * need des + */ +#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) +/** I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0)) +#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (I2C_ANA_MST_I2C_MST_BURST_DONE_V << I2C_ANA_MST_I2C_MST_BURST_DONE_S) +#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x00000001U +#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0 +/** I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S) +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U +#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1 +/** I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S) +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U +#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2 +/** I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024; + * need des + */ +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M (I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S) +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU +#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20 + +/** I2C_ANA_MST_ANA_CONF0_REG register + * need des + */ +#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) +/** I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFFU +#define I2C_ANA_MST_ANA_CONF0_M (I2C_ANA_MST_ANA_CONF0_V << I2C_ANA_MST_ANA_CONF0_S) +#define I2C_ANA_MST_ANA_CONF0_V 0x00FFFFFFU +#define I2C_ANA_MST_ANA_CONF0_S 0 +/** I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define I2C_ANA_MST_ANA_STATUS0 0x000000FFU +#define I2C_ANA_MST_ANA_STATUS0_M (I2C_ANA_MST_ANA_STATUS0_V << I2C_ANA_MST_ANA_STATUS0_S) +#define I2C_ANA_MST_ANA_STATUS0_V 0x000000FFU +#define I2C_ANA_MST_ANA_STATUS0_S 24 + +/** I2C_ANA_MST_ANA_CONF1_REG register + * need des + */ +#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) +/** I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU +#define I2C_ANA_MST_ANA_CONF1_M (I2C_ANA_MST_ANA_CONF1_V << I2C_ANA_MST_ANA_CONF1_S) +#define I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU +#define I2C_ANA_MST_ANA_CONF1_S 0 +/** I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define I2C_ANA_MST_ANA_STATUS1 0x000000FFU +#define I2C_ANA_MST_ANA_STATUS1_M (I2C_ANA_MST_ANA_STATUS1_V << I2C_ANA_MST_ANA_STATUS1_S) +#define I2C_ANA_MST_ANA_STATUS1_V 0x000000FFU +#define I2C_ANA_MST_ANA_STATUS1_S 24 + +/** I2C_ANA_MST_ANA_CONF2_REG register + * need des + */ +#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) +/** I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFFU +#define I2C_ANA_MST_ANA_CONF2_M (I2C_ANA_MST_ANA_CONF2_V << I2C_ANA_MST_ANA_CONF2_S) +#define I2C_ANA_MST_ANA_CONF2_V 0x00FFFFFFU +#define I2C_ANA_MST_ANA_CONF2_S 0 +/** I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define I2C_ANA_MST_ANA_STATUS2 0x000000FFU +#define I2C_ANA_MST_ANA_STATUS2_M (I2C_ANA_MST_ANA_STATUS2_V << I2C_ANA_MST_ANA_STATUS2_S) +#define I2C_ANA_MST_ANA_STATUS2_V 0x000000FFU +#define I2C_ANA_MST_ANA_STATUS2_S 24 + +/** I2C_ANA_MST_I2C0_CTRL1_REG register + * need des + */ +#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) +/** I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003FU +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 +/** I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 + +/** I2C_ANA_MST_I2C1_CTRL1_REG register + * need des + */ +#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) +/** I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003FU +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 +/** I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 + +/** I2C_ANA_MST_HW_I2C_CTRL_REG register + * need des + */ +#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c) +/** I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2; + * need des + */ +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 +/** I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1; + * need des + */ +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/** I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0; + * need des + */ +#define I2C_ANA_MST_ARBITER_DIS (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_M (I2C_ANA_MST_ARBITER_DIS_V << I2C_ANA_MST_ARBITER_DIS_S) +#define I2C_ANA_MST_ARBITER_DIS_V 0x00000001U +#define I2C_ANA_MST_ARBITER_DIS_S 11 + +/** I2C_ANA_MST_NOUSE_REG register + * need des + */ +#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) +/** I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU +#define I2C_ANA_MST_I2C_MST_NOUSE_M (I2C_ANA_MST_I2C_MST_NOUSE_V << I2C_ANA_MST_I2C_MST_NOUSE_S) +#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU +#define I2C_ANA_MST_I2C_MST_NOUSE_S 0 + +/** I2C_ANA_MST_CLK160M_REG register + * need des + */ +#define I2C_ANA_MST_CLK160M_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) +/** I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; + * need des + */ +#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M (BIT(0)) +#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M (I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S) +#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U +#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S 0 + +/** I2C_ANA_MST_DATE_REG register + * need des + */ +#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x38) +/** I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 35656448; + * need des + */ +#define I2C_ANA_MST_DATE 0x0FFFFFFFU +#define I2C_ANA_MST_DATE_M (I2C_ANA_MST_DATE_V << I2C_ANA_MST_DATE_S) +#define I2C_ANA_MST_DATE_V 0x0FFFFFFFU +#define I2C_ANA_MST_DATE_S 0 +/** I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0; + * need des + */ +#define I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28)) +#define I2C_ANA_MST_I2C_MST_CLK_EN_M (I2C_ANA_MST_I2C_MST_CLK_EN_V << I2C_ANA_MST_I2C_MST_CLK_EN_S) +#define I2C_ANA_MST_I2C_MST_CLK_EN_V 0x00000001U +#define I2C_ANA_MST_I2C_MST_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/ana_i2c_mst_struct.h b/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h similarity index 81% rename from components/soc/esp32p4/include/soc/ana_i2c_mst_struct.h rename to components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h index 77e4e096de..bbf169b28b 100644 --- a/components/soc/esp32p4/include/soc/ana_i2c_mst_struct.h +++ b/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h @@ -27,7 +27,7 @@ typedef union { uint32_t reserved_26:6; }; uint32_t val; -} ana_i2c_mst_i2c0_ctrl_reg_t; +} i2c_ana_mst_i2c0_ctrl_reg_t; /** Type of i2c1_ctrl register * need des @@ -45,7 +45,7 @@ typedef union { uint32_t reserved_26:6; }; uint32_t val; -} ana_i2c_mst_i2c1_ctrl_reg_t; +} i2c_ana_mst_i2c1_ctrl_reg_t; /** Type of i2c0_conf register * need des @@ -62,7 +62,7 @@ typedef union { uint32_t i2c0_status:8; }; uint32_t val; -} ana_i2c_mst_i2c0_conf_reg_t; +} i2c_ana_mst_i2c0_conf_reg_t; /** Type of i2c1_conf register * need des @@ -79,7 +79,7 @@ typedef union { uint32_t i2c1_status:8; }; uint32_t val; -} ana_i2c_mst_i2c1_conf_reg_t; +} i2c_ana_mst_i2c1_conf_reg_t; /** Type of i2c_burst_conf register * need des @@ -92,7 +92,7 @@ typedef union { uint32_t i2c_mst_burst_ctrl:32; }; uint32_t val; -} ana_i2c_mst_i2c_burst_conf_reg_t; +} i2c_ana_mst_i2c_burst_conf_reg_t; /** Type of i2c_burst_status register * need des @@ -118,7 +118,7 @@ typedef union { uint32_t i2c_mst_burst_timeout_cnt:12; }; uint32_t val; -} ana_i2c_mst_i2c_burst_status_reg_t; +} i2c_ana_mst_i2c_burst_status_reg_t; /** Type of ana_conf0 register * need des @@ -135,7 +135,7 @@ typedef union { uint32_t ana_status0:8; }; uint32_t val; -} ana_i2c_mst_ana_conf0_reg_t; +} i2c_ana_mst_ana_conf0_reg_t; /** Type of ana_conf1 register * need des @@ -152,7 +152,7 @@ typedef union { uint32_t ana_status1:8; }; uint32_t val; -} ana_i2c_mst_ana_conf1_reg_t; +} i2c_ana_mst_ana_conf1_reg_t; /** Type of ana_conf2 register * need des @@ -169,7 +169,7 @@ typedef union { uint32_t ana_status2:8; }; uint32_t val; -} ana_i2c_mst_ana_conf2_reg_t; +} i2c_ana_mst_ana_conf2_reg_t; /** Type of i2c0_ctrl1 register * need des @@ -187,7 +187,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} ana_i2c_mst_i2c0_ctrl1_reg_t; +} i2c_ana_mst_i2c0_ctrl1_reg_t; /** Type of i2c1_ctrl1 register * need des @@ -205,7 +205,7 @@ typedef union { uint32_t reserved_11:21; }; uint32_t val; -} ana_i2c_mst_i2c1_ctrl1_reg_t; +} i2c_ana_mst_i2c1_ctrl1_reg_t; /** Type of hw_i2c_ctrl register * need des @@ -227,7 +227,7 @@ typedef union { uint32_t reserved_12:20; }; uint32_t val; -} ana_i2c_mst_hw_i2c_ctrl_reg_t; +} i2c_ana_mst_hw_i2c_ctrl_reg_t; /** Type of nouse register * need des @@ -240,7 +240,7 @@ typedef union { uint32_t i2c_mst_nouse:32; }; uint32_t val; -} ana_i2c_mst_nouse_reg_t; +} i2c_ana_mst_nouse_reg_t; /** Type of clk160m register * need des @@ -254,7 +254,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} ana_i2c_mst_clk160m_reg_t; +} i2c_ana_mst_clk160m_reg_t; /** Type of date register * need des @@ -272,30 +272,30 @@ typedef union { uint32_t reserved_29:3; }; uint32_t val; -} ana_i2c_mst_date_reg_t; +} i2c_ana_mst_date_reg_t; typedef struct { - volatile ana_i2c_mst_i2c0_ctrl_reg_t i2c0_ctrl; - volatile ana_i2c_mst_i2c1_ctrl_reg_t i2c1_ctrl; - volatile ana_i2c_mst_i2c0_conf_reg_t i2c0_conf; - volatile ana_i2c_mst_i2c1_conf_reg_t i2c1_conf; - volatile ana_i2c_mst_i2c_burst_conf_reg_t i2c_burst_conf; - volatile ana_i2c_mst_i2c_burst_status_reg_t i2c_burst_status; - volatile ana_i2c_mst_ana_conf0_reg_t ana_conf0; - volatile ana_i2c_mst_ana_conf1_reg_t ana_conf1; - volatile ana_i2c_mst_ana_conf2_reg_t ana_conf2; - volatile ana_i2c_mst_i2c0_ctrl1_reg_t i2c0_ctrl1; - volatile ana_i2c_mst_i2c1_ctrl1_reg_t i2c1_ctrl1; - volatile ana_i2c_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl; - volatile ana_i2c_mst_nouse_reg_t nouse; - volatile ana_i2c_mst_clk160m_reg_t clk160m; - volatile ana_i2c_mst_date_reg_t date; -} ana_i2c_mst_dev_t; + volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; + volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl; + volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; + volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf; + volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf; + volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status; + volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0; + volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1; + volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2; + volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1; + volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1; + volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl; + volatile i2c_ana_mst_nouse_reg_t nouse; + volatile i2c_ana_mst_clk160m_reg_t clk160m; + volatile i2c_ana_mst_date_reg_t date; +} i2c_ana_mst_dev_t; #ifndef __cplusplus -_Static_assert(sizeof(ana_i2c_mst_dev_t) == 0x3c, "Invalid size of ana_i2c_mst_dev_t structure"); +_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure"); #endif #ifdef __cplusplus