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Merge branch 'feature/esp32h2beta2_chip_env' into 'master'

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Support esp32h2beta2 chip

See merge request espressif/esp-idf!17503
This commit is contained in:
Wu Zheng Hui
2022-03-31 09:51:12 +08:00
parent e8aef07502 f29d329e55
commit 506768c9fa
15 changed files with 958 additions and 990 deletions
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1
Kconfig
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@@ -13,7 +13,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_ENV_FPGA config IDF_ENV_FPGA
# This option is for internal use only # This option is for internal use only
bool bool
default "y" if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3378
option env="IDF_ENV_FPGA" option env="IDF_ENV_FPGA"
config IDF_TARGET_ARCH_RISCV config IDF_TARGET_ARCH_RISCV

1322
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld
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File diff suppressed because it is too large Load Diff

189
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld
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@@ -1,13 +1,12 @@
/* /*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM function interface esp32h2.rom.libgcc.ld for esp32h2 /* ROM function interface esp32h2.rom.libgcc.ld for esp32h2
* *
* *
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -19,95 +18,95 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
__absvdi2 = 0x4000098c; __absvdi2 = 0x40000998;
__absvsi2 = 0x40000990; __absvsi2 = 0x4000099c;
__adddf3 = 0x40000994; __adddf3 = 0x400009a0;
__addsf3 = 0x40000998; __addsf3 = 0x400009a4;
__addvdi3 = 0x4000099c; __addvdi3 = 0x400009a8;
__addvsi3 = 0x400009a0; __addvsi3 = 0x400009ac;
__ashldi3 = 0x400009a4; __ashldi3 = 0x400009b0;
__ashrdi3 = 0x400009a8; __ashrdi3 = 0x400009b4;
__bswapdi2 = 0x400009ac; __bswapdi2 = 0x400009b8;
__bswapsi2 = 0x400009b0; __bswapsi2 = 0x400009bc;
__clear_cache = 0x400009b4; __clear_cache = 0x400009c0;
__clrsbdi2 = 0x400009b8; __clrsbdi2 = 0x400009c4;
__clrsbsi2 = 0x400009bc; __clrsbsi2 = 0x400009c8;
__clzdi2 = 0x400009c0; __clzdi2 = 0x400009cc;
__clzsi2 = 0x400009c4; __clzsi2 = 0x400009d0;
__cmpdi2 = 0x400009c8; __cmpdi2 = 0x400009d4;
__ctzdi2 = 0x400009cc; __ctzdi2 = 0x400009d8;
__ctzsi2 = 0x400009d0; __ctzsi2 = 0x400009dc;
__divdc3 = 0x400009d4; __divdc3 = 0x400009e0;
__divdf3 = 0x400009d8; __divdf3 = 0x400009e4;
__divdi3 = 0x400009dc; __divdi3 = 0x400009e8;
__divsc3 = 0x400009e0; __divsc3 = 0x400009ec;
__divsf3 = 0x400009e4; __divsf3 = 0x400009f0;
__divsi3 = 0x400009e8; __divsi3 = 0x400009f4;
__eqdf2 = 0x400009ec; __eqdf2 = 0x400009f8;
__eqsf2 = 0x400009f0; __eqsf2 = 0x400009fc;
__extendsfdf2 = 0x400009f4; __extendsfdf2 = 0x40000a00;
__ffsdi2 = 0x400009f8; __ffsdi2 = 0x40000a04;
__ffssi2 = 0x400009fc; __ffssi2 = 0x40000a08;
__fixdfdi = 0x40000a00; __fixdfdi = 0x40000a0c;
__fixdfsi = 0x40000a04; __fixdfsi = 0x40000a10;
__fixsfdi = 0x40000a08; __fixsfdi = 0x40000a14;
__fixsfsi = 0x40000a0c; __fixsfsi = 0x40000a18;
__fixunsdfsi = 0x40000a10; __fixunsdfsi = 0x40000a1c;
__fixunssfdi = 0x40000a14; __fixunssfdi = 0x40000a20;
__fixunssfsi = 0x40000a18; __fixunssfsi = 0x40000a24;
__floatdidf = 0x40000a1c; __floatdidf = 0x40000a28;
__floatdisf = 0x40000a20; __floatdisf = 0x40000a2c;
__floatsidf = 0x40000a24; __floatsidf = 0x40000a30;
__floatsisf = 0x40000a28; __floatsisf = 0x40000a34;
__floatundidf = 0x40000a2c; __floatundidf = 0x40000a38;
__floatundisf = 0x40000a30; __floatundisf = 0x40000a3c;
__floatunsidf = 0x40000a34; __floatunsidf = 0x40000a40;
__floatunsisf = 0x40000a38; __floatunsisf = 0x40000a44;
__gcc_bcmp = 0x40000a3c; __gcc_bcmp = 0x40000a48;
__gedf2 = 0x40000a40; __gedf2 = 0x40000a4c;
__gesf2 = 0x40000a44; __gesf2 = 0x40000a50;
__gtdf2 = 0x40000a48; __gtdf2 = 0x40000a54;
__gtsf2 = 0x40000a4c; __gtsf2 = 0x40000a58;
__ledf2 = 0x40000a50; __ledf2 = 0x40000a5c;
__lesf2 = 0x40000a54; __lesf2 = 0x40000a60;
__lshrdi3 = 0x40000a58; __lshrdi3 = 0x40000a64;
__ltdf2 = 0x40000a5c; __ltdf2 = 0x40000a68;
__ltsf2 = 0x40000a60; __ltsf2 = 0x40000a6c;
__moddi3 = 0x40000a64; __moddi3 = 0x40000a70;
__modsi3 = 0x40000a68; __modsi3 = 0x40000a74;
__muldc3 = 0x40000a6c; __muldc3 = 0x40000a78;
__muldf3 = 0x40000a70; __muldf3 = 0x40000a7c;
__muldi3 = 0x40000a74; __muldi3 = 0x40000a80;
__mulsc3 = 0x40000a78; __mulsc3 = 0x40000a84;
__mulsf3 = 0x40000a7c; __mulsf3 = 0x40000a88;
__mulsi3 = 0x40000a80; __mulsi3 = 0x40000a8c;
__mulvdi3 = 0x40000a84; __mulvdi3 = 0x40000a90;
__mulvsi3 = 0x40000a88; __mulvsi3 = 0x40000a94;
__nedf2 = 0x40000a8c; __nedf2 = 0x40000a98;
__negdf2 = 0x40000a90; __negdf2 = 0x40000a9c;
__negdi2 = 0x40000a94; __negdi2 = 0x40000aa0;
__negsf2 = 0x40000a98; __negsf2 = 0x40000aa4;
__negvdi2 = 0x40000a9c; __negvdi2 = 0x40000aa8;
__negvsi2 = 0x40000aa0; __negvsi2 = 0x40000aac;
__nesf2 = 0x40000aa4; __nesf2 = 0x40000ab0;
__paritysi2 = 0x40000aa8; __paritysi2 = 0x40000ab4;
__popcountdi2 = 0x40000aac; __popcountdi2 = 0x40000ab8;
__popcountsi2 = 0x40000ab0; __popcountsi2 = 0x40000abc;
__powidf2 = 0x40000ab4; __powidf2 = 0x40000ac0;
__powisf2 = 0x40000ab8; __powisf2 = 0x40000ac4;
__subdf3 = 0x40000abc; __subdf3 = 0x40000ac8;
__subsf3 = 0x40000ac0; __subsf3 = 0x40000acc;
__subvdi3 = 0x40000ac4; __subvdi3 = 0x40000ad0;
__subvsi3 = 0x40000ac8; __subvsi3 = 0x40000ad4;
__truncdfsf2 = 0x40000acc; __truncdfsf2 = 0x40000ad8;
__ucmpdi2 = 0x40000ad0; __ucmpdi2 = 0x40000adc;
__udivdi3 = 0x40000ad4; __udivdi3 = 0x40000ae0;
__udivmoddi4 = 0x40000ad8; __udivmoddi4 = 0x40000ae4;
__udivsi3 = 0x40000adc; __udivsi3 = 0x40000ae8;
__udiv_w_sdiv = 0x40000ae0; __udiv_w_sdiv = 0x40000aec;
__umoddi3 = 0x40000ae4; __umoddi3 = 0x40000af0;
__umodsi3 = 0x40000ae8; __umodsi3 = 0x40000af4;
__unorddf2 = 0x40000aec; __unorddf2 = 0x40000af8;
__unordsf2 = 0x40000af0; __unordsf2 = 0x40000afc;
__extenddftf2 = 0x40000af4; __extenddftf2 = 0x40000b00;
__trunctfdf2 = 0x40000af8; __trunctfdf2 = 0x40000b04;

59
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld
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@@ -1,13 +1,12 @@
/* /*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2 /* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2
* *
* *
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -19,30 +18,30 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
__sprint_r = 0x40000674; __sprint_r = 0x40000684;
_fiprintf_r = 0x40000678; _fiprintf_r = 0x40000688;
_fprintf_r = 0x4000067c; _fprintf_r = 0x4000068c;
_printf_common = 0x40000680; _printf_common = 0x40000690;
_printf_i = 0x40000684; _printf_i = 0x40000694;
_vfiprintf_r = 0x40000688; _vfiprintf_r = 0x40000698;
_vfprintf_r = 0x4000068c; _vfprintf_r = 0x4000069c;
fiprintf = 0x40000690; fiprintf = 0x400006a0;
fprintf = 0x40000694; fprintf = 0x400006a4;
printf = 0x40000698; printf = 0x400006a8;
vfiprintf = 0x4000069c; vfiprintf = 0x400006ac;
vfprintf = 0x400006a0; vfprintf = 0x400006b0;
asprintf = 0x400006a4; asprintf = 0x400006b4;
sprintf = 0x400006a8; sprintf = 0x400006b8;
snprintf = 0x400006ac; snprintf = 0x400006bc;
siprintf = 0x400006b0; siprintf = 0x400006c0;
sniprintf = 0x400006b4; sniprintf = 0x400006c4;
vprintf = 0x400006b8; vprintf = 0x400006c8;
viprintf = 0x400006bc; viprintf = 0x400006cc;
vsnprintf = 0x400006c0; vsnprintf = 0x400006d0;
vsniprintf = 0x400006c4; vsniprintf = 0x400006d4;
__rom_printf_float = 0x400006c8; _printf_float = 0x400006d8;
__rom_scanf_float = 0x400006cc; _scanf_float = 0x400006dc;
_scanf_i = 0x400006d0; _scanf_i = 0x400006e0;
_scanf_chars = 0x400006d4; _scanf_chars = 0x400006e4;
sscanf = 0x400006d8; sscanf = 0x400006e8;
siscanf = 0x400006dc; siscanf = 0x400006ec;

253
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld
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@@ -1,13 +1,12 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM function interface esp32h2.rom.newlib.ld for esp32h2 /* ROM function interface esp32h2.rom.newlib.ld for esp32h2
* *
* *
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6
* *
* Compatible with ROM where ECO version equal or greater to 0. * Compatible with ROM where ECO version equal or greater to 0.
* *
@@ -19,126 +18,130 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
esp_rom_newlib_init_common_mutexes = 0x40000484; esp_rom_newlib_init_common_mutexes = 0x40000494;
memset = 0x40000488; memset = 0x40000498;
memcpy = 0x4000048c; memcpy = 0x4000049c;
memmove = 0x40000490; memmove = 0x400004a0;
memcmp = 0x40000494; memcmp = 0x400004a4;
strcpy = 0x40000498; strcpy = 0x400004a8;
strncpy = 0x4000049c; strncpy = 0x400004ac;
strcmp = 0x400004a0; strcmp = 0x400004b0;
strncmp = 0x400004a4; strncmp = 0x400004b4;
strlen = 0x400004a8; strlen = 0x400004b8;
strstr = 0x400004ac; strstr = 0x400004bc;
bzero = 0x400004b0; bzero = 0x400004c0;
sbrk = 0x400004b8; _isatty_r = 0x400004c4;
isalnum = 0x400004bc; sbrk = 0x400004c8;
isalpha = 0x400004c0; isalnum = 0x400004cc;
isascii = 0x400004c4; isalpha = 0x400004d0;
isblank = 0x400004c8; isascii = 0x400004d4;
iscntrl = 0x400004cc; isblank = 0x400004d8;
isdigit = 0x400004d0; iscntrl = 0x400004dc;
islower = 0x400004d4; isdigit = 0x400004e0;
isgraph = 0x400004d8; islower = 0x400004e4;
isprint = 0x400004dc; isgraph = 0x400004e8;
ispunct = 0x400004e0; isprint = 0x400004ec;
isspace = 0x400004e4; ispunct = 0x400004f0;
isupper = 0x400004e8; isspace = 0x400004f4;
toupper = 0x400004ec; isupper = 0x400004f8;
tolower = 0x400004f0; toupper = 0x400004fc;
toascii = 0x400004f4; tolower = 0x40000500;
memccpy = 0x400004f8; toascii = 0x40000504;
memchr = 0x400004fc; memccpy = 0x40000508;
memrchr = 0x40000500; memchr = 0x4000050c;
strcasecmp = 0x40000504; memrchr = 0x40000510;
strcasestr = 0x40000508; strcasecmp = 0x40000514;
strcat = 0x4000050c; strcasestr = 0x40000518;
strdup = 0x40000510; strcat = 0x4000051c;
strchr = 0x40000514; strdup = 0x40000520;
strcspn = 0x40000518; strchr = 0x40000524;
strcoll = 0x4000051c; strcspn = 0x40000528;
strlcat = 0x40000520; strcoll = 0x4000052c;
strlcpy = 0x40000524; strlcat = 0x40000530;
strlwr = 0x40000528; strlcpy = 0x40000534;
strncasecmp = 0x4000052c; strlwr = 0x40000538;
strncat = 0x40000530; strncasecmp = 0x4000053c;
strndup = 0x40000534; strncat = 0x40000540;
strnlen = 0x40000538; strndup = 0x40000544;
strrchr = 0x4000053c; strnlen = 0x40000548;
strsep = 0x40000540; strrchr = 0x4000054c;
strspn = 0x40000544; strsep = 0x40000550;
strtok_r = 0x40000548; strspn = 0x40000554;
strupr = 0x4000054c; strtok_r = 0x40000558;
longjmp = 0x40000550; strupr = 0x4000055c;
setjmp = 0x40000554; longjmp = 0x40000560;
abs = 0x40000558; setjmp = 0x40000564;
div = 0x4000055c; abs = 0x40000568;
labs = 0x40000560; div = 0x4000056c;
ldiv = 0x40000564; labs = 0x40000570;
qsort = 0x40000568; ldiv = 0x40000574;
rand_r = 0x4000056c; qsort = 0x40000578;
rand = 0x40000570; rand_r = 0x4000057c;
srand = 0x40000574; rand = 0x40000580;
utoa = 0x40000578; srand = 0x40000584;
itoa = 0x4000057c; utoa = 0x40000588;
atoi = 0x40000580; itoa = 0x4000058c;
atol = 0x40000584; atoi = 0x40000590;
strtol = 0x40000588; atol = 0x40000594;
strtoul = 0x4000058c; strtol = 0x40000598;
fflush = 0x40000590; strtoul = 0x4000059c;
_fflush_r = 0x40000594; fflush = 0x400005a0;
_fwalk = 0x40000598; _fflush_r = 0x400005a4;
_fwalk_reent = 0x4000059c; _fwalk = 0x400005a8;
__swbuf_r = 0x400005a8; _fwalk_reent = 0x400005ac;
__swbuf = 0x400005ac; __smakebuf_r = 0x400005b0;
_strtod_l = 0x400005b4; __swhatbuf_r = 0x400005b4;
_strtod_r = 0x400005b8; __swbuf_r = 0x400005b8;
strtod_l = 0x400005bc; __swbuf = 0x400005bc;
strtod = 0x400005c0; __swsetup_r = 0x400005c0;
strtof_l = 0x400005c4; _strtod_l = 0x400005c4;
strtof = 0x400005c8; _strtod_r = 0x400005c8;
_strtol_r = 0x400005cc; strtod_l = 0x400005cc;
strtol_l = 0x400005d0; strtod = 0x400005d0;
_strtoul_r = 0x400005d4; strtof_l = 0x400005d4;
strtoul_l = 0x400005d8; strtof = 0x400005d8;
__match = 0x400005dc; _strtol_r = 0x400005dc;
__hexnan = 0x400005e0; strtol_l = 0x400005e0;
__hexdig_fun = 0x400005e4; _strtoul_r = 0x400005e4;
__gethex = 0x400005e8; strtoul_l = 0x400005e8;
_Balloc = 0x400005ec; __match = 0x400005ec;
_Bfree = 0x400005f0; __hexnan = 0x400005f0;
__multadd = 0x400005f4; __hexdig_fun = 0x400005f4;
__s2b = 0x400005f8; __gethex = 0x400005f8;
__hi0bits = 0x400005fc; _Balloc = 0x400005fc;
__lo0bits = 0x40000600; _Bfree = 0x40000600;
__i2b = 0x40000604; __multadd = 0x40000604;
__multiply = 0x40000608; __s2b = 0x40000608;
__pow5mult = 0x4000060c; __hi0bits = 0x4000060c;
__lshift = 0x40000610; __lo0bits = 0x40000610;
__mcmp = 0x40000614; __i2b = 0x40000614;
__mdiff = 0x40000618; __multiply = 0x40000618;
__ulp = 0x4000061c; __pow5mult = 0x4000061c;
__b2d = 0x40000620; __lshift = 0x40000620;
__d2b = 0x40000624; __mcmp = 0x40000624;
__ratio = 0x40000628; __mdiff = 0x40000628;
_mprec_log10 = 0x4000062c; __ulp = 0x4000062c;
__copybits = 0x40000630; __b2d = 0x40000630;
__any_on = 0x40000634; __d2b = 0x40000634;
asctime = 0x40000638; __ratio = 0x40000638;
asctime_r = 0x4000063c; _mprec_log10 = 0x4000063c;
atof = 0x40000640; __copybits = 0x40000640;
atoff = 0x40000644; __any_on = 0x40000644;
_dtoa_r = 0x40000648; asctime = 0x40000648;
_wctomb_r = 0x4000064c; asctime_r = 0x4000064c;
__ascii_wctomb = 0x40000650; atof = 0x40000650;
_mbtowc_r = 0x40000654; atoff = 0x40000654;
__ascii_mbtowc = 0x40000658; _dtoa_r = 0x40000658;
puts = 0x4000065c; _wctomb_r = 0x4000065c;
putc = 0x40000660; __ascii_wctomb = 0x40000660;
putchar = 0x40000664; _mbtowc_r = 0x40000664;
nan = 0x40000668; __ascii_mbtowc = 0x40000668;
nanf = 0x4000066c; puts = 0x4000066c;
__errno = 0x40000670; putc = 0x40000670;
putchar = 0x40000674;
nan = 0x40000678;
nanf = 0x4000067c;
__errno = 0x40000680;
/* Data (.data, .bss, .rodata) */ /* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fcdffd8; syscall_table_ptr = 0x3fcdffd4;
_global_impure_ptr = 0x3fcdffd4; _global_impure_ptr = 0x3fcdffd0;

3
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld
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@@ -1,9 +1,8 @@
/* /*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* ROM version variables for esp32h2 /* ROM version variables for esp32h2
* *
* These addresses should be compatible with any ROM version for this chip. * These addresses should be compatible with any ROM version for this chip.

47
components/esp_rom/include/esp32h2/rom/rom_layout.h
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once #pragma once
@@ -20,9 +12,6 @@
extern "C" { extern "C" {
#endif #endif
#define SUPPORT_BTDM 1
#define SUPPORT_WIFI 1
/* Structure and functions for returning ROM global layout /* Structure and functions for returning ROM global layout
* *
* This is for address symbols defined in the linker script, which may change during ECOs. * This is for address symbols defined in the linker script, which may change during ECOs.
@@ -32,8 +21,6 @@ typedef struct {
void *dram0_rtos_reserved_start; void *dram0_rtos_reserved_start;
void *stack_sentry; void *stack_sentry;
void *stack; void *stack;
void *stack_sentry_app;
void *stack_app;
/* BTDM data */ /* BTDM data */
void *data_start_btdm; void *data_start_btdm;
@@ -47,31 +34,9 @@ typedef struct {
void *bss_start_interface_btdm; void *bss_start_interface_btdm;
void *bss_end_interface_btdm; void *bss_end_interface_btdm;
/* Other DRAM ranges */
#if SUPPORT_BTDM || SUPPORT_WIFI
void *dram_start_phyrom; void *dram_start_phyrom;
void *dram_end_phyrom; void *dram_end_phyrom;
#endif
#if SUPPORT_WIFI
void *dram_start_coexist;
void *dram_end_coexist;
void *dram_start_net80211;
void *dram_end_net80211;
void *dram_start_pp;
void *dram_end_pp;
void *data_start_interface_coexist;
void *data_end_interface_coexist;
void *bss_start_interface_coexist;
void *bss_end_interface_coexist;
void *data_start_interface_net80211;
void *data_end_interface_net80211;
void *bss_start_interface_net80211;
void *bss_end_interface_net80211;
void *data_start_interface_pp;
void *data_end_interface_pp;
void *bss_start_interface_pp;
void *bss_end_interface_pp;
#endif
void *dram_start_usbdev_rom; void *dram_start_usbdev_rom;
void *dram_end_usbdev_rom; void *dram_end_usbdev_rom;
void *dram_start_uart_rom; void *dram_start_uart_rom;

4
components/hal/esp32h2/include/hal/efuse_ll.h
View File

@@ -10,7 +10,7 @@
#include <stdbool.h> #include <stdbool.h>
#include "soc/efuse_periph.h" #include "soc/efuse_periph.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "esp32c3/rom/efuse.h" #include "esp32h2/rom/efuse.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -32,7 +32,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{ {
return EFUSE.rd_mac_spi_sys_0; return EFUSE.rd_mac_spi_sys_0.mac_0;
} }
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)

1
components/heap/port/memory_layout_utils.c
View File

@@ -17,6 +17,7 @@
#define ROM_HAS_LAYOUT_TABLE 1 #define ROM_HAS_LAYOUT_TABLE 1
#elif CONFIG_IDF_TARGET_ESP32H2 #elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/rom_layout.h" #include "esp32h2/rom/rom_layout.h"
#define ROM_HAS_LAYOUT_TABLE 1
#elif CONFIG_IDF_TARGET_ESP32C2 #elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/rom_layout.h" #include "esp32c2/rom/rom_layout.h"
#define ROM_HAS_LAYOUT_TABLE 1 #define ROM_HAS_LAYOUT_TABLE 1

7
components/soc/esp32h2/include/rev1/soc/efuse_struct.h
View File

@@ -167,7 +167,12 @@ typedef volatile struct efuse_dev_s {
}; };
uint32_t val; uint32_t val;
} rd_repeat_data4; } rd_repeat_data4;
uint32_t rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/ union {
struct {
uint32_t mac_0;
};
uint32_t val;
} rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/
union { union {
struct { struct {
uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/ uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/

42
components/soc/esp32h2/include/rev2/soc/clkrst_reg.h
View File

@@ -15,7 +15,7 @@ extern "C" {
/** SYSTEM_SYSCLK_CONF_REG register /** SYSTEM_SYSCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x0) #define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0)
/** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [7:0]; default: 0; /** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [7:0]; default: 0;
* Need add description * Need add description
*/ */
@@ -41,7 +41,7 @@ extern "C" {
/** SYSTEM_CPUCLK_CONF_REG register /** SYSTEM_CPUCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_CPUCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x4) #define SYSTEM_CPUCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x4)
/** SYSTEM_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; /** SYSTEM_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
* Need add description * Need add description
*/ */
@@ -67,7 +67,7 @@ extern "C" {
/** SYSTEM_BUSCLK_CONF_REG register /** SYSTEM_BUSCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_BUSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x8) #define SYSTEM_BUSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x8)
/** SYSTEM_APB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; /** SYSTEM_APB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
* Need add description * Need add description
*/ */
@@ -86,7 +86,7 @@ extern "C" {
/** SYSTEM_MODCLK_CONF_REG register /** SYSTEM_MODCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_MODCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0xc) #define SYSTEM_MODCLK_CONF_REG (DR_REG_CLKRST_BASE + 0xc)
/** SYSTEM_MODEM_CLK_SEL : R/W; bitpos: [1:0]; default: 1; /** SYSTEM_MODEM_CLK_SEL : R/W; bitpos: [1:0]; default: 1;
* Need add description * Need add description
*/ */
@@ -133,7 +133,7 @@ extern "C" {
/** SYSTEM_CLK_OUT_EN_REG register /** SYSTEM_CLK_OUT_EN_REG register
* register description * register description
*/ */
#define SYSTEM_CLK_OUT_EN_REG (DR_REG_SYSTEM_BASE + 0x10) #define SYSTEM_CLK_OUT_EN_REG (DR_REG_CLKRST_BASE + 0x10)
/** SYSTEM_CLK_8M_BT_OEN : R/W; bitpos: [3]; default: 1; /** SYSTEM_CLK_8M_BT_OEN : R/W; bitpos: [3]; default: 1;
* Need add description * Need add description
*/ */
@@ -208,7 +208,7 @@ extern "C" {
/** SYSTEM_MODEM_CLK_EN_REG register /** SYSTEM_MODEM_CLK_EN_REG register
* register description * register description
*/ */
#define SYSTEM_MODEM_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x14) #define SYSTEM_MODEM_CLK_EN_REG (DR_REG_CLKRST_BASE + 0x14)
/** SYSTEM_FE_CAL_CLK_EN : R/W; bitpos: [0]; default: 0; /** SYSTEM_FE_CAL_CLK_EN : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -374,7 +374,7 @@ extern "C" {
/** SYSTEM_MODEM_RST_EN_REG register /** SYSTEM_MODEM_RST_EN_REG register
* register description * register description
*/ */
#define SYSTEM_MODEM_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x18) #define SYSTEM_MODEM_RST_EN_REG (DR_REG_CLKRST_BASE + 0x18)
/** SYSTEM_FE_RST : R/W; bitpos: [0]; default: 0; /** SYSTEM_FE_RST : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -526,7 +526,7 @@ extern "C" {
/** SYSTEM_PERIP_CLK_CONF_REG register /** SYSTEM_PERIP_CLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x1c) #define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_CLKRST_BASE + 0x1c)
/** SYSTEM_SEC_DIV_NUM : R/W; bitpos: [7:0]; default: 1; /** SYSTEM_SEC_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
* Need add description * Need add description
*/ */
@@ -559,7 +559,7 @@ extern "C" {
/** SYSTEM_PERIP_CLK_EN0_REG register /** SYSTEM_PERIP_CLK_EN0_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x20) #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_CLKRST_BASE + 0x20)
/** SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1; /** SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description * Need add description
*/ */
@@ -788,7 +788,7 @@ extern "C" {
/** SYSTEM_PERIP_CLK_EN1_REG register /** SYSTEM_PERIP_CLK_EN1_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x24) #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_CLKRST_BASE + 0x24)
/** SYSTEM_RETENTION_TOP_CLK_EN : R/W; bitpos: [0]; default: 1; /** SYSTEM_RETENTION_TOP_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description * Need add description
*/ */
@@ -905,7 +905,7 @@ extern "C" {
/** SYSTEM_PERIP_RST_EN0_REG register /** SYSTEM_PERIP_RST_EN0_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x28) #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_CLKRST_BASE + 0x28)
/** SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0; /** SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -1134,7 +1134,7 @@ extern "C" {
/** SYSTEM_PERIP_RST_EN1_REG register /** SYSTEM_PERIP_RST_EN1_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x2c) #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_CLKRST_BASE + 0x2c)
/** SYSTEM_RETENTION_TOP_RST : R/W; bitpos: [0]; default: 0; /** SYSTEM_RETENTION_TOP_RST : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -1251,7 +1251,7 @@ extern "C" {
/** SYSTEM_FPGA_DBG_REG register /** SYSTEM_FPGA_DBG_REG register
* register description * register description
*/ */
#define SYSTEM_FPGA_DBG_REG (DR_REG_SYSTEM_BASE + 0x30) #define SYSTEM_FPGA_DBG_REG (DR_REG_CLKRST_BASE + 0x30)
/** SYSTEM_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; /** SYSTEM_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
* Need add description * Need add description
*/ */
@@ -1263,7 +1263,7 @@ extern "C" {
/** SYSTEM_REGCLK_CONF_REG register /** SYSTEM_REGCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_REGCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x34) #define SYSTEM_REGCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x34)
/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; /** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -1272,17 +1272,17 @@ extern "C" {
#define SYSTEM_CLK_EN_V 0x00000001U #define SYSTEM_CLK_EN_V 0x00000001U
#define SYSTEM_CLK_EN_S 0 #define SYSTEM_CLK_EN_S 0
/** SYSTEM_DATE_REG register /** SYSTEM_CLKRST_DATE_REG register
* register description * register description
*/ */
#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0x38) #define SYSTEM_CLKRST_DATE_REG (DR_REG_SYSTEM_BASE + 0x38)
/** SYSTEM_DATE : R/W; bitpos: [27:0]; default: 34672962; /** CLKRST_DATE : R/W; bitpos: [27:0]; default: 34672962;
* Need add description * Need add description
*/ */
#define SYSTEM_DATE 0x0FFFFFFFU #define CLKRST_DATE 0x0FFFFFFFU
#define SYSTEM_DATE_M (SYSTEM_DATE_V << SYSTEM_DATE_S) #define CLKRST_DATE_M (CLKRST_DATE_V << CLKRST_DATE_S)
#define SYSTEM_DATE_V 0x0FFFFFFFU #define CLKRST_DATE_V 0x0FFFFFFFU
#define SYSTEM_DATE_S 0 #define CLKRST_DATE_S 0
#ifdef __cplusplus #ifdef __cplusplus
} }

1
components/soc/esp32h2/include/rev2/soc/efuse_struct.h
View File

@@ -2166,6 +2166,7 @@ typedef struct {
volatile efuse_date_reg_t date; volatile efuse_date_reg_t date;
} efuse_dev_t; } efuse_dev_t;
extern efuse_dev_t EFUSE;
#ifndef __cplusplus #ifndef __cplusplus
_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");

16
components/soc/esp32h2/include/rev2/soc/system_reg.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -356,17 +356,17 @@ extern "C" {
#define SYSTEM_MEM_VT_SEL_V 0x00000003U #define SYSTEM_MEM_VT_SEL_V 0x00000003U
#define SYSTEM_MEM_VT_SEL_S 22 #define SYSTEM_MEM_VT_SEL_S 22
/** SYSTEM_SYSTEM_REG_DATE_REG register /** SYSTEM_REG_DATE_REG register
* register description * register description
*/ */
#define SYSTEM_SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) #define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
/** SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872; /** SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872;
* Need add description * Need add description
*/ */
#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFFU #define SYSTEM_REG_DATE 0x0FFFFFFFU
#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S) #define SYSTEM_REG_DATE_M (SYSTEM_REG_DATE_V << SYSTEM_REG_DATE_S)
#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFFU #define SYSTEM_REG_DATE_V 0x0FFFFFFFU
#define SYSTEM_SYSTEM_REG_DATE_S 0 #define SYSTEM_REG_DATE_S 0
#ifdef __cplusplus #ifdef __cplusplus
} }

2
components/soc/esp32h2/include/soc/soc.h
View File

@@ -208,7 +208,7 @@
#define SOC_DEBUG_HIGH 0x28000000 #define SOC_DEBUG_HIGH 0x28000000
// Start (highest address) of ROM boot stack, only relevant during early boot // Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fcebf10 #define SOC_ROM_STACK_START 0x3fcdf120
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.

1
tools/ci/check_copyright_ignore.txt
View File

@@ -586,7 +586,6 @@ components/esp_rom/include/esp32h2/rom/libc_stubs.h
components/esp_rom/include/esp32h2/rom/lldesc.h components/esp_rom/include/esp32h2/rom/lldesc.h
components/esp_rom/include/esp32h2/rom/md5_hash.h components/esp_rom/include/esp32h2/rom/md5_hash.h
components/esp_rom/include/esp32h2/rom/miniz.h components/esp_rom/include/esp32h2/rom/miniz.h
components/esp_rom/include/esp32h2/rom/rom_layout.h
components/esp_rom/include/esp32h2/rom/rsa_pss.h components/esp_rom/include/esp32h2/rom/rsa_pss.h
components/esp_rom/include/esp32h2/rom/sha.h components/esp_rom/include/esp32h2/rom/sha.h
components/esp_rom/include/esp32h2/rom/tjpgd.h components/esp_rom/include/esp32h2/rom/tjpgd.h