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Merge branch 'bugfix/yield_issue_c5' into 'master'

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fix(interrupt): fixed exit critical section on P4/C5

See merge request espressif/esp-idf!29798
This commit is contained in:
Marius Vikhammer
2024-03-24 14:30:15 +08:00
parent 821d3e2cee be839733ed
commit 5154be52ac
1 changed files with 10 additions and 0 deletions
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10
components/riscv/include/riscv/rv_utils.h
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@@ -232,6 +232,16 @@ FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_restore_intlevel_
* a single write to the mintthresh register without further manipulations needed. * a single write to the mintthresh register without further manipulations needed.
* This is done to quicken up exit for critical sections */ * This is done to quicken up exit for critical sections */
REG_WRITE(CLIC_INT_THRESH_REG, restoreval); REG_WRITE(CLIC_INT_THRESH_REG, restoreval);
/**
* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
* operations is forced, making the new threshold active.
*
* Without this we risk executing the next several instrucitons before getting interrupted
* This is especially bad if we immediatly enter a new critical section
*/
REG_READ(CLIC_INT_THRESH_REG);
} }
/* Direct register write version of rv_utils_set_intlevel(). Used to speed up critical sections. */ /* Direct register write version of rv_utils_set_intlevel(). Used to speed up critical sections. */