diff --git a/components/esp_driver_gpio/test_apps/.build-test-rules.yml b/components/esp_driver_gpio/test_apps/.build-test-rules.yml
index f69bb5b7af..f05a6dcaa0 100644
--- a/components/esp_driver_gpio/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_gpio/test_apps/.build-test-rules.yml
@@ -3,11 +3,6 @@
 components/esp_driver_gpio/test_apps:
   depends_components:
     - esp_driver_gpio
-  disable:
-    - if: IDF_TARGET in ["esp32h21"]
-      temporary: true
-      reason: not support yet # TODO: [esp32h21] IDF-11611
-
 components/esp_driver_gpio/test_apps/gpio_extensions:
   enable:
     - if: SOC_DEDICATED_GPIO_SUPPORTED == 1
diff --git a/components/esp_driver_gpio/test_apps/gpio/README.md b/components/esp_driver_gpio/test_apps/gpio/README.md
index 7b96141437..15bfc62bf3 100644
--- a/components/esp_driver_gpio/test_apps/gpio/README.md
+++ b/components/esp_driver_gpio/test_apps/gpio/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
diff --git a/components/esp_hw_support/port/esp32h21/io_mux.c b/components/esp_hw_support/port/esp32h21/io_mux.c
index 38762bd4f7..bb7aaa713b 100644
--- a/components/esp_hw_support/port/esp32h21/io_mux.c
+++ b/components/esp_hw_support/port/esp32h21/io_mux.c
@@ -1,8 +1,77 @@
 
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-//TODO: [ESP32H21] IDF-11611
+#include "freertos/FreeRTOS.h"
+#include "esp_private/io_mux.h"
+#include "esp_private/periph_ctrl.h"
+#include "hal/gpio_ll.h"
+#include "hal/rtc_io_ll.h"
+
+#define RTCIO_RCC_ATOMIC()  PERIPH_RCC_ATOMIC()
+
+static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
+static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter)
+static uint8_t s_rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM] = { 0 };
+static uint32_t s_rtc_io_using_mask = 0;
+
+esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
+{
+    bool clk_conflict = false;
+    // check is the IO MUX has been set to another clock source
+    portENTER_CRITICAL(&s_io_mux_spinlock);
+    if (s_io_mux_clk_src != 0 && s_io_mux_clk_src != clk_src) {
+        clk_conflict = true;
+    } else {
+        s_io_mux_clk_src = clk_src;
+    }
+    portEXIT_CRITICAL(&s_io_mux_spinlock);
+
+    if (clk_conflict) {
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    gpio_ll_iomux_set_clk_src(clk_src);
+
+    return ESP_OK;
+}
+
+void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
+{
+    portENTER_CRITICAL(&s_io_mux_spinlock);
+    if (enable) {
+        if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
+            s_rtc_io_using_mask |= (1ULL << gpio_num);
+        }
+        s_rtc_io_enabled_cnt[gpio_num]++;
+    } else if (!enable && (s_rtc_io_enabled_cnt[gpio_num] > 0)) {
+        s_rtc_io_enabled_cnt[gpio_num]--;
+        if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
+            s_rtc_io_using_mask &= ~(1ULL << gpio_num);
+        }
+    }
+    RTCIO_RCC_ATOMIC() {
+        if (s_rtc_io_using_mask == 0) {
+            rtcio_ll_enable_io_clock(false);
+        } else {
+            rtcio_ll_enable_io_clock(true);
+        }
+    }
+    portEXIT_CRITICAL(&s_io_mux_spinlock);
+}
+
+void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
+{
+    portENTER_CRITICAL(&s_io_mux_spinlock);
+    s_rtc_io_enabled_cnt[gpio_num] = 0;
+    s_rtc_io_using_mask &= ~(1ULL << gpio_num);
+    if (s_rtc_io_using_mask == 0) {
+        RTCIO_RCC_ATOMIC() {
+            rtcio_ll_enable_io_clock(false);
+        }
+    }
+    portEXIT_CRITICAL(&s_io_mux_spinlock);
+}
diff --git a/components/hal/esp32h21/include/hal/gpio_ll.h b/components/hal/esp32h21/include/hal/gpio_ll.h
index e01fcbee95..62c68295b5 100644
--- a/components/hal/esp32h21/include/hal/gpio_ll.h
+++ b/components/hal/esp32h21/include/hal/gpio_ll.h
@@ -544,8 +544,9 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
  */
 static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
 {
-    uint32_t val = REG_GET_BIT(GPIO_FUNC0_IN_SEL_CFG_REG + in_sig_idx * 4, GPIO_SIG0_IN_SEL);
-    return (val ? val : -1);
+    gpio_func_in_sel_cfg_reg_t reg;
+    reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
+    return (reg.sig_in_sel ? reg.func_in_sel : -1);
 }
 
 /**
@@ -689,21 +690,21 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n
  */
 static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_14) &&
-               "only gpio7~14 support deep sleep wake-up function");
+    HAL_ASSERT((gpio_num >= GPIO_NUM_5 && gpio_num <= GPIO_NUM_11) &&
+               "only gpio5~11 support deep sleep wake-up function");
 
     LP_AON.ext_wakeup_cntl.aon_ext_wakeup_filter = 1;
 
     uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel);
-    wakeup_sel_mask |= BIT(gpio_num - 7);
+    wakeup_sel_mask |= BIT(gpio_num - 5);
     HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, wakeup_sel_mask);
 
     bool trigger_level = (intr_type == GPIO_INTR_LOW_LEVEL) ? 0 : 1;
     uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv);
     if (trigger_level) {
-        wakeup_level_mask |= BIT(gpio_num - 7);
+        wakeup_level_mask |= BIT(gpio_num - 5);
     } else {
-        wakeup_level_mask &= ~BIT(gpio_num - 7);
+        wakeup_level_mask &= ~BIT(gpio_num - 5);
     }
     HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv, wakeup_level_mask);
 }
@@ -716,11 +717,11 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gp
  */
 static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_14) &&
-               "only gpio7~14 support deep sleep wake-up function");
+    HAL_ASSERT((gpio_num >= GPIO_NUM_5 && gpio_num <= GPIO_NUM_11) &&
+               "only gpio5~11 support deep sleep wake-up function");
 
     uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel);
-    wakeup_sel_mask &= ~BIT(gpio_num - 7);
+    wakeup_sel_mask &= ~BIT(gpio_num - 5);
     HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, wakeup_sel_mask);
 }
 
@@ -733,11 +734,11 @@ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t g
  */
 static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_14) &&
-               "only gpio7~14 support deep sleep wake-up function");
+    HAL_ASSERT((gpio_num >= GPIO_NUM_5 && gpio_num <= GPIO_NUM_11) &&
+               "only gpio5~11 support deep sleep wake-up function");
 
     uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel);
-    return wakeup_sel_mask & BIT(gpio_num - 7);
+    return wakeup_sel_mask & BIT(gpio_num - 5);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32h21/include/hal/rtc_io_ll.h b/components/hal/esp32h21/include/hal/rtc_io_ll.h
new file mode 100644
index 0000000000..71ad47d961
--- /dev/null
+++ b/components/hal/esp32h21/include/hal/rtc_io_ll.h
@@ -0,0 +1,123 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in hal/readme.md
+ ******************************************************************************/
+
+#pragma once
+
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "soc/lp_aon_struct.h"
+#include "soc/lpperi_struct.h"
+#include "soc/pmu_struct.h"
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTCIO_LL_GPIO_NUM_OFFSET    5 // rtcio 0-6 correspond to gpio 5-11
+
+typedef enum {
+    RTCIO_LL_FUNC_RTC = 0x0,         /*!< The pin controlled by RTC module. */
+    RTCIO_LL_FUNC_DIGITAL = 0x1,     /*!< The pin controlled by DIGITAL module. */
+} rtcio_ll_func_t;
+
+
+/**
+ * @brief Enable/Disable LP_IO peripheral clock.
+ *
+ * @param enable true to enable the clock / false to disable the clock
+ */
+static inline void _rtcio_ll_enable_io_clock(bool enable)
+{
+    LPPERI.clk_en.lp_io_ck_en = enable;
+    while (LPPERI.clk_en.lp_io_ck_en != enable) {
+        ;
+    }
+}
+
+#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__)
+
+/**
+ * @brief Select the rtcio function.
+ *
+ * @note The RTC function must be selected before the pad analog function is enabled.
+ *
+ * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
+ * @param func Select pin function.
+ */
+static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
+{
+    if (func == RTCIO_LL_FUNC_RTC) {
+        // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
+        uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, aon_gpio_mux_sel);
+        sel_mask |= BIT(rtcio_num);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, aon_gpio_mux_sel, sel_mask);
+    } else if (func == RTCIO_LL_FUNC_DIGITAL) {
+        // Clear the bit to use digital GPIO module
+        uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, aon_gpio_mux_sel);
+        sel_mask &= ~BIT(rtcio_num);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, aon_gpio_mux_sel, sel_mask);
+    }
+}
+
+/**
+ * Enable force hold function for an RTC IO pad.
+ *
+ * Enabling HOLD function will cause the pad to lock current status, such as,
+ * input/output enable, input/output value, function, drive strength values.
+ * This function is useful when going into light or deep sleep mode to prevent
+ * the pin configuration from changing.
+ *
+ * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
+ */
+static inline void rtcio_ll_force_hold_enable(int rtcio_num)
+{
+    LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num + RTCIO_LL_GPIO_NUM_OFFSET);
+}
+
+/**
+ * Disable hold function on an RTC IO pad
+ *
+ * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
+ * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
+ */
+static inline void rtcio_ll_force_hold_disable(int rtcio_num)
+{
+    LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num + RTCIO_LL_GPIO_NUM_OFFSET);
+}
+
+/**
+ * Enable force hold function for all RTC IO pads
+ *
+ * Enabling HOLD function will cause the pad to lock current status, such as,
+ * input/output enable, input/output value, function, drive strength values.
+ * This function is useful when going into light or deep sleep mode to prevent
+ * the pin configuration from changing.
+ */
+static inline void rtcio_ll_force_hold_all(void)
+{
+    PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
+}
+
+/**
+ * Disable hold function fon all RTC IO pads
+ *
+ * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
+ */
+static inline void rtcio_ll_force_unhold_all(void)
+{
+    PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
index 93a249d4d0..7794c15324 100644
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -235,6 +235,10 @@ config SOC_GPIO_PIN_COUNT
     int
     default 26
 
+config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
+    bool
+    default y
+
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y
@@ -259,6 +263,22 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y
 
+config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+    bool
+    default y
+
+config SOC_RTCIO_PIN_COUNT
+    int
+    default 7
+
+config SOC_RTCIO_HOLD_SUPPORTED
+    bool
+    default y
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32h21/include/soc/rtc_io_channel.h b/components/soc/esp32h21/include/soc/rtc_io_channel.h
new file mode 100644
index 0000000000..bb2e121b04
--- /dev/null
+++ b/components/soc/esp32h21/include/soc/rtc_io_channel.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define RTCIO_GPIO5_CHANNEL         0   //RTCIO_CHANNEL_0
+#define RTCIO_CHANNEL_0_GPIO_NUM    5
+
+#define RTCIO_GPIO6_CHANNEL         1   //RTCIO_CHANNEL_1
+#define RTCIO_CHANNEL_1_GPIO_NUM    6
+
+#define RTCIO_GPIO7_CHANNEL         2   //RTCIO_CHANNEL_2
+#define RTCIO_CHANNEL_2_GPIO_NUM    7
+
+#define RTCIO_GPIO8_CHANNEL         3   //RTCIO_CHANNEL_3
+#define RTCIO_CHANNEL_3_GPIO_NUM    8
+
+#define RTCIO_GPIO9_CHANNEL         4   //RTCIO_CHANNEL_4
+#define RTCIO_CHANNEL_4_GPIO_NUM    9
+
+#define RTCIO_GPIO10_CHANNEL        5   //RTCIO_CHANNEL_5
+#define RTCIO_CHANNEL_5_GPIO_NUM    10
+
+#define RTCIO_GPIO11_CHANNEL        6   //RTCIO_CHANNEL_6
+#define RTCIO_CHANNEL_6_GPIO_NUM    11
diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h
index 978bfacc9c..f3ed7c078e 100644
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -192,7 +192,7 @@
 #define SOC_GPIO_PIN_COUNT                      26
 // #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER      1
 // #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM         8
-// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER         1
+#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER         1
 
 // GPIO peripheral has the ETM extension
 // #define SOC_GPIO_SUPPORT_ETM          1
@@ -216,8 +216,10 @@
 
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
+// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
+#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 // Support to hold a single digital I/O when the digital domain is powered off
-// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
+#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
 // The Clock Out signal is route to the pin by GPIO matrix
 // #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
@@ -227,9 +229,8 @@
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 /* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported
  * for hold, wake & 32kHz crystal functions - via LP_AON registers */
-// #define SOC_RTCIO_PIN_COUNT         (8U)
-// #define SOC_RTCIO_HOLD_SUPPORTED    (1)
-// #define SOC_RTCIO_VALID_RTCIO_MASK  (0x7F80)
+#define SOC_RTCIO_PIN_COUNT         (7U)
+#define SOC_RTCIO_HOLD_SUPPORTED    (1)
 
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
diff --git a/components/soc/esp32h21/register/soc/gpio_struct.h b/components/soc/esp32h21/register/soc/gpio_struct.h
index 2061a6042a..b44e408838 100644
--- a/components/soc/esp32h21/register/soc/gpio_struct.h
+++ b/components/soc/esp32h21/register/soc/gpio_struct.h
@@ -352,8 +352,8 @@ typedef struct {
     uint32_t reserved_0c8[3];
     volatile gpio_pinn_reg_t pinn[30];
     uint32_t reserved_14c[98];
-    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128];  //0-128. reserved: 0-6, 17-19, 19-28, 35-40, 42-45, 56-6, 73-77, 82-87, 95-97, 124-128;
-    uint32_t reserved_4ac[384];
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256];  //0-255. reserved: 0-6, 17-19, 19-28, 35-40, 42-45, 56-6, 73-77, 82-87, 95-97, 162-255;
+    uint32_t reserved_4ac[256];
     volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[30];
     uint32_t reserved_b4c[171];
     volatile gpio_clock_gate_reg_t clock_gate;
diff --git a/components/soc/esp32h21/register/soc/io_mux_reg.h b/components/soc/esp32h21/register/soc/io_mux_reg.h
index b2ba8e00a2..55266e5e92 100644
--- a/components/soc/esp32h21/register/soc/io_mux_reg.h
+++ b/components/soc/esp32h21/register/soc/io_mux_reg.h
@@ -5,7 +5,12 @@
  */
 
 #pragma once
+
+#include <stdint.h>
 #include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
 /* Output enable in sleep mode */
@@ -98,16 +103,14 @@
 #define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
 #define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
 
-#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
 
 #define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_MTMS
 #define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_MTDO
@@ -138,14 +141,10 @@
 
 #define PIN_FUNC_GPIO								1
 
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
 #define USB_INT_PHY0_DM_GPIO_NUM      17
 #define USB_INT_PHY0_DP_GPIO_NUM      18
 
-#define EXT_OSC_SLOW_GPIO_NUM        13
+#define EXT_OSC_SLOW_GPIO_NUM        6
 
 
 #define MAX_RTC_GPIO_NUM             11             // GPIO5~11 are the pads with LP function
@@ -322,3 +321,7 @@
 #define IO_MUX_REG_DATE_M  ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S))
 #define IO_MUX_REG_DATE_V  0xFFFFFFF
 #define IO_MUX_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h21/rtc_io_periph.c b/components/soc/esp32h21/rtc_io_periph.c
new file mode 100644
index 0000000000..edb07c52a0
--- /dev/null
+++ b/components/soc/esp32h21/rtc_io_periph.c
@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/rtc_io_periph.h"
+
+const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
+    -1,//GPIO0
+    -1,//GPIO1
+    -1,//GPIO2
+    -1,//GPIO3
+    -1,//GPIO4
+    RTCIO_GPIO5_CHANNEL,//GPIO5
+    RTCIO_GPIO6_CHANNEL,//GPIO6
+    RTCIO_GPIO7_CHANNEL,//GPIO7
+    RTCIO_GPIO8_CHANNEL,//GPIO8
+    RTCIO_GPIO9_CHANNEL,//GPIO9
+    RTCIO_GPIO10_CHANNEL,//GPIO10
+    RTCIO_GPIO11_CHANNEL,//GPIO11
+    -1,//GPIO12
+    -1,//GPIO13
+    -1,//GPIO14
+    -1,//GPIO15
+    -1,//GPIO16
+    -1,//GPIO17
+    -1,//GPIO18
+    -1,//GPIO19
+    -1,//GPIO20
+    -1,//GPIO21
+    -1,//GPIO22
+    -1,//GPIO23
+    -1,//GPIO24
+    -1,//GPIO25
+};
diff --git a/docs/docs_not_updated/esp32h21.txt b/docs/docs_not_updated/esp32h21.txt
index 5b315478e6..fcc007c17a 100644
--- a/docs/docs_not_updated/esp32h21.txt
+++ b/docs/docs_not_updated/esp32h21.txt
@@ -213,7 +213,6 @@ api-reference/peripherals/parlio.rst
 api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/lp_i2s.rst
 api-reference/peripherals/ecdsa.rst
-api-reference/peripherals/gpio.rst
 api-reference/peripherals/dac.rst
 api-reference/peripherals/spi_slave.rst
 api-reference/peripherals/spi_flash/index.rst
diff --git a/docs/en/api-reference/peripherals/gpio/esp32h21.inc b/docs/en/api-reference/peripherals/gpio/esp32h21.inc
index 96eb0e5017..7b4d306d4a 100644
--- a/docs/en/api-reference/peripherals/gpio/esp32h21.inc
+++ b/docs/en/api-reference/peripherals/gpio/esp32h21.inc
@@ -25,12 +25,12 @@ The table below provides more information on pin usage, and please note the comm
     * - GPIO0
       -
       -
-      - Strapping pin
+      -
 
     * - GPIO1
       - ADC1_CH0
       -
-      - Strapping pin
+      -
 
     * - GPIO2
       - ADC1_CH1
@@ -65,7 +65,7 @@ The table below provides more information on pin usage, and please note the comm
     * - GPIO8
       -
       - LP_GPIO3
-      -
+      - Strapping pin
 
     * - GPIO9
       -
@@ -154,7 +154,7 @@ The table below provides more information on pin usage, and please note the comm
 
 .. note::
 
-    - Strapping pin: GPIO0, GPIO1, GPIO13, and GPIO14 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
+    - Strapping pin: GPIO8, GPIO13, and GPIO14 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
 	  - SPI0/1: GPIO19 ~ GPIO25 are usually used for SPI flash and not recommended for other uses.
 	  - USB-JTAG: GPIO17 and GPIO18 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled.
 
diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32h21.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32h21.inc
index 7fb05ed6be..5f08f0733d 100644
--- a/docs/zh_CN/api-reference/peripherals/gpio/esp32h21.inc
+++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32h21.inc
@@ -25,12 +25,12 @@
     * - GPIO0
       -
       -
-      - Strapping 管脚
+      -
 
     * - GPIO1
       - ADC1_CH0
       -
-      - Strapping 管脚
+      -
 
     * - GPIO2
       - ADC1_CH1
@@ -65,7 +65,7 @@
     * - GPIO8
       -
       - LP_GPIO3
-      -
+      - Strapping 管脚
 
     * - GPIO9
       -
@@ -154,7 +154,7 @@
 
 .. note::
 
-    - Strapping 管脚：GPIO0、GPIO1、GPIO13 和 GPIO14 是 Strapping 管脚。更多信息请参考 `ESP32-H21 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
+    - Strapping 管脚：GPIO8、GPIO13 和 GPIO14 是 Strapping 管脚。更多信息请参考 `ESP32-H21 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
     - SPI0/1：GPIO19 ~ GPIO25 通常用于 SPI flash，不推荐用于其他用途。
     - USB-JTAG：GPIO17 和 GPIO18 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。