diff --git a/components/driver/.build-test-rules.yml b/components/driver/.build-test-rules.yml index 23ed2a0ee6..3dff406d38 100644 --- a/components/driver/.build-test-rules.yml +++ b/components/driver/.build-test-rules.yml @@ -40,9 +40,7 @@ components/driver/test_apps/ledc: components/driver/test_apps/legacy_adc_driver: disable: - - if: IDF_TARGET == "esp32c6" - temporary: true - reason: target esp32c6 is not supported yet + - if: SOC_ADC_SUPPORTED != 1 components/driver/test_apps/legacy_mcpwm_driver: disable: diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c index 2a864463cb..b7b3e2526e 100644 --- a/components/driver/deprecated/adc_legacy.c +++ b/components/driver/deprecated/adc_legacy.c @@ -764,7 +764,7 @@ int adc1_get_raw(adc1_channel_t channel) #endif ADC_REG_LOCK_ENTER(); - adc_oneshot_ll_set_atten(ADC_UNIT_2, channel, atten); + adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten); adc_hal_convert(ADC_UNIT_1, channel, &raw_out); ADC_REG_LOCK_EXIT(); diff --git a/components/driver/test_apps/legacy_adc_driver/README.md b/components/driver/test_apps/legacy_adc_driver/README.md index b5be4985c5..7e7523ec85 100644 --- a/components/driver/test_apps/legacy_adc_driver/README.md +++ b/components/driver/test_apps/legacy_adc_driver/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c index c76a0a8e53..a5b58e9720 100644 --- a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c +++ b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c @@ -53,6 +53,13 @@ #define ADC_TEST_HIGH_VAL 3400 #define ADC_TEST_HIGH_THRESH 200 +#elif CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5312 +#define ADC_TEST_LOW_VAL 2144 +#define ADC_TEST_LOW_THRESH 200 + +#define ADC_TEST_HIGH_VAL 4081 +#define ADC_TEST_HIGH_THRESH 200 + #endif //ADC Channels diff --git a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py index 00789424d6..081f0d547e 100644 --- a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py +++ b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py @@ -9,6 +9,7 @@ from pytest_embedded import Dut @pytest.mark.esp32s2 @pytest.mark.esp32s3 @pytest.mark.esp32c3 +@pytest.mark.esp32c6 @pytest.mark.adc @pytest.mark.parametrize( 'config', diff --git a/components/esp_adc/.build-test-rules.yml b/components/esp_adc/.build-test-rules.yml index 9237324a1a..389eceee9d 100644 --- a/components/esp_adc/.build-test-rules.yml +++ b/components/esp_adc/.build-test-rules.yml @@ -2,6 +2,4 @@ components/esp_adc/test_apps/adc: disable: - - if: IDF_TARGET == "esp32c6" - temporary: true - reason: target esp32c6 is not supported yet + - if: SOC_ADC_SUPPORTED != 1 diff --git a/components/esp_adc/CMakeLists.txt b/components/esp_adc/CMakeLists.txt index fdeaf44f69..6edb190c97 100644 --- a/components/esp_adc/CMakeLists.txt +++ b/components/esp_adc/CMakeLists.txt @@ -32,15 +32,6 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/deprecated/${target}/esp_adc_cal_legacy.c list(APPEND srcs "deprecated/${target}/esp_adc_cal_legacy.c") endif() -# ESP32C6-TODO -if(CONFIG_IDF_TARGET_ESP32C6) - list(REMOVE_ITEM srcs - "adc_cali_curve_fitting.c" # TODO: IDF-5312 - "adc_oneshot.c" # TODO: IDF-5310 - "adc_common.c" - ) -endif() - idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} PRIV_REQUIRES driver efuse diff --git a/components/esp_adc/test_apps/adc/README.md b/components/esp_adc/test_apps/adc/README.md index b5be4985c5..7e7523ec85 100644 --- a/components/esp_adc/test_apps/adc/README.md +++ b/components/esp_adc/test_apps/adc/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_adc/test_apps/adc/main/test_common_adc.h b/components/esp_adc/test_apps/adc/main/test_common_adc.h index 1deb93c68b..d822404a3f 100644 --- a/components/esp_adc/test_apps/adc/main/test_common_adc.h +++ b/components/esp_adc/test_apps/adc/main/test_common_adc.h @@ -70,6 +70,14 @@ extern "C" { #define ADC_TEST_HIGH_VAL 3400 #define ADC_TEST_HIGH_THRESH 200 + +#elif CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5312 +#define ADC_TEST_LOW_VAL 2144 +#define ADC_TEST_LOW_THRESH 200 + +#define ADC_TEST_HIGH_VAL 4081 +#define ADC_TEST_HIGH_VAL_DMA 4081 +#define ADC_TEST_HIGH_THRESH 200 #endif diff --git a/components/esp_adc/test_apps/adc/pytest_adc.py b/components/esp_adc/test_apps/adc/pytest_adc.py index 6b87bc81d1..31ce345c8d 100644 --- a/components/esp_adc/test_apps/adc/pytest_adc.py +++ b/components/esp_adc/test_apps/adc/pytest_adc.py @@ -9,6 +9,7 @@ from pytest_embedded import Dut @pytest.mark.esp32s2 @pytest.mark.esp32s3 @pytest.mark.esp32c3 +@pytest.mark.esp32c6 @pytest.mark.adc @pytest.mark.parametrize('config', [ 'iram_safe', diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 7a0ac71c50..0d35e41999 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -70,13 +70,6 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "esp_ds.c") endif() - # ESP32C6-TODO - if(CONFIG_IDF_TARGET_ESP32C6) - list(REMOVE_ITEM srcs - "adc_share_hw_ctrl.c" # TODO: IDF-5312 - ) - endif() - else() # Requires "_esp_error_check_failed()" function list(APPEND priv_requires "esp_system") diff --git a/components/esp_hw_support/port/esp32c6/rtc_init.c b/components/esp_hw_support/port/esp32c6/rtc_init.c index 60a77df39a..0d418b5a6a 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_init.c +++ b/components/esp_hw_support/port/esp32c6/rtc_init.c @@ -13,8 +13,10 @@ void rtc_init(rtc_config_t cfg) { + /* Peripheral reg i2c power up */ SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index bb638925e5..234d90d294 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -191,11 +191,6 @@ if(NOT BOOTLOADER_BUILD) "esp32c6/brownout_hal.c" "esp32c6/rtc_cntl_hal.c") - # TODO: IDF-5310 - list(REMOVE_ITEM srcs - "adc_oneshot_hal.c" - "adc_hal_common.c" - ) endif() if(${target} STREQUAL "esp32h2") diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index eafc2fcf10..7b8dd16237 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -141,11 +141,8 @@ void adc_hal_digi_deinit(adc_hal_dma_ctx_t *hal) ---------------------------------------------------------------*/ static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t convert_mode) { -#if CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 || SOC_ADC_DIGI_CONTROLLER_NUM == 1 return ADC_LL_DIGI_CONV_ONLY_ADC1; -#endif -#if (SOC_ADC_DIGI_CONTROLLER_NUM == 1) - return ADC_LL_DIGI_CONV_ALTER_UNIT; #elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2) switch (convert_mode) { case ADC_CONV_SINGLE_UNIT_1: diff --git a/components/hal/esp32/include/hal/adc_ll.h b/components/hal/esp32/include/hal/adc_ll.h index dff4e6d3a7..0f93dcb607 100644 --- a/components/hal/esp32/include/hal/adc_ll.h +++ b/components/hal/esp32/include/hal/adc_ll.h @@ -13,6 +13,7 @@ #include "soc/adc_periph.h" #include "soc/rtc_io_struct.h" #include "soc/sens_struct.h" +#include "soc/sens_reg.h" #include "soc/syscon_struct.h" #include "soc/rtc_cntl_struct.h" #include "soc/clk_tree_defs.h" @@ -46,12 +47,6 @@ typedef enum { ADC_LL_CTRL_PWDET = 3, ///< For ADC2. Select PWDET controller. } adc_ll_controller_t; -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - /** * @brief ADC digital controller (DMA mode) work mode. * diff --git a/components/hal/esp32c2/include/hal/adc_ll.h b/components/hal/esp32c2/include/hal/adc_ll.h index 89a6a986f1..89320fc4d1 100644 --- a/components/hal/esp32c2/include/hal/adc_ll.h +++ b/components/hal/esp32c2/include/hal/adc_ll.h @@ -51,12 +51,6 @@ typedef enum { ADC_LL_CTRL_DIG = 0, ///< For ADC1. Select DIG controller. } adc_ll_controller_t; -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - /*--------------------------------------------------------------- Digital controller setting ---------------------------------------------------------------*/ @@ -150,9 +144,9 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div * * @param clk_src clock source for ADC digital controller. */ -static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) { - APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clk_sel = (clk_src == ADC_DIGI_CLK_SRC_XTAL); + APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clk_sel = 2; APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; } diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h index 117e43dbe5..f76656afb4 100644 --- a/components/hal/esp32c3/include/hal/adc_ll.h +++ b/components/hal/esp32c3/include/hal/adc_ll.h @@ -36,8 +36,8 @@ extern "C" { #define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31) #define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) #define ADC_LL_EVENT_THRES0_HIGH BIT(29) -#define ADC_LL_event_THRES1_HIGH BIT(28) -#define ADC_LL_event_THRES0_LOW BIT(27) +#define ADC_LL_EVENT_THRES1_HIGH BIT(28) +#define ADC_LL_EVENT_THRES0_LOW BIT(27) #define ADC_LL_EVENT_THRES1_LOW BIT(26) typedef enum { @@ -59,21 +59,15 @@ typedef enum { ADC_LL_CTRL_ARB = 1, ///< For ADC2. The controller is selected by the arbiter. } adc_ll_controller_t; -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - /** * @brief ADC digital controller (DMA mode) work mode. * * @note The conversion mode affects the sampling frequency: - * ESP32C3 only support ALTER_UNIT mode - * ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately. + * ESP32C3 only support ONLY_ADC1 mode + * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. */ typedef enum { - ADC_LL_DIGI_CONV_ALTER_UNIT = 0, // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 ..... + ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion } adc_ll_digi_convert_mode_t; typedef struct { @@ -166,7 +160,7 @@ static inline void adc_ll_digi_convert_limit_enable(bool enable) */ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) { - //ESP32C3 only supports ADC_CONV_ALTER_UNIT mode + //ESP32C3 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode } /** @@ -292,10 +286,10 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div * * @param clk_src clock source for ADC digital controller. */ -static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) { - // Only support APB clock, should always set to 0 - APB_SARADC.apb_adc_clkm_conf.clk_sel = 0; + // Only support APB clock, should always set to 1 or 2 + APB_SARADC.apb_adc_clkm_conf.clk_sel = 2; APB_SARADC.ctrl.sar_clk_gated = 1; } @@ -647,6 +641,60 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param } /* Temp code end. */ +/** + * Output ADCn inter reference voltage to ADC2 channels. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC1's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @param[in] adc ADC unit select + * @param[in] channel ADC1 channel number + * @param[in] en Enable/disable the reference voltage output + */ +static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en) +{ + if (en) { + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3); + SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); + + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF; + APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF; + APB_SARADC.onetime_sample.adc1_onetime_sample = 1; + APB_SARADC.onetime_sample.onetime_channel = channel; + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); + if (adc == ADC_UNIT_1) { + /* Config test mux to route v_ref to ADC1 Channels */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); + } else { + /* Config test mux to route v_ref to ADC2 Channels */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + } + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + APB_SARADC.onetime_sample.adc1_onetime_sample = 0; + APB_SARADC.onetime_sample.onetime_channel = 0xf; + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0); + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + } +} + /*--------------------------------------------------------------- Oneshot Read ---------------------------------------------------------------*/ diff --git a/components/hal/esp32c6/include/hal/adc_hal_conf.h b/components/hal/esp32c6/include/hal/adc_hal_conf.h index 55e742d388..1cafdf935f 100644 --- a/components/hal/esp32c6/include/hal/adc_hal_conf.h +++ b/components/hal/esp32c6/include/hal/adc_hal_conf.h @@ -10,7 +10,7 @@ Single Read ---------------------------------------------------------------*/ #define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) -#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1) +#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2) /*--------------------------------------------------------------- DMA Read diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h index fca4c7909f..9dd051b716 100644 --- a/components/hal/esp32c6/include/hal/adc_ll.h +++ b/components/hal/esp32c6/include/hal/adc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,6 +20,7 @@ #include "hal/adc_types.h" #include "hal/adc_types_private.h" #include "hal/regi2c_ctrl.h" +#include "hal/sar_ctrl_ll.h" #include "soc/regi2c_saradc.h" @@ -36,49 +37,30 @@ extern "C" { #define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31) #define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) #define ADC_LL_EVENT_THRES0_HIGH BIT(29) -#define ADC_LL_event_THRES1_HIGH BIT(28) -#define ADC_LL_event_THRES0_LOW BIT(27) +#define ADC_LL_EVENT_THRES1_HIGH BIT(28) +#define ADC_LL_EVENT_THRES0_LOW BIT(27) #define ADC_LL_EVENT_THRES1_LOW BIT(26) typedef enum { - ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ + ADC_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ ADC_POWER_MAX, /*!< For parameter check. */ } adc_ll_power_t; typedef enum { - ADC_RTC_DATA_OK = 0, - ADC_RTC_CTRL_UNSELECTED = 1, - ADC_RTC_CTRL_BREAK = 2, - ADC_RTC_DATA_FAIL = -1, -} adc_ll_rtc_raw_data_t; - -typedef enum { - ADC_LL_CTRL_DIG = 0, ///< Only support ADC1, i.e. only digital controller available. + ADC_LL_CTRL_DIG = 0, ///< ADC digital controller } adc_ll_controller_t; -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - /** * @brief ADC digital controller (DMA mode) work mode. * * @note The conversion mode affects the sampling frequency: - * ESP32C3 only support ALTER_UNIT mode - * ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately. + * ESP32C6 only support ONLY_ADC1 mode + * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. */ typedef enum { - ADC_LL_DIGI_CONV_ALTER_UNIT = 0, // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 ..... + ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion } adc_ll_digi_convert_mode_t; typedef struct { @@ -123,9 +105,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa */ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) { - // TODO: [adc_c6] Maybe this REG I2C for peripheral needs a reference lock - /* Should be called before writing I2C registers. */ - SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); + /* Peripheral reg i2c has powered up in rtc_init, write directly */ REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); } @@ -137,7 +117,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) */ static inline void adc_ll_digi_set_clk_div(uint32_t div) { - /* ADC clock devided from digital controller clock clk */ + /* ADC clock divided from digital controller clock clk */ HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div); } @@ -166,18 +146,18 @@ static inline void adc_ll_digi_convert_limit_enable(bool enable) /** * Set adc conversion mode for digital controller. * - * @note ESP32C3 only support ADC1 single mode. + * @note ESP32C6 only support ADC1 single mode. * * @param mode Conversion mode select. */ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) { - //ESP32C3 only supports ADC_CONV_ALTER_UNIT mode + //ESP32C6 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode } /** * Set pattern table length for digital controller. - * The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection, + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, * and attenuation are stored. When the conversion is started, the controller reads conversion rules from the * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. * @@ -191,7 +171,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t /** * Set pattern table for digital controller. - * The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection, + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. * @@ -208,15 +188,15 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5); if (index == 0) { - tab = APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1; // Read old register value - tab &= (~(0xFC0000 >> offset)); // Clear old data - tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data - APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back + tab = APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back } else { - tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2; // Read old register value - tab &= (~(0xFC0000 >> offset)); // Clear old data - tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data - APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = tab; // Write back + tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = tab; // Write back } } @@ -252,8 +232,6 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en) { if (adc_n == ADC_UNIT_1) { APB_SARADC.saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert - } else { // adc_n == ADC_UNIT_2 - APB_SARADC.saradc_ctrl2.saradc_saradc_sar2_inv = inv_en; // Enable / Disable ADC data invert } } @@ -305,7 +283,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div * * @param clk_src clock source for ADC digital controller. */ -static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) { switch (clk_src) { case ADC_DIGI_CLK_SRC_XTAL: @@ -318,10 +296,10 @@ static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) PCR.saradc_clkm_conf.saradc_clkm_sel = 2; break; default: - PCR.saradc_clkm_conf.saradc_clkm_sel = 1; + HAL_ASSERT(false && "unsupported clock"); } // Enable ADC_CTRL_CLK (i.e. digital domain clock) - PCR.saradc_clkm_conf.saradc_clkm_en = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; } /** @@ -329,7 +307,7 @@ static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) */ static inline void adc_ll_digi_controller_clk_disable(void) { - PCR.saradc_clkm_conf.saradc_clkm_en = 0; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; } /** @@ -480,9 +458,7 @@ static inline void adc_ll_digi_reset(void) */ static inline void adc_ll_pwdet_set_cct(uint32_t cct) { - /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - // RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; - // TODO: [adc_c6] check cct validation on C6 + (void)cct; } /** @@ -493,9 +469,6 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct) */ static inline uint32_t adc_ll_pwdet_get_cct(void) { - /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - // return RTCCNTL.sensor_ctrl.sar2_pwdet_cct; - // TODO: [adc_c6] check cct validation on C6 return 0; } @@ -512,13 +485,13 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage) /* Bit1 0:Fsm 1: SW mode Bit0 0:SW mode power down 1: SW mode power on */ if (manage == ADC_POWER_SW_ON) { - PCR.saradc_clkm_conf.saradc_clkm_en = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; } else if (manage == ADC_POWER_BY_FSM) { - PCR.saradc_clkm_conf.saradc_clkm_en = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0; } else if (manage == ADC_POWER_SW_OFF) { - PCR.saradc_clkm_conf.saradc_clkm_en = 0; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2; } } @@ -536,11 +509,8 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c __attribute__((always_inline)) static inline void adc_ll_calibration_init(adc_unit_t adc_n) { - if (adc_n == ADC_UNIT_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); - } + HAL_ASSERT(adc_n == ADC_UNIT_1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); } /** @@ -554,19 +524,12 @@ static inline void adc_ll_calibration_init(adc_unit_t adc_n) */ static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gnd) { + HAL_ASSERT(adc_n == ADC_UNIT_1); /* Enable/disable internal connect GND (for calibration). */ - if (adc_n == ADC_UNIT_1) { - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); - } + if (internal_gnd) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); } else { - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); - } + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); } } @@ -577,11 +540,8 @@ static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gn */ static inline void adc_ll_calibration_finish(adc_unit_t adc_n) { - if (adc_n == ADC_UNIT_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); - } + HAL_ASSERT(adc_n == ADC_UNIT_1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); } /** @@ -594,17 +554,12 @@ static inline void adc_ll_calibration_finish(adc_unit_t adc_n) __attribute__((always_inline)) static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param) { + HAL_ASSERT(adc_n == ADC_UNIT_1); uint8_t msb = param >> 8; uint8_t lsb = param & 0xFF; - if (adc_n == ADC_UNIT_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); - } + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); } -/* Temp code end. */ /*--------------------------------------------------------------- Oneshot Read @@ -612,13 +567,13 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param /** * Set adc output data format for oneshot mode * - * @note ESP32C3 Oneshot mode only supports 12bit. + * @note ESP32C6 Oneshot mode only supports 12bit. * @param adc_n ADC unit. * @param bits Output data bits width option. */ static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits) { - //ESP32C3 only supports 12bit, leave here for compatibility + //ESP32C6 only supports 12bit, leave here for compatibility HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT); } @@ -632,6 +587,7 @@ static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth */ static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel) { + HAL_ASSERT(adc_n == ADC_UNIT_1); APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | channel); } @@ -644,11 +600,8 @@ static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t ch */ static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n) { - if (adc_n == ADC_UNIT_1) { - APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF); - } else { // adc_n == ADC_UNIT_2 - APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0x1); - } + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF); } /** @@ -688,7 +641,7 @@ static inline bool adc_oneshot_ll_get_event(uint32_t event_mask) } /** - * Get the converted value for each ADCn for RTC controller. + * Get the converted value for each ADCn for controller. * * @param adc_n ADC unit. * @return @@ -696,12 +649,9 @@ static inline bool adc_oneshot_ll_get_event(uint32_t event_mask) */ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n) { + HAL_ASSERT(adc_n == ADC_UNIT_1); uint32_t ret_val = 0; - if (adc_n == ADC_UNIT_1) { - ret_val = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff; - } else { // adc_n == ADC_UNIT_2 - ret_val = APB_SARADC.saradc_sar2data_status.saradc_apb_saradc2_data & 0xfff; - } + ret_val = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff; return ret_val; } @@ -717,15 +667,7 @@ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n) */ static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data) { - if (adc_n == ADC_UNIT_1) { - return true; - } - - //The raw data API returns value without channel information. Read value directly from the register - if (((APB_SARADC.saradc_sar2data_status.saradc_apb_saradc2_data >> 13) & 0xF) > 9) { - return false; - } - + HAL_ASSERT(adc_n == ADC_UNIT_1); return true; } @@ -737,7 +679,7 @@ static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw */ static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en) { - (void)adc_n; + HAL_ASSERT(adc_n == ADC_UNIT_1); (void)inv_en; //For compatibility } @@ -749,11 +691,8 @@ static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en) */ static inline void adc_oneshot_ll_enable(adc_unit_t adc_n) { - if (adc_n == ADC_UNIT_1) { - APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1; - } else { - APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 1; - } + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1; } /** @@ -776,7 +715,7 @@ static inline void adc_oneshot_ll_disable_all_unit(void) */ static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten) { - (void)adc_n; + HAL_ASSERT(adc_n == ADC_UNIT_1); (void)channel; // Attenuation is for all channels, unit and channel are for compatibility APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = atten; @@ -792,7 +731,7 @@ static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t chan __attribute__((always_inline)) static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel) { - (void)adc_n; + HAL_ASSERT(adc_n == ADC_UNIT_1); (void)channel; return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten; } diff --git a/components/hal/esp32h4/include/hal/adc_ll.h b/components/hal/esp32h4/include/hal/adc_ll.h index 5510fd98fc..a187cfc1fa 100644 --- a/components/hal/esp32h4/include/hal/adc_ll.h +++ b/components/hal/esp32h4/include/hal/adc_ll.h @@ -54,21 +54,15 @@ typedef enum { ADC_LL_CTRL_ARB = 1, ///< For ADC2. The controller is selected by the arbiter. } adc_ll_controller_t; -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - /** * @brief ADC digital controller (DMA mode) work mode. * * @note The conversion mode affects the sampling frequency: - * ESP32H4 only support ALTER_UNIT mode - * ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately. + * ESP32H4 only support ONLY_ADC1 mode + * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. */ typedef enum { - ADC_LL_DIGI_CONV_ALTER_UNIT = 0, // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 ..... + ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion } adc_ll_digi_convert_mode_t; //These values should be set according to the HW @@ -172,7 +166,7 @@ static inline void adc_ll_digi_convert_limit_enable(bool enable) */ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) { - //ESP32H4 only supports ADC_CONV_ALTER_UNIT mode + //ESP32H4 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode } /** @@ -298,7 +292,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div * * @param clk_src clock source for ADC digital controller. */ -static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) { // TODO: temporary support APB_SARADC.apb_adc_clkm_conf.clk_sel = 0; diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h index edf7f040d0..fc8f730a05 100644 --- a/components/hal/esp32s2/include/hal/adc_ll.h +++ b/components/hal/esp32s2/include/hal/adc_ll.h @@ -14,6 +14,7 @@ #include "hal/assert.h" #include "soc/apb_saradc_struct.h" #include "soc/sens_struct.h" +#include "soc/sens_reg.h" #include "soc/apb_saradc_reg.h" #include "soc/rtc_cntl_struct.h" #include "soc/rtc_cntl_reg.h" @@ -56,12 +57,6 @@ typedef enum { ADC_LL_CTRL_ARB = 3, ///< For ADC2. The controller is selected by the arbiter. } adc_ll_controller_t; -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - /** * @brief ADC digital controller (DMA mode) work mode. * @@ -344,7 +339,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div * * @param clk_src clock source for ADC digital controller. */ -static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) { APB_SARADC.apb_adc_clkm_conf.clk_sel = (clk_src == ADC_DIGI_CLK_SRC_APLL) ? 1 : 2; APB_SARADC.ctrl.sar_clk_gated = 1; diff --git a/components/hal/esp32s3/include/hal/adc_ll.h b/components/hal/esp32s3/include/hal/adc_ll.h index 3793660e59..e0a5e8d03b 100644 --- a/components/hal/esp32s3/include/hal/adc_ll.h +++ b/components/hal/esp32s3/include/hal/adc_ll.h @@ -57,12 +57,6 @@ typedef enum { ADC_LL_CTRL_ARB = 3, ///< For ADC2. The controller is selected by the arbiter. } adc_ll_controller_t; -/** - * @brief Clock source of ADC digital controller - * @note Not public as it always uses a default value for now - */ -typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t; - /** * @brief ADC digital controller (DMA mode) work mode. * @@ -350,7 +344,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div * * @param clk_src clock source for ADC digital controller. */ -static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src) +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) { APB_SARADC.apb_adc_clkm_conf.clk_sel = (clk_src == ADC_DIGI_CLK_SRC_APB) ? 2 : 1; APB_SARADC.ctrl.sar_clk_gated = 1; diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h index 9f06cb236f..8568c195c5 100644 --- a/components/hal/include/hal/adc_types.h +++ b/components/hal/include/hal/adc_types.h @@ -9,6 +9,7 @@ #include #include "sdkconfig.h" #include "soc/soc_caps.h" +#include "soc/clk_tree_defs.h" #include "esp_attr.h" /** @@ -78,6 +79,14 @@ typedef enum { ADC_DIGI_OUTPUT_FORMAT_TYPE2, ///< See `adc_digi_output_data_t.type2` } adc_digi_output_format_t; +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED +typedef soc_periph_adc_digi_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses digital controller +typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller +#elif SOC_ADC_RTC_CTRL_SUPPORTED +typedef soc_periph_adc_rtc_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses RTC controller +typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller +#endif + /** * @brief ADC digital controller pattern configuration */ @@ -155,6 +164,26 @@ typedef struct { uint32_t val; /*! ADC_CHANNEL_MAX), The data is invalid. */ + uint32_t reserved17_31: 15; /*!type1.channel) +#define EXAMPLE_ADC_GET_DATA(p_data) ((p_data)->type1.data) #else -#define EXAMPLE_ADC_OUTPUT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE2 +#define EXAMPLE_ADC_OUTPUT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE2 +#define EXAMPLE_ADC_GET_CHANNEL(p_data) ((p_data)->type2.channel) +#define EXAMPLE_ADC_GET_DATA(p_data) ((p_data)->type2.data) #endif +#define EXAMPLE_READ_LEN 256 + #if CONFIG_IDF_TARGET_ESP32 static adc_channel_t channel[2] = {ADC_CHANNEL_6, ADC_CHANNEL_7}; #else @@ -61,16 +70,14 @@ static void continuous_adc_init(adc_channel_t *channel, uint8_t channel_num, adc adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0}; dig_cfg.pattern_num = channel_num; for (int i = 0; i < channel_num; i++) { - uint8_t unit = ADC_UNIT_1; - uint8_t ch = channel[i] & 0x7; - adc_pattern[i].atten = ADC_ATTEN_DB_0; - adc_pattern[i].channel = ch; - adc_pattern[i].unit = unit; - adc_pattern[i].bit_width = SOC_ADC_DIGI_MAX_BITWIDTH; + adc_pattern[i].atten = EXAMPLE_ADC_ATTEN; + adc_pattern[i].channel = channel[i] & 0x7; + adc_pattern[i].unit = EXAMPLE_ADC_UNIT; + adc_pattern[i].bit_width = EXAMPLE_ADC_BIT_WIDTH; - ESP_LOGI(TAG, "adc_pattern[%d].atten is :%x", i, adc_pattern[i].atten); - ESP_LOGI(TAG, "adc_pattern[%d].channel is :%x", i, adc_pattern[i].channel); - ESP_LOGI(TAG, "adc_pattern[%d].unit is :%x", i, adc_pattern[i].unit); + ESP_LOGI(TAG, "adc_pattern[%d].atten is :%"PRIx8, i, adc_pattern[i].atten); + ESP_LOGI(TAG, "adc_pattern[%d].channel is :%"PRIx8, i, adc_pattern[i].channel); + ESP_LOGI(TAG, "adc_pattern[%d].unit is :%"PRIx8, i, adc_pattern[i].unit); } dig_cfg.adc_pattern = adc_pattern; ESP_ERROR_CHECK(adc_continuous_config(handle, &dig_cfg)); @@ -78,21 +85,6 @@ static void continuous_adc_init(adc_channel_t *channel, uint8_t channel_num, adc *out_handle = handle; } -static bool check_valid_data(const adc_digi_output_data_t *data) -{ -#if EXAMPLE_ADC_USE_OUTPUT_TYPE1 - if (data->type1.channel >= SOC_ADC_CHANNEL_NUM(ADC_UNIT_1)) { - return false; - } -#else - if (data->type2.channel >= SOC_ADC_CHANNEL_NUM(ADC_UNIT_1)) { - return false; - } -#endif - - return true; -} - void app_main(void) { esp_err_t ret; @@ -123,20 +115,21 @@ void app_main(void) */ ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + char unit[] = EXAMPLE_ADC_UNIT_STR(EXAMPLE_ADC_UNIT); + while (1) { ret = adc_continuous_read(handle, result, EXAMPLE_READ_LEN, &ret_num, 0); if (ret == ESP_OK) { ESP_LOGI("TASK", "ret is %x, ret_num is %"PRIu32, ret, ret_num); for (int i = 0; i < ret_num; i += SOC_ADC_DIGI_RESULT_BYTES) { adc_digi_output_data_t *p = (void*)&result[i]; - if (check_valid_data(p)) { - #if EXAMPLE_ADC_USE_OUTPUT_TYPE1 - ESP_LOGI(TAG, "Unit: %d, Channel: %d, Value: %x", 1, p->type1.channel, p->type1.data); - #else - ESP_LOGI(TAG, "Unit: %d,_Channel: %d, Value: %x", 1, p->type2.channel, p->type2.data); - #endif + uint32_t chan_num = EXAMPLE_ADC_GET_CHANNEL(p); + uint32_t data = EXAMPLE_ADC_GET_DATA(p); + /* Check the channel number validation, the data is invalid if the channel num exceed the maximum channel */ + if (chan_num < SOC_ADC_CHANNEL_NUM(EXAMPLE_ADC_UNIT)) { + ESP_LOGI(TAG, "Unit: %s, Channel: %"PRIu32", Value: %"PRIx32, unit, chan_num, data); } else { - ESP_LOGI(TAG, "Invalid data"); + ESP_LOGW(TAG, "Invalid data [%s_%"PRIu32"_%"PRIx32"]", unit, chan_num, data); } } /** diff --git a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py index c4156a7865..556ddff5f5 100644 --- a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py +++ b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py @@ -9,6 +9,7 @@ from pytest_embedded.dut import Dut @pytest.mark.esp32s2 @pytest.mark.esp32s3 @pytest.mark.esp32c3 +@pytest.mark.esp32c6 @pytest.mark.adc def test_adc_continuous(dut: Dut) -> None: res = dut.expect(r'TASK: ret is 0, ret_num is (\d+)') diff --git a/examples/peripherals/adc/oneshot_read/README.md b/examples/peripherals/adc/oneshot_read/README.md index 93700344f8..8cbce51458 100644 --- a/examples/peripherals/adc/oneshot_read/README.md +++ b/examples/peripherals/adc/oneshot_read/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ADC Single Read Example diff --git a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py index 8f2c266e99..af2b45cfd1 100644 --- a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py +++ b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py @@ -9,6 +9,7 @@ from pytest_embedded.dut import Dut @pytest.mark.esp32s2 @pytest.mark.esp32s3 @pytest.mark.esp32c3 +@pytest.mark.esp32c6 @pytest.mark.adc def test_adc_oneshot(dut: Dut) -> None: dut.expect(r'EXAMPLE: ADC1 Channel\[(\d+)\] Raw Data: (\d+)', timeout=5)