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Merge branch 'bugfix/periph_clk_init_p4' into 'master'

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fix(esp_system): hp periph clk should not be gated on core/system reset

Closes FCS-1638

See merge request espressif/esp-idf!35317
This commit is contained in:
Song Ruo Jing
2024-12-03 15:45:28 +08:00
parent bcd80c92f3 7b852faf66
commit 547fa88a44
3 changed files with 37 additions and 26 deletions
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6
components/bootloader_support/src/bootloader_console.c
View File

@@ -74,6 +74,12 @@ void bootloader_console_init(void)
// Enable the peripheral // Enable the peripheral
uart_ll_enable_bus_clock(uart_num, true); uart_ll_enable_bus_clock(uart_num, true);
uart_ll_reset_register(uart_num); uart_ll_reset_register(uart_num);
// Set clock source
#if SOC_UART_SUPPORT_XTAL_CLK
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_XTAL);
#else
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_APB);
#endif
// Reset TX and RX FIFOs // Reset TX and RX FIFOs
uart_ll_txfifo_rst(UART_LL_GET_HW(uart_num)); uart_ll_txfifo_rst(UART_LL_GET_HW(uart_num));
uart_ll_rxfifo_rst(UART_LL_GET_HW(uart_num)); uart_ll_rxfifo_rst(UART_LL_GET_HW(uart_num));

2
components/esp_system/port/soc/esp32c6/clk.c
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@@ -316,8 +316,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \
|| (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) { || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
_lp_i2c_ll_enable_bus_clock(0, false); _lp_i2c_ll_enable_bus_clock(0, false);
_lp_uart_ll_enable_bus_clock(0, false);
lp_uart_ll_sclk_disable(0); lp_uart_ll_sclk_disable(0);
_lp_uart_ll_enable_bus_clock(0, false);
lp_core_ll_enable_bus_clock(false); lp_core_ll_enable_bus_clock(false);
_lp_clkrst_ll_enable_rng_clock(false); _lp_clkrst_ll_enable_rng_clock(false);

15
components/esp_system/port/soc/esp32p4/clk.c
View File

@@ -244,9 +244,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
} }
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if ((rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU_MWDT) \ // HP related clock control
&& (rst_reason != RESET_REASON_CPU_RWDT) && (rst_reason != RESET_REASON_CPU_JTAG) \ if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)) {
&& (rst_reason != RESET_REASON_CPU_LOCKUP)) { // hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp
_gdma_ll_enable_bus_clock(0, false); _gdma_ll_enable_bus_clock(0, false);
_gdma_ll_enable_bus_clock(1, false); _gdma_ll_enable_bus_clock(1, false);
_pau_ll_enable_bus_clock(false); _pau_ll_enable_bus_clock(false);
@@ -357,12 +357,16 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#endif #endif
} }
// LP related clock control
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \
|| (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) { || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) {
_lp_uart_ll_enable_bus_clock(0, false); // lpperi,lp peripheral registers get reset for reset level equal or higher than system reset
lp_uart_ll_sclk_disable(0); lp_uart_ll_sclk_disable(0);
_lp_uart_ll_enable_bus_clock(0, false);
_rtcio_ll_enable_io_clock(false); _rtcio_ll_enable_io_clock(false);
// LP_Peri & Clock Control
if (rst_reason == RESET_REASON_CHIP_POWER_ON) {
// lp_aon_clkrst, lp_system registers get reset only if chip reset
_uart_ll_enable_pad_sleep_clock(&UART0, false); _uart_ll_enable_pad_sleep_clock(&UART0, false);
_uart_ll_enable_pad_sleep_clock(&UART1, false); _uart_ll_enable_pad_sleep_clock(&UART1, false);
_uart_ll_enable_pad_sleep_clock(&UART2, false); _uart_ll_enable_pad_sleep_clock(&UART2, false);
@@ -386,4 +390,5 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#endif #endif
REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN); REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN);
} }
}
} }