From 55ff2325c51e90ab5097ff31377df38b29fa6e58 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 11 Oct 2024 14:39:20 +0800 Subject: [PATCH] change(esp_hw_support): improve gpio deepsleep wakeup configuration code --- .../include/esp_private/io_mux.h | 2 +- components/esp_hw_support/sleep_modes.c | 22 ++++++++++++------- .../esp32c5/beta3/include/soc/io_mux_reg.h | 2 +- .../soc/esp32c5/mp/include/soc/io_mux_reg.h | 2 +- .../soc/esp32c6/include/soc/io_mux_reg.h | 2 +- .../soc/esp32c61/include/soc/io_mux_reg.h | 2 +- .../soc/esp32p4/include/soc/io_mux_reg.h | 2 +- 7 files changed, 20 insertions(+), 14 deletions(-) diff --git a/components/esp_hw_support/include/esp_private/io_mux.h b/components/esp_hw_support/include/esp_private/io_mux.h index dd8ea49ffb..34d5fdce8f 100644 --- a/components/esp_hw_support/include/esp_private/io_mux.h +++ b/components/esp_hw_support/include/esp_private/io_mux.h @@ -32,7 +32,7 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src); #if SOC_LP_IO_CLOCK_IS_INDEPENDENT typedef struct { - uint8_t rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM]; + uint8_t rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM + 1]; uint32_t rtc_io_using_mask; } rtc_io_status_t; diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 4d38a17a3d..b9c4fbdead 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -1925,8 +1925,9 @@ uint64_t esp_sleep_get_gpio_wakeup_status(void) static void gpio_deep_sleep_wakeup_prepare(void) { - for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++) { - if (((1ULL << gpio_idx) & s_config.gpio_wakeup_mask) == 0) { + uint32_t valid_wake_io_mask = SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK; + for (gpio_num_t gpio_idx = __builtin_ctz(valid_wake_io_mask); valid_wake_io_mask >> gpio_idx; gpio_idx++) { + if ((s_config.gpio_wakeup_mask & BIT64(gpio_idx)) == 0) { continue; } #if CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS @@ -1952,13 +1953,18 @@ esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepslee } gpio_int_type_t intr_type = ((mode == ESP_GPIO_WAKEUP_GPIO_LOW) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL); esp_err_t err = ESP_OK; - for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++, gpio_pin_mask >>= 1) { - if ((gpio_pin_mask & 1) == 0) { - continue; + uint64_t invalid_io_mask = gpio_pin_mask & ~SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK; + if (invalid_io_mask != 0) { + for (gpio_num_t gpio_idx = __builtin_ctzll(invalid_io_mask); invalid_io_mask >> gpio_idx; gpio_idx++) { + if (invalid_io_mask & BIT64(gpio_idx)) { + ESP_LOGE(TAG, "gpio %d is an invalid deep sleep wakeup IO", gpio_idx); + return ESP_ERR_INVALID_ARG; + } } - if (!esp_sleep_is_valid_wakeup_gpio(gpio_idx)) { - ESP_LOGE(TAG, "gpio %d is an invalid deep sleep wakeup IO", gpio_idx); - return ESP_ERR_INVALID_ARG; + } + for (gpio_num_t gpio_idx = __builtin_ctzll(gpio_pin_mask); gpio_pin_mask >> gpio_idx; gpio_idx++) { + if ((gpio_pin_mask & BIT64(gpio_idx)) == 0) { + continue; } err = gpio_deep_sleep_wakeup_enable(gpio_idx, intr_type); diff --git a/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h b/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h index 2cb8bd4349..6b7fdbf4f1 100644 --- a/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h +++ b/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h @@ -147,7 +147,7 @@ extern "C" { #define EXT_OSC_SLOW_GPIO_NUM 0 -#define MAX_RTC_GPIO_NUM 8 +#define MAX_RTC_GPIO_NUM 7 #define MAX_PAD_GPIO_NUM 26 #define MAX_GPIO_NUM 30 #define DIG_IO_HOLD_BIT_SHIFT 32 diff --git a/components/soc/esp32c5/mp/include/soc/io_mux_reg.h b/components/soc/esp32c5/mp/include/soc/io_mux_reg.h index 1a9dec1b88..dee1873ce8 100644 --- a/components/soc/esp32c5/mp/include/soc/io_mux_reg.h +++ b/components/soc/esp32c5/mp/include/soc/io_mux_reg.h @@ -144,7 +144,7 @@ extern "C" { #define EXT_OSC_SLOW_GPIO_NUM 0 -#define MAX_RTC_GPIO_NUM 8 +#define MAX_RTC_GPIO_NUM 7 #define MAX_PAD_GPIO_NUM 28 #define MAX_GPIO_NUM 32 #define DIG_IO_HOLD_BIT_SHIFT 32 diff --git a/components/soc/esp32c6/include/soc/io_mux_reg.h b/components/soc/esp32c6/include/soc/io_mux_reg.h index aa95643237..698a2b5785 100644 --- a/components/soc/esp32c6/include/soc/io_mux_reg.h +++ b/components/soc/esp32c6/include/soc/io_mux_reg.h @@ -148,7 +148,7 @@ #define EXT_OSC_SLOW_GPIO_NUM 0 -#define MAX_RTC_GPIO_NUM 8 +#define MAX_RTC_GPIO_NUM 7 #define MAX_PAD_GPIO_NUM 30 #define MAX_GPIO_NUM 34 #define DIG_IO_HOLD_BIT_SHIFT 32 diff --git a/components/soc/esp32c61/include/soc/io_mux_reg.h b/components/soc/esp32c61/include/soc/io_mux_reg.h index 17b2c01feb..945e18430f 100644 --- a/components/soc/esp32c61/include/soc/io_mux_reg.h +++ b/components/soc/esp32c61/include/soc/io_mux_reg.h @@ -137,7 +137,7 @@ extern "C" { #define SPI_D_GPIO_NUM 21 #define SPI_Q_GPIO_NUM 16 -#define MAX_RTC_GPIO_NUM 7 +#define MAX_RTC_GPIO_NUM 6 #define MAX_PAD_GPIO_NUM 30 #define MAX_GPIO_NUM 34 #define HIGH_IO_HOLD_BIT_SHIFT 32 diff --git a/components/soc/esp32p4/include/soc/io_mux_reg.h b/components/soc/esp32p4/include/soc/io_mux_reg.h index 85eed69098..02440af903 100644 --- a/components/soc/esp32p4/include/soc/io_mux_reg.h +++ b/components/soc/esp32p4/include/soc/io_mux_reg.h @@ -194,7 +194,7 @@ #define EXT_OSC_SLOW_GPIO_NUM 0 // XTAL_32K_N -#define MAX_RTC_GPIO_NUM 16 +#define MAX_RTC_GPIO_NUM 15 #define MAX_PAD_GPIO_NUM 54 #define MAX_GPIO_NUM 56 #define HIGH_IO_HOLD_BIT_SHIFT 32