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fix(uart): fifo read may generate load byte instruction

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This commit is contained in:
morris
2025-04-08 17:35:04 +08:00
parent 53e84d9729
commit 5655ee9ba8
9 changed files with 10 additions and 10 deletions
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2
components/hal/esp32c2/include/hal/uart_ll.h
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@@ -339,7 +339,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->ahb_fifo.rw_byte; buf[i] = hw->ahb_fifo.val;
} }
} }

2
components/hal/esp32c3/include/hal/uart_ll.h
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@@ -344,7 +344,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->ahb_fifo.rw_byte; buf[i] = hw->ahb_fifo.val;
} }
} }

2
components/hal/esp32c6/include/hal/uart_ll.h
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@@ -544,7 +544,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte; buf[i] = hw->fifo.val;
} }
} }

2
components/hal/esp32c61/include/hal/uart_ll.h
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@@ -391,7 +391,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte; buf[i] = hw->fifo.val;
} }
} }

2
components/hal/esp32h2/include/hal/uart_ll.h
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@@ -370,7 +370,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte; buf[i] = hw->fifo.val;
} }
} }

2
components/hal/esp32h21/include/hal/uart_ll.h
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@@ -369,7 +369,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte; buf[i] = hw->fifo.val;
} }
} }

4
components/hal/esp32h4/include/hal/uart_ll.h
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@@ -388,7 +388,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte; buf[i] = hw->fifo.val;
} }
} }
@@ -404,7 +404,7 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{ {
for (int i = 0; i < (int)wr_len; i++) { for (int i = 0; i < (int)wr_len; i++) {
hw->fifo.rxfifo_rd_byte = buf[i]; hw->fifo.val = buf[i];
} }
} }

2
components/hal/esp32p4/include/hal/uart_ll.h
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@@ -664,7 +664,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte; buf[i] = hw->fifo.val;
} }
} }

2
components/hal/esp32s3/include/hal/uart_ll.h
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@@ -349,7 +349,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{ {
for (int i = 0; i < (int)rd_len; i++) { for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte; buf[i] = hw->fifo.val;
} }
} }