From b4cf035608f57e09d918e2ffb4bfc5bb7843dff7 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Mon, 31 Jul 2023 15:26:31 +0530 Subject: [PATCH 1/2] feat(soc): Add hwcrypto_reg.h for esp32p4 --- components/soc/esp32p4/include/soc/hwcrypto_reg.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 components/soc/esp32p4/include/soc/hwcrypto_reg.h diff --git a/components/soc/esp32p4/include/soc/hwcrypto_reg.h b/components/soc/esp32p4/include/soc/hwcrypto_reg.h new file mode 100644 index 0000000000..844d1c8127 --- /dev/null +++ b/components/soc/esp32p4/include/soc/hwcrypto_reg.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __HWCRYPTO_REG_H__ +#define __HWCRYPTO_REG_H__ + +#include "soc/aes_reg.h" +#include "soc/ds_reg.h" +#include "soc/hmac_reg.h" +#include "soc/rsa_reg.h" +#include "soc/sha_reg.h" + +#endif From f2801ae4c95e4f30af19067f52cbfcebc6fc96d5 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Tue, 18 Jul 2023 12:22:44 +0530 Subject: [PATCH 2/2] feat(ecc): add ECC peripheral support for esp32p4 --- components/hal/esp32p4/include/hal/ecc_ll.h | 210 ++++++++++++++++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 8 + .../soc/esp32p4/include/soc/ecc_mult_reg.h | 18 ++ .../soc/esp32p4/include/soc/ecc_mult_struct.h | 3 + .../soc/esp32p4/include/soc/hwcrypto_reg.h | 2 + components/soc/esp32p4/include/soc/soc_caps.h | 3 +- 6 files changed, 243 insertions(+), 1 deletion(-) create mode 100644 components/hal/esp32p4/include/hal/ecc_ll.h diff --git a/components/hal/esp32p4/include/hal/ecc_ll.h b/components/hal/esp32p4/include/hal/ecc_ll.h new file mode 100644 index 0000000000..eda0458db3 --- /dev/null +++ b/components/hal/esp32p4/include/hal/ecc_ll.h @@ -0,0 +1,210 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "hal/assert.h" +#include "hal/ecc_types.h" +#include "soc/ecc_mult_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ECC_PARAM_PX = 0x0, + ECC_PARAM_PY, + ECC_PARAM_K, + ECC_PARAM_QX, + ECC_PARAM_QY, + ECC_PARAM_QZ, +} ecc_ll_param_t; + +static inline void ecc_ll_enable_interrupt(void) +{ + REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); +} + +static inline void ecc_ll_disable_interrupt(void) +{ + REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0); +} + +static inline void ecc_ll_clear_interrupt(void) +{ + REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1); +} + +static inline void ecc_ll_set_mode(ecc_mode_t mode) +{ + switch(mode) { + case ECC_MODE_POINT_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0); + break; + case ECC_MODE_VERIFY: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2); + break; + case ECC_MODE_VERIFY_THEN_POINT_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3); + break; + case ECC_MODE_JACOBIAN_POINT_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4); + break; + case ECC_MODE_POINT_ADD: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5); + break; + case ECC_MODE_JACOBIAN_POINT_VERIFY: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6); + break; + case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7); + break; + case ECC_MODE_MOD_ADD: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8); + break; + case ECC_MODE_MOD_SUB: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9); + break; + case ECC_MODE_MOD_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10); + break; + case ECC_MODE_INVERSE_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11); + break; + default: + HAL_ASSERT(false && "Unsupported mode"); + break; + } +} + +static inline void ecc_ll_set_curve(ecc_curve_t curve) +{ + switch(curve) { + case ECC_CURVE_SECP256R1: + REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); + break; + case ECC_CURVE_SECP192R1: + REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); + break; + default: + HAL_ASSERT(false && "Unsupported curve"); + return; + } +} + +static inline void ecc_ll_set_mod_base(ecc_mod_base_t base) +{ + switch(base) { + case ECC_MOD_N: + REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE); + break; + case ECC_MOD_P: + REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE); + break; + default: + HAL_ASSERT(false && "Unsupported curve"); + return; + } +} + +static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len) +{ + uint32_t reg; + uint32_t word; + switch (param) { + case ECC_PARAM_PX: + reg = ECC_MULT_PX_MEM; + break; + case ECC_PARAM_PY: + reg = ECC_MULT_PY_MEM; + break; + case ECC_PARAM_K: + reg = ECC_MULT_K_MEM; + break; + case ECC_PARAM_QX: + reg = ECC_MULT_QX_MEM; + break; + case ECC_PARAM_QY: + reg = ECC_MULT_QY_MEM; + break; + case ECC_PARAM_QZ: + reg = ECC_MULT_QZ_MEM; + break; + default: + HAL_ASSERT(false && "Invalid parameter"); + return; + } + + for (int i = 0; i < len; i += 4) { + memcpy(&word, buf + i, 4); + REG_WRITE(reg + i, word); + } +} + +static inline void ecc_ll_start_calc(void) +{ + REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START); +} + +static inline int ecc_ll_is_calc_finished(void) +{ + return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW); +} + +static inline ecc_mode_t ecc_ll_get_mode(void) +{ + return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE); +} + +static inline int ecc_ll_get_verification_result(void) +{ + return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT); +} + +static inline ecc_curve_t ecc_ll_get_curve(void) +{ + return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); +} + +static inline ecc_mod_base_t ecc_ll_get_mod_base(void) +{ + return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE); +} + +static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len) +{ + uint32_t reg; + switch (param) { + case ECC_PARAM_PX: + reg = ECC_MULT_PX_MEM; + break; + case ECC_PARAM_PY: + reg = ECC_MULT_PY_MEM; + break; + case ECC_PARAM_K: + reg = ECC_MULT_K_MEM; + break; + case ECC_PARAM_QX: + reg = ECC_MULT_QX_MEM; + break; + case ECC_PARAM_QY: + reg = ECC_MULT_QY_MEM; + break; + case ECC_PARAM_QZ: + reg = ECC_MULT_QZ_MEM; + break; + default: + HAL_ASSERT(false && "Invalid parameter"); + return; + } + + memcpy(buf, (void *)reg, len); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 7dd7b0b22f..2e2b4bb67f 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -43,6 +43,14 @@ config SOC_SYSTIMER_SUPPORTED bool default y +config SOC_ECC_SUPPORTED + bool + default y + +config SOC_ECC_EXTENDED_MODES_SUPPORTED + bool + default y + config SOC_FLASH_ENC_SUPPORTED bool default y diff --git a/components/soc/esp32p4/include/soc/ecc_mult_reg.h b/components/soc/esp32p4/include/soc/ecc_mult_reg.h index c67c09ab47..2bec4bb8c7 100644 --- a/components/soc/esp32p4/include/soc/ecc_mult_reg.h +++ b/components/soc/esp32p4/include/soc/ecc_mult_reg.h @@ -162,6 +162,24 @@ extern "C" { #define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) #define ECC_MULT_PY_MEM_SIZE_BYTES 32 +/** ECC_MULT_QX_MEM register + * The memory that stores Qx. + */ +#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160) +#define ECC_MULT_QX_MEM_SIZE_BYTES 32 + +/** ECC_MULT_QY_MEM register + * The memory that stores Qy. + */ +#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180) +#define ECC_MULT_QY_MEM_SIZE_BYTES 32 + +/** ECC_MULT_QZ_MEM register + * The memory that stores Qz. + */ +#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0) +#define ECC_MULT_QZ_MEM_SIZE_BYTES 32 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/ecc_mult_struct.h b/components/soc/esp32p4/include/soc/ecc_mult_struct.h index ee5f93e90b..4cb6a8afba 100644 --- a/components/soc/esp32p4/include/soc/ecc_mult_struct.h +++ b/components/soc/esp32p4/include/soc/ecc_mult_struct.h @@ -151,6 +151,9 @@ typedef struct { volatile uint32_t k[8]; volatile uint32_t px[8]; volatile uint32_t py[8]; + volatile uint32_t qx[8]; + volatile uint32_t qy[8]; + volatile uint32_t qz[8]; } ecc_mult_dev_t; diff --git a/components/soc/esp32p4/include/soc/hwcrypto_reg.h b/components/soc/esp32p4/include/soc/hwcrypto_reg.h index 844d1c8127..f3eff43667 100644 --- a/components/soc/esp32p4/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32p4/include/soc/hwcrypto_reg.h @@ -3,6 +3,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#pragma once + #ifndef __HWCRYPTO_REG_H__ #define __HWCRYPTO_REG_H__ diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 9cec44c48d..bb74d630a2 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -59,7 +59,8 @@ // #define SOC_SHA_SUPPORTED 1 //TODO: IDF-7541 // #define SOC_HMAC_SUPPORTED 1 //TODO: IDF-7543 // #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: IDF-6518 -// #define SOC_ECC_SUPPORTED 1 //TODO: IDF-7549 +#define SOC_ECC_SUPPORTED 1 +#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 #define SOC_FLASH_ENC_SUPPORTED 1 // #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: IDF-7544 // #define SOC_BOD_SUPPORTED 1 //TODO: IDF-7519