diff --git a/components/driver/parlio/parlio_tx.c b/components/driver/parlio/parlio_tx.c index e4a89cac1c..91b5ce7460 100644 --- a/components/driver/parlio/parlio_tx.c +++ b/components/driver/parlio/parlio_tx.c @@ -215,7 +215,11 @@ static esp_err_t parlio_tx_unit_init_dma(parlio_tx_unit_t *tx_unit) gdma_channel_alloc_config_t dma_chan_config = { .direction = GDMA_CHANNEL_DIRECTION_TX, }; - ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_chan_config, &tx_unit->dma_chan), TAG, "allocate TX DMA channel failed"); +#if SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS == SOC_GDMA_BUS_AHB + ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &tx_unit->dma_chan), TAG, "allocate TX DMA channel failed"); +#elif SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS == SOC_GDMA_BUS_AXI + ESP_RETURN_ON_ERROR(gdma_new_axi_channel(&dma_chan_config, &tx_unit->dma_chan), TAG, "allocate TX DMA channel failed"); +#endif gdma_connect(tx_unit->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_PARLIO, 0)); gdma_strategy_config_t gdma_strategy_conf = { .auto_update_desc = true, diff --git a/components/driver/rmt/rmt_rx.c b/components/driver/rmt/rmt_rx.c index 7d7969a529..5505c0179b 100644 --- a/components/driver/rmt/rmt_rx.c +++ b/components/driver/rmt/rmt_rx.c @@ -74,7 +74,9 @@ static esp_err_t rmt_rx_init_dma_link(rmt_rx_channel_t *rx_channel, const rmt_rx gdma_channel_alloc_config_t dma_chan_config = { .direction = GDMA_CHANNEL_DIRECTION_RX, }; - ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_chan_config, &rx_channel->base.dma_chan), TAG, "allocate RX DMA channel failed"); +#if SOC_GDMA_TRIG_PERIPH_RMT0_BUS == SOC_GDMA_BUS_AHB + ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &rx_channel->base.dma_chan), TAG, "allocate RX DMA channel failed"); +#endif gdma_strategy_config_t gdma_strategy_conf = { .auto_update_desc = true, .owner_check = true, diff --git a/components/driver/rmt/rmt_tx.c b/components/driver/rmt/rmt_tx.c index d4b7cf21a2..6ca6f15fab 100644 --- a/components/driver/rmt/rmt_tx.c +++ b/components/driver/rmt/rmt_tx.c @@ -61,7 +61,9 @@ static esp_err_t rmt_tx_init_dma_link(rmt_tx_channel_t *tx_channel, const rmt_tx gdma_channel_alloc_config_t dma_chan_config = { .direction = GDMA_CHANNEL_DIRECTION_TX, }; - ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_chan_config, &tx_channel->base.dma_chan), TAG, "allocate TX DMA channel failed"); +#if SOC_GDMA_TRIG_PERIPH_RMT0_BUS == SOC_GDMA_BUS_AHB + ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &tx_channel->base.dma_chan), TAG, "allocate TX DMA channel failed"); +#endif gdma_strategy_config_t gdma_strategy_conf = { .auto_update_desc = true, .owner_check = true, diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index c521e6311b..759cc09bf6 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -218,6 +218,13 @@ menu "Hardware Settings" This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash cache misses, and also be able to run whilst the cache is disabled. (e.g. SPI Flash write). + + config GDMA_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for GDMA driver. + Note that, this option only controls the GDMA driver log, won't affect other drivers. endmenu # GDMA Configuration menu "Main XTAL Config" diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index 2d36db0616..90428e7659 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -4,12 +4,37 @@ * SPDX-License-Identifier: Apache-2.0 */ -// #define LOG_LOCAL_LEVEL ESP_LOG_DEBUG +/** + * AHB-Bus --------+ +-------- AXI-Bus + * | | + * | | + * +-----------------------------------+--+ +--+-----------------------------------+ + * | GDMA-Group-X | | | | GDMA-Group-Y | + * | +-------------+ +------------+ | | | | +-------------+ +------------+ | + * | | GDMA-Pair-0 |... |GDMA-Pair-N | | | | | | GDMA-Pair-0 |... |GDMA-Pair-N | | + * | | | | | | | | | | | | | | + * | | TX-Chan |... | TX-Chan | | | | | | TX-Chan |... | TX-Chan | | + * | | RX-Chan | | RX-Chan | | | | | | RX-Chan | | RX-Chan | | + * | +-------------+ +------------+ | | | | +-------------+ +------------+ | + * | | | | | | + * +-----------------------------------+--+ +--+-----------------------------------+ + * | | + * | | + * + * - Channel is allocated when user calls `gdma_new_ahb/axi_channel`, its lifecycle is maintained by the user. + * - Pair and Group are all lazy allocated, their life cycles are maintained by this driver. + * - We're not using a global spin lock, instead, we created different spin locks at different level (group, pair). + */ #include #include #include #include "sdkconfig.h" +#if CONFIG_GDMA_ENABLE_DEBUG_LOG +// The local log level must be defined before including esp_log.h +// Set the maximum log level for this source file +#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG +#endif #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "soc/soc_caps.h" @@ -27,20 +52,8 @@ static const char *TAG = "gdma"; #define SEARCH_REQUEST_RX_CHANNEL (1 << 0) #define SEARCH_REQUEST_TX_CHANNEL (1 << 1) -/** - * GDMA driver consists of there object class, namely: Group, Pair and Channel. - * Channel is allocated when user calls `gdma_new_channel`, its lifecycle is maintained by user. - * Pair and Group are all lazy allocated, their life cycles are maintained by this driver. - * We use reference count to track their life cycles, i.e. the driver will free their memory only when their reference count reached to 0. - * - * We don't use an all-in-one spin lock in this driver, instead, we created different spin locks at different level. - * For platform, it has a spinlock, which is used to protect the group handle slots and reference count of each group. - * For group, it has a spinlock, which is used to protect group level stuffs, e.g. hal object, pair handle slots and reference count of each pair. - * For pair, it has a spinlock, which is used to protect pair level stuffs, e.g. channel handle slots, occupy code. - */ - typedef struct gdma_platform_t { - portMUX_TYPE spinlock; // platform level spinlock + portMUX_TYPE spinlock; // platform level spinlock, protect the group handle slots and reference count of each group. gdma_group_t *groups[SOC_GDMA_NUM_GROUPS_MAX]; // array of GDMA group instances int group_ref_counts[SOC_GDMA_NUM_GROUPS_MAX]; // reference count used to protect group install/uninstall } gdma_platform_t; @@ -69,6 +82,9 @@ typedef struct { static esp_err_t do_allocate_gdma_channel(const gdma_channel_search_info_t *search_info, const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan) { +#if CONFIG_GDMA_ENABLE_DEBUG_LOG + esp_log_level_set(TAG, ESP_LOG_DEBUG); +#endif esp_err_t ret = ESP_OK; gdma_tx_channel_t *alloc_tx_channel = NULL; gdma_rx_channel_t *alloc_rx_channel = NULL; @@ -118,14 +134,19 @@ static esp_err_t do_allocate_gdma_channel(const gdma_channel_search_info_t *sear search_code = 0; // exit search loop } portEXIT_CRITICAL(&pair->spinlock); - if (search_code) { - gdma_release_pair_handle(pair); - pair = NULL; + // found a pair that satisfies the search condition + if (search_code == 0) { + portENTER_CRITICAL(&group->spinlock); + group->pair_ref_counts[pair->pair_id]++; // channel obtains a reference to pair + portEXIT_CRITICAL(&group->spinlock); } + gdma_release_pair_handle(pair); } // loop used to search pair + gdma_release_group_handle(group); + // restore to initial state if no suitable channel slot is found if (search_code) { - gdma_release_group_handle(group); group = NULL; + pair = NULL; } } // loop used to search group ESP_GOTO_ON_FALSE(search_code == 0, ESP_ERR_NOT_FOUND, err, TAG, "no free gdma channel, search code=%d", search_code); @@ -665,7 +686,7 @@ static esp_err_t gdma_del_tx_channel(gdma_channel_t *dma_channel) if (dma_channel->intr) { esp_intr_free(dma_channel->intr); portENTER_CRITICAL(&pair->spinlock); - gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, UINT32_MAX, false); // disable all interupt events + gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, UINT32_MAX, false); // disable all interrupt events gdma_hal_clear_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_TX, UINT32_MAX); // clear all pending events portEXIT_CRITICAL(&pair->spinlock); ESP_LOGD(TAG, "uninstall interrupt service for tx channel (%d,%d)", group_id, pair_id); @@ -694,7 +715,7 @@ static esp_err_t gdma_del_rx_channel(gdma_channel_t *dma_channel) if (dma_channel->intr) { esp_intr_free(dma_channel->intr); portENTER_CRITICAL(&pair->spinlock); - gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, UINT32_MAX, false); // disable all interupt events + gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, UINT32_MAX, false); // disable all interrupt events gdma_hal_clear_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, UINT32_MAX); // clear all pending events portEXIT_CRITICAL(&pair->spinlock); ESP_LOGD(TAG, "uninstall interrupt service for rx channel (%d,%d)", group_id, pair_id); @@ -792,7 +813,7 @@ static esp_err_t gdma_install_rx_interrupt(gdma_rx_channel_t *rx_chan) rx_chan->base.intr = intr; portENTER_CRITICAL(&pair->spinlock); - gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, UINT32_MAX, false); // disable all interupt events + gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, UINT32_MAX, false); // disable all interrupt events gdma_hal_clear_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, UINT32_MAX); // clear all pending events portEXIT_CRITICAL(&pair->spinlock); ESP_LOGD(TAG, "install interrupt service for rx channel (%d,%d)", group->group_id, pair_id); @@ -821,7 +842,7 @@ static esp_err_t gdma_install_tx_interrupt(gdma_tx_channel_t *tx_chan) tx_chan->base.intr = intr; portENTER_CRITICAL(&pair->spinlock); - gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, UINT32_MAX, false); // disable all interupt events + gdma_hal_enable_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, UINT32_MAX, false); // disable all interrupt events gdma_hal_clear_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, UINT32_MAX); // clear all pending events portEXIT_CRITICAL(&pair->spinlock); ESP_LOGD(TAG, "install interrupt service for tx channel (%d,%d)", group->group_id, pair_id); diff --git a/components/esp_hw_support/dma/gdma_priv.h b/components/esp_hw_support/dma/gdma_priv.h index 6274108b4d..202f3ec949 100644 --- a/components/esp_hw_support/dma/gdma_priv.h +++ b/components/esp_hw_support/dma/gdma_priv.h @@ -45,7 +45,7 @@ typedef struct gdma_group_t { int group_id; // Group ID, index from 0 int bus_id; // which system does the GDMA instance attached to gdma_hal_context_t hal; // HAL instance is at group level - portMUX_TYPE spinlock; // group level spinlock + portMUX_TYPE spinlock; // group level spinlock, protect group level stuffs, e.g. hal object, pair handle slots and reference count of each pair uint32_t tx_periph_in_use_mask; // each bit indicates which peripheral (TX direction) has been occupied uint32_t rx_periph_in_use_mask; // each bit indicates which peripheral (RX direction) has been occupied gdma_pair_t *pairs[SOC_GDMA_PAIRS_PER_GROUP_MAX]; // handles of GDMA pairs @@ -58,7 +58,7 @@ struct gdma_pair_t { gdma_tx_channel_t *tx_chan; // pointer of tx channel in the pair gdma_rx_channel_t *rx_chan; // pointer of rx channel in the pair int occupy_code; // each bit indicates which channel has been occupied (an occupied channel will be skipped during channel search) - portMUX_TYPE spinlock; // pair level spinlock + portMUX_TYPE spinlock; // pair level spinlock, protect pair level stuffs, e.g. channel handle slots, occupy code }; struct gdma_channel_t { diff --git a/components/esp_hw_support/include/esp_private/gdma.h b/components/esp_hw_support/include/esp_private/gdma.h index 0260ce183b..fa11019cad 100644 --- a/components/esp_hw_support/include/esp_private/gdma.h +++ b/components/esp_hw_support/include/esp_private/gdma.h @@ -120,6 +120,18 @@ typedef struct { } gdma_strategy_config_t; /** @cond */ +/** + * @brief Create GDMA channel (only create AHB GDMA channel) + * @note This API is going to be deprecated, please use `gdma_new_ahb_channel` or `gdma_new_axi_channel` instead. + * + * @param[in] config Pointer to a collection of configurations for allocating GDMA channel + * @param[out] ret_chan Returned channel handle + * @return + * - ESP_OK: Create DMA channel successfully + * - ESP_ERR_INVALID_ARG: Create DMA channel failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA channel failed because out of memory + * - ESP_FAIL: Create DMA channel failed because of other error + */ esp_err_t gdma_new_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan); /** @endcond */ diff --git a/components/esp_hw_support/test_apps/dma/main/test_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_gdma.c index da085157e9..3e27fec750 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_gdma.c +++ b/components/esp_hw_support/test_apps/dma/main/test_gdma.c @@ -3,26 +3,32 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" #include "unity.h" +#include "esp_heap_caps.h" #include "esp_private/gdma.h" +#include "hal/dma_types.h" #include "soc/soc_caps.h" #include "hal/gdma_ll.h" +#include "rom/cache.h" -TEST_CASE("AHB GDMA channel allocation", "[gdma]") +TEST_CASE("GDMA channel allocation", "[GDMA]") { gdma_channel_alloc_config_t channel_config = {}; - gdma_channel_handle_t tx_channels[GDMA_LL_AHB_PAIRS_PER_GROUP] = {}; - gdma_channel_handle_t rx_channels[GDMA_LL_AHB_PAIRS_PER_GROUP] = {}; + gdma_channel_handle_t tx_channels[SOC_GDMA_PAIRS_PER_GROUP_MAX] = {}; + gdma_channel_handle_t rx_channels[SOC_GDMA_PAIRS_PER_GROUP_MAX] = {}; channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; - gdma_tx_event_callbacks_t tx_cbs = {}; - gdma_rx_event_callbacks_t rx_cbs = {}; +#if SOC_AHB_GDMA_SUPPORTED // install TX channels for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) { - TEST_ESP_OK(gdma_new_channel(&channel_config, &tx_channels[i])); - TEST_ESP_OK(gdma_register_tx_event_callbacks(tx_channels[i], &tx_cbs, NULL)); + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channels[i])); }; - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_channel(&channel_config, &tx_channels[0])); + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_ahb_channel(&channel_config, &tx_channels[0])); // Free interrupts before installing RX interrupts to ensure enough free interrupts for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) { @@ -32,32 +38,91 @@ TEST_CASE("AHB GDMA channel allocation", "[gdma]") // install RX channels channel_config.direction = GDMA_CHANNEL_DIRECTION_RX; for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) { - TEST_ESP_OK(gdma_new_channel(&channel_config, &rx_channels[i])); - TEST_ESP_OK(gdma_register_rx_event_callbacks(rx_channels[i], &rx_cbs, NULL)); + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[i])); } - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_channel(&channel_config, &rx_channels[0])); + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_ahb_channel(&channel_config, &rx_channels[0])); for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) { TEST_ESP_OK(gdma_del_channel(rx_channels[i])); } +#endif // SOC_AHB_GDMA_SUPPORTED // install single and paired TX/RX channels #if GDMA_LL_AHB_PAIRS_PER_GROUP >= 2 // single tx channel channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; - TEST_ESP_OK(gdma_new_channel(&channel_config, &tx_channels[0])); + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channels[0])); // create tx channel and reserve sibling channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; channel_config.flags.reserve_sibling = 1; - TEST_ESP_OK(gdma_new_channel(&channel_config, &tx_channels[1])); + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channels[1])); // create rx channel and specify sibling channel channel_config.flags.reserve_sibling = 0; channel_config.sibling_chan = tx_channels[1]; // specify sibling channel channel_config.direction = GDMA_CHANNEL_DIRECTION_RX; - TEST_ESP_OK(gdma_new_channel(&channel_config, &rx_channels[1])); + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[1])); channel_config.sibling_chan = NULL; - TEST_ESP_OK(gdma_new_channel(&channel_config, &rx_channels[0])); + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[0])); + + TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); + // can't connect multiple channels to the same peripheral + TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); + TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); + + TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); + // but rx and tx can connect to the same peripheral + TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); + for (int i = 0; i < 2; i++) { + TEST_ESP_OK(gdma_disconnect(tx_channels[i])); + TEST_ESP_OK(gdma_disconnect(rx_channels[i])); + TEST_ESP_OK(gdma_del_channel(tx_channels[i])); + TEST_ESP_OK(gdma_del_channel(rx_channels[i])); + } +#endif // GDMA_LL_AHB_PAIRS_PER_GROUP >= 2 + +#if SOC_AXI_GDMA_SUPPORTED + // install TX channels + channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; + for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) { + TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &tx_channels[i])); + }; + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_axi_channel(&channel_config, &tx_channels[0])); + + // Free interrupts before installing RX interrupts to ensure enough free interrupts + for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) { + TEST_ESP_OK(gdma_del_channel(tx_channels[i])); + } + + // install RX channels + channel_config.direction = GDMA_CHANNEL_DIRECTION_RX; + for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) { + TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[i])); + } + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_axi_channel(&channel_config, &rx_channels[0])); + + for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) { + TEST_ESP_OK(gdma_del_channel(rx_channels[i])); + } +#endif // SOC_AXI_GDMA_SUPPORTED + + // install single and paired TX/RX channels +#if GDMA_LL_AXI_PAIRS_PER_GROUP >= 2 + // single tx channel + channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; + TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &tx_channels[0])); + + // create tx channel and reserve sibling + channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; + channel_config.flags.reserve_sibling = 1; + TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &tx_channels[1])); + // create rx channel and specify sibling channel + channel_config.flags.reserve_sibling = 0; + channel_config.sibling_chan = tx_channels[1]; // specify sibling channel + channel_config.direction = GDMA_CHANNEL_DIRECTION_RX; + TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[1])); + channel_config.sibling_chan = NULL; + TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[0])); TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2))); // can't connect multiple channels to the same peripheral @@ -73,5 +138,141 @@ TEST_CASE("AHB GDMA channel allocation", "[gdma]") TEST_ESP_OK(gdma_del_channel(tx_channels[i])); TEST_ESP_OK(gdma_del_channel(rx_channels[i])); } -#endif +#endif // GDMA_LL_AXI_PAIRS_PER_GROUP >= 2 +} + +static bool test_gdma_m2m_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +{ + BaseType_t task_woken = pdFALSE; + SemaphoreHandle_t done_sem = (SemaphoreHandle_t)user_data; + xSemaphoreGiveFromISR(done_sem, &task_woken); + return task_woken == pdTRUE; +} + +static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan) +{ + gdma_rx_event_callbacks_t rx_cbs = { + .on_recv_eof = test_gdma_m2m_rx_eof_callback, + }; + SemaphoreHandle_t done_sem = xSemaphoreCreateBinary(); + TEST_ESP_OK(gdma_register_rx_event_callbacks(rx_chan, &rx_cbs, done_sem)); + + gdma_strategy_config_t strategy = { + .auto_update_desc = true, + .owner_check = true, + }; + TEST_ESP_OK(gdma_apply_strategy(tx_chan, &strategy)); + TEST_ESP_OK(gdma_apply_strategy(rx_chan, &strategy)); + + gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0); + // get a free DMA trigger ID for memory copy + uint32_t free_m2m_id_mask = 0; + gdma_get_free_m2m_trig_id_mask(tx_chan, &free_m2m_id_mask); + m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask); + TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger)); + TEST_ESP_OK(gdma_connect(rx_chan, m2m_trigger)); + + uint8_t *src_buf = heap_caps_aligned_alloc(64, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + uint8_t *dst_buf = heap_caps_aligned_alloc(64, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(src_buf); + TEST_ASSERT_NOT_NULL(dst_buf); + memset(src_buf, 0, 256); + memset(dst_buf, 0, 256); + + dma_descriptor_t *tx_desc = (dma_descriptor_t *) src_buf; + dma_descriptor_t *rx_desc = (dma_descriptor_t *) dst_buf; + uint8_t *src_data = src_buf + 64; + uint8_t *dst_data = dst_buf + 64; + + for (int i = 0; i < 100; i++) { + src_data[i] = i; + } + + tx_desc->buffer = src_data; + tx_desc->dw0.size = 100; + tx_desc->dw0.length = 100; + tx_desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + tx_desc->dw0.suc_eof = 1; + tx_desc->next = NULL; + + rx_desc->buffer = dst_data; + rx_desc->dw0.size = 100; + rx_desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + rx_desc->next = NULL; + +#if CONFIG_IDF_TARGET_ESP32P4 + // descriptors are in the cache, DMA engine may not see the changes, so do a write-back + Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)tx_desc, sizeof(tx_desc)); + Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)rx_desc, sizeof(rx_desc)); + // do write-back for the source data + Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)src_data, 100); +#endif + + TEST_ESP_OK(gdma_start(rx_chan, (intptr_t)rx_desc)); + TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_desc)); + + xSemaphoreTake(done_sem, portMAX_DELAY); + +#if CONFIG_IDF_TARGET_ESP32P4 + // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data + Cache_Invalidate_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)dst_data, 100); + // the DMA descriptors are updated by the DMA as well, so do an invalidate + Cache_Invalidate_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)tx_desc, sizeof(tx_desc)); + Cache_Invalidate_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)rx_desc, sizeof(rx_desc)); +#endif + + // check the DMA descriptor write-back feature + TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, tx_desc->dw0.owner); + TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, rx_desc->dw0.owner); + + for (int i = 0; i < 100; i++) { + TEST_ASSERT_EQUAL(i, dst_data[i]); + } + free((void *)src_buf); + free((void *)dst_buf); + vSemaphoreDelete(done_sem); +} + +TEST_CASE("GDMA M2M Mode", "[GDMA]") +{ + gdma_channel_handle_t tx_chan = NULL; + gdma_channel_handle_t rx_chan = NULL; + gdma_channel_alloc_config_t tx_chan_alloc_config = {}; + gdma_channel_alloc_config_t rx_chan_alloc_config = {}; + +#if SOC_AHB_GDMA_SUPPORTED + tx_chan_alloc_config = (gdma_channel_alloc_config_t) { + .direction = GDMA_CHANNEL_DIRECTION_TX, + .flags.reserve_sibling = true, + }; + TEST_ESP_OK(gdma_new_ahb_channel(&tx_chan_alloc_config, &tx_chan)); + rx_chan_alloc_config = (gdma_channel_alloc_config_t) { + .direction = GDMA_CHANNEL_DIRECTION_RX, + .sibling_chan = tx_chan, + }; + TEST_ESP_OK(gdma_new_ahb_channel(&rx_chan_alloc_config, &rx_chan)); + + test_gdma_m2m_mode(tx_chan, rx_chan); + + TEST_ESP_OK(gdma_del_channel(tx_chan)); + TEST_ESP_OK(gdma_del_channel(rx_chan)); +#endif // SOC_AHB_GDMA_SUPPORTED + +#if SOC_AXI_GDMA_SUPPORTED + tx_chan_alloc_config = (gdma_channel_alloc_config_t) { + .direction = GDMA_CHANNEL_DIRECTION_TX, + .flags.reserve_sibling = true, + }; + TEST_ESP_OK(gdma_new_axi_channel(&tx_chan_alloc_config, &tx_chan)); + rx_chan_alloc_config = (gdma_channel_alloc_config_t) { + .direction = GDMA_CHANNEL_DIRECTION_RX, + .sibling_chan = tx_chan, + }; + TEST_ESP_OK(gdma_new_axi_channel(&rx_chan_alloc_config, &rx_chan)); + + test_gdma_m2m_mode(tx_chan, rx_chan); + + TEST_ESP_OK(gdma_del_channel(tx_chan)); + TEST_ESP_OK(gdma_del_channel(rx_chan)); +#endif // SOC_AXI_GDMA_SUPPORTED } diff --git a/components/esp_lcd/src/esp_lcd_panel_io_i80.c b/components/esp_lcd/src/esp_lcd_panel_io_i80.c index 214c03bd14..36a8fd9e8a 100644 --- a/components/esp_lcd/src/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/src/esp_lcd_panel_io_i80.c @@ -522,7 +522,11 @@ static esp_err_t lcd_i80_init_dma_link(esp_lcd_i80_bus_handle_t bus) gdma_channel_alloc_config_t dma_chan_config = { .direction = GDMA_CHANNEL_DIRECTION_TX, }; - ret = gdma_new_channel(&dma_chan_config, &bus->dma_chan); +#if SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB + ret = gdma_new_ahb_channel(&dma_chan_config, &bus->dma_chan); +#elif SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AXI + ret = gdma_new_axi_channel(&dma_chan_config, &bus->dma_chan); +#endif ESP_GOTO_ON_ERROR(ret, err, TAG, "alloc DMA channel failed"); gdma_connect(bus->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0)); gdma_strategy_config_t strategy_config = { diff --git a/components/esp_lcd/src/esp_lcd_panel_rgb.c b/components/esp_lcd/src/esp_lcd_panel_rgb.c index 9ff8bcc96a..f746c842e3 100644 --- a/components/esp_lcd/src/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/src/esp_lcd_panel_rgb.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -979,7 +979,11 @@ static esp_err_t lcd_rgb_panel_create_trans_link(esp_rgb_panel_t *panel) gdma_channel_alloc_config_t dma_chan_config = { .direction = GDMA_CHANNEL_DIRECTION_TX, }; - ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_chan_config, &panel->dma_chan), TAG, "alloc DMA channel failed"); +#if SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB + ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &panel->dma_chan), TAG, "alloc DMA channel failed"); +#elif SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AXI + ESP_RETURN_ON_ERROR(gdma_new_axi_channel(&dma_chan_config, &panel->dma_chan), TAG, "alloc DMA channel failed"); +#endif gdma_connect(panel->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0)); gdma_transfer_ability_t ability = { .psram_trans_align = panel->psram_trans_align, diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index 2d71c39366..92c72ebebc 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -60,6 +60,10 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return HP_SYS_CLKRST_REG_TWAI1_CLK_EN; case PERIPH_TWAI2_MODULE: return HP_SYS_CLKRST_REG_TWAI2_CLK_EN; + case PERIPH_AHB_PDMA_MODULE: + return HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN; + case PERIPH_AXI_PDMA_MODULE: + return HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN; case PERIPH_GPSPI_MODULE: return HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN; case PERIPH_GPSPI2_MODULE: @@ -109,7 +113,7 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) case PERIPH_ISP_MODULE: return HP_SYS_CLKRST_REG_ISP_CLK_EN; default: - return 0; + return 0; } } @@ -217,13 +221,16 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_EMAC_MODULE: return LP_CLKRST_RST_EN_EMAC; default: - return 0; + return 0; } } static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) { switch (periph) { + case PERIPH_AHB_PDMA_MODULE: + case PERIPH_AXI_PDMA_MODULE: + return HP_SYS_CLKRST_SOC_CLK_CTRL1_REG; case PERIPH_MSPI_FLASH_MODULE: case PERIPH_MSPI_PSRAM_MODULE: return HP_SYS_CLKRST_PERI_CLK_CTRL00_REG; @@ -282,7 +289,7 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) return LP_CLKRST_HP_CLK_CTRL_REG; default: abort(); - return 0; + return 0; } } @@ -296,10 +303,10 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) case PERIPH_ISP_MODULE: case PERIPH_JPEG_MODULE: case PERIPH_DMA2D_MODULE: + return HP_SYS_CLKRST_HP_RST_EN0_REG; case PERIPH_PPA_MODULE: case PERIPH_AHB_PDMA_MODULE: case PERIPH_AXI_PDMA_MODULE: - return HP_SYS_CLKRST_HP_RST_EN0_REG; case PERIPH_SYSTIMER_MODULE: case PERIPH_TIMG0_MODULE: case PERIPH_TIMG1_MODULE: @@ -343,7 +350,7 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) return LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG; default: abort(); - return 0; + return 0; } } diff --git a/components/hal/esp32p4/include/hal/gdma_ll.h b/components/hal/esp32p4/include/hal/gdma_ll.h index cc68213ea4..649620bd3e 100644 --- a/components/hal/esp32p4/include/hal/gdma_ll.h +++ b/components/hal/esp32p4/include/hal/gdma_ll.h @@ -19,8 +19,7 @@ extern "C" { #define GDMA_LL_RX_EVENT_MASK (0x1F) #define GDMA_LL_TX_EVENT_MASK (0x0F) -//To check this //TODO: IDF-6504 -#define GDMA_LL_INVALID_PERIPH_ID (0x3F) +#define GDMA_LL_INVALID_PERIPH_ID (0x3F) #define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3) #define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2) diff --git a/components/soc/esp32p4/gdma_periph.c b/components/soc/esp32p4/gdma_periph.c index 890525bc2b..49c0611848 100644 --- a/components/soc/esp32p4/gdma_periph.c +++ b/components/soc/esp32p4/gdma_periph.c @@ -6,4 +6,41 @@ #include "soc/gdma_periph.h" -const gdma_signal_conn_t gdma_periph_signals = {}; +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_AHB_PDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_AHB_PDMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_AHB_PDMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_AHB_PDMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_AHB_PDMA_OUT_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_AHB_PDMA_IN_CH2_INTR_SOURCE, + .tx_irq_id = ETS_AHB_PDMA_OUT_CH2_INTR_SOURCE, + } + } + }, + [1] = { + .module = PERIPH_AXI_PDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_AXI_PDMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_AXI_PDMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_AXI_PDMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_AXI_PDMA_OUT_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_AXI_PDMA_IN_CH2_INTR_SOURCE, + .tx_irq_id = ETS_AXI_PDMA_OUT_CH2_INTR_SOURCE, + } + } + } + } +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 8b758c0289..9deb48926b 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -7,7 +7,15 @@ config SOC_UART_SUPPORTED bool default y -config SOC_ASYNC_MEMCPY_SUPPORTED +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_AHB_GDMA_SUPPORTED + bool + default y + +config SOC_AXI_GDMA_SUPPORTED bool default y diff --git a/components/soc/esp32p4/include/soc/ahb_dma_reg.h b/components/soc/esp32p4/include/soc/ahb_dma_reg.h index f75a0ceae8..11cedbf1d8 100644 --- a/components/soc/esp32p4/include/soc/ahb_dma_reg.h +++ b/components/soc/esp32p4/include/soc/ahb_dma_reg.h @@ -239,12 +239,12 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S 6 /** AHB_DMA_IN_INT_RAW_CH1_REG register - * Raw status interrupt of channel 0 + * Raw status interrupt of channel 1 */ #define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10) /** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. + * descriptor has been received for Rx channel 1. */ #define AHB_DMA_IN_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_RAW_M (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S) @@ -252,9 +252,9 @@ extern "C" { #define AHB_DMA_IN_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit * turns to high level when the last data pointed by one inlink descriptor has been - * received and no data error is detected for Rx channel 0. + * received and no data error is detected for Rx channel 1. */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S) @@ -262,7 +262,7 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when data error is detected only in the - * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw * interrupt is reserved. */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) @@ -272,7 +272,7 @@ extern "C" { /** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when detecting inlink descriptor error * including owner error and the second and third word error of inlink descriptor for - * Rx channel 0. + * Rx channel 1. */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S) @@ -280,14 +280,14 @@ extern "C" { #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full - * and receiving data is not completed but there is no more inlink for Rx channel 0. + * and receiving data is not completed but there is no more inlink for Rx channel 1. */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is * overflow. */ #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) @@ -295,7 +295,7 @@ extern "C" { #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is * underflow. */ #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) @@ -304,7 +304,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S 6 /** AHB_DMA_IN_INT_ST_CH1_REG register - * Masked interrupt of channel 0 + * Masked interrupt of channel 1 */ #define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14) /** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -358,7 +358,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S 6 /** AHB_DMA_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of channel 0 + * Interrupt enable bits of channel 1 */ #define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18) /** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -412,7 +412,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S 6 /** AHB_DMA_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of channel 0 + * Interrupt clear bits of channel 1 */ #define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c) /** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -466,12 +466,12 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S 6 /** AHB_DMA_IN_INT_RAW_CH2_REG register - * Raw status interrupt of channel 0 + * Raw status interrupt of channel 2 */ #define AHB_DMA_IN_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20) /** AHB_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. + * descriptor has been received for Rx channel 2. */ #define AHB_DMA_IN_DONE_CH2_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH2_INT_RAW_M (AHB_DMA_IN_DONE_CH2_INT_RAW_V << AHB_DMA_IN_DONE_CH2_INT_RAW_S) @@ -479,9 +479,9 @@ extern "C" { #define AHB_DMA_IN_DONE_CH2_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit * turns to high level when the last data pointed by one inlink descriptor has been - * received and no data error is detected for Rx channel 0. + * received and no data error is detected for Rx channel 2. */ #define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S) @@ -489,7 +489,7 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when data error is detected only in the - * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw * interrupt is reserved. */ #define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) @@ -499,7 +499,7 @@ extern "C" { /** AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when detecting inlink descriptor error * including owner error and the second and third word error of inlink descriptor for - * Rx channel 0. + * Rx channel 2. */ #define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S) @@ -507,14 +507,14 @@ extern "C" { #define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full - * and receiving data is not completed but there is no more inlink for Rx channel 0. + * and receiving data is not completed but there is no more inlink for Rx channel 2. */ #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is * overflow. */ #define AHB_DMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) @@ -522,7 +522,7 @@ extern "C" { #define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is * underflow. */ #define AHB_DMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) @@ -531,7 +531,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S 6 /** AHB_DMA_IN_INT_ST_CH2_REG register - * Masked interrupt of channel 0 + * Masked interrupt of channel 2 */ #define AHB_DMA_IN_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x24) /** AHB_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; @@ -585,7 +585,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH2_INT_ST_S 6 /** AHB_DMA_IN_INT_ENA_CH2_REG register - * Interrupt enable bits of channel 0 + * Interrupt enable bits of channel 2 */ #define AHB_DMA_IN_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x28) /** AHB_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -639,7 +639,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S 6 /** AHB_DMA_IN_INT_CLR_CH2_REG register - * Interrupt clear bits of channel 0 + * Interrupt clear bits of channel 2 */ #define AHB_DMA_IN_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x2c) /** AHB_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; @@ -889,12 +889,12 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 /** AHB_DMA_OUT_INT_RAW_CH1_REG register - * Raw status interrupt of channel 0 + * Raw status interrupt of channel 1 */ #define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40) /** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. + * descriptor has been transmitted to peripherals for Tx channel 1. */ #define AHB_DMA_OUT_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_RAW_M (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S) @@ -902,7 +902,7 @@ extern "C" { #define AHB_DMA_OUT_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. + * descriptor has been read from memory for Tx channel 1. */ #define AHB_DMA_OUT_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S) @@ -911,7 +911,7 @@ extern "C" { /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when detecting outlink descriptor error * including owner error and the second and third word error of outlink descriptor for - * Tx channel 0. + * Tx channel 1. */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) @@ -920,14 +920,14 @@ extern "C" { /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when data corresponding a outlink * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. + * channel 1. */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is * overflow. */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) @@ -935,7 +935,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is * underflow. */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) @@ -944,7 +944,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 /** AHB_DMA_OUT_INT_ST_CH1_REG register - * Masked interrupt of channel 0 + * Masked interrupt of channel 1 */ #define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44) /** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -991,7 +991,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S 5 /** AHB_DMA_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of channel 0 + * Interrupt enable bits of channel 1 */ #define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48) /** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -1038,7 +1038,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 /** AHB_DMA_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of channel 0 + * Interrupt clear bits of channel 1 */ #define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c) /** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -1085,12 +1085,12 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 /** AHB_DMA_OUT_INT_RAW_CH2_REG register - * Raw status interrupt of channel 0 + * Raw status interrupt of channel 2 */ #define AHB_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x50) /** AHB_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. + * descriptor has been transmitted to peripherals for Tx channel 2. */ #define AHB_DMA_OUT_DONE_CH2_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH2_INT_RAW_M (AHB_DMA_OUT_DONE_CH2_INT_RAW_V << AHB_DMA_OUT_DONE_CH2_INT_RAW_S) @@ -1098,7 +1098,7 @@ extern "C" { #define AHB_DMA_OUT_DONE_CH2_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. + * descriptor has been read from memory for Tx channel 2. */ #define AHB_DMA_OUT_EOF_CH2_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_EOF_CH2_INT_RAW_S) @@ -1107,7 +1107,7 @@ extern "C" { /** AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when detecting outlink descriptor error * including owner error and the second and third word error of outlink descriptor for - * Tx channel 0. + * Tx channel 2. */ #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S) @@ -1116,14 +1116,14 @@ extern "C" { /** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when data corresponding a outlink * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. + * channel 2. */ #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is * overflow. */ #define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) @@ -1131,7 +1131,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is * underflow. */ #define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) @@ -1140,7 +1140,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 /** AHB_DMA_OUT_INT_ST_CH2_REG register - * Masked interrupt of channel 0 + * Masked interrupt of channel 2 */ #define AHB_DMA_OUT_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x54) /** AHB_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; @@ -1187,7 +1187,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S 5 /** AHB_DMA_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of channel 0 + * Interrupt enable bits of channel 2 */ #define AHB_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x58) /** AHB_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -1234,7 +1234,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 /** AHB_DMA_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of channel 0 + * Interrupt clear bits of channel 2 */ #define AHB_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x5c) /** AHB_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; @@ -1930,11 +1930,11 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH0_S 0 /** AHB_DMA_IN_CONF0_CH1_REG register - * Configure 0 register of Rx channel 0 + * Configure 0 register of Rx channel 1 */ #define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130) /** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer. + * This bit is used to reset AHB_DMA channel 1 Rx FSM and Rx FIFO pointer. */ #define AHB_DMA_IN_RST_CH1 (BIT(0)) #define AHB_DMA_IN_RST_CH1_M (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S) @@ -1948,7 +1948,7 @@ extern "C" { #define AHB_DMA_IN_LOOP_TEST_CH1_V 0x00000001U #define AHB_DMA_IN_LOOP_TEST_CH1_S 1 /** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link * descriptor when accessing internal SRAM. */ #define AHB_DMA_INDSCR_BURST_EN_CH1 (BIT(2)) @@ -1956,7 +1956,7 @@ extern "C" { #define AHB_DMA_INDSCR_BURST_EN_CH1_V 0x00000001U #define AHB_DMA_INDSCR_BURST_EN_CH1_S 2 /** AHB_DMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data * when accessing internal SRAM. */ #define AHB_DMA_IN_DATA_BURST_EN_CH1 (BIT(3)) @@ -1972,7 +1972,7 @@ extern "C" { #define AHB_DMA_MEM_TRANS_EN_CH1_V 0x00000001U #define AHB_DMA_MEM_TRANS_EN_CH1_S 4 /** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * Set this bit to 1 to enable etm control mode, dma Rx channel 1 is triggered by etm * task. */ #define AHB_DMA_IN_ETM_EN_CH1 (BIT(5)) @@ -1981,7 +1981,7 @@ extern "C" { #define AHB_DMA_IN_ETM_EN_CH1_S 5 /** AHB_DMA_IN_CONF1_CH1_REG register - * Configure 1 register of Rx channel 0 + * Configure 1 register of Rx channel 1 */ #define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x134) /** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; @@ -1993,25 +1993,25 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH1_S 12 /** AHB_DMA_INFIFO_STATUS_CH1_REG register - * Receive FIFO status of Rx channel 0 + * Receive FIFO status of Rx channel 1 */ #define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138) /** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 0. + * L1 Rx FIFO full signal for Rx channel 1. */ #define AHB_DMA_INFIFO_FULL_CH1 (BIT(0)) #define AHB_DMA_INFIFO_FULL_CH1_M (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S) #define AHB_DMA_INFIFO_FULL_CH1_V 0x00000001U #define AHB_DMA_INFIFO_FULL_CH1_S 0 /** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 0. + * L1 Rx FIFO empty signal for Rx channel 1. */ #define AHB_DMA_INFIFO_EMPTY_CH1 (BIT(1)) #define AHB_DMA_INFIFO_EMPTY_CH1_M (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S) #define AHB_DMA_INFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH1_S 1 /** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. */ #define AHB_DMA_INFIFO_CNT_CH1 0x0000003FU #define AHB_DMA_INFIFO_CNT_CH1_M (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S) @@ -2054,7 +2054,7 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH1_S 27 /** AHB_DMA_IN_POP_CH1_REG register - * Pop control register of Rx channel 0 + * Pop control register of Rx channel 1 */ #define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c) /** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; @@ -2073,7 +2073,7 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH1_S 12 /** AHB_DMA_IN_LINK_CH1_REG register - * Link descriptor configure and control register of Rx channel 0 + * Link descriptor configure and control register of Rx channel 1 */ #define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140) /** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; @@ -2115,7 +2115,7 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH1_S 4 /** AHB_DMA_IN_STATE_CH1_REG register - * Receive status of Rx channel 0 + * Receive status of Rx channel 1 */ #define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144) /** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -2141,7 +2141,7 @@ extern "C" { #define AHB_DMA_IN_STATE_CH1_S 20 /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Inlink descriptor address when EOF occurs of Rx channel 0 + * Inlink descriptor address when EOF occurs of Rx channel 1 */ #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x148) /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2154,7 +2154,7 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Inlink descriptor address when errors occur of Rx channel 0 + * Inlink descriptor address when errors occur of Rx channel 1 */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c) /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2167,7 +2167,7 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_CH1_REG register - * Current inlink descriptor address of Rx channel 0 + * Current inlink descriptor address of Rx channel 1 */ #define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150) /** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2179,7 +2179,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH1_S 0 /** AHB_DMA_IN_DSCR_BF0_CH1_REG register - * The last inlink descriptor address of Rx channel 0 + * The last inlink descriptor address of Rx channel 1 */ #define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154) /** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2191,7 +2191,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_IN_DSCR_BF1_CH1_REG register - * The second-to-last inlink descriptor address of Rx channel 0 + * The second-to-last inlink descriptor address of Rx channel 1 */ #define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158) /** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2203,11 +2203,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF1_CH1_S 0 /** AHB_DMA_IN_PRI_CH1_REG register - * Priority register of Rx channel 0 + * Priority register of Rx channel 1 */ #define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) /** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 0. The larger of the value the higher of the priority. + * The priority of Rx channel 1. The larger of the value the higher of the priority. */ #define AHB_DMA_RX_PRI_CH1 0x0000000FU #define AHB_DMA_RX_PRI_CH1_M (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S) @@ -2215,7 +2215,7 @@ extern "C" { #define AHB_DMA_RX_PRI_CH1_S 0 /** AHB_DMA_IN_PERI_SEL_CH1_REG register - * Peripheral selection of Rx channel 0 + * Peripheral selection of Rx channel 1 */ #define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x160) /** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; @@ -2288,7 +2288,7 @@ extern "C" { #define AHB_DMA_OUT_ETM_EN_CH1_S 6 /** AHB_DMA_OUT_CONF1_CH1_REG register - * Configure 1 register of Tx channel 0 + * Configure 1 register of Tx channel 1 */ #define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x194) /** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; @@ -2300,25 +2300,25 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH1_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH1_REG register - * Transmit FIFO status of Tx channel 0 + * Transmit FIFO status of Tx channel 1 */ #define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198) /** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 0. + * L1 Tx FIFO full signal for Tx channel 1. */ #define AHB_DMA_OUTFIFO_FULL_CH1 (BIT(0)) #define AHB_DMA_OUTFIFO_FULL_CH1_M (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S) #define AHB_DMA_OUTFIFO_FULL_CH1_V 0x00000001U #define AHB_DMA_OUTFIFO_FULL_CH1_S 0 /** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 0. + * L1 Tx FIFO empty signal for Tx channel 1. */ #define AHB_DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) #define AHB_DMA_OUTFIFO_EMPTY_CH1_M (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S) #define AHB_DMA_OUTFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH1_S 1 /** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. */ #define AHB_DMA_OUTFIFO_CNT_CH1 0x0000003FU #define AHB_DMA_OUTFIFO_CNT_CH1_M (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S) @@ -2354,7 +2354,7 @@ extern "C" { #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 /** AHB_DMA_OUT_PUSH_CH1_REG register - * Push control register of Rx channel 0 + * Push control register of Rx channel 1 */ #define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c) /** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; @@ -2373,7 +2373,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH1_S 9 /** AHB_DMA_OUT_LINK_CH1_REG register - * Link descriptor configure and control register of Tx channel 0 + * Link descriptor configure and control register of Tx channel 1 */ #define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0) /** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; @@ -2407,7 +2407,7 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH1_S 3 /** AHB_DMA_OUT_STATE_CH1_REG register - * Transmit status of Tx channel 0 + * Transmit status of Tx channel 1 */ #define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -2433,7 +2433,7 @@ extern "C" { #define AHB_DMA_OUT_STATE_CH1_S 20 /** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register - * Outlink descriptor address when EOF occurs of Tx channel 0 + * Outlink descriptor address when EOF occurs of Tx channel 1 */ #define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a8) /** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2446,7 +2446,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register - * The last outlink descriptor address when EOF occurs of Tx channel 0 + * The last outlink descriptor address when EOF occurs of Tx channel 1 */ #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1ac) /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2459,7 +2459,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_CH1_REG register - * Current inlink descriptor address of Tx channel 0 + * Current inlink descriptor address of Tx channel 1 */ #define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0) /** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2471,7 +2471,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH1_REG register - * The last inlink descriptor address of Tx channel 0 + * The last inlink descriptor address of Tx channel 1 */ #define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2483,7 +2483,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH1_REG register - * The second-to-last inlink descriptor address of Tx channel 0 + * The second-to-last inlink descriptor address of Tx channel 1 */ #define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2495,11 +2495,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S 0 /** AHB_DMA_OUT_PRI_CH1_REG register - * Priority register of Tx channel 0. + * Priority register of Tx channel 1 */ #define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) /** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 0. The larger of the value the higher of the priority. + * The priority of Tx channel 1. The larger of the value the higher of the priority. */ #define AHB_DMA_TX_PRI_CH1 0x0000000FU #define AHB_DMA_TX_PRI_CH1_M (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S) @@ -2507,7 +2507,7 @@ extern "C" { #define AHB_DMA_TX_PRI_CH1_S 0 /** AHB_DMA_OUT_PERI_SEL_CH1_REG register - * Peripheral selection of Tx channel 0 + * Peripheral selection of Tx channel 1 */ #define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c0) /** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; @@ -2521,11 +2521,11 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH1_S 0 /** AHB_DMA_IN_CONF0_CH2_REG register - * Configure 0 register of Rx channel 0 + * Configure 0 register of Rx channel 2 */ #define AHB_DMA_IN_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f0) /** AHB_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer. + * This bit is used to reset AHB_DMA channel 2 Rx FSM and Rx FIFO pointer. */ #define AHB_DMA_IN_RST_CH2 (BIT(0)) #define AHB_DMA_IN_RST_CH2_M (AHB_DMA_IN_RST_CH2_V << AHB_DMA_IN_RST_CH2_S) @@ -2539,7 +2539,7 @@ extern "C" { #define AHB_DMA_IN_LOOP_TEST_CH2_V 0x00000001U #define AHB_DMA_IN_LOOP_TEST_CH2_S 1 /** AHB_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link * descriptor when accessing internal SRAM. */ #define AHB_DMA_INDSCR_BURST_EN_CH2 (BIT(2)) @@ -2547,7 +2547,7 @@ extern "C" { #define AHB_DMA_INDSCR_BURST_EN_CH2_V 0x00000001U #define AHB_DMA_INDSCR_BURST_EN_CH2_S 2 /** AHB_DMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data * when accessing internal SRAM. */ #define AHB_DMA_IN_DATA_BURST_EN_CH2 (BIT(3)) @@ -2563,7 +2563,7 @@ extern "C" { #define AHB_DMA_MEM_TRANS_EN_CH2_V 0x00000001U #define AHB_DMA_MEM_TRANS_EN_CH2_S 4 /** AHB_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * Set this bit to 1 to enable etm control mode, dma Rx channel 2 is triggered by etm * task. */ #define AHB_DMA_IN_ETM_EN_CH2 (BIT(5)) @@ -2572,7 +2572,7 @@ extern "C" { #define AHB_DMA_IN_ETM_EN_CH2_S 5 /** AHB_DMA_IN_CONF1_CH2_REG register - * Configure 1 register of Rx channel 0 + * Configure 1 register of Rx channel 2 */ #define AHB_DMA_IN_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f4) /** AHB_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; @@ -2584,25 +2584,25 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH2_S 12 /** AHB_DMA_INFIFO_STATUS_CH2_REG register - * Receive FIFO status of Rx channel 0 + * Receive FIFO status of Rx channel 2 */ #define AHB_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f8) /** AHB_DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 0. + * L1 Rx FIFO full signal for Rx channel 2. */ #define AHB_DMA_INFIFO_FULL_CH2 (BIT(0)) #define AHB_DMA_INFIFO_FULL_CH2_M (AHB_DMA_INFIFO_FULL_CH2_V << AHB_DMA_INFIFO_FULL_CH2_S) #define AHB_DMA_INFIFO_FULL_CH2_V 0x00000001U #define AHB_DMA_INFIFO_FULL_CH2_S 0 /** AHB_DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 0. + * L1 Rx FIFO empty signal for Rx channel 2. */ #define AHB_DMA_INFIFO_EMPTY_CH2 (BIT(1)) #define AHB_DMA_INFIFO_EMPTY_CH2_M (AHB_DMA_INFIFO_EMPTY_CH2_V << AHB_DMA_INFIFO_EMPTY_CH2_S) #define AHB_DMA_INFIFO_EMPTY_CH2_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH2_S 1 /** AHB_DMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. */ #define AHB_DMA_INFIFO_CNT_CH2 0x0000003FU #define AHB_DMA_INFIFO_CNT_CH2_M (AHB_DMA_INFIFO_CNT_CH2_V << AHB_DMA_INFIFO_CNT_CH2_S) @@ -2645,7 +2645,7 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH2_S 27 /** AHB_DMA_IN_POP_CH2_REG register - * Pop control register of Rx channel 0 + * Pop control register of Rx channel 2 */ #define AHB_DMA_IN_POP_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1fc) /** AHB_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; @@ -2664,7 +2664,7 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH2_S 12 /** AHB_DMA_IN_LINK_CH2_REG register - * Link descriptor configure and control register of Rx channel 0 + * Link descriptor configure and control register of Rx channel 2 */ #define AHB_DMA_IN_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x200) /** AHB_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1; @@ -2706,7 +2706,7 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH2_S 4 /** AHB_DMA_IN_STATE_CH2_REG register - * Receive status of Rx channel 0 + * Receive status of Rx channel 2 */ #define AHB_DMA_IN_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x204) /** AHB_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; @@ -2732,7 +2732,7 @@ extern "C" { #define AHB_DMA_IN_STATE_CH2_S 20 /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register - * Inlink descriptor address when EOF occurs of Rx channel 0 + * Inlink descriptor address when EOF occurs of Rx channel 2 */ #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x208) /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2745,7 +2745,7 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register - * Inlink descriptor address when errors occur of Rx channel 0 + * Inlink descriptor address when errors occur of Rx channel 2 */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20c) /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2758,7 +2758,7 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 /** AHB_DMA_IN_DSCR_CH2_REG register - * Current inlink descriptor address of Rx channel 0 + * Current inlink descriptor address of Rx channel 2 */ #define AHB_DMA_IN_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x210) /** AHB_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2770,7 +2770,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH2_S 0 /** AHB_DMA_IN_DSCR_BF0_CH2_REG register - * The last inlink descriptor address of Rx channel 0 + * The last inlink descriptor address of Rx channel 2 */ #define AHB_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x214) /** AHB_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2782,7 +2782,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH2_S 0 /** AHB_DMA_IN_DSCR_BF1_CH2_REG register - * The second-to-last inlink descriptor address of Rx channel 0 + * The second-to-last inlink descriptor address of Rx channel 2 */ #define AHB_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x218) /** AHB_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2794,11 +2794,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF1_CH2_S 0 /** AHB_DMA_IN_PRI_CH2_REG register - * Priority register of Rx channel 0 + * Priority register of Rx channel 2 */ #define AHB_DMA_IN_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x21c) /** AHB_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 0. The larger of the value the higher of the priority. + * The priority of Rx channel 2. The larger of the value the higher of the priority. */ #define AHB_DMA_RX_PRI_CH2 0x0000000FU #define AHB_DMA_RX_PRI_CH2_M (AHB_DMA_RX_PRI_CH2_V << AHB_DMA_RX_PRI_CH2_S) @@ -2806,7 +2806,7 @@ extern "C" { #define AHB_DMA_RX_PRI_CH2_S 0 /** AHB_DMA_IN_PERI_SEL_CH2_REG register - * Peripheral selection of Rx channel 0 + * Peripheral selection of Rx channel 2 */ #define AHB_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x220) /** AHB_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; @@ -2820,11 +2820,11 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH2_S 0 /** AHB_DMA_OUT_CONF0_CH2_REG register - * Configure 0 register of Tx channel 1 + * Configure 0 register of Tx channel 2 */ #define AHB_DMA_OUT_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x250) /** AHB_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer. + * This bit is used to reset AHB_DMA channel 2 Tx FSM and Tx FIFO pointer. */ #define AHB_DMA_OUT_RST_CH2 (BIT(0)) #define AHB_DMA_OUT_RST_CH2_M (AHB_DMA_OUT_RST_CH2_V << AHB_DMA_OUT_RST_CH2_S) @@ -2846,7 +2846,7 @@ extern "C" { #define AHB_DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U #define AHB_DMA_OUT_AUTO_WRBACK_CH2_S 2 /** AHB_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is * generated when data need to transmit has been popped from FIFO in AHB_DMA */ #define AHB_DMA_OUT_EOF_MODE_CH2 (BIT(3)) @@ -2854,7 +2854,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_MODE_CH2_V 0x00000001U #define AHB_DMA_OUT_EOF_MODE_CH2_S 3 /** AHB_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link * descriptor when accessing internal SRAM. */ #define AHB_DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) @@ -2862,7 +2862,7 @@ extern "C" { #define AHB_DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U #define AHB_DMA_OUTDSCR_BURST_EN_CH2_S 4 /** AHB_DMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data * when accessing internal SRAM. */ #define AHB_DMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) @@ -2870,7 +2870,7 @@ extern "C" { #define AHB_DMA_OUT_DATA_BURST_EN_CH2_V 0x00000001U #define AHB_DMA_OUT_DATA_BURST_EN_CH2_S 5 /** AHB_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm + * Set this bit to 1 to enable etm control mode, dma Tx channel 2 is triggered by etm * task. */ #define AHB_DMA_OUT_ETM_EN_CH2 (BIT(6)) @@ -2879,7 +2879,7 @@ extern "C" { #define AHB_DMA_OUT_ETM_EN_CH2_S 6 /** AHB_DMA_OUT_CONF1_CH2_REG register - * Configure 1 register of Tx channel 0 + * Configure 1 register of Tx channel 2 */ #define AHB_DMA_OUT_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x254) /** AHB_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; @@ -2891,25 +2891,25 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH2_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH2_REG register - * Transmit FIFO status of Tx channel 0 + * Transmit FIFO status of Tx channel 2 */ #define AHB_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x258) /** AHB_DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 0. + * L1 Tx FIFO full signal for Tx channel 2. */ #define AHB_DMA_OUTFIFO_FULL_CH2 (BIT(0)) #define AHB_DMA_OUTFIFO_FULL_CH2_M (AHB_DMA_OUTFIFO_FULL_CH2_V << AHB_DMA_OUTFIFO_FULL_CH2_S) #define AHB_DMA_OUTFIFO_FULL_CH2_V 0x00000001U #define AHB_DMA_OUTFIFO_FULL_CH2_S 0 /** AHB_DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 0. + * L1 Tx FIFO empty signal for Tx channel 2. */ #define AHB_DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) #define AHB_DMA_OUTFIFO_EMPTY_CH2_M (AHB_DMA_OUTFIFO_EMPTY_CH2_V << AHB_DMA_OUTFIFO_EMPTY_CH2_S) #define AHB_DMA_OUTFIFO_EMPTY_CH2_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH2_S 1 /** AHB_DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. */ #define AHB_DMA_OUTFIFO_CNT_CH2 0x0000003FU #define AHB_DMA_OUTFIFO_CNT_CH2_M (AHB_DMA_OUTFIFO_CNT_CH2_V << AHB_DMA_OUTFIFO_CNT_CH2_S) @@ -2945,7 +2945,7 @@ extern "C" { #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 /** AHB_DMA_OUT_PUSH_CH2_REG register - * Push control register of Rx channel 0 + * Push control register of Rx channel 2 */ #define AHB_DMA_OUT_PUSH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x25c) /** AHB_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; @@ -2964,7 +2964,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH2_S 9 /** AHB_DMA_OUT_LINK_CH2_REG register - * Link descriptor configure and control register of Tx channel 0 + * Link descriptor configure and control register of Tx channel 2 */ #define AHB_DMA_OUT_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x260) /** AHB_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0; @@ -2998,7 +2998,7 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH2_S 3 /** AHB_DMA_OUT_STATE_CH2_REG register - * Transmit status of Tx channel 0 + * Transmit status of Tx channel 2 */ #define AHB_DMA_OUT_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x264) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; @@ -3024,7 +3024,7 @@ extern "C" { #define AHB_DMA_OUT_STATE_CH2_S 20 /** AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG register - * Outlink descriptor address when EOF occurs of Tx channel 0 + * Outlink descriptor address when EOF occurs of Tx channel 2 */ #define AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x268) /** AHB_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3037,7 +3037,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_DES_ADDR_CH2_S 0 /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register - * The last outlink descriptor address when EOF occurs of Tx channel 0 + * The last outlink descriptor address when EOF occurs of Tx channel 2 */ #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x26c) /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3050,7 +3050,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 /** AHB_DMA_OUT_DSCR_CH2_REG register - * Current inlink descriptor address of Tx channel 0 + * Current inlink descriptor address of Tx channel 2 */ #define AHB_DMA_OUT_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x270) /** AHB_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3062,7 +3062,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH2_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH2_REG register - * The last inlink descriptor address of Tx channel 0 + * The last inlink descriptor address of Tx channel 2 */ #define AHB_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x274) /** AHB_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3074,7 +3074,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH2_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH2_REG register - * The second-to-last inlink descriptor address of Tx channel 0 + * The second-to-last inlink descriptor address of Tx channel 2 */ #define AHB_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x278) /** AHB_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3086,11 +3086,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF1_CH2_S 0 /** AHB_DMA_OUT_PRI_CH2_REG register - * Priority register of Tx channel 0. + * Priority register of Tx channel 2 */ #define AHB_DMA_OUT_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x27c) /** AHB_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 0. The larger of the value the higher of the priority. + * The priority of Tx channel 2. The larger of the value the higher of the priority. */ #define AHB_DMA_TX_PRI_CH2 0x0000000FU #define AHB_DMA_TX_PRI_CH2_M (AHB_DMA_TX_PRI_CH2_V << AHB_DMA_TX_PRI_CH2_S) @@ -3098,7 +3098,7 @@ extern "C" { #define AHB_DMA_TX_PRI_CH2_S 0 /** AHB_DMA_OUT_PERI_SEL_CH2_REG register - * Peripheral selection of Tx channel 0 + * Peripheral selection of Tx channel 2 */ #define AHB_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x280) /** AHB_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; @@ -3241,11 +3241,11 @@ extern "C" { #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S 0 /** AHB_DMA_OUT_CRC_INIT_DATA_CH1_REG register - * This register is used to config ch0 crc initial data(max 32 bit) + * This register is used to config ch1 crc initial data(max 32 bit) */ #define AHB_DMA_OUT_CRC_INIT_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2e4) /** AHB_DMA_OUT_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295; - * This register is used to config ch0 of tx crc initial value + * This register is used to config ch1 of tx crc initial value */ #define AHB_DMA_OUT_CRC_INIT_DATA_CH1 0xFFFFFFFFU #define AHB_DMA_OUT_CRC_INIT_DATA_CH1_M (AHB_DMA_OUT_CRC_INIT_DATA_CH1_V << AHB_DMA_OUT_CRC_INIT_DATA_CH1_S) @@ -3253,7 +3253,7 @@ extern "C" { #define AHB_DMA_OUT_CRC_INIT_DATA_CH1_S 0 /** AHB_DMA_TX_CRC_WIDTH_CH1_REG register - * This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width + * This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width * <=8bit,2'b01 8