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Power Management: add XTAL power domain to control whether external 40MHz xtal is powered down during sleep

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This commit is contained in:
Li Shuai
2021-09-06 14:17:43 +08:00
parent f5b39a7cde
commit 58292a7d22
8 changed files with 24 additions and 11 deletions
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4
components/esp_hw_support/port/esp32c3/rtc_sleep.c
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@@ -129,8 +129,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
/* gating XTAL clock */ REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period)

2
components/esp_hw_support/port/esp32s2/rtc_sleep.c
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@@ -130,6 +130,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
/* Set wait cycle for touch or COCPU after deep sleep and light sleep. */ /* Set wait cycle for touch or COCPU after deep sleep and light sleep. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP); REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP);
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period)

4
components/esp_hw_support/port/esp32s3/rtc_sleep.c
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@@ -139,8 +139,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
/* gating XTAL clock */ REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period)

13
components/esp_hw_support/sleep_modes.c
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@@ -1164,9 +1164,9 @@ static uint32_t get_power_down_flags(void)
} }
#endif #endif
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) { #ifdef CONFIG_IDF_TARGET_ESP32
s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF; s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF;
} #endif
const char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */}; const char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
ESP_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]]); ESP_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]]);
@@ -1197,10 +1197,9 @@ static uint32_t get_power_down_flags(void)
if (s_config.pd_options[ESP_PD_DOMAIN_RTC8M] != ESP_PD_OPTION_ON) { if (s_config.pd_options[ESP_PD_DOMAIN_RTC8M] != ESP_PD_OPTION_ON) {
pd_flags |= RTC_SLEEP_PD_INT_8M; pd_flags |= RTC_SLEEP_PD_INT_8M;
} }
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) {
#ifdef CONFIG_IDF_TARGET_ESP32 pd_flags |= RTC_SLEEP_PD_XTAL;
pd_flags |= RTC_SLEEP_PD_XTAL; }
#endif
/** /**
* VDD_SDIO power domain shall be kept on during the light sleep * VDD_SDIO power domain shall be kept on during the light sleep

3
components/soc/esp32c3/include/soc/rtc.h
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@@ -650,6 +650,7 @@ typedef struct {
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t deep_slp_reject : 1; uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1; uint32_t light_slp_reject : 1;
} rtc_sleep_config_t; } rtc_sleep_config_t;
@@ -685,6 +686,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \ : RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \ .deep_slp_reject = 1, \
.light_slp_reject = 1 \ .light_slp_reject = 1 \
}; };
@@ -700,6 +702,7 @@ typedef struct {
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart #define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals #define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
/** /**
* @brief Prepare the chip to enter sleep mode * @brief Prepare the chip to enter sleep mode

3
components/soc/esp32h2/include/soc/rtc.h
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@@ -662,6 +662,7 @@ typedef struct {
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t deep_slp_reject : 1; uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1; uint32_t light_slp_reject : 1;
} rtc_sleep_config_t; } rtc_sleep_config_t;
@@ -697,6 +698,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \ : RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \ .deep_slp_reject = 1, \
.light_slp_reject = 1 \ .light_slp_reject = 1 \
}; };
@@ -712,6 +714,7 @@ typedef struct {
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart #define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals #define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
/** /**
* @brief Prepare the chip to enter sleep mode * @brief Prepare the chip to enter sleep mode

3
components/soc/esp32s2/include/soc/rtc.h
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@@ -667,6 +667,7 @@ typedef struct {
uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t deep_slp_reject : 1; uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1; uint32_t light_slp_reject : 1;
} rtc_sleep_config_t; } rtc_sleep_config_t;
@@ -699,6 +700,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_1V00, \ : RTC_CNTL_DBIAS_1V00, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \ .deep_slp_reject = 1, \
.light_slp_reject = 1 \ .light_slp_reject = 1 \
}; };
@@ -711,6 +713,7 @@ typedef struct {
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6) #define RTC_SLEEP_PD_WIFI BIT(6)
#define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator
#define RTC_SLEEP_PD_XTAL BIT(8) //!< Power down main XTAL
/** /**
* @brief Prepare the chip to enter sleep mode * @brief Prepare the chip to enter sleep mode

3
components/soc/esp32s3/include/soc/rtc.h
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@@ -653,6 +653,7 @@ typedef struct {
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t deep_slp_reject : 1; uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1; uint32_t light_slp_reject : 1;
} rtc_sleep_config_t; } rtc_sleep_config_t;
@@ -688,6 +689,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \ : RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \ .deep_slp_reject = 1, \
.light_slp_reject = 1 \ .light_slp_reject = 1 \
}; };
@@ -703,6 +705,7 @@ typedef struct {
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart #define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals #define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
/** /**
* @brief Prepare the chip to enter sleep mode * @brief Prepare the chip to enter sleep mode