From 58d222e66c773cecb01ccd1d2e52d18dd43aa432 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 25 Dec 2023 11:00:04 +0800 Subject: [PATCH] change(mpll): use fast write as reg is 8bit --- components/hal/esp32p4/include/hal/clk_tree_ll.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index a607f723bf..eec54323fc 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -302,9 +302,7 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_ // MPLL_Freq = XTAL_Freq * (div + 1) / (ref_div + 1) uint8_t ref_div = 1; uint8_t div = mpll_freq_mhz / 20 - 1; - - uint32_t val = REGI2C_READ(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR); - val |= ((div << 3) | ref_div); + uint8_t val = ((div << 3) | ref_div); REGI2C_WRITE(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR, val); }