From e3148369f32fdc6de62c35a67f7adb6f4faef4e3 Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Fri, 14 Apr 2023 18:16:14 +0800 Subject: [PATCH] support c6 eco1 fosc calibration support c6 eco1 fosc calibration support c6 eco1 fosc calibration support c6 eco1 fosc calibration Apply suggestion Apply support c6 eco1 fosc calibration support c6 eco1 fosc calibration --- .../esp_hw_support/port/esp32c6/rtc_clk_init.c | 2 ++ .../esp_hw_support/port/esp32c6/rtc_time.c | 11 +++++++++++ .../hal/esp32c6/include/hal/clk_tree_ll.h | 17 +++++++++++++++++ components/soc/esp32c6/include/soc/rtc.h | 3 ++- 4 files changed, 32 insertions(+), 1 deletion(-) diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c index a605456a6a..0f911ace88 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c @@ -73,6 +73,8 @@ void rtc_clk_init(rtc_clk_config_t cfg) REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap); REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); + clk_ll_rc_fast_tick_conf(); + rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; esp_rom_uart_tx_wait_idle(0); rtc_clk_xtal_freq_update(xtal_freq); diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c index 184455b260..0b894ee479 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_time.c +++ b/components/esp_hw_support/port/esp32c6/rtc_time.c @@ -13,6 +13,8 @@ #include "soc/timer_group_reg.h" #include "esp_rom_sys.h" #include "assert.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" static const char *TAG = "rtc_time"; @@ -130,6 +132,15 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) while (true) { if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); + + /*The Fosc CLK of calibration circuit is divided by 32 for ECO1. + So we need to multiply the frequency of the Fosc for ECO1 and above chips by 32 times. + And ensure that this modification will not affect ECO0.*/ + if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { + if (cal_clk == RTC_CAL_RC_FAST) { + cal_val = cal_val >> 5; + } + } break; } if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { diff --git a/components/hal/esp32c6/include/hal/clk_tree_ll.h b/components/hal/esp32c6/include/hal/clk_tree_ll.h index 8b6199968e..19729af92a 100644 --- a/components/hal/esp32c6/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c6/include/hal/clk_tree_ll.h @@ -40,6 +40,13 @@ extern "C" { .dbuf = 1, \ } +/* +Set the frequency division factor of ref_tick +The FOSC of rtc calibration uses the 32 frequency division clock for ECO1, +So the frequency division factor of ref_tick must be greater than or equal to 32 +*/ +#define REG_FOSC_TICK_NUM 255 + /** * @brief XTAL32K_CLK enable modes */ @@ -798,6 +805,16 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v return REG_READ(RTC_SLOW_CLK_CAL_REG); } + +/* +Set the frequency division factor of ref_tick +*/ +static inline void clk_ll_rc_fast_tick_conf(void) +{ + PCR.ctrl_tick_conf.fosc_tick_num = REG_FOSC_TICK_NUM; +} + + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c6/include/soc/rtc.h b/components/soc/esp32c6/include/soc/rtc.h index 3458c33ce7..6261b72c2a 100644 --- a/components/soc/esp32c6/include/soc/rtc.h +++ b/components/soc/esp32c6/include/soc/rtc.h @@ -150,6 +150,7 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + /** * @brief Clock source to be calibrated using rtc_clk_cal function * @@ -177,7 +178,7 @@ typedef struct { uint32_t clk_rtc_clk_div : 8; uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency) uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 8; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) + uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t;