diff --git a/components/driver/uart.c b/components/driver/uart.c
index f9431f0b02..d9df14571b 100644
--- a/components/driver/uart.c
+++ b/components/driver/uart.c
@@ -768,7 +768,6 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
                         // Set RS485 RTS pin before transmission if the half duplex mode is enabled
                         if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
                             UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
-                            uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
                             uart_hal_set_rts(&(uart_context[uart_num].hal), 0);
                             uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
                             UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
@@ -1056,14 +1055,13 @@ int uart_tx_chars(uart_port_t uart_num, const char *buffer, uint32_t len)
     }
     int tx_len = 0;
     xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY);
+    UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
     if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
-        UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
-        uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
         uart_hal_set_rts(&(uart_context[uart_num].hal), 0);
         uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
-        UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
     }
-    uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t *) buffer, len, (uint32_t *)&tx_len);
+    uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t*) buffer, len, (uint32_t *)&tx_len);
+    UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
     xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
     return tx_len;
 }
@@ -1102,15 +1100,15 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool
             //semaphore for tx_fifo available
             if (pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) {
                 uint32_t sent = 0;
+                UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
                 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
-                    UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
-                    uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
                     uart_hal_set_rts(&(uart_context[uart_num].hal), 0);
                     uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
-                    UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
                 }
-                uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t *)src, size, &sent);
-                if (sent < size) {
+                // Write of TX FIFO inside critical section to prevent context switch
+                uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t*)src, size, &sent);
+                UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
+                if(sent < size) {
                     p_uart_obj[uart_num]->tx_waiting_fifo = true;
                     uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
                 }