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feat(system): gate the LP peripheral clock by default for esp32c6 and esp32h2

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This commit is contained in:
wuzhenghui
2023-12-11 15:27:32 +08:00
parent 0528c8b4f4
commit 60e985e7af
2 changed files with 23 additions and 0 deletions
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14
components/esp_system/port/soc/esp32c6/clk.c
View File

@@ -18,6 +18,7 @@
#include "soc/rtc.h" #include "soc/rtc.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "soc/i2s_reg.h" #include "soc/i2s_reg.h"
#include "soc/lpperi_reg.h"
#include "esp_cpu.h" #include "esp_cpu.h"
#include "hal/wdt_hal.h" #include "hal/wdt_hal.h"
#include "hal/uart_ll.h" #include "hal/uart_ll.h"
@@ -34,6 +35,7 @@
#include "hal/gdma_ll.h" #include "hal/gdma_ll.h"
#include "hal/spi_ll.h" #include "hal/spi_ll.h"
#include "hal/clk_gate_ll.h" #include "hal/clk_gate_ll.h"
#include "hal/lp_core_ll.h"
#include "hal/temperature_sensor_ll.h" #include "hal/temperature_sensor_ll.h"
#include "esp_private/esp_modem_clock.h" #include "esp_private/esp_modem_clock.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
@@ -269,4 +271,16 @@ __attribute__((weak)) void esp_perip_clk_init(void)
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
} }
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
|| rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) {
_lp_i2c_ll_enable_bus_clock(0, false);
_lp_uart_ll_enable_bus_clock(0, false);
lp_core_ll_enable_bus_clock(false);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
}
} }

9
components/esp_system/port/soc/esp32h2/clk.c
View File

@@ -20,6 +20,7 @@
#include "soc/rtc.h" #include "soc/rtc.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "soc/i2s_reg.h" #include "soc/i2s_reg.h"
#include "soc/lpperi_reg.h"
#include "soc/pcr_reg.h" #include "soc/pcr_reg.h"
#include "hal/wdt_hal.h" #include "hal/wdt_hal.h"
#include "hal/uart_ll.h" #include "hal/uart_ll.h"
@@ -260,4 +261,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
} }
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
|| rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) {
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
}
} }