diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c
index 30e0ba880e..afca5a6d91 100644
--- a/components/driver/deprecated/adc_legacy.c
+++ b/components/driver/deprecated/adc_legacy.c
@@ -842,8 +842,10 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true);
     adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
 
+#if SOC_ADC_ARBITER_SUPPORTED
     adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
     adc_hal_arbiter_config(&config);
+#endif
 
     adc_atten_t atten = s_atten2_single[channel];
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
diff --git a/components/driver/deprecated/driver/adc_types_legacy.h b/components/driver/deprecated/driver/adc_types_legacy.h
index 9186b9c245..9888f03cba 100644
--- a/components/driver/deprecated/driver/adc_types_legacy.h
+++ b/components/driver/deprecated/driver/adc_types_legacy.h
@@ -70,7 +70,7 @@ typedef enum {
     ADC1_CHANNEL_4,     /*!< ADC1 channel 4 is GPIO4 */
     ADC1_CHANNEL_MAX,
 } adc1_channel_t;
-#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
 typedef enum {
     ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
     ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO1 */
@@ -93,6 +93,14 @@ typedef enum {
     ADC1_CHANNEL_7,     /*!< ADC1 channel 7 is GPIO23 */
     ADC1_CHANNEL_MAX,
 } adc1_channel_t;
+#elif CONFIG_IDF_TARGET_ESP32C61
+typedef enum {
+    ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO1 */
+    ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO3 */
+    ADC1_CHANNEL_2,     /*!< ADC1 channel 2 is GPIO4 */
+    ADC1_CHANNEL_3,     /*!< ADC1 channel 3 is GPIO5 */
+    ADC1_CHANNEL_MAX,
+} adc1_channel_t;
 #endif // CONFIG_IDF_TARGET_*
 
 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
diff --git a/components/driver/test_apps/.build-test-rules.yml b/components/driver/test_apps/.build-test-rules.yml
index f78fff4f30..5554901f8c 100644
--- a/components/driver/test_apps/.build-test-rules.yml
+++ b/components/driver/test_apps/.build-test-rules.yml
@@ -21,6 +21,9 @@ components/driver/test_apps/legacy_adc_driver:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: lack of runners, TODO IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: lack of runners
   depends_components:
     - efuse
     - esp_driver_i2s
diff --git a/components/driver/test_apps/legacy_adc_driver/README.md b/components/driver/test_apps/legacy_adc_driver/README.md
index 3a502b1f86..7b96141437 100644
--- a/components/driver/test_apps/legacy_adc_driver/README.md
+++ b/components/driver/test_apps/legacy_adc_driver/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
diff --git a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
index 7a22fa26dc..ba4918e24d 100644
--- a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
+++ b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
@@ -81,6 +81,13 @@
 #define ADC_TEST_HIGH_VAL        4095
 #define ADC_TEST_HIGH_THRESH     200
 
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define ADC_TEST_LOW_VAL         2140
+#define ADC_TEST_LOW_THRESH      200
+
+#define ADC_TEST_HIGH_VAL        4095
+#define ADC_TEST_HIGH_THRESH     200
+
 #endif
 
 //ADC Channels
diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml
index 6a284fa6d2..83598edd3a 100644
--- a/components/esp_adc/test_apps/.build-test-rules.yml
+++ b/components/esp_adc/test_apps/.build-test-rules.yml
@@ -8,6 +8,9 @@ components/esp_adc/test_apps/adc:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: not runners for ESP32P4 ADC # TODO: IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: not runners for ESP32C61 ADC
   depends_components:
     - esp_adc
     - esp_driver_gpio
diff --git a/components/esp_adc/test_apps/adc/README.md b/components/esp_adc/test_apps/adc/README.md
index 3a502b1f86..7b96141437 100644
--- a/components/esp_adc/test_apps/adc/README.md
+++ b/components/esp_adc/test_apps/adc/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
diff --git a/components/esp_adc/test_apps/adc/main/test_adc_wifi.c b/components/esp_adc/test_apps/adc/main/test_adc_wifi.c
index b236f8ea2d..e9380a825b 100644
--- a/components/esp_adc/test_apps/adc/main/test_adc_wifi.c
+++ b/components/esp_adc/test_apps/adc/main/test_adc_wifi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,7 +43,7 @@ static const char* TAG = "test_adc_wifi";
 static int read_raw;
 static int target_value;
 static int test_adc_io;
-static bool test_list[TEST_NUM] = {1, 1, 0, 0, 1, 0, 1, 0};
+static bool test_list[TEST_NUM] = {0, 1, 0, 0, 1, 0, 1, 0};
 
 static void wifi_event_handler(void* arg, esp_event_base_t event_base,
                                int32_t event_id, void* event_data)
@@ -215,14 +215,14 @@ __attribute__((unused)) static void adc_work_with_wifi(adc_unit_t unit_id, adc_c
     TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop.");
 }
 
-#if CONFIG_IDF_TARGET_ESP32C6
-// On ESP32C6, ADC need to call two modem clocks: modem_syscon_ll_enable_fe_80m_clock and modem_syscon_ll_enable_fe_apb_clock.
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61
+// ADC need to call two modem clocks: modem_syscon_ll_enable_fe_80m_clock and modem_syscon_ll_enable_fe_apb_clock.
 // Without calling these two clocks, PWDET mode will not take into effect, so ADC readings will be wrong.
 TEST_CASE("ADC1 work with WiFi", "[adc]")
 {
     adc_work_with_wifi(ADC_UNIT_1, ADC1_WIFI_TEST_CHAN0);
 }
-#endif  // CONFIG_IDF_TARGET_ESP32C6
+#endif
 
 #if (SOC_ADC_PERIPH_NUM >= 2) && !CONFIG_IDF_TARGET_ESP32C3
 // On ESP32C3, ADC2 is no longer supported, due to its HW limitation.
diff --git a/components/esp_adc/test_apps/adc/main/test_common_adc.h b/components/esp_adc/test_apps/adc/main/test_common_adc.h
index c2bd4cd198..89e3477b4c 100644
--- a/components/esp_adc/test_apps/adc/main/test_common_adc.h
+++ b/components/esp_adc/test_apps/adc/main/test_common_adc.h
@@ -103,6 +103,14 @@ extern "C" {
 #define ADC_TEST_HIGH_VAL_DMA    4095
 #define ADC_TEST_HIGH_THRESH     200
 
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define ADC_TEST_LOW_VAL         2140
+#define ADC_TEST_LOW_THRESH      200
+
+#define ADC_TEST_HIGH_VAL        4095
+#define ADC_TEST_HIGH_VAL_DMA    4095
+#define ADC_TEST_HIGH_THRESH     200
+
 #endif
 
 /*---------------------------------------------------------------
diff --git a/components/esp_hw_support/port/esp32c61/CMakeLists.txt b/components/esp_hw_support/port/esp32c61/CMakeLists.txt
index 0e720dc029..ea0e988a9d 100644
--- a/components/esp_hw_support/port/esp32c61/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32c61/CMakeLists.txt
@@ -17,13 +17,6 @@ if(NOT BOOTLOADER_BUILD)
 
 endif()
 
-# TODO: [ESP32C61] IDF-9304
-if(CONFIG_IDF_TARGET_ESP32C61)
-    list(REMOVE_ITEM srcs
-        "sar_periph_ctrl.c"
-    )
-endif()
-
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
diff --git a/components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c
new file mode 100644
index 0000000000..ffdd973ed5
--- /dev/null
+++ b/components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ */
+
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "esp_private/esp_modem_clock.h"
+#include "hal/sar_ctrl_ll.h"
+
+static const char *TAG = "sar_periph_ctrl";
+extern portMUX_TYPE rtc_spinlock;
+
+void sar_periph_ctrl_init(void)
+{
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
+
+    //Add other periph power control initialisation here
+}
+
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(false);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+/**
+ * This gets incremented when s_sar_power_acquire() is called,
+ * and decremented when s_sar_power_release() is called.
+ * PWDET is powered down when the value reaches zero.
+ * Should be modified within critical section.
+ */
+static int s_pwdet_power_on_cnt;
+
+static void s_sar_power_acquire(void)
+{
+    modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+static void s_sar_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+    modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
+}
+
+
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    s_sar_power_release();
+}
+
+
+/*------------------------------------------------------------------------------
+* ADC Power
+*----------------------------------------------------------------------------*/
+void sar_periph_ctrl_adc_oneshot_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_adc_oneshot_power_release(void)
+{
+    s_sar_power_release();
+}
+
+void sar_periph_ctrl_adc_continuous_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_adc_continuous_power_release(void)
+{
+    s_sar_power_release();
+}
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 1b568026ff..3f5f1536bd 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -687,7 +687,7 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(uint32_t pd_flags, bool deep_s
 #endif
     }
 
-#if !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C61
+#if !CONFIG_IDF_TARGET_ESP32P4
     // TODO: IDF-7370
     if (!(deep_sleep && (s_sleep_sub_mode_ref_cnt[ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE] != 0))){
         sar_periph_ctrl_power_disable();
@@ -714,9 +714,7 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
     sleep_console_usj_pad_restore();
 #endif
-#if !CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9304
     sar_periph_ctrl_power_enable();
-#endif
 #if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_CPU_RETENTION_BY_RTCCNTL
     sleep_disable_cpu_retention();
 #endif
diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index 37f85dc351..e32a879fff 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -566,7 +566,6 @@ static inline void adc_ll_enable_bus_clock(bool enable)
     PCR.saradc_conf.saradc_reg_clk_en = enable;
 }
 
-#if SOC_RCC_IS_INDEPENDENT
 /**
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
@@ -575,7 +574,6 @@ static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
 }
-#endif
 
 /**
  * @brief Reset ADC module
diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h
index e362259ddf..0b09c3cd86 100644
--- a/components/hal/esp32c6/include/hal/adc_ll.h
+++ b/components/hal/esp32c6/include/hal/adc_ll.h
@@ -565,7 +565,6 @@ static inline void adc_ll_enable_bus_clock(bool enable)
     PCR.saradc_conf.saradc_reg_clk_en = enable;
 }
 
-#if SOC_RCC_IS_INDEPENDENT
 /**
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
@@ -574,7 +573,6 @@ static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
 }
-#endif
 
 /**
  * @brief Reset ADC module
diff --git a/components/hal/esp32c61/include/hal/adc_ll.h b/components/hal/esp32c61/include/hal/adc_ll.h
new file mode 100644
index 0000000000..5a57f347ad
--- /dev/null
+++ b/components/hal/esp32c61/include/hal/adc_ll.h
@@ -0,0 +1,800 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include "esp_attr.h"
+
+#include "soc/adc_periph.h"
+#include "soc/apb_saradc_struct.h"
+#include "soc/apb_saradc_reg.h"
+#include "soc/pmu_reg.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/pcr_struct.h"
+#include "hal/misc.h"
+#include "hal/assert.h"
+#include "hal/adc_types.h"
+#include "hal/adc_types_private.h"
+#include "hal/regi2c_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+#include "soc/regi2c_saradc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ADC_LL_EVENT_ADC1_ONESHOT_DONE    BIT(31)
+#define ADC_LL_EVENT_ADC2_ONESHOT_DONE    BIT(30)
+
+#define ADC_LL_THRES_ALL_INTR_ST_M  (SARADC_THRES0_HIGH_INT_ST_M | \
+                                     SARADC_THRES1_HIGH_INT_ST_M | \
+                                     SARADC_THRES0_LOW_INT_ST_M  | \
+                                     SARADC_THRES1_LOW_INT_ST_M)
+
+#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id)    ((monitor_id == 0) ? SARADC_THRES0_HIGH_INT_ST_M : SARADC_THRES1_HIGH_INT_ST_M)
+#define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? SARADC_THRES0_LOW_INT_ST_M : SARADC_THRES1_LOW_INT_ST_M)
+
+/*---------------------------------------------------------------
+                    Oneshot
+---------------------------------------------------------------*/
+#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM)         (0)
+#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL           (0)
+
+/*---------------------------------------------------------------
+                    DMA
+---------------------------------------------------------------*/
+#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM)    (0)
+#define ADC_LL_FSM_RSTB_WAIT_DEFAULT                   (8)
+#define ADC_LL_FSM_START_WAIT_DEFAULT                  (5)
+#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT                (100)
+#define ADC_LL_SAMPLE_CYCLE_DEFAULT                    (2)
+#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT                (1)
+#define ADC_LL_CLKM_DIV_NUM_DEFAULT       15
+#define ADC_LL_CLKM_DIV_B_DEFAULT         1
+#define ADC_LL_CLKM_DIV_A_DEFAULT         0
+#define ADC_LL_DEFAULT_CONV_LIMIT_EN      0
+#define ADC_LL_DEFAULT_CONV_LIMIT_NUM     10
+
+#define ADC_LL_POWER_MANAGE_SUPPORTED     1 //ESP32C61 supported to manage power mode
+/*---------------------------------------------------------------
+                    PWDET (Power Detect)
+---------------------------------------------------------------*/
+#define ADC_LL_PWDET_CCT_DEFAULT                       (4)
+
+typedef enum {
+    ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM,   /*!< ADC XPD controlled by FSM. Used for polling mode */
+    ADC_LL_POWER_SW_ON = SAR_CTRL_LL_POWER_ON,    /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
+    ADC_LL_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF,   /*!< ADC XPD controlled by SW. power off. */
+} adc_ll_power_t;
+
+typedef enum {
+    ADC_LL_CTRL_DIG = 0,    ///< ADC digital controller
+} adc_ll_controller_t;
+
+/**
+ * @brief ADC digital controller (DMA mode) work mode.
+ *
+ * @note  The conversion mode affects the sampling frequency:
+ *        ESP32C61 only support ONLY_ADC1 mode
+ *        SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
+ */
+typedef enum {
+    ADC_LL_DIGI_CONV_ONLY_ADC1 = 0,     // Only use ADC1 for conversion
+} adc_ll_digi_convert_mode_t;
+
+typedef struct  {
+    union {
+        struct {
+            uint8_t atten:      2;
+            uint8_t channel:    3;
+            uint8_t unit:       1;
+            uint8_t reserved:   2;
+        };
+        uint8_t val;
+    };
+} __attribute__((packed)) adc_ll_digi_pattern_table_t;
+
+/*---------------------------------------------------------------
+                    Digital controller setting
+---------------------------------------------------------------*/
+
+/**
+ * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms.
+ *
+ * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor.
+ * @param start_wait Delay time after open xpd.
+ * @param standby_wait Delay time to close xpd.
+ */
+static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
+{
+    // Internal FSM reset wait time
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_fsm_wait, saradc_rstb_wait, rst_wait);
+    // Internal FSM start wait time
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_fsm_wait, saradc_xpd_wait, start_wait);
+    // Internal FSM standby wait time
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_fsm_wait, saradc_standby_wait, standby_wait);
+}
+
+/**
+ * Set adc sample cycle for digital controller.
+ *
+ * @note Normally, please use default value.
+ * @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
+ *                     Range: 2 ~ 0xFF.
+ */
+static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
+{
+    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
+}
+
+/**
+ * Set SAR ADC module clock division factor.
+ * SAR ADC clock divided from digital controller clock.
+ *
+ * @param div Division factor.
+ */
+static inline void adc_ll_digi_set_clk_div(uint32_t div)
+{
+    /* ADC clock divided from digital controller clock clk */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_ctrl, saradc_sar_clk_div, div);
+}
+
+/**
+ * Set adc max conversion number for digital controller.
+ * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
+ *
+ * @param meas_num Max conversion number. Range: 0 ~ 255.
+ */
+static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_ctrl2, saradc_max_meas_num, meas_num);
+}
+
+/**
+ * Enable max conversion number detection for digital controller.
+ * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
+ *
+ * @param enable  true: enable; false: disable
+ */
+static inline void adc_ll_digi_convert_limit_enable(bool enable)
+{
+    ADC.saradc_ctrl2.saradc_meas_num_limit = enable;
+}
+
+/**
+ * Set adc conversion mode for digital controller.
+ *
+ * @note ESP32C61 only support ADC1 single mode.
+ *
+ * @param mode Conversion mode select.
+ */
+static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
+{
+    //ESP32C61 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode
+}
+
+/**
+ * Set pattern table length for digital controller.
+ * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection,
+ * and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
+ * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
+ *
+ * @param adc_n ADC unit.
+ * @param patt_len Items range: 1 ~ 8.
+ */
+static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
+{
+    ADC.saradc_ctrl.saradc_sar_patt_len = patt_len - 1;
+}
+
+/**
+ * Set pattern table for digital controller.
+ * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection,
+ * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
+ * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
+ *
+ * @param adc_n ADC unit.
+ * @param pattern_index Items index. Range: 0 ~ 7.
+ * @param pattern Stored conversion rules.
+ */
+static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
+{
+    uint32_t tab;
+    uint8_t index = pattern_index / 4;
+    uint8_t offset = (pattern_index % 4) * 6;
+    adc_ll_digi_pattern_table_t pattern = {0};
+
+    pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5);
+    if (index == 0) {
+        tab = ADC.saradc_sar_patt_tab1.saradc_sar_patt_tab1;         // Read old register value
+        tab &= (~(0xFC0000 >> offset));                             // Clear old data
+        tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset;    // Fill in the new data
+        ADC.saradc_sar_patt_tab1.saradc_sar_patt_tab1 = tab;         // Write back
+    } else {
+        tab = ADC.saradc_sar_patt_tab2.saradc_sar_patt_tab2;         // Read old register value
+        tab &= (~(0xFC0000 >> offset));                             // Clear old data
+        tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset;    // Fill in the new data
+        ADC.saradc_sar_patt_tab2.saradc_sar_patt_tab2 = tab;         // Write back
+    }
+}
+
+/**
+ * Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
+ *
+ * @param adc_n ADC unit.
+ */
+static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
+{
+    ADC.saradc_ctrl.saradc_sar_patt_p_clear = 1;
+    ADC.saradc_ctrl.saradc_sar_patt_p_clear = 0;
+}
+
+/**
+ * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize.
+ *
+ * @note Only ADC2 have arbiter function.
+ * @param cycle range: 0 ~ 4.
+ */
+static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
+{
+    ADC.saradc_ctrl.saradc_wait_arb_cycle = cycle;
+}
+
+/**
+ * ADC Digital controller output data invert or not.
+ *
+ * @param adc_n ADC unit.
+ * @param inv_en data invert or not.
+ */
+static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
+{
+    if (adc_n == ADC_UNIT_1) {
+        ADC.saradc_ctrl2.saradc_sar1_inv = inv_en;   // Enable / Disable ADC data invert
+    } else { // adc_n == ADC_UNIT_2
+        ADC.saradc_ctrl2.saradc_sar2_inv = inv_en;   // Enable / Disable ADC data invert
+    }
+}
+
+/**
+ * Set the interval clock cycle for the digital controller to trigger the measurement.
+ * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval.
+ *
+ * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
+ * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
+ */
+static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
+{
+    ADC.saradc_ctrl2.saradc_timer_target = cycle;
+}
+
+/**
+ * Enable digital controller timer to trigger the measurement.
+ */
+static inline void adc_ll_digi_trigger_enable(void)
+{
+    ADC.saradc_ctrl2.saradc_timer_en = 1;
+}
+
+/**
+ * Disable digital controller timer to trigger the measurement.
+ */
+static inline void adc_ll_digi_trigger_disable(void)
+{
+    ADC.saradc_ctrl2.saradc_timer_en = 0;
+}
+
+/**
+ * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
+ * Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1).
+ *
+ * @param div_num Division factor. Range: 0 ~ 255.
+ * @param div_b Division factor. Range: 1 ~ 63.
+ * @param div_a Division factor. Range: 0 ~ 63.
+ */
+static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
+    PCR.saradc_clkm_conf.saradc_clkm_div_b = div_b;
+    PCR.saradc_clkm_conf.saradc_clkm_div_a = div_a;
+}
+
+/**
+ * Enable clock and select clock source for ADC digital controller.
+ *
+ * @param clk_src clock source for ADC digital controller.
+ */
+static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
+{
+    switch (clk_src) {
+        case ADC_DIGI_CLK_SRC_XTAL:
+            PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
+            break;
+        case ADC_DIGI_CLK_SRC_RC_FAST:
+            PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
+            break;
+        case ADC_DIGI_CLK_SRC_PLL_F80M:
+            PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
+            break;
+        default:
+            HAL_ASSERT(false && "unsupported clock");
+    }
+    // Enable ADC_CTRL_CLK (i.e. digital domain clock)
+    ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
+}
+
+/**
+ * Disable clock for ADC digital controller.
+ */
+static inline void adc_ll_digi_controller_clk_disable(void)
+{
+    ADC.saradc_ctrl.saradc_sar_clk_gated = 0;
+}
+
+/**
+ * Reset adc digital controller filter.
+ *
+ * @param idx   Filter index
+ * @param adc_n ADC unit.
+ */
+static inline void adc_ll_digi_filter_reset(adc_digi_iir_filter_t idx, adc_unit_t adc_n)
+{
+    (void)adc_n;
+    ADC.saradc_filter_ctrl0.saradc_adc_filter_reset = 1;
+    ADC.saradc_filter_ctrl0.saradc_adc_filter_reset = 0;
+}
+
+/**
+ * Set adc digital controller filter coeff.
+ *
+ * @param idx      filter index
+ * @param adc_n    adc unit
+ * @param channel  adc channel
+ * @param coeff    filter coeff
+ */
+static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff)
+{
+    uint32_t factor_reg_val = 0;
+    switch (coeff) {
+        case ADC_DIGI_IIR_FILTER_COEFF_2:
+            factor_reg_val = 1;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_4:
+            factor_reg_val = 2;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_8:
+            factor_reg_val = 3;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_16:
+            factor_reg_val = 4;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_64:
+            factor_reg_val = 6;
+            break;
+        default:
+            HAL_ASSERT(false);
+    }
+
+    if (idx == ADC_DIGI_IIR_FILTER_0) {
+        ADC.saradc_filter_ctrl0.saradc_adc_filter_channel0 = ((adc_n + 1) << 3) | (channel & 0x7);
+        ADC.saradc_filter_ctrl1.saradc_adc_filter_factor0 = factor_reg_val;
+    } else if (idx == ADC_DIGI_IIR_FILTER_1) {
+        ADC.saradc_filter_ctrl0.saradc_adc_filter_channel1 = ((adc_n + 1) << 3) | (channel & 0x7);
+        ADC.saradc_filter_ctrl1.saradc_adc_filter_factor1 = factor_reg_val;
+    }
+}
+
+/**
+ * Enable adc digital controller filter.
+ * Filtering the ADC data to obtain smooth data at higher sampling rates.
+ *
+ * @param idx      filter index
+ * @param adc_n    ADC unit
+ * @param enable   Enable / Disable
+ */
+static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit_t adc_n, bool enable)
+{
+    (void)adc_n;
+    if (!enable) {
+        if (idx == ADC_DIGI_IIR_FILTER_0) {
+            ADC.saradc_filter_ctrl0.saradc_adc_filter_channel0 = 0xF;
+            ADC.saradc_filter_ctrl1.saradc_adc_filter_factor0 = 0;
+        } else if (idx == ADC_DIGI_IIR_FILTER_1) {
+            ADC.saradc_filter_ctrl0.saradc_adc_filter_channel1 = 0xF;
+            ADC.saradc_filter_ctrl1.saradc_adc_filter_factor1 = 0;
+        }
+    }
+    //nothing to do to enable, after adc_ll_digi_filter_set_factor, it's enabled.
+}
+
+/**
+ * Set monitor threshold of adc digital controller on specific channel.
+ *
+ * @param monitor_id ADC digi monitor unit index.
+ * @param adc_n      Which adc unit the channel belong to.
+ * @param channel    Which channel of adc want to be monitored.
+ * @param h_thresh   High threshold of this monitor.
+ * @param l_thresh   Low threshold of this monitor.
+ */
+static inline void adc_ll_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t channel, int32_t h_thresh, int32_t l_thresh)
+{
+    if (monitor_id == ADC_MONITOR_0) {
+        ADC.saradc_thres0_ctrl.saradc_adc_thres0_channel = (adc_n << 3) | (channel & 0x7);
+        ADC.saradc_thres0_ctrl.saradc_adc_thres0_high = h_thresh;
+        ADC.saradc_thres0_ctrl.saradc_adc_thres0_low = l_thresh;
+    } else { // ADC_MONITOR_1
+        ADC.saradc_thres1_ctrl.saradc_adc_thres1_channel = (adc_n << 3) | (channel & 0x7);
+        ADC.saradc_thres1_ctrl.saradc_adc_thres1_high = h_thresh;
+        ADC.saradc_thres1_ctrl.saradc_adc_thres1_low = l_thresh;
+    }
+}
+
+/**
+ * Start/Stop monitor of adc digital controller.
+ *
+ * @param monitor_id ADC digi monitor unit index.
+ * @param start 1 for start, 0 for stop
+ */
+static inline void adc_ll_digi_monitor_user_start(adc_monitor_id_t monitor_id, bool start)
+{
+    if (monitor_id == ADC_MONITOR_0) {
+        ADC.saradc_thres_ctrl.saradc_adc_thres0_en = start;
+    } else {
+        ADC.saradc_thres_ctrl.saradc_adc_thres1_en = start;
+    }
+}
+
+/**
+ * Enable/disable a intr of adc digital monitor.
+ *
+ * @param monitor_id ADC digi monitor unit index.
+ * @param mode monit mode to enable/disable intr.
+ * @param enable enable or disable.
+ */
+static inline void adc_ll_digi_monitor_enable_intr(adc_monitor_id_t monitor_id, adc_monitor_mode_t mode, bool enable)
+{
+    if (monitor_id == ADC_MONITOR_0) {
+        if (mode == ADC_MONITOR_MODE_HIGH) {
+            ADC.saradc_int_ena.saradc_adc_thres0_high_int_ena = enable;
+        } else {
+            ADC.saradc_int_ena.saradc_adc_thres0_low_int_ena = enable;
+        }
+    }
+    if (monitor_id == ADC_MONITOR_1) {
+        if (mode == ADC_MONITOR_MODE_HIGH) {
+            ADC.saradc_int_ena.saradc_adc_thres1_high_int_ena = enable;
+        } else {
+            ADC.saradc_int_ena.saradc_adc_thres1_low_int_ena = enable;
+        }
+    }
+}
+
+/**
+ * Clear intr raw for adc digi monitors.
+ */
+__attribute__((always_inline))
+static inline void adc_ll_digi_monitor_clear_intr(void)
+{
+    ADC.saradc_int_clr.val |= ADC_LL_THRES_ALL_INTR_ST_M;
+}
+
+/**
+ * Get the address of digi monitor intr statue register.
+ *
+ * @return address of register.
+ */
+__attribute__((always_inline))
+static inline volatile const void *adc_ll_digi_monitor_get_intr_status_addr(void)
+{
+    return &ADC.saradc_int_st.val;
+}
+
+/**
+ * Set DMA eof num of adc digital controller.
+ * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated.
+ *
+ * @param num eof num of DMA.
+ */
+static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_dma_conf, saradc_apb_adc_eof_num, num);
+}
+
+/**
+ * Enable output data to DMA from adc digital controller.
+ */
+static inline void adc_ll_digi_dma_enable(void)
+{
+    ADC.saradc_dma_conf.saradc_apb_adc_trans = 1;
+}
+
+/**
+ * Disable output data to DMA from adc digital controller.
+ */
+static inline void adc_ll_digi_dma_disable(void)
+{
+    ADC.saradc_dma_conf.saradc_apb_adc_trans = 0;
+}
+
+/**
+ * Reset adc digital controller.
+ */
+static inline void adc_ll_digi_reset(void)
+{
+    ADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 1;
+    ADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 0;
+}
+
+/*---------------------------------------------------------------
+                    PWDET(Power detect) controller setting
+---------------------------------------------------------------*/
+/**
+ * Set adc cct for PWDET controller.
+ *
+ * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
+ * @param cct Range: 0 ~ 7.
+ */
+static inline void adc_ll_pwdet_set_cct(uint32_t cct)
+{
+    (void)cct;
+}
+
+/**
+ * Get adc cct for PWDET controller.
+ *
+ * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
+ * @return cct Range: 0 ~ 7.
+ */
+static inline uint32_t adc_ll_pwdet_get_cct(void)
+{
+    return 0;
+}
+
+/*---------------------------------------------------------------
+                    Common setting
+---------------------------------------------------------------*/
+
+/**
+ * @brief Enable the ADC APB clock
+ * @param enable true to enable, false to disable
+ */
+static inline void adc_ll_enable_bus_clock(bool enable)
+{
+    PCR.saradc_conf.saradc_reg_clk_en = enable;
+}
+
+/**
+ * @brief Enable the ADC function clock
+ * @param enable true to enable, false to disable
+ */
+static inline void adc_ll_enable_func_clock(bool enable)
+{
+    PCR.saradc_clkm_conf.saradc_clkm_en = enable;
+}
+
+/**
+ * @brief Reset ADC module
+ */
+static inline void adc_ll_reset_register(void)
+{
+    PCR.saradc_conf.saradc_reg_rst_en = 1;
+    PCR.saradc_conf.saradc_reg_rst_en = 0;
+}
+
+/**
+ * Set ADC module power management.
+ *
+ * @param manage Set ADC power status.
+ */
+static inline void adc_ll_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage)
+{
+    (void) adc_n;
+    /* Bit1  0:Fsm  1: SW mode
+       Bit0  0:SW mode power down  1: SW mode power on */
+    if (manage == ADC_LL_POWER_SW_ON) {
+        ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
+        ADC.saradc_ctrl.saradc_xpd_sar_force = 3;
+    } else if (manage == ADC_LL_POWER_BY_FSM) {
+        ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
+        ADC.saradc_ctrl.saradc_xpd_sar_force = 0;
+    } else if (manage == ADC_LL_POWER_SW_OFF) {
+        ADC.saradc_ctrl.saradc_sar_clk_gated = 0;
+        ADC.saradc_ctrl.saradc_xpd_sar_force = 2;
+    }
+}
+
+__attribute__((always_inline))
+static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
+{
+    //Not used on ESP32C61
+}
+
+/*---------------------------------------------------------------
+                    Oneshot Read
+---------------------------------------------------------------*/
+/**
+ * Set adc output data format for oneshot mode
+ *
+ * @note ESP32C61 Oneshot mode only supports 12bit.
+ * @param adc_n ADC unit.
+ * @param bits  Output data bits width option.
+ */
+static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
+{
+    (void) adc_n;
+    //ESP32C61 only supports 12bit, leave here for compatibility
+    HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT);
+}
+
+/**
+ * Enable adc channel to start convert.
+ *
+ * @note Only one channel can be selected for measurement.
+ *
+ * @param adc_n   ADC unit.
+ * @param channel ADC channel number for each ADCn.
+ */
+static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel)
+{
+    ADC.saradc_onetime_sample.saradc_onetime_channel = ((adc_n << 3) | channel);
+}
+
+/**
+ * Disable adc channel to start convert.
+ *
+ * @note Only one channel can be selected in once measurement.
+ *
+ * @param adc_n ADC unit.
+ */
+static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n)
+{
+    ADC.saradc_onetime_sample.saradc_onetime_channel = ((adc_n << 3) | 0xF);
+}
+
+/**
+ * Start oneshot conversion by software
+ *
+ * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle,
+ *            otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow.
+ *            This hardware limitation will be removed in future versions.
+ */
+static inline void adc_oneshot_ll_start(bool val)
+{
+    ADC.saradc_onetime_sample.saradc_onetime_start = val;
+}
+
+/**
+ * Clear the event for each ADCn for Oneshot mode
+ *
+ * @param event ADC event
+ */
+static inline void adc_oneshot_ll_clear_event(uint32_t event_mask)
+{
+    ADC.saradc_int_clr.val |= event_mask;
+}
+
+/**
+ * Check the event for each ADCn for Oneshot mode
+ *
+ * @param event ADC event
+ *
+ * @return
+ *      -true  : The conversion process is finish.
+ *      -false : The conversion process is not finish.
+ */
+static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
+{
+    return (ADC.saradc_int_raw.val & event_mask);
+}
+
+/**
+ * Get the converted value for each ADCn for controller.
+ *
+ * @param adc_n ADC unit.
+ * @return
+ *      - Converted value.
+ */
+static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
+{
+    uint32_t ret_val = 0;
+    if (adc_n == ADC_UNIT_1) {
+        ret_val = ADC.saradc_sar1data_status.saradc_adc1_data & 0xfff;
+    } else { // adc_n == ADC_UNIT_2
+        ret_val = ADC.saradc_sar2data_status.saradc_adc2_data & 0xfff;
+    }
+    return ret_val;
+}
+
+
+/**
+ * Analyze whether the obtained raw data is correct.
+ * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
+ *
+ * @param adc_n    ADC unit.
+ * @param raw_data ADC raw data input (convert value).
+ * @return
+ *        - 1: The data is correct to use.
+ *        - 0: The data is invalid.
+ */
+static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data)
+{
+    (void)adc_n;
+    return true;
+}
+
+/**
+ * ADC module RTC output data invert or not.
+ *
+ * @param adc_n ADC unit.
+ * @param inv_en data invert or not.
+ */
+static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
+{
+    (void)adc_n;
+    (void)inv_en;
+    //For compatibility
+}
+
+/**
+ * Enable oneshot conversion trigger
+ *
+ * @param adc_n  ADC unit
+ */
+static inline void adc_oneshot_ll_enable(adc_unit_t adc_n)
+{
+    if (adc_n == ADC_UNIT_1) {
+        ADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1;
+    } else {
+        ADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 1;
+    }
+}
+
+/**
+ * Disable oneshot conversion trigger for all the ADC units
+ */
+static inline void adc_oneshot_ll_disable_all_unit(void)
+{
+    ADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0;
+    ADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0;
+}
+
+/**
+ * Set attenuation
+ *
+ * @note Attenuation is for all channels
+ *
+ * @param adc_n   ADC unit
+ * @param channel ADC channel
+ * @param atten   ADC attenuation
+ */
+static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
+{
+    (void)adc_n;
+    (void)channel;
+    // Attenuation is for all channels, unit and channel are for compatibility
+    ADC.saradc_onetime_sample.saradc_onetime_atten = atten;
+}
+
+/**
+ * Get the attenuation of a particular channel on ADCn.
+ *
+ * @param adc_n ADC unit.
+ * @param channel ADCn channel number.
+ * @return atten The attenuation option.
+ */
+__attribute__((always_inline))
+static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
+{
+    (void)adc_n;
+    (void)channel;
+    return (adc_atten_t)ADC.saradc_onetime_sample.saradc_onetime_atten;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c61/include/hal/sar_ctrl_ll.h b/components/hal/esp32c61/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..48d511dd3c
--- /dev/null
+++ b/components/hal/esp32c61/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "soc/apb_saradc_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
+#define PWDET_LL_SAR_POWER_CNTL_BIT  BIT(23)
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+__attribute__((always_inline))
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
+    }
+}
+
+/**
+ * @brief Set SAR power ctrl source
+ *
+ * @param[in] force  set PWDET as SAR power ctrl source when force is true
+ */
+static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force)
+{
+    ADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index de1ce835c5..9b0210a341 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -566,7 +566,6 @@ static inline void adc_ll_enable_bus_clock(bool enable)
     PCR.saradc_conf.saradc_reg_clk_en = enable;
 }
 
-#if SOC_RCC_IS_INDEPENDENT
 /**
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
@@ -575,7 +574,6 @@ static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
 }
-#endif
 
 /**
  * @brief Reset ADC module
diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h
index 8660047579..a96fe36f85 100644
--- a/components/hal/include/hal/adc_types.h
+++ b/components/hal/include/hal/adc_types.h
@@ -214,7 +214,7 @@ typedef struct {
     };
 } adc_digi_output_data_t;
 
-#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 /**
  * @brief ADC digital controller (DMA mode) output data format.
  *        Used to analyze the acquired ADC (DMA) data.
diff --git a/components/idf_test/include/esp32c61/idf_performance_target.h b/components/idf_test/include/esp32c61/idf_performance_target.h
index 1053cbef3d..f6f6179265 100644
--- a/components/idf_test/include/esp32c61/idf_performance_target.h
+++ b/components/idf_test/include/esp32c61/idf_performance_target.h
@@ -7,3 +7,11 @@
 #pragma once
 
 #define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL                         1300
+
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER                 5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2                  5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4                  5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8                  5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16                 5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64                 5
+#define IDF_PERFORMANCE_MAX_ADC_ONESHOT_STD_ATTEN3                              5
diff --git a/components/soc/esp32c61/adc_periph.c b/components/soc/esp32c61/adc_periph.c
new file mode 100644
index 0000000000..a0819f8db1
--- /dev/null
+++ b/components/soc/esp32c61/adc_periph.c
@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/adc_periph.h"
+
+/* Store IO number corresponding to the ADC channel number. */
+const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
+    /* ADC1 */
+    {
+        ADC1_CHANNEL_0_GPIO_NUM,
+        ADC1_CHANNEL_1_GPIO_NUM,
+        ADC1_CHANNEL_2_GPIO_NUM,
+        ADC1_CHANNEL_3_GPIO_NUM,
+    },
+};
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index 039ca67ffe..a55c771921 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -3,6 +3,10 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
+config SOC_ADC_SUPPORTED
+    bool
+    default y
+
 config SOC_DEDICATED_GPIO_SUPPORTED
     bool
     default y
@@ -167,18 +171,90 @@ config SOC_XTAL_SUPPORT_40M
     bool
     default y
 
+config SOC_ADC_DIG_CTRL_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_DIG_IIR_FILTER_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_MONITOR_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_DMA_SUPPORTED
+    bool
+    default y
+
 config SOC_ADC_PERIPH_NUM
-    int
-    default 1
+    bool
+    default y
 
 config SOC_ADC_MAX_CHANNEL_NUM
     int
-    default 7
+    default 4
+
+config SOC_ADC_ATTEN_NUM
+    int
+    default 4
+
+config SOC_ADC_DIGI_CONTROLLER_NUM
+    int
+    default 1
+
+config SOC_ADC_PATT_LEN_MAX
+    int
+    default 8
+
+config SOC_ADC_DIGI_MAX_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_DIGI_MIN_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_DIGI_IIR_FILTER_NUM
+    int
+    default 2
+
+config SOC_ADC_DIGI_MONITOR_NUM
+    int
+    default 2
+
+config SOC_ADC_DIGI_RESULT_BYTES
+    int
+    default 4
+
+config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
+    int
+    default 4
+
+config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
+    int
+    default 83333
+
+config SOC_ADC_SAMPLE_FREQ_THRES_LOW
+    int
+    default 611
+
+config SOC_ADC_RTC_MIN_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_RTC_MAX_BITWIDTH
+    int
+    default 12
 
 config SOC_ADC_TEMPERATURE_SHARE_INTR
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_APB_BACKUP_DMA
     bool
     default n
diff --git a/components/soc/esp32c61/include/soc/adc_channel.h b/components/soc/esp32c61/include/soc/adc_channel.h
index c3a9f1c748..27d45a98ad 100644
--- a/components/soc/esp32c61/include/soc/adc_channel.h
+++ b/components/soc/esp32c61/include/soc/adc_channel.h
@@ -6,24 +6,14 @@
 
 #pragma once
 
-// TODO: [ESP32-C61] IDF-9302 Check the channel
-#define ADC1_GPIO0_CHANNEL      0
-#define ADC1_CHANNEL_0_GPIO_NUM 0
+#define ADC1_GPIO1_CHANNEL      0
+#define ADC1_CHANNEL_0_GPIO_NUM 1
 
-#define ADC1_GPIO1_CHANNEL      1
-#define ADC1_CHANNEL_1_GPIO_NUM 1
+#define ADC1_GPIO3_CHANNEL      1
+#define ADC1_CHANNEL_1_GPIO_NUM 3
 
-#define ADC1_GPIO2_CHANNEL      2
-#define ADC1_CHANNEL_2_GPIO_NUM 2
+#define ADC1_GPIO4_CHANNEL      2
+#define ADC1_CHANNEL_2_GPIO_NUM 4
 
-#define ADC1_GPIO3_CHANNEL      3
-#define ADC1_CHANNEL_3_GPIO_NUM 3
-
-#define ADC1_GPIO4_CHANNEL      4
-#define ADC1_CHANNEL_4_GPIO_NUM 4
-
-#define ADC1_GPIO5_CHANNEL      5
-#define ADC1_CHANNEL_5_GPIO_NUM 5
-
-#define ADC1_GPIO6_CHANNEL      6
-#define ADC1_CHANNEL_6_GPIO_NUM 6
+#define ADC1_GPIO5_CHANNEL      3
+#define ADC1_CHANNEL_3_GPIO_NUM 5
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index e7d7e341ef..202f604b30 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -17,7 +17,7 @@
 #pragma once
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
-//  \#define SOC_ADC_SUPPORTED               1    //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
+#define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_UART_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
@@ -67,35 +67,34 @@
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
 
-//TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
 /*-------------------------- ADC CAPS -------------------------------*/
 /*!< SAR ADC Module*/
-//  \#define SOC_ADC_DIG_CTRL_SUPPORTED              1
-//  \#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
-//  \#define SOC_ADC_MONITOR_SUPPORTED               1
-//  \#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
-//  \#define SOC_ADC_DMA_SUPPORTED                   1
-#define SOC_ADC_PERIPH_NUM                      (1U)
-#define SOC_ADC_MAX_CHANNEL_NUM                 (7)
-//  \#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (7)
-//  \#define SOC_ADC_ATTEN_NUM                       (4)
+#define SOC_ADC_DIG_CTRL_SUPPORTED              1
+#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
+#define SOC_ADC_MONITOR_SUPPORTED               1
+#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
+#define SOC_ADC_DMA_SUPPORTED                   1
+#define SOC_ADC_PERIPH_NUM                      (1)
+#define SOC_ADC_MAX_CHANNEL_NUM                 (4)
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (4)
+#define SOC_ADC_ATTEN_NUM                       (4)
 
-// /*!< Digital */
-//  \#define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
-//  \#define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
-//  \#define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
-//  \#define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
-//  \#define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
-//  \#define SOC_ADC_DIGI_MONITOR_NUM                (2)
-//  \#define SOC_ADC_DIGI_RESULT_BYTES               (4)
-//  \#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
-// /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
-//  \#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
-//  \#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+/*!< Digital */
+#define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
+#define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
+#define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
+#define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
+#define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
+#define SOC_ADC_DIGI_MONITOR_NUM                (2)
+#define SOC_ADC_DIGI_RESULT_BYTES               (4)
+#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
+/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
+#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
+#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
 
-// /*!< RTC */
-//  \#define SOC_ADC_RTC_MIN_BITWIDTH                (12)
-//  \#define SOC_ADC_RTC_MAX_BITWIDTH                (12)
+/*!< RTC */
+#define SOC_ADC_RTC_MIN_BITWIDTH                (12)
+#define SOC_ADC_RTC_MAX_BITWIDTH                (12)
 
 // /*!< Calibration */  // TODO: [ESP32C61] IDF-9303
 //  \#define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
@@ -106,7 +105,7 @@
 #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
 
 /*!< ADC power control is shared by PWDET */
-//  \#define SOC_ADC_SHARED_POWER                    1
+#define SOC_ADC_SHARED_POWER                    1
 
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (0)
diff --git a/components/soc/esp32c61/register/soc/reg_base.h b/components/soc/esp32c61/register/soc/reg_base.h
index e52fc35286..67732ccf6a 100644
--- a/components/soc/esp32c61/register/soc/reg_base.h
+++ b/components/soc/esp32c61/register/soc/reg_base.h
@@ -61,3 +61,4 @@
 #define DR_REG_INTPRI_BASE                      0x600C5000
 #define DR_REG_CACHE_BASE                       0x600C8000
 #define DR_REG_CLINT_M_BASE                     0x20000000
+#define PWDET_CONF_REG                          0x600A0808
diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt
index 43c9109f73..7458f86219 100644
--- a/docs/docs_not_updated/esp32c61.txt
+++ b/docs/docs_not_updated/esp32c61.txt
@@ -35,8 +35,6 @@ api-reference/storage/fatfsgen.rst
 api-reference/storage/index.rst
 api-reference/storage/nvs_partition_parse.rst
 api-reference/peripherals/isp.rst
-api-reference/peripherals/adc_continuous.rst
-api-reference/peripherals/adc_oneshot.rst
 api-reference/peripherals/usb_host.rst
 api-reference/peripherals/usb_host/usb_host_notes_arch.rst
 api-reference/peripherals/usb_host/usb_host_notes_index.rst
diff --git a/docs/en/api-reference/peripherals/adc_continuous.rst b/docs/en/api-reference/peripherals/adc_continuous.rst
index 923f50e2cc..c0a946a10b 100644
--- a/docs/en/api-reference/peripherals/adc_continuous.rst
+++ b/docs/en/api-reference/peripherals/adc_continuous.rst
@@ -3,7 +3,7 @@ Analog to Digital Converter (ADC) Continuous Mode Driver
 
 :link_to_translation:`zh_CN:[中文]`
 
-{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one"}
+{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one", esp32c61="one"}
 
 Introduction
 ------------
diff --git a/docs/en/api-reference/peripherals/gpio/esp32c61.inc b/docs/en/api-reference/peripherals/gpio/esp32c61.inc
index 53cc2200f7..dde339064a 100644
--- a/docs/en/api-reference/peripherals/gpio/esp32c61.inc
+++ b/docs/en/api-reference/peripherals/gpio/esp32c61.inc
@@ -23,7 +23,7 @@ The table below provides more information on pin usage, and please note the comm
       - Comments
 
     * - GPIO0
-      - ADC2_CH0
+      -
       - LP_GPIO0
       -
 
@@ -53,7 +53,7 @@ The table below provides more information on pin usage, and please note the comm
       -
 
     * - GPIO6
-      - ADC1_CH5
+      -
       - LP_GPIO6
       -
 
diff --git a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
index de07d35705..2232c31b3e 100644
--- a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
+++ b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
@@ -3,7 +3,7 @@
 
 :link_to_translation:`en:[English]`
 
-{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一"}
+{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一", esp32c61="一"}
 
 简介
 ------------
diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
index 346ff4836e..aa7cc6fc8f 100644
--- a/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
+++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
@@ -23,7 +23,7 @@
       - 注释
 
     * - GPIO0
-      - ADC2_CH0
+      -
       - LP_GPIO0
       -
 
diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml
index bdcdec3d51..dbf5565c56 100644
--- a/examples/peripherals/.build-test-rules.yml
+++ b/examples/peripherals/.build-test-rules.yml
@@ -14,6 +14,9 @@ examples/peripherals/adc/continuous_read:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: lack of runners, TODO IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: lack of runner
   <<: *adc_dependencies
 
 examples/peripherals/adc/oneshot_read:
@@ -23,6 +26,9 @@ examples/peripherals/adc/oneshot_read:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: lack of runner, TODO IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: lack of runner
   <<: *adc_dependencies
 
 examples/peripherals/analog_comparator:
diff --git a/examples/peripherals/adc/continuous_read/README.md b/examples/peripherals/adc/continuous_read/README.md
index 614dedffb6..8e7861d7de 100644
--- a/examples/peripherals/adc/continuous_read/README.md
+++ b/examples/peripherals/adc/continuous_read/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # ADC DMA Example
 
diff --git a/examples/peripherals/adc/oneshot_read/README.md b/examples/peripherals/adc/oneshot_read/README.md
index 431ae89904..491964fb0b 100644
--- a/examples/peripherals/adc/oneshot_read/README.md
+++ b/examples/peripherals/adc/oneshot_read/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # ADC Single Read Example