diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 9a20457d3e..75200e16c8 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -45,6 +45,10 @@ if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG) list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S") endif() +if(CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE) + list(APPEND sources "patches/esp_rom_mmap.c") +endif() + idf_component_register(SRCS ${sources} INCLUDE_DIRS ${include_dirs} PRIV_REQUIRES ${private_required_comp} diff --git a/components/esp_rom/esp32c2/Kconfig.soc_caps.in b/components/esp_rom/esp32c2/Kconfig.soc_caps.in index d676d6ce03..1806ced68a 100644 --- a/components/esp_rom/esp32c2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c2/Kconfig.soc_caps.in @@ -42,3 +42,7 @@ config ESP_ROM_HAS_HEAP_TLSF config ESP_ROM_TLSF_CHECK_PATCH bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32c2/esp_rom_caps.h b/components/esp_rom/esp32c2/esp_rom_caps.h index 60706ac706..9d39e43bae 100644 --- a/components/esp_rom/esp32c2/esp_rom_caps.h +++ b/components/esp_rom/esp32c2/esp_rom_caps.h @@ -16,3 +16,4 @@ #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check() +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in index dddaa79ade..e234513ad4 100644 --- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in @@ -46,3 +46,7 @@ config ESP_ROM_NEEDS_SWSETUP_WORKAROUND config ESP_ROM_HAS_ETS_PRINTF_BUG bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h index 1b1c468bbf..d2b5005b06 100644 --- a/components/esp_rom/esp32c3/esp_rom_caps.h +++ b/components/esp_rom/esp32c3/esp_rom_caps.h @@ -17,3 +17,4 @@ #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing #define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index 90b876658a..1164062b62 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -42,3 +42,7 @@ config ESP_ROM_GET_CLK_FREQ config ESP_ROM_HAS_ETS_PRINTF_BUG bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index a416990d2a..f72ae90ceb 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -16,3 +16,4 @@ #define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index ca74bc46ac..b628b8d2a7 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -66,3 +66,7 @@ config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG config ESP_ROM_HAS_CACHE_WRITEBACK_BUG bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index fe3c2bc391..9986389862 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -22,3 +22,4 @@ #define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value #define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti #define ESP_ROM_HAS_CACHE_WRITEBACK_BUG (1) // ROM api Cache_WriteBack_Addr access cacheline being writen back may cause cache hit with wrong value. +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/linker.lf b/components/esp_rom/linker.lf index b33d0c8286..cb618d04d5 100644 --- a/components/esp_rom/linker.lf +++ b/components/esp_rom/linker.lf @@ -11,3 +11,5 @@ entries: esp_rom_tlsf (noflash) if SOC_SYSTIMER_SUPPORTED = y: esp_rom_systimer (noflash) + if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE = y: + esp_rom_mmap (noflash) diff --git a/components/esp_rom/patches/esp_rom_mmap.c b/components/esp_rom/patches/esp_rom_mmap.c new file mode 100644 index 0000000000..1d62c42c22 --- /dev/null +++ b/components/esp_rom/patches/esp_rom_mmap.c @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "soc/ext_mem_defs.h" + + +uint32_t Cache_Get_IROM_MMU_End(void) +{ +#if CONFIG_IDF_TARGET_ESP32S3 + return 0x800; +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 + return 0x200; +#elif CONFIG_IDF_TARGET_ESP32C2 + return 0x100; +#else + assert(false); +#endif +} + +uint32_t Cache_Get_DROM_MMU_End(void) +{ +#if CONFIG_IDF_TARGET_ESP32S3 + return 0x800; +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 + return 0x200; +#elif CONFIG_IDF_TARGET_ESP32C2 + return 0x100; +#else + assert(false); +#endif +} diff --git a/components/soc/esp32c2/include/soc/ext_mem_defs.h b/components/soc/esp32c2/include/soc/ext_mem_defs.h index 0333de5403..ed3902cb31 100644 --- a/components/soc/esp32c2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c2/include/soc/ext_mem_defs.h @@ -51,7 +51,7 @@ extern "C" { #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_START 0 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) diff --git a/components/soc/esp32c3/include/soc/ext_mem_defs.h b/components/soc/esp32c3/include/soc/ext_mem_defs.h index 3e10ac1f6b..7cea495ab8 100644 --- a/components/soc/esp32c3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c3/include/soc/ext_mem_defs.h @@ -49,7 +49,7 @@ extern "C" { #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_START 0 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h index 164d45d4f8..18427bca62 100644 --- a/components/soc/esp32h2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h @@ -49,7 +49,7 @@ extern "C" { #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_START 0 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) diff --git a/components/soc/esp32s2/include/soc/mmu.h b/components/soc/esp32s2/include/soc/mmu.h index c1ef03b4c4..1400e65995 100644 --- a/components/soc/esp32s2/include/soc/mmu.h +++ b/components/soc/esp32s2/include/soc/mmu.h @@ -22,6 +22,7 @@ extern "C" { #define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t)) #define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK #define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM) #define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START) #define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW diff --git a/components/soc/esp32s3/include/soc/ext_mem_defs.h b/components/soc/esp32s3/include/soc/ext_mem_defs.h index 0260c7bb81..46a53fa080 100644 --- a/components/soc/esp32s3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s3/include/soc/ext_mem_defs.h @@ -48,7 +48,7 @@ extern "C" { #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_START 0 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) diff --git a/components/soc/esp32s3/include/soc/mmu.h b/components/soc/esp32s3/include/soc/mmu.h index 81aafdf4d3..599e9e43b1 100644 --- a/components/soc/esp32s3/include/soc/mmu.h +++ b/components/soc/esp32s3/include/soc/mmu.h @@ -22,6 +22,7 @@ extern "C" { #define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) #define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK #define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM) #define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START #define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index e5ee1250bc..7950be40fb 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -198,6 +198,13 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp for (pos = start; pos < start + page_count; ++pos, ++pageno) { int table_val = (int) mmu_ll_read_entry(MMU_TABLE_CORE0, pos); uint8_t refcnt = s_mmap_page_refcnt[pos]; + +#if !CONFIG_IDF_TARGET_ESP32 && SOC_SPIRAM_SUPPORTED + if (table_val == SOC_MMU_PAGE_IN_PSRAM(pages[pageno])) { + break; + } +#endif //#if !CONFIG_IDF_TARGET_ESP32 + if (refcnt != 0 && table_val != SOC_MMU_PAGE_IN_FLASH(pages[pageno])) { break; } @@ -219,6 +226,12 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 uint32_t entry_app = mmu_ll_read_entry(MMU_TABLE_CORE1, i); #endif + if (s_mmap_page_refcnt[i] == 0) { + assert(mmu_ll_get_entry_is_invalid(MMU_TABLE_CORE0, i)); +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 + assert(mmu_ll_get_entry_is_invalid(MMU_TABLE_CORE1, i)); +#endif + } assert(s_mmap_page_refcnt[i] == 0 || (entry_pro == SOC_MMU_PAGE_IN_FLASH(pages[pageno]) #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32