From 0eee2287001f20a04b624c045a7ccedbed9af7d1 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 18 Nov 2022 19:26:58 +0800 Subject: [PATCH 1/3] efuse(esp32-c6): Update efuse_table and rs coding error func --- components/efuse/esp32c6/esp_efuse_table.c | 81 ++++++++++--------- components/efuse/esp32c6/esp_efuse_table.csv | 17 ++-- .../efuse/esp32c6/include/esp_efuse_table.h | 13 +-- components/hal/esp32c6/efuse_hal.c | 14 +--- 4 files changed, 65 insertions(+), 60 deletions(-) diff --git a/components/efuse/esp32c6/esp_efuse_table.c b/components/efuse/esp32c6/esp_efuse_table.c index a1f3859807..6dc42cd469 100644 --- a/components/efuse/esp32c6/esp_efuse_table.c +++ b/components/efuse/esp32c6/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280 +// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -191,6 +191,10 @@ static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, }; +static const esp_efuse_desc_t DIS_SPI_DOWNLOAD_MSPI[] = { + {EFUSE_BLK0, 45, 1}, // Represents whether the SPI0 controller is disabled in boot_mode_download, +}; + static const esp_efuse_desc_t DIS_TWAI[] = { {EFUSE_BLK0, 46, 1}, // Disable TWAI function, }; @@ -200,25 +204,17 @@ static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., + {EFUSE_BLK0, 48, 3}, // Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module., }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently., + {EFUSE_BLK0, 51, 1}, // Hard disable JTAG. JTAG is disabled permanently., }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes., }; -static const esp_efuse_desc_t USB_DREFH[] = { - {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., -}; - -static const esp_efuse_desc_t USB_DREFL[] = { - {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., -}; - static const esp_efuse_desc_t USB_EXCHG_PINS[] = { {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, }; @@ -272,7 +268,11 @@ static const esp_efuse_desc_t KEY_PURPOSE_5[] = { }; static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { - {EFUSE_BLK0, 112, 2}, // Configures the clock random divide mode to determine the spa secure level, + {EFUSE_BLK0, 112, 2}, // Configures the clock random divide mode to determine the DPA security level, +}; + +static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = { + {EFUSE_BLK0, 115, 1}, // Represents whether defense against DPA attack is enabled, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { @@ -295,16 +295,16 @@ static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { {EFUSE_BLK0, 129, 1}, // Disable direct boot mode, }; -static const esp_efuse_desc_t DIS_USB_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // Disable USB Print, +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 130, 1}, // Represents whether print from USB-Serial-JTAG during ROM boot is disabled, }; -static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // Disable download through USB, +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 132, 1}, // Represents whether the USB-Serial-JTAG download func- tion is disabled, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // Enable security download mode, + {EFUSE_BLK0, 133, 1}, // Enable secure download mode, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { @@ -319,6 +319,10 @@ static const esp_efuse_desc_t SECURE_VERSION[] = { {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, }; +static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 158, 1}, // Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled, +}; + static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, }; @@ -729,6 +733,11 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI[] = { + &DIS_SPI_DOWNLOAD_MSPI[0], // Represents whether the SPI0 controller is disabled in boot_mode_download + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { &DIS_TWAI[0], // Disable TWAI function NULL @@ -740,12 +749,12 @@ const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. + &SOFT_DIS_JTAG[0], // Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module. NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently. + &DIS_PAD_JTAG[0], // Hard disable JTAG. JTAG is disabled permanently. NULL }; @@ -754,16 +763,6 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { - &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { - &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { &USB_EXCHG_PINS[0], // Exchange D+ D- pins NULL @@ -830,7 +829,12 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { - &SEC_DPA_LEVEL[0], // Configures the clock random divide mode to determine the spa secure level + &SEC_DPA_LEVEL[0], // Configures the clock random divide mode to determine the DPA security level + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = { + &CRYPT_DPA_ENABLE[0], // Represents whether defense against DPA attack is enabled NULL }; @@ -859,18 +863,18 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[] = { - &DIS_USB_PRINT[0], // Disable USB Print +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // Represents whether print from USB-Serial-JTAG during ROM boot is disabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = { - &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // Represents whether the USB-Serial-JTAG download func- tion is disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + &ENABLE_SECURITY_DOWNLOAD[0], // Enable secure download mode NULL }; @@ -889,6 +893,11 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major NULL diff --git a/components/efuse/esp32c6/esp_efuse_table.csv b/components/efuse/esp32c6/esp_efuse_table.csv index c7a34c4308..242a5c6fee 100644 --- a/components/efuse/esp32c6/esp_efuse_table.csv +++ b/components/efuse/esp32c6/esp_efuse_table.csv @@ -59,13 +59,12 @@ DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, Disable USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function + DIS_SPI_DOWNLOAD_MSPI, EFUSE_BLK0, 45, 1, Represents whether the SPI0 controller is disabled in boot_mode_download DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. - SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. - DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently. + SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module. + DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Hard disable JTAG. JTAG is disabled permanently. DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes. - USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio @@ -84,7 +83,8 @@ KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose - SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, Configures the clock random divide mode to determine the spa secure level + SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, Configures the clock random divide mode to determine the DPA security level + CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, Represents whether defense against DPA attack is enabled SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms @@ -92,12 +92,13 @@ # EFUSE_RD_REPEAT_DATA3_REG # DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode - DIS_USB_PRINT, EFUSE_BLK0, 130, 1, Disable USB Print - DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode + DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Represents whether print from USB-Serial-JTAG during ROM boot is disabled + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Represents whether the USB-Serial-JTAG download func- tion is disabled + ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable secure download mode UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback + SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled # EFUSE_RD_REPEAT_DATA4_REG # DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major diff --git a/components/efuse/esp32c6/include/esp_efuse_table.h b/components/efuse/esp32c6/include/esp_efuse_table.h index f82e1c3d51..fe437ad20e 100644 --- a/components/efuse/esp32c6/include/esp_efuse_table.h +++ b/components/efuse/esp32c6/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280 +// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -61,13 +61,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; @@ -82,17 +81,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; diff --git a/components/hal/esp32c6/efuse_hal.c b/components/hal/esp32c6/efuse_hal.c index 02a3486fab..c3d781632b 100644 --- a/components/hal/esp32c6/efuse_hal.c +++ b/components/hal/esp32c6/efuse_hal.c @@ -78,17 +78,11 @@ bool efuse_hal_is_coding_error_in_block(unsigned block) } } } else if (block <= 10) { - // The order of error in these regs is different only for the C3 chip. - // Fail bit (mask=0x8): - // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low) - // EFUSE_RD_RS_ERR1_REG: BLOCK9, BLOCK8 - // Error num bits (mask=0x7): // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low) - // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 - // BLOCK10 is not presented in the error regs. - uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); - uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4); - return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0); + // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 + block--; + uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); + return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0; } return false; } From 2e8c3c61b3052cc59148b09a2a6defb4968ee073 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 18 Nov 2022 20:39:04 +0800 Subject: [PATCH 2/3] efuse: Adds an option to disable eFuse FPGA tests --- .../efuse/test_apps/main/Kconfig.projbuild | 11 ++++++++++ .../test_apps/main/one_key_block/test_efuse.c | 4 ++-- .../main/one_key_block/test_efuse_keys.c | 22 +++++++++---------- components/efuse/test_apps/main/test_efuse.c | 4 ++-- .../main/with_key_purposes/test_efuse.c | 8 +++---- .../main/with_key_purposes/test_efuse_keys.c | 20 ++++++++--------- 6 files changed, 40 insertions(+), 29 deletions(-) create mode 100644 components/efuse/test_apps/main/Kconfig.projbuild diff --git a/components/efuse/test_apps/main/Kconfig.projbuild b/components/efuse/test_apps/main/Kconfig.projbuild new file mode 100644 index 0000000000..b43354f5a3 --- /dev/null +++ b/components/efuse/test_apps/main/Kconfig.projbuild @@ -0,0 +1,11 @@ +menu "eFuse Tests" + visible if IDF_ENV_FPGA + + config EFUSE_FPGA_TEST + bool "Enable eFuse tests for FPGA (developers only, will PERMANENTLY burn efuses)" + default y if IDF_ENV_FPGA + help + This includes eFuse tests for FPGA. These tests expect actual eFuse burning. + Disable EFUSE_VIRTUAL to use real eFuse burning. + +endmenu diff --git a/components/efuse/test_apps/main/one_key_block/test_efuse.c b/components/efuse/test_apps/main/one_key_block/test_efuse.c index 8b2f3e10c1..ed23c1a4fd 100644 --- a/components/efuse/test_apps/main/one_key_block/test_efuse.c +++ b/components/efuse/test_apps/main/one_key_block/test_efuse.c @@ -121,7 +121,7 @@ TEST_CASE("Test a key read protection 2", "[efuse]") } #endif // CONFIG_EFUSE_VIRTUAL -#ifdef CONFIG_IDF_ENV_FPGA +#ifdef CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test a real write (FPGA)2", "[efuse]") { esp_efuse_utility_debug_dump_blocks(); @@ -150,4 +150,4 @@ TEST_CASE("Test a real write (FPGA)2", "[efuse]") #endif // CONFIG_EFUSE_VIRTUAL esp_efuse_utility_debug_dump_blocks(); } -#endif // CONFIG_IDF_ENV_FPGA +#endif // CONFIG_EFUSE_FPGA_TEST diff --git a/components/efuse/test_apps/main/one_key_block/test_efuse_keys.c b/components/efuse/test_apps/main/one_key_block/test_efuse_keys.c index 7ef8c4091c..8e0e9cd98a 100644 --- a/components/efuse/test_apps/main/one_key_block/test_efuse_keys.c +++ b/components/efuse/test_apps/main/one_key_block/test_efuse_keys.c @@ -46,7 +46,7 @@ TEST_CASE("Test keys and purposes, rd, wr, wr_key_purposes are in the initial st #endif // CONFIG_EFUSE_VIRTUAL // If using efuse is real, then turn off writing tests. -#if CONFIG_EFUSE_VIRTUAL || CONFIG_IDF_ENV_FPGA +#if CONFIG_EFUSE_VIRTUAL || CONFIG_EFUSE_FPGA_TEST static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key, esp_efuse_purpose_t purpose) { @@ -63,16 +63,16 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key, esp_efuse_ uint8_t rd_key[32] = { 0xEE }; TEST_ESP_OK(esp_efuse_read_block(EFUSE_BLK_KEY0, &rd_key, offset_in_bits, key_size * 8)); -#ifndef CONFIG_IDF_ENV_FPGA +#ifndef CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_EQUAL_HEX8_ARRAY(wr_key, rd_key, key_size); -#endif // not CONFIG_IDF_ENV_FPGA +#endif // not CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_TRUE(esp_efuse_get_key_dis_write(num_key)); if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY || purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY_DERIVED_FROM_128_EFUSE_BITS) { TEST_ASSERT_TRUE(esp_efuse_get_key_dis_read(num_key)); -#if CONFIG_IDF_ENV_FPGA && !CONFIG_EFUSE_VIRTUAL +#if CONFIG_EFUSE_FPGA_TEST && !CONFIG_EFUSE_VIRTUAL TEST_ASSERT_EACH_EQUAL_HEX8(0, rd_key, key_size); -#endif // CONFIG_IDF_ENV_FPGA && ! CONFIG_EFUSE_VIRTUAL +#endif // CONFIG_EFUSE_FPGA_TEST && ! CONFIG_EFUSE_VIRTUAL } else { TEST_ASSERT_EQUAL_HEX8_ARRAY(wr_key, rd_key, key_size); } @@ -106,7 +106,7 @@ void test_write_key(esp_efuse_block_t num_key, esp_efuse_purpose_t purpose) { printf("EFUSE_BLK_KEY%d, purpose=%d ... OK\n", id, purpose); } -#ifndef CONFIG_IDF_ENV_FPGA +#ifndef CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]") { uint8_t rd_key[32] = { 0xEE }; @@ -135,7 +135,7 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]") esp_efuse_utility_debug_dump_blocks(); } } -#endif // not CONFIG_IDF_ENV_FPGA +#endif // not CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]") { @@ -151,7 +151,7 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]") esp_efuse_utility_debug_dump_blocks(); TEST_ASSERT_FALSE(esp_efuse_key_block_unused(EFUSE_BLK_KEY0)); -#ifdef CONFIG_IDF_ENV_FPGA +#ifdef CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_TRUE(esp_efuse_block_is_empty(EFUSE_BLK_KEY0)); #else TEST_ASSERT_FALSE(esp_efuse_block_is_empty(EFUSE_BLK_KEY0)); @@ -195,7 +195,7 @@ TEST_CASE("Test 3 esp_efuse_write_key for FPGA", "[efuse]") esp_efuse_utility_debug_dump_blocks(); TEST_ASSERT_FALSE(esp_efuse_key_block_unused(EFUSE_BLK_KEY0)); -#ifdef CONFIG_IDF_ENV_FPGA +#ifdef CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_TRUE(esp_efuse_block_is_empty(EFUSE_BLK_KEY0)); #else TEST_ASSERT_FALSE(esp_efuse_block_is_empty(EFUSE_BLK_KEY0)); @@ -281,11 +281,11 @@ TEST_CASE("Test esp_efuse_write_keys for returned errors", "[efuse]") esp_efuse_utility_debug_dump_blocks(); TEST_ASSERT_FALSE(esp_efuse_key_block_unused(EFUSE_BLK_KEY0)); -#ifdef CONFIG_IDF_ENV_FPGA +#ifdef CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_TRUE(esp_efuse_block_is_empty(EFUSE_BLK_KEY0)); #else TEST_ASSERT_FALSE(esp_efuse_block_is_empty(EFUSE_BLK_KEY0)); #endif } -#endif // CONFIG_EFUSE_VIRTUAL || CONFIG_IDF_ENV_FPGA +#endif // CONFIG_EFUSE_VIRTUAL || CONFIG_EFUSE_FPGA_TEST diff --git a/components/efuse/test_apps/main/test_efuse.c b/components/efuse/test_apps/main/test_efuse.c index 3b4db06d76..1075b3de08 100644 --- a/components/efuse/test_apps/main/test_efuse.c +++ b/components/efuse/test_apps/main/test_efuse.c @@ -824,7 +824,7 @@ TEST_CASE("Check a case when ESP_ERR_DAMAGED_READING occurs during reading efuse } #endif // if not CONFIG_FREERTOS_UNICORE -#ifdef CONFIG_IDF_ENV_FPGA +#ifdef CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test a real write (FPGA)", "[efuse]") { ESP_LOGI(TAG, "1. Write MAC address"); @@ -859,7 +859,7 @@ TEST_CASE("Test a real write (FPGA)", "[efuse]") TEST_ASSERT_EQUAL_INT(i + 1, read_sec_version); } } -#endif // CONFIG_IDF_ENV_FPGA +#endif // CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test chip_ver_pkg APIs return the same value", "[efuse]") { diff --git a/components/efuse/test_apps/main/with_key_purposes/test_efuse.c b/components/efuse/test_apps/main/with_key_purposes/test_efuse.c index 4217a903c9..0f276d9e52 100644 --- a/components/efuse/test_apps/main/with_key_purposes/test_efuse.c +++ b/components/efuse/test_apps/main/with_key_purposes/test_efuse.c @@ -84,7 +84,7 @@ TEST_CASE("Test a write/read protection", "[efuse]") } #endif // CONFIG_EFUSE_VIRTUAL -#ifdef CONFIG_IDF_ENV_FPGA +#ifdef CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test a real write (FPGA)2", "[efuse]") { esp_efuse_utility_debug_dump_blocks(); @@ -113,9 +113,9 @@ TEST_CASE("Test a real write (FPGA)2", "[efuse]") #endif // CONFIG_EFUSE_VIRTUAL esp_efuse_utility_debug_dump_blocks(); } -#endif // CONFIG_IDF_ENV_FPGA +#endif // CONFIG_EFUSE_FPGA_TEST -#if CONFIG_IDF_ENV_FPGA || CONFIG_EFUSE_VIRTUAL +#if CONFIG_EFUSE_FPGA_TEST || CONFIG_EFUSE_VIRTUAL TEST_CASE("Test writing order is BLK_MAX->BLK0", "[efuse]") { uint8_t new_key[32] = {33, 1, 2, 3, 4, 5, 6, 7, 8, 9, @@ -191,4 +191,4 @@ TEST_CASE("Test reading inside of batch mode in a nested way", "[efuse]") esp_efuse_utility_debug_dump_blocks(); } -#endif // CONFIG_IDF_ENV_FPGA || CONFIG_EFUSE_VIRTUAL +#endif // CONFIG_EFUSE_FPGA_TEST || CONFIG_EFUSE_VIRTUAL diff --git a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c index f4bdad6431..9fc3113a9a 100644 --- a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c +++ b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c @@ -49,16 +49,16 @@ TEST_CASE("Test keys and purposes, rd, wr, wr_key_purposes are in the initial st #endif // CONFIG_EFUSE_VIRTUAL // If using efuse is real, then turn off writing tests. -#if CONFIG_EFUSE_VIRTUAL || CONFIG_IDF_ENV_FPGA +#if CONFIG_EFUSE_VIRTUAL || CONFIG_EFUSE_FPGA_TEST static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key) { uint8_t rd_key[32] = { 0xEE }; esp_efuse_purpose_t purpose = esp_efuse_get_key_purpose(num_key); TEST_ESP_OK(esp_efuse_read_field_blob(esp_efuse_get_key(num_key), &rd_key, sizeof(rd_key) * 8)); -#ifndef CONFIG_IDF_ENV_FPGA +#ifndef CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_EQUAL_HEX8_ARRAY(wr_key, rd_key, sizeof(wr_key)); -#endif // not CONFIG_IDF_ENV_FPGA +#endif // not CONFIG_EFUSE_FPGA_TEST TEST_ASSERT_TRUE(esp_efuse_get_key_dis_write(num_key)); if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY || @@ -71,9 +71,9 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key) purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE || purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP) { TEST_ASSERT_TRUE(esp_efuse_get_key_dis_read(num_key)); -#if CONFIG_IDF_ENV_FPGA && !CONFIG_EFUSE_VIRTUAL +#if CONFIG_EFUSE_FPGA_TEST && !CONFIG_EFUSE_VIRTUAL TEST_ASSERT_EACH_EQUAL_HEX8(0, rd_key, sizeof(rd_key)); -#endif // CONFIG_IDF_ENV_FPGA && ! CONFIG_EFUSE_VIRTUAL +#endif // CONFIG_EFUSE_FPGA_TEST && ! CONFIG_EFUSE_VIRTUAL } else { TEST_ASSERT_FALSE(esp_efuse_get_key_dis_read(num_key)); TEST_ASSERT_EQUAL_HEX8_ARRAY(wr_key, rd_key, sizeof(wr_key)); @@ -108,7 +108,7 @@ void test_write_key(esp_efuse_block_t num_key, esp_efuse_purpose_t purpose) { printf("EFUSE_BLK_KEY%d, purpose=%d ... OK\n", id, purpose); } -#ifndef CONFIG_IDF_ENV_FPGA +#ifndef CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]") { uint8_t rd_key[32] = { 0xEE }; @@ -137,7 +137,7 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]") esp_efuse_utility_debug_dump_blocks(); } } -#endif // not CONFIG_IDF_ENV_FPGA +#endif // not CONFIG_EFUSE_FPGA_TEST TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]") { @@ -372,7 +372,7 @@ TEST_CASE("Test set_write_protect_of_digest_revoke", "[efuse]") TEST_ESP_OK(esp_efuse_set_digest_revoke(1)); TEST_ESP_OK(esp_efuse_set_digest_revoke(2)); -#if CONFIG_IDF_ENV_FPGA && !CONFIG_EFUSE_VIRTUAL +#if CONFIG_EFUSE_FPGA_TEST && !CONFIG_EFUSE_VIRTUAL // the write protection bits are set and the revocation bits will not be changed. TEST_ASSERT_FALSE(esp_efuse_get_digest_revoke(0)); TEST_ASSERT_FALSE(esp_efuse_get_digest_revoke(1)); @@ -381,8 +381,8 @@ TEST_CASE("Test set_write_protect_of_digest_revoke", "[efuse]") TEST_ASSERT_TRUE(esp_efuse_get_digest_revoke(0)); TEST_ASSERT_TRUE(esp_efuse_get_digest_revoke(1)); TEST_ASSERT_TRUE(esp_efuse_get_digest_revoke(2)); -#endif // CONFIG_IDF_ENV_FPGA && !CONFIG_EFUSE_VIRTUAL +#endif // CONFIG_EFUSE_FPGA_TEST && !CONFIG_EFUSE_VIRTUAL } #endif // SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY -#endif // CONFIG_EFUSE_VIRTUAL || CONFIG_IDF_ENV_FPGA +#endif // CONFIG_EFUSE_VIRTUAL || CONFIG_EFUSE_FPGA_TEST From f40aed1fe0e4dab9ed61be7b62d95a3d31ac6539 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 18 Nov 2022 21:11:08 +0800 Subject: [PATCH 3/3] doc: Update efuse doc --- .../system/inc/espefuse_summary_ESP32-C6.rst | 150 ++++++++++++++- .../system/inc/show-efuse-table_ESP32-C6.rst | 172 +++++++++++++++++- 2 files changed, 320 insertions(+), 2 deletions(-) diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst index 7d58c58d57..eae9d3c08e 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst @@ -1,3 +1,151 @@ .. code-block:: none - TO BE UPDATED IDF-5919 \ No newline at end of file + espefuse.py -p PORT summary + + Connecting.... + Detecting chip type... ESP32-C6 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) + DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) + DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) + DIS_SPI_DOWNLOAD_MSPI (BLOCK0) SPI0 controller is disabled in boot_mode_download = False R/W (0b0) + DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) + VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0) + BTLC_GPIO_ENABLE (BLOCK0) Enable btlc gpio = 0 R/W (0b00) + POWERGLITCH_EN (BLOCK0) Set this bit to enable power glitch function = False R/W (0b0) + POWER_GLITCH_DSENSE (BLOCK0) Sample delay configuration of power glitch = 0 R/W (0b00) + DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0) + UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) + UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) + FORCE_SEND_RESUME (BLOCK0) Force ROM code to send a resume command during SPI = False R/W (0b0) + bootduring SPI boot + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Efuse fuses: + WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) + + Flash Config fuses: + FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) + unit is (ms/2). When the value is 15, delay is 7. + 5 ms + FLASH_ECC_MODE (BLOCK0) Set this bit to set flsah ecc mode. + = flash ecc 16to18 byte mode R/W (0b0) + FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) + FLASH_PAGE_SIZE (BLOCK0) Flash page size = 0 R/W (0b00) + FLASH_ECC_EN (BLOCK0) Enable ECC for flash boot = False R/W (0b0) + + Identity fuses: + SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) + ure) + MAC (BLOCK1) Factory MAC Address + = 60:55:f9:f6:03:24 (OK) R/W + WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + BLK_VERSION_MINOR (BLOCK1) BLOCK version minor = 0 R/W (0b000) + WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bits = 0 R/W (0b0) + WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLK_VERSION_MAJOR (BLOCK2) BLOCK version major = No calibration R/W (0b00) + CUSTOM_MAC (BLOCK3) Custom MAC Address + = 00:00:00:00:00:00 (OK) R/W + WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) + << 3 + WAFER_VERSION_MINOR_LO (read only) + + Jtag Config fuses: + JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio10 when b + oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa + l to 0. + SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = 0 R/W (0b000) + AG can be activated temporarily by HMAC peripheral + DIS_PAD_JTAG (BLOCK0) Permanently disable JTAG access via pads. USB JTAG = False R/W (0b0) + is controlled separately. + + Security fuses: + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) + des + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) + t mode is set. Enabled when 1 or 3 bits are set,di + sabled otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) + SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) + DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) + h only) + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) FAST VERIFY ON WAKE is disabled or enabled when = False R/W (0b0) + Secure Boot is enabled + SEC_DPA_LEVEL (BLOCK0) Configures the clock random divide mode to = 0 R/W (0b00) + determine the DPA security level + CRYPT_DPA_ENABLE (BLOCK0) Defense against DPA attack is enabled = True R/W (0b1) + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Encryption key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Encryption key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Encryption key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Encryption key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Encryption key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Encryption key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data (part 2) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Spi_Pad_Config fuses: + SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) + SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) + + Usb Config fuses: + DIS_USB_JTAG (BLOCK0) Disables USB JTAG. JTAG access via pads is control = False R/W (0b0) + led separately + DIS_USB_DEVICE (BLOCK0) Disables USB DEVICE = False R/W (0b0) + DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) + USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB-Serial-JTAG during ROM boot is disabled = False R/W (0b0) + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) USB-Serial-JTAG download function is disabled = False R/W (0b0) + + Vdd_Spi Config fuses: + PIN_POWER_SELECTION (BLOCK0) GPIO33-GPIO37 power supply selection in ROM code = VDD3P3_CPU R/W (0b0) + + Wdt Config fuses: + WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = False R/W (0b0) diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst index af20255cc9..55f67a6321 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst @@ -1,4 +1,174 @@ .. code-block:: none - TO BE UPDATED IDF-5919 \ No newline at end of file + $ ./efuse_table_gen.py -t IDF_TARGET_PATH_NAME {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info + + Max number of bits in BLK 256 + Parsing efuse CSV input file esp32c6/esp_efuse_table.csv ... + Verifying efuse table... + Sorted efuse table: + # field_name efuse_block bit_start bit_count + 1 WR_DIS EFUSE_BLK0 0 32 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.SWAP_UART_SDIO_EN EFUSE_BLK0 1 1 + 4 WR_DIS.GROUP_1 EFUSE_BLK0 2 1 + 5 WR_DIS.GROUP_2 EFUSE_BLK0 3 1 + 6 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 + 7 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 + 8 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 + 9 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 + 10 WR_DIS.KEY0_PURPOSE EFUSE_BLK0 8 1 + 11 WR_DIS.KEY1_PURPOSE EFUSE_BLK0 9 1 + 12 WR_DIS.KEY2_PURPOSE EFUSE_BLK0 10 1 + 13 WR_DIS.KEY3_PURPOSE EFUSE_BLK0 11 1 + 14 WR_DIS.KEY4_PURPOSE EFUSE_BLK0 12 1 + 15 WR_DIS.KEY5_PURPOSE EFUSE_BLK0 13 1 + 16 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1 + 17 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 + 18 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 + 19 WR_DIS.GROUP_3 EFUSE_BLK0 18 1 + 20 WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 19 1 + 21 WR_DIS.BLK1 EFUSE_BLK0 20 1 + 22 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 + 23 WR_DIS.USER_DATA EFUSE_BLK0 22 1 + 24 WR_DIS.KEY0 EFUSE_BLK0 23 1 + 25 WR_DIS.KEY1 EFUSE_BLK0 24 1 + 26 WR_DIS.KEY2 EFUSE_BLK0 25 1 + 27 WR_DIS.KEY3 EFUSE_BLK0 26 1 + 28 WR_DIS.KEY4 EFUSE_BLK0 27 1 + 29 WR_DIS.KEY5 EFUSE_BLK0 28 1 + 30 WR_DIS.SYS_DATA_PART2 EFUSE_BLK0 29 1 + 31 RD_DIS EFUSE_BLK0 32 7 + 32 RD_DIS.KEY0 EFUSE_BLK0 32 1 + 33 RD_DIS.KEY1 EFUSE_BLK0 33 1 + 34 RD_DIS.KEY2 EFUSE_BLK0 34 1 + 35 RD_DIS.KEY3 EFUSE_BLK0 35 1 + 36 RD_DIS.KEY4 EFUSE_BLK0 36 1 + 37 RD_DIS.KEY5 EFUSE_BLK0 37 1 + 38 RD_DIS.SYS_DATA_PART2 EFUSE_BLK0 38 1 + 39 SWAP_UART_SDIO_EN EFUSE_BLK0 39 1 + 40 DIS_ICACHE EFUSE_BLK0 40 1 + 41 DIS_USB_JTAG EFUSE_BLK0 41 1 + 42 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 + 43 DIS_USB_SERIAL_JTAG EFUSE_BLK0 43 1 + 44 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 45 DIS_SPI_DOWNLOAD_MSPI EFUSE_BLK0 45 1 + 46 DIS_TWAI EFUSE_BLK0 46 1 + 47 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 + 48 SOFT_DIS_JTAG EFUSE_BLK0 48 3 + 49 DIS_PAD_JTAG EFUSE_BLK0 51 1 + 50 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 + 51 USB_EXCHG_PINS EFUSE_BLK0 57 1 + 52 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1 + 53 WDT_DELAY_SEL EFUSE_BLK0 80 2 + 54 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 + 55 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 + 56 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 + 57 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 + 58 KEY_PURPOSE_0 EFUSE_BLK0 88 4 + 59 KEY_PURPOSE_1 EFUSE_BLK0 92 4 + 60 KEY_PURPOSE_2 EFUSE_BLK0 96 4 + 61 KEY_PURPOSE_3 EFUSE_BLK0 100 4 + 62 KEY_PURPOSE_4 EFUSE_BLK0 104 4 + 63 KEY_PURPOSE_5 EFUSE_BLK0 108 4 + 64 SEC_DPA_LEVEL EFUSE_BLK0 112 2 + 65 CRYPT_DPA_ENABLE EFUSE_BLK0 115 1 + 66 SECURE_BOOT_EN EFUSE_BLK0 116 1 + 67 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 + 68 FLASH_TPUW EFUSE_BLK0 124 4 + 69 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 + 70 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 + 71 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 + 72 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 + 73 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 + 74 UART_PRINT_CONTROL EFUSE_BLK0 134 2 + 75 FORCE_SEND_RESUME EFUSE_BLK0 141 1 + 76 SECURE_VERSION EFUSE_BLK0 142 16 + 77 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 158 1 + 78 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 160 1 + 79 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 161 1 + 80 MAC_FACTORY EFUSE_BLK1 0 8 + 81 MAC_FACTORY EFUSE_BLK1 8 8 + 82 MAC_FACTORY EFUSE_BLK1 16 8 + 83 MAC_FACTORY EFUSE_BLK1 24 8 + 84 MAC_FACTORY EFUSE_BLK1 32 8 + 85 MAC_FACTORY EFUSE_BLK1 40 8 + 86 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 + 87 SPI_PAD_CONFIG_Q_D1 EFUSE_BLK1 54 6 + 88 SPI_PAD_CONFIG_D_D0 EFUSE_BLK1 60 6 + 89 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 + 90 SPI_PAD_CONFIG_HD_D3 EFUSE_BLK1 72 6 + 91 SPI_PAD_CONFIG_WP_D2 EFUSE_BLK1 78 6 + 92 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 + 93 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 + 94 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 + 95 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 + 96 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 + 97 WAFER_VERSION_MINOR EFUSE_BLK1 114 3 + 98 PKG_VERSION EFUSE_BLK1 117 3 + 99 BLK_VERSION_MINOR EFUSE_BLK1 120 3 + 100 K_RTC_LDO EFUSE_BLK1 135 7 + 101 K_DIG_LDO EFUSE_BLK1 142 7 + 102 V_RTC_DBIAS20 EFUSE_BLK1 149 8 + 103 V_DIG_DBIAS20 EFUSE_BLK1 157 8 + 104 DIG_DBIAS_HVT EFUSE_BLK1 165 5 + 105 THRES_HVT EFUSE_BLK1 170 10 + 106 WAFER_VERSION_MINOR EFUSE_BLK1 183 1 + 107 WAFER_VERSION_MAJOR EFUSE_BLK1 184 2 + 108 SYS_DATA_PART2 EFUSE_BLK10 0 256 + 109 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 110 BLK_VERSION_MAJOR EFUSE_BLK2 128 2 + 111 TEMP_CALIB EFUSE_BLK2 131 9 + 112 OCODE EFUSE_BLK2 140 8 + 113 ADC1_INIT_CODE_ATTEN0 EFUSE_BLK2 148 10 + 114 ADC1_INIT_CODE_ATTEN1 EFUSE_BLK2 158 10 + 115 ADC1_INIT_CODE_ATTEN2 EFUSE_BLK2 168 10 + 116 ADC1_INIT_CODE_ATTEN3 EFUSE_BLK2 178 10 + 117 ADC1_CAL_VOL_ATTEN0 EFUSE_BLK2 188 10 + 118 ADC1_CAL_VOL_ATTEN1 EFUSE_BLK2 198 10 + 119 ADC1_CAL_VOL_ATTEN2 EFUSE_BLK2 208 10 + 120 ADC1_CAL_VOL_ATTEN3 EFUSE_BLK2 218 10 + 121 USER_DATA EFUSE_BLK3 0 256 + 122 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 123 KEY0 EFUSE_BLK4 0 256 + 124 KEY1 EFUSE_BLK5 0 256 + 125 KEY2 EFUSE_BLK6 0 256 + 126 KEY3 EFUSE_BLK7 0 256 + 127 KEY4 EFUSE_BLK8 0 256 + 128 KEY5 EFUSE_BLK9 0 256 + + Used bits in efuse table: + EFUSE_BLK0 + [0 31] [0 16] [18 29] [32 38] [32 52] [57 58] [80 113] [115 117] [124 130] [132 135] [141 158] [160 161] + + EFUSE_BLK1 + [0 122] [135 179] [183 185] + + EFUSE_BLK10 + [0 255] + + EFUSE_BLK2 + [0 129] [131 227] + + EFUSE_BLK3 + [0 255] [200 247] + + EFUSE_BLK4 + [0 255] + + EFUSE_BLK5 + [0 255] + + EFUSE_BLK6 + [0 255] + + EFUSE_BLK7 + [0 255] + + EFUSE_BLK8 + [0 255] + + EFUSE_BLK9 + [0 255] + + Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)