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refactor(soc): update soc_etm for esp32c61

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morris
2025-04-10 18:50:36 +08:00
parent 7dd093fc10
commit 62c1e8171e
2 changed files with 2 additions and 30 deletions
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18
components/soc/esp32c61/register/soc/soc_etm_reg.h
View File

@@ -6022,15 +6022,6 @@ extern "C" {
#define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S)
#define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U #define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U
#define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 4 #define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 4
/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [5]; default: 0;
* Represents ADC_TASK_SAMPLE1 trigger status.
* 0: Not triggered
* 1: Triggered
*/
#define SOC_ETM_ADC_TASK_SAMPLE1_ST (BIT(5))
#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S)
#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V 0x00000001U
#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S 5
/** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [6]; default: 0; /** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [6]; default: 0;
* Represents ADC_TASK_START0 trigger status. * Represents ADC_TASK_START0 trigger status.
* 0: Not triggered * 0: Not triggered
@@ -6180,15 +6171,6 @@ extern "C" {
#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S)
#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U
#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 4 #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 4
/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear ADC_TASK_SAMPLE1 trigger status.
* 0: Invalid. No effect
* 1: Clear
*/
#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR (BIT(5))
#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S)
#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V 0x00000001U
#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S 5
/** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [6]; default: 0; /** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [6]; default: 0;
* Configures whether or not to clear ADC_TASK_START0 trigger status. * Configures whether or not to clear ADC_TASK_START0 trigger status.
* 0: Invalid. No effect * 0: Invalid. No effect

14
components/soc/esp32c61/register/soc/soc_etm_struct.h
View File

@@ -1546,12 +1546,7 @@ typedef union {
* 1: Triggered * 1: Triggered
*/ */
uint32_t adc_task_sample0_st:1; uint32_t adc_task_sample0_st:1;
/** adc_task_sample1_st : R/WTC/SS; bitpos: [5]; default: 0; uint32_t reserved_5:1;
* Represents ADC_TASK_SAMPLE1 trigger status.
* 0: Not triggered
* 1: Triggered
*/
uint32_t adc_task_sample1_st:1;
/** adc_task_start0_st : R/WTC/SS; bitpos: [6]; default: 0; /** adc_task_start0_st : R/WTC/SS; bitpos: [6]; default: 0;
* Represents ADC_TASK_START0 trigger status. * Represents ADC_TASK_START0 trigger status.
* 0: Not triggered * 0: Not triggered
@@ -3532,12 +3527,7 @@ typedef union {
* 1: Clear * 1: Clear
*/ */
uint32_t adc_task_sample0_st_clr:1; uint32_t adc_task_sample0_st_clr:1;
/** adc_task_sample1_st_clr : WT; bitpos: [5]; default: 0; uint32_t reserved_5:1;
* Configures whether or not to clear ADC_TASK_SAMPLE1 trigger status.
* 0: Invalid. No effect
* 1: Clear
*/
uint32_t adc_task_sample1_st_clr:1;
/** adc_task_start0_st_clr : WT; bitpos: [6]; default: 0; /** adc_task_start0_st_clr : WT; bitpos: [6]; default: 0;
* Configures whether or not to clear ADC_TASK_START0 trigger status. * Configures whether or not to clear ADC_TASK_START0 trigger status.
* 0: Invalid. No effect * 0: Invalid. No effect