From 2e3c42e41f6a28e5a579e446a355ab06a10f728b Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Sat, 20 Apr 2024 00:56:01 +0800 Subject: [PATCH 1/4] fix(mmap): fixed spi_flash_cache2phys return addr in PSRAM issue When SPIRAM_FETCH_INSTRUCTIONS or SPIRAM_RODATA enabled --- components/esp_psram/mmu_psram_flash.c | 6 +- components/spi_flash/flash_mmap.c | 107 +++++++++++++------------ 2 files changed, 60 insertions(+), 53 deletions(-) diff --git a/components/esp_psram/mmu_psram_flash.c b/components/esp_psram/mmu_psram_flash.c index bfa3daec3b..165589afcf 100644 --- a/components/esp_psram/mmu_psram_flash.c +++ b/components/esp_psram/mmu_psram_flash.c @@ -166,7 +166,8 @@ void instruction_flash_page_info_init(uint32_t psram_start_physical_page) instr_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START))[instr_mmu_offset]; #elif CONFIG_IDF_TARGET_ESP32S3 uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - instr_start_page = *((volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START)); + uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE; + instr_start_page = *((volatile uint32_t *)(DR_REG_MMU_TABLE + instr_mmu_offset * 4)); #endif instr_start_page &= MMU_VALID_VAL_MASK; instr_end_page = instr_start_page + instr_page_cnt - 1; @@ -219,7 +220,8 @@ void rodata_flash_page_info_init(uint32_t psram_start_physical_page) rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_mmu_offset]; #elif CONFIG_IDF_TARGET_ESP32S3 uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START); + uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE; + rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + rodata_mmu_offset * 4); #endif rodata_start_page &= MMU_VALID_VAL_MASK; rodata_end_page = rodata_start_page + rodata_page_cnt - 1; diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index 7950be40fb..b4618b710a 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -81,6 +81,8 @@ static LIST_HEAD(mmap_entries_head, mmap_entry_) s_mmap_entries_head = static uint8_t s_mmap_page_refcnt[SOC_MMU_REGIONS_COUNT * SOC_MMU_PAGES_PER_REGION] = {0}; static uint32_t s_mmap_last_handle = 0; +static uint32_t spi_flash_protected_read_mmu_entry(int index); + static void IRAM_ATTR spi_flash_mmap_init(void) { @@ -330,15 +332,6 @@ static void IRAM_ATTR NOINLINE_ATTR spi_flash_protected_mmap_init(void) spi_flash_enable_interrupts_caches_and_other_cpu(); } -static uint32_t IRAM_ATTR NOINLINE_ATTR spi_flash_protected_read_mmu_entry(int index) -{ - uint32_t value; - spi_flash_disable_interrupts_caches_and_other_cpu(); - value = mmu_ll_read_entry(MMU_TABLE_CORE0, index); - spi_flash_enable_interrupts_caches_and_other_cpu(); - return value; -} - void spi_flash_mmap_dump(void) { spi_flash_protected_mmap_init(); @@ -373,48 +366,6 @@ uint32_t IRAM_ATTR spi_flash_mmap_get_free_pages(spi_flash_mmap_memory_t memory) spi_flash_enable_interrupts_caches_and_other_cpu(); return count; } - -size_t spi_flash_cache2phys(const void *cached) -{ - intptr_t c = (intptr_t)cached; - size_t cache_page; - int offset = 0; - if (c >= SOC_MMU_VADDR1_START_ADDR && c < SOC_MMU_VADDR1_FIRST_USABLE_ADDR) { - /* IRAM address, doesn't map to flash */ - return SPI_FLASH_CACHE2PHYS_FAIL; - } - if (c < SOC_MMU_VADDR1_FIRST_USABLE_ADDR) { - /* expect cache is in DROM */ - cache_page = (c - SOC_MMU_VADDR0_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_DROM0_PAGES_START; -#if CONFIG_SPIRAM_RODATA - if (c >= (uint32_t)&_rodata_reserved_start && c <= (uint32_t)&_rodata_reserved_end) { - offset = rodata_flash2spiram_offset(); - } -#endif - } else { - /* expect cache is in IROM */ - cache_page = (c - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START; -#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS - if (c >= (uint32_t)&_instruction_reserved_start && c <= (uint32_t)&_instruction_reserved_end) { - offset = instruction_flash2spiram_offset(); - } -#endif - } - - if (cache_page >= PAGES_LIMIT) { - /* cached address was not in IROM or DROM */ - return SPI_FLASH_CACHE2PHYS_FAIL; - } - uint32_t phys_page = spi_flash_protected_read_mmu_entry(cache_page); - bool entry_is_invalid = mmu_ll_get_entry_is_invalid(MMU_TABLE_CORE0, cache_page); - if (entry_is_invalid) { - /* page is not mapped */ - return SPI_FLASH_CACHE2PHYS_FAIL; - } - uint32_t phys_offs = ((phys_page & SOC_MMU_ADDR_MASK) + offset) * SPI_FLASH_MMU_PAGE_SIZE; - return phys_offs | (c & (SPI_FLASH_MMU_PAGE_SIZE-1)); -} - const void *IRAM_ATTR spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory) { uint32_t phys_page = phys_offs / SPI_FLASH_MMU_PAGE_SIZE; @@ -532,3 +483,57 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length) return ret; } #endif //!CONFIG_SPI_FLASH_ROM_IMPL + +#if !CONFIG_SPI_FLASH_ROM_IMPL || CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA +static uint32_t IRAM_ATTR NOINLINE_ATTR spi_flash_protected_read_mmu_entry(int index) +{ + uint32_t value; + spi_flash_disable_interrupts_caches_and_other_cpu(); + value = mmu_ll_read_entry(MMU_TABLE_CORE0, index); + spi_flash_enable_interrupts_caches_and_other_cpu(); + return value; +} + +//The ROM implementation returns physical address of the PSRAM when the .text or .rodata is in the PSRAM. +//Always patch it when SPIRAM_FETCH_INSTRUCTIONS or SPIRAM_RODATA is set. +size_t spi_flash_cache2phys(const void *cached) +{ + intptr_t c = (intptr_t)cached; + size_t cache_page; + int offset = 0; + if (c >= SOC_MMU_VADDR1_START_ADDR && c < SOC_MMU_VADDR1_FIRST_USABLE_ADDR) { + /* IRAM address, doesn't map to flash */ + return SPI_FLASH_CACHE2PHYS_FAIL; + } + if (c < SOC_MMU_VADDR1_FIRST_USABLE_ADDR) { + /* expect cache is in DROM */ + cache_page = (c - SOC_MMU_VADDR0_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_DROM0_PAGES_START; +#if CONFIG_SPIRAM_RODATA + if (c >= (uint32_t)&_rodata_reserved_start && c <= (uint32_t)&_rodata_reserved_end) { + offset = rodata_flash2spiram_offset(); + } +#endif + } else { + /* expect cache is in IROM */ + cache_page = (c - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START; +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS + if (c >= (uint32_t)&_instruction_reserved_start && c <= (uint32_t)&_instruction_reserved_end) { + offset = instruction_flash2spiram_offset(); + } +#endif + } + + if (cache_page >= PAGES_LIMIT) { + /* cached address was not in IROM or DROM */ + return SPI_FLASH_CACHE2PHYS_FAIL; + } + uint32_t phys_page = spi_flash_protected_read_mmu_entry(cache_page); + bool entry_is_invalid = mmu_ll_get_entry_is_invalid(MMU_TABLE_CORE0, cache_page); + if (entry_is_invalid) { + /* page is not mapped */ + return SPI_FLASH_CACHE2PHYS_FAIL; + } + uint32_t phys_offs = ((phys_page & SOC_MMU_ADDR_MASK) + offset) * SPI_FLASH_MMU_PAGE_SIZE; + return phys_offs | (c & (SPI_FLASH_MMU_PAGE_SIZE-1)); +} +#endif From 0f1c8cc986788cd855cf550a2669becf4ed97dbe Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Sun, 8 Sep 2024 23:13:52 +0800 Subject: [PATCH 2/4] fix(mmap): fixed spi_flash_phys2cache return addr in PSRAM issue When SPIRAM_FETCH_INSTRUCTIONS or SPIRAM_RODATA enabled --- components/spi_flash/flash_mmap.c | 93 ++++++++++++++++--------------- 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index b4618b710a..2a469ac7fd 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -366,52 +366,6 @@ uint32_t IRAM_ATTR spi_flash_mmap_get_free_pages(spi_flash_mmap_memory_t memory) spi_flash_enable_interrupts_caches_and_other_cpu(); return count; } -const void *IRAM_ATTR spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory) -{ - uint32_t phys_page = phys_offs / SPI_FLASH_MMU_PAGE_SIZE; - int start, end, page_delta; - intptr_t base; - - if (memory == SPI_FLASH_MMAP_DATA) { - start = SOC_MMU_DROM0_PAGES_START; - end = SOC_MMU_DROM0_PAGES_END; - base = SOC_MMU_VADDR0_START_ADDR; - page_delta = SOC_MMU_DROM0_PAGES_START; - } else { - start = SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE; - end = SOC_MMU_IROM0_PAGES_END; - base = SOC_MMU_VADDR1_START_ADDR; - page_delta = SOC_MMU_IROM0_PAGES_START; - } - spi_flash_disable_interrupts_caches_and_other_cpu(); - for (int i = start; i < end; i++) { - uint32_t mmu_value = mmu_ll_read_entry(MMU_TABLE_CORE0, i); -#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS - if (phys_page >= instruction_flash_start_page_get() && phys_page <= instruction_flash_end_page_get()) { - if (mmu_value & MMU_ACCESS_SPIRAM) { - mmu_value += instruction_flash2spiram_offset(); - mmu_value = (mmu_value & SOC_MMU_ADDR_MASK) | MMU_ACCESS_FLASH; - } - } -#endif -#if CONFIG_SPIRAM_RODATA - if (phys_page >= rodata_flash_start_page_get() && phys_page <= rodata_flash_start_page_get()) { - if (mmu_value & MMU_ACCESS_SPIRAM) { - mmu_value += rodata_flash2spiram_offset(); - mmu_value = (mmu_value & SOC_MMU_ADDR_MASK) | MMU_ACCESS_FLASH; - } - } -#endif - if (mmu_value == SOC_MMU_PAGE_IN_FLASH(phys_page)) { - i -= page_delta; - intptr_t cache_page = base + (SPI_FLASH_MMU_PAGE_SIZE * i); - spi_flash_enable_interrupts_caches_and_other_cpu(); - return (const void *) (cache_page | (phys_offs & (SPI_FLASH_MMU_PAGE_SIZE-1))); - } - } - spi_flash_enable_interrupts_caches_and_other_cpu(); - return NULL; -} static bool IRAM_ATTR is_page_mapped_in_cache(uint32_t phys_page, const void **out_ptr) { @@ -536,4 +490,51 @@ size_t spi_flash_cache2phys(const void *cached) uint32_t phys_offs = ((phys_page & SOC_MMU_ADDR_MASK) + offset) * SPI_FLASH_MMU_PAGE_SIZE; return phys_offs | (c & (SPI_FLASH_MMU_PAGE_SIZE-1)); } + +const void *IRAM_ATTR spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory) +{ + uint32_t phys_page = phys_offs / SPI_FLASH_MMU_PAGE_SIZE; + int start, end, page_delta; + intptr_t base; + + if (memory == SPI_FLASH_MMAP_DATA) { + start = SOC_MMU_DROM0_PAGES_START; + end = SOC_MMU_DROM0_PAGES_END; + base = SOC_MMU_VADDR0_START_ADDR; + page_delta = SOC_MMU_DROM0_PAGES_START; + } else { + start = SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE; + end = SOC_MMU_IROM0_PAGES_END; + base = SOC_MMU_VADDR1_START_ADDR; + page_delta = SOC_MMU_IROM0_PAGES_START; + } + spi_flash_disable_interrupts_caches_and_other_cpu(); + for (int i = start; i < end; i++) { + uint32_t mmu_value = mmu_ll_read_entry(MMU_TABLE_CORE0, i); +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS + if (phys_page >= instruction_flash_start_page_get() && phys_page <= instruction_flash_end_page_get()) { + if (mmu_value & MMU_ACCESS_SPIRAM) { + mmu_value += instruction_flash2spiram_offset(); + mmu_value = (mmu_value & SOC_MMU_ADDR_MASK) | MMU_ACCESS_FLASH; + } + } #endif +#if CONFIG_SPIRAM_RODATA + if (phys_page >= rodata_flash_start_page_get() && phys_page <= rodata_flash_start_page_get()) { + if (mmu_value & MMU_ACCESS_SPIRAM) { + mmu_value += rodata_flash2spiram_offset(); + mmu_value = (mmu_value & SOC_MMU_ADDR_MASK) | MMU_ACCESS_FLASH; + } + } +#endif + if (mmu_value == SOC_MMU_PAGE_IN_FLASH(phys_page)) { + i -= page_delta; + intptr_t cache_page = base + (SPI_FLASH_MMU_PAGE_SIZE * i); + spi_flash_enable_interrupts_caches_and_other_cpu(); + return (const void *) (cache_page | (phys_offs & (SPI_FLASH_MMU_PAGE_SIZE-1))); + } + } + spi_flash_enable_interrupts_caches_and_other_cpu(); + return NULL; +} +#endif //!CONFIG_SPI_FLASH_ROM_IMPL || CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA From 4e6af199f20ebacbcfef3473bb0c3837b7a63e61 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Mon, 27 May 2024 01:45:02 +0800 Subject: [PATCH 3/4] ci(spi_flash): add tests for cache2phys with XIP --- components/app_update/test/test_ota_ops.c | 9 +++++++++ components/spi_flash/test/test_mmap.c | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/components/app_update/test/test_ota_ops.c b/components/app_update/test/test_ota_ops.c index b72142d6e1..0dbfabb76c 100644 --- a/components/app_update/test/test_ota_ops.c +++ b/components/app_update/test/test_ota_ops.c @@ -6,6 +6,7 @@ #include #include #include +#include "esp_log.h" #include #include #include @@ -113,3 +114,11 @@ TEST_CASE("esp_ota_get_partition_description", "[ota]") }; TEST_ESP_ERR(ESP_ERR_NOT_FOUND, bootloader_common_get_partition_description(¬_app_pos, &app_desc1)); } + +TEST_CASE("esp_ota_get_running_partition points to correct address", "[spi_flash]") +{ + const esp_partition_t *factory = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, "factory"); + const esp_partition_t* part = esp_ota_get_running_partition(); + ESP_LOGI("running bin", "0x%p", (void*)part->address); + TEST_ASSERT_EQUAL_HEX32(factory->address, part->address); +} diff --git a/components/spi_flash/test/test_mmap.c b/components/spi_flash/test/test_mmap.c index 7dc3e8d104..be28feac28 100644 --- a/components/spi_flash/test/test_mmap.c +++ b/components/spi_flash/test/test_mmap.c @@ -1,6 +1,7 @@ #include #include #include +#include "esp_log.h" #include #include #include @@ -475,4 +476,15 @@ TEST_CASE("no stale data read post mmap and write partition", "[spi_flash][mmap] esp_partition_munmap(handle); TEST_ASSERT_EQUAL(0, memcmp(buf, read_data, sizeof(buf))); } + +TEST_CASE("spi_flash_cache2phys points to correct address", "[spi_flash]") +{ + //_rodata_start, which begins with appdesc, is always the first segment of the bin. + extern int _rodata_start; + size_t addr = spi_flash_cache2phys(&_rodata_start); + + const esp_partition_t *factory = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, "factory"); + ESP_LOGI("running bin", "0x%p", (void*)addr); + TEST_ASSERT_HEX32_WITHIN(CONFIG_MMU_PAGE_SIZE/2, factory->address + CONFIG_MMU_PAGE_SIZE/2, addr); +} #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) From b71af88f45507f477d29afab55f976a22c82809b Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Thu, 27 Mar 2025 18:24:53 +0800 Subject: [PATCH 4/4] ci: increase UT_C2 parallel num --- .gitlab/ci/target-test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index 11a1934083..917c5831a3 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -1012,7 +1012,7 @@ UT_S2_SDSPI: UT_C2: extends: .unit_test_esp32c2_template - parallel: 23 + parallel: 24 tags: - ESP32C2_IDF - UT_T1_1