diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c index 742b2315c0..0eeb53e48f 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_quad.c +++ b/components/esp_psram/device/esp_psram_impl_ap_quad.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,7 +16,7 @@ #include "esp_private/mspi_timing_tuning.h" #include "esp_private/esp_gpio_reserve.h" #include "hal/psram_ctrlr_ll.h" -#include "esp_quad_psram_defs.h" +#include "esp_quad_psram_defs_ap.h" #include "soc/soc_caps.h" static const char* TAG = "quad_psram"; @@ -60,7 +60,7 @@ void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode, static void psram_disable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_QPI, - PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ + PSRAM_QUAD_EXIT_QMODE, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -75,7 +75,7 @@ static void psram_disable_qio_mode(int spi_num) static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode) { psram_exec_cmd(spi_num, mode, - PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ + PSRAM_QUAD_SET_BURST_LEN, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -88,7 +88,7 @@ static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode) static void psram_reset_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_RESET_EN, 8, /* command and command bit len*/ + PSRAM_QUAD_RESET_EN, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -97,7 +97,7 @@ static void psram_reset_mode(int spi_num) false); /* whether is program/erase operation */ psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_RESET, 8, /* command and command bit len*/ + PSRAM_QUAD_RESET, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -144,7 +144,7 @@ bool psram_support_wrap_size(uint32_t wrap_size) static void psram_read_id(int spi_num, uint8_t* dev_id, int id_bits) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_DEVICE_ID, 8, /* command and command bit len*/ + PSRAM_QUAD_DEVICE_ID, 8, /* command and command bit len*/ 0, 24, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -157,7 +157,7 @@ static void psram_read_id(int spi_num, uint8_t* dev_id, int id_bits) static void psram_enable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ + PSRAM_QUAD_ENTER_QMODE, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -168,14 +168,14 @@ static void psram_enable_qio_mode(int spi_num) static void psram_set_cs_timing(void) { - psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_HOLD_VAL); - psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_SETUP_VAL); + psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_HOLD_VAL); + psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_SETUP_VAL); } static void psram_gpio_config(void) { //CS1 - uint8_t cs1_io = PSRAM_CS_IO; + uint8_t cs1_io = PSRAM_QUAD_CS_IO; if (cs1_io == MSPI_IOMUX_PIN_NUM_CS1) { gpio_ll_func_sel(&GPIO, cs1_io, FUNC_SPICS1_SPICS1); } else { @@ -185,7 +185,7 @@ static void psram_gpio_config(void) s_psram_cs_io = cs1_io; //WP HD - uint8_t wp_io = PSRAM_SPIWP_SD3_IO; + uint8_t wp_io = PSRAM_QUAD_SPIWP_SD3_IO; #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { @@ -224,7 +224,7 @@ static void s_config_psram_clock(void) bool s_check_aps3204_2tmode(void) { uint64_t full_eid = 0; - psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_EID_BITS_NUM); + psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_QUAD_EID_BITS_NUM); bool is_2t = false; uint32_t eid_47_16 = __builtin_bswap32((full_eid >> 16) & UINT32_MAX); @@ -250,31 +250,31 @@ esp_err_t esp_psram_impl_enable(void) //We use SPI1 to init PSRAM psram_disable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1); - psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM); - if (!PSRAM_IS_VALID(psram_id)) { + psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM); + if (!PSRAM_QUAD_IS_VALID(psram_id)) { /* 16Mbit psram ID read error workaround: * treat the first read id as a dummy one as the pre-condition, * Send Read ID command again */ - psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM); - if (!PSRAM_IS_VALID(psram_id)) { + psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM); + if (!PSRAM_QUAD_IS_VALID(psram_id)) { ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)psram_id); return ESP_ERR_NOT_SUPPORTED; } } - if (PSRAM_IS_64MBIT_TRIAL(psram_id)) { + if (PSRAM_QUAD_IS_64MBIT_TRIAL(psram_id)) { s_psram_size = PSRAM_SIZE_8MB; } else { - uint8_t density = PSRAM_SIZE_ID(psram_id); - const int eid = PSRAM_EID_BIT_47_40(psram_id); + uint8_t density = PSRAM_QUAD_SIZE_ID(psram_id); + const int eid = PSRAM_QUAD_EID_BIT_47_40(psram_id); s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB : density == 0x1 ? PSRAM_SIZE_4MB : density == 0x2 ? PSRAM_SIZE_8MB : /* Do not use `density` for QEMU PSRAM since we don't want any future QSPI PSRAM * that are 16MB or 32MB to be interpreted as QEMU PSRAM devices */ - eid == PSRAM_QEMU_16MB_ID ? PSRAM_SIZE_16MB : - eid == PSRAM_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0; + eid == PSRAM_QUAD_QEMU_16MB_ID ? PSRAM_SIZE_16MB : + eid == PSRAM_QUAD_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0; } if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_aps3204_2tmode()) { @@ -306,10 +306,10 @@ esp_err_t esp_psram_impl_enable(void) static void config_psram_spi_phases(void) { psram_ctrlr_ll_set_read_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_HAL_CMD_QPI); - psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_QUAD_WRITE); - psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_FAST_READ_QUAD); - psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_ADDR_LENGTH); - psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_FAST_READ_QUAD_DUMMY); + psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CMD_LENGTH, PSRAM_QUAD_WRITE_QUAD); + psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CMD_LENGTH, PSRAM_QUAD_FAST_READ_QUAD); + psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_ADDR_LENGTH); + psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_FAST_READ_QUAD_DUMMY); psram_ctrlr_ll_set_cs_pin(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_CS_ID_1); } diff --git a/components/esp_psram/device/esp_quad_psram_defs.h b/components/esp_psram/device/esp_quad_psram_defs.h deleted file mode 100644 index e78437768f..0000000000 --- a/components/esp_psram/device/esp_quad_psram_defs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -//Commands for PSRAM chip - -#pragma once - -#include "soc/spi_pins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PSRAM_READ 0x03 -#define PSRAM_FAST_READ 0x0B -#define PSRAM_FAST_READ_QUAD 0xEB -#define PSRAM_WRITE 0x02 -#define PSRAM_QUAD_WRITE 0x38 -#define PSRAM_ENTER_QMODE 0x35 -#define PSRAM_EXIT_QMODE 0xF5 -#define PSRAM_RESET_EN 0x66 -#define PSRAM_RESET 0x99 -#define PSRAM_SET_BURST_LEN 0xC0 -#define PSRAM_DEVICE_ID 0x9F - -#define PSRAM_FAST_READ_DUMMY 4 -#define PSRAM_FAST_READ_QUAD_DUMMY 6 - -// ID -#define PSRAM_ID_BITS_NUM 24 -#define PSRAM_EID_BITS_NUM 48 -#define PSRAM_ID_KGD_M 0xff -#define PSRAM_ID_KGD_S 8 -#define PSRAM_ID_KGD 0x5d -#define PSRAM_ID_EID_BIT_47_40_M 0xff -#define PSRAM_ID_EID_BIT_47_40_S 16 - -// Use the [47:45](bit47~bit45) of EID to distinguish the psram size: -// -// BIT47 | BIT46 | BIT45 | SIZE(MBIT) -// ------------------------------------- -// 0 | 0 | 0 | 16 -// 0 | 0 | 1 | 32 -// 0 | 1 | 0 | 64 -#define PSRAM_EID_BIT_47_45_M 0x07 -#define PSRAM_EID_BIT_47_45_S 5 - -#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) -#define PSRAM_EID_BIT_47_40(id) (((id) >> PSRAM_ID_EID_BIT_47_40_S) & PSRAM_ID_EID_BIT_47_40_M) -#define PSRAM_SIZE_ID(id) ((PSRAM_EID_BIT_47_40(id) >> PSRAM_EID_BIT_47_45_S) & PSRAM_EID_BIT_47_45_M) -#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) - -#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID_BIT_47_40(id) == 0x26) - -// IO-pins for PSRAM. -// PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO MSPI_IOMUX_PIN_NUM_CLK -#define PSRAM_CS_IO MSPI_IOMUX_PIN_NUM_CS1 -#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO -#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI -#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP -#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD - -#define PSRAM_CMD_LENGTH 8 -#define PSRAM_ADDR_LENGTH 24 - -#define PSRAM_CS_HOLD_VAL 1 -#define PSRAM_CS_SETUP_VAL 1 - -// QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these. -#define PSRAM_QEMU_16MB_ID 0x6a -#define PSRAM_QEMU_32MB_ID 0x8e - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_psram/device/esp_quad_psram_defs_ap.h b/components/esp_psram/device/esp_quad_psram_defs_ap.h new file mode 100644 index 0000000000..e1b0cb4481 --- /dev/null +++ b/components/esp_psram/device/esp_quad_psram_defs_ap.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//Commands for PSRAM chip + +#pragma once + +#include "soc/spi_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------------------------- + * AP Memory PSRAM + *-------------------------------------------------------------------------------*/ + +#define PSRAM_QUAD_READ 0x03 +#define PSRAM_QUAD_FAST_READ 0x0B +#define PSRAM_QUAD_FAST_READ_QUAD 0xEB +#define PSRAM_QUAD_WRITE 0x02 +#define PSRAM_QUAD_WRITE_QUAD 0x38 +#define PSRAM_QUAD_ENTER_QMODE 0x35 +#define PSRAM_QUAD_EXIT_QMODE 0xF5 +#define PSRAM_QUAD_RESET_EN 0x66 +#define PSRAM_QUAD_RESET 0x99 +#define PSRAM_QUAD_SET_BURST_LEN 0xC0 +#define PSRAM_QUAD_DEVICE_ID 0x9F + +#define PSRAM_QUAD_FAST_READ_DUMMY 4 +#define PSRAM_QUAD_FAST_READ_QUAD_DUMMY 6 + +// ID +#define PSRAM_QUAD_ID_BITS_NUM 24 +#define PSRAM_QUAD_EID_BITS_NUM 48 +#define PSRAM_QUAD_ID_KGD_M 0xff +#define PSRAM_QUAD_ID_KGD_S 8 +#define PSRAM_QUAD_ID_KGD 0x5d +#define PSRAM_QUAD_ID_EID_BIT_47_40_M 0xff +#define PSRAM_QUAD_ID_EID_BIT_47_40_S 16 + +// Use the [47:45](bit47~bit45) of EID to distinguish the psram size: +// +// BIT47 | BIT46 | BIT45 | SIZE(MBIT) +// ------------------------------------- +// 0 | 0 | 0 | 16 +// 0 | 0 | 1 | 32 +// 0 | 1 | 0 | 64 +#define PSRAM_QUAD_EID_BIT_47_45_M 0x07 +#define PSRAM_QUAD_EID_BIT_47_45_S 5 + +#define PSRAM_QUAD_KGD(id) (((id) >> PSRAM_QUAD_ID_KGD_S) & PSRAM_QUAD_ID_KGD_M) +#define PSRAM_QUAD_EID_BIT_47_40(id) (((id) >> PSRAM_QUAD_ID_EID_BIT_47_40_S) & PSRAM_QUAD_ID_EID_BIT_47_40_M) +#define PSRAM_QUAD_SIZE_ID(id) ((PSRAM_QUAD_EID_BIT_47_40(id) >> PSRAM_QUAD_EID_BIT_47_45_S) & PSRAM_QUAD_EID_BIT_47_45_M) +#define PSRAM_QUAD_IS_VALID(id) (PSRAM_QUAD_KGD(id) == PSRAM_QUAD_ID_KGD) + +#define PSRAM_QUAD_IS_64MBIT_TRIAL(id) (PSRAM_QUAD_EID_BIT_47_40(id) == 0x26) + +// IO-pins for PSRAM. +// PSRAM clock and cs IO should be configured based on hardware design. +#define PSRAM_QUAD_CLK_IO MSPI_IOMUX_PIN_NUM_CLK +#define PSRAM_QUAD_CS_IO MSPI_IOMUX_PIN_NUM_CS1 +#define PSRAM_QUAD_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO +#define PSRAM_QUAD_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI +#define PSRAM_QUAD_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP +#define PSRAM_QUAD_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD + +#define PSRAM_QUAD_CMD_LENGTH 8 +#define PSRAM_QUAD_ADDR_LENGTH 24 + +#define PSRAM_QUAD_CS_HOLD_VAL 1 +#define PSRAM_QUAD_CS_SETUP_VAL 1 + +// QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these. +#define PSRAM_QUAD_QEMU_16MB_ID 0x6a +#define PSRAM_QUAD_QEMU_32MB_ID 0x8e + +#ifdef __cplusplus +} +#endif