forked from espressif/esp-idf
i2s_tdm: fixed half sample bit calculation and added check for slot mask
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@ -93,6 +93,7 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
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static esp_err_t i2s_tdm_set_slot(i2s_chan_handle_t handle, const i2s_tdm_slot_config_t *slot_cfg)
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static esp_err_t i2s_tdm_set_slot(i2s_chan_handle_t handle, const i2s_tdm_slot_config_t *slot_cfg)
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{
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{
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ESP_RETURN_ON_FALSE(slot_cfg->slot_mask, ESP_ERR_INVALID_ARG, TAG, "At least one channel should be enabled");
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/* Update the total slot num and active slot num */
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/* Update the total slot num and active slot num */
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handle->active_slot = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO ? 1 : __builtin_popcount(slot_cfg->slot_mask);
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handle->active_slot = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO ? 1 : __builtin_popcount(slot_cfg->slot_mask);
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uint32_t max_slot_num = 32 - __builtin_clz(slot_cfg->slot_mask);
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uint32_t max_slot_num = 32 - __builtin_clz(slot_cfg->slot_mask);
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@ -251,7 +251,7 @@ void i2s_hal_tdm_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
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i2s_ll_tx_set_active_chan_mask(hal->dev, (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ?
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i2s_ll_tx_set_active_chan_mask(hal->dev, (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ?
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I2S_TDM_SLOT0 : (uint32_t)slot_cfg->tdm.slot_mask);
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I2S_TDM_SLOT0 : (uint32_t)slot_cfg->tdm.slot_mask);
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i2s_ll_tx_set_skip_mask(hal->dev, slot_cfg->tdm.skip_mask);
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i2s_ll_tx_set_skip_mask(hal->dev, slot_cfg->tdm.skip_mask);
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i2s_ll_tx_set_half_sample_bit(hal->dev, __builtin_popcount(slot_cfg->tdm.slot_mask) * slot_bit_width / 2);
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i2s_ll_tx_set_half_sample_bit(hal->dev, total_slot * slot_bit_width / 2);
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i2s_ll_tx_set_bit_order(hal->dev, slot_cfg->tdm.bit_order_lsb);
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i2s_ll_tx_set_bit_order(hal->dev, slot_cfg->tdm.bit_order_lsb);
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i2s_ll_tx_enable_left_align(hal->dev, slot_cfg->tdm.left_align);
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i2s_ll_tx_enable_left_align(hal->dev, slot_cfg->tdm.left_align);
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i2s_ll_tx_enable_big_endian(hal->dev, slot_cfg->tdm.big_endian);
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i2s_ll_tx_enable_big_endian(hal->dev, slot_cfg->tdm.big_endian);
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@ -284,7 +284,7 @@ void i2s_hal_tdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
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/* In mono mode, there only should be one slot enabled, other inactive slots will transmit same data as enabled slot */
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/* In mono mode, there only should be one slot enabled, other inactive slots will transmit same data as enabled slot */
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i2s_ll_rx_set_active_chan_mask(hal->dev, (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ?
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i2s_ll_rx_set_active_chan_mask(hal->dev, (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ?
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I2S_TDM_SLOT0 : (uint32_t)slot_cfg->tdm.slot_mask);
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I2S_TDM_SLOT0 : (uint32_t)slot_cfg->tdm.slot_mask);
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i2s_ll_rx_set_half_sample_bit(hal->dev, __builtin_popcount(slot_cfg->tdm.slot_mask) * slot_bit_width / 2);
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i2s_ll_rx_set_half_sample_bit(hal->dev, total_slot * slot_bit_width / 2);
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i2s_ll_rx_set_bit_order(hal->dev, slot_cfg->tdm.bit_order_lsb);
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i2s_ll_rx_set_bit_order(hal->dev, slot_cfg->tdm.bit_order_lsb);
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i2s_ll_rx_enable_left_align(hal->dev, slot_cfg->tdm.left_align);
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i2s_ll_rx_enable_left_align(hal->dev, slot_cfg->tdm.left_align);
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i2s_ll_rx_enable_big_endian(hal->dev, slot_cfg->tdm.big_endian);
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i2s_ll_rx_enable_big_endian(hal->dev, slot_cfg->tdm.big_endian);
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