diff --git a/components/hal/include/hal/i2c_types.h b/components/hal/include/hal/i2c_types.h index 5e37c7e411..ea733f3566 100644 --- a/components/hal/include/hal/i2c_types.h +++ b/components/hal/include/hal/i2c_types.h @@ -92,11 +92,12 @@ typedef struct { int timeout; /*!< timeout value */ } i2c_hal_timing_config_t; - +#if SOC_I2C_SUPPORTED /** * @brief I2C group clock source */ typedef soc_periph_i2c_clk_src_t i2c_clock_source_t; +#endif #ifdef __cplusplus diff --git a/components/soc/esp32c6/include/soc/parl_io_struct.h b/components/soc/esp32c6/include/soc/parl_io_struct.h index 21b5f63495..816a7de3ef 100644 --- a/components/soc/esp32c6/include/soc/parl_io_struct.h +++ b/components/soc/esp32c6/include/soc/parl_io_struct.h @@ -14,7 +14,7 @@ extern "C" { /** Type of rx_cfg0 register * Parallel RX module configuration register0. */ -typedef volatile union { +typedef union { struct { /** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0; * Write 0 to select eof generated manchnism by configured data byte length. Write 1 diff --git a/components/soc/esp32p4/adc_periph.c b/components/soc/esp32p4/adc_periph.c index 050fb96675..47081cfc68 100644 --- a/components/soc/esp32p4/adc_periph.c +++ b/components/soc/esp32p4/adc_periph.c @@ -7,15 +7,4 @@ #include "soc/adc_periph.h" /* Store IO number corresponding to the ADC channel number. */ -const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { - /* ADC1 */ - { - ADC1_CHANNEL_0_GPIO_NUM, - ADC1_CHANNEL_1_GPIO_NUM, - ADC1_CHANNEL_2_GPIO_NUM, - ADC1_CHANNEL_3_GPIO_NUM, - ADC1_CHANNEL_4_GPIO_NUM, - ADC1_CHANNEL_5_GPIO_NUM, - ADC1_CHANNEL_6_GPIO_NUM, - }, -}; +const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {}; diff --git a/components/soc/esp32p4/gdma_periph.c b/components/soc/esp32p4/gdma_periph.c index 5ddc769de5..890525bc2b 100644 --- a/components/soc/esp32p4/gdma_periph.c +++ b/components/soc/esp32p4/gdma_periph.c @@ -6,20 +6,4 @@ #include "soc/gdma_periph.h" -const gdma_signal_conn_t gdma_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_GDMA_MODULE, - .pairs = { - [0] = { - .rx_irq_id = ETS_DMA2D_IN_CH0_INTR_SOURCE, - .tx_irq_id = ETS_DMA2D_OUT_CH0_INTR_SOURCE, - }, - [1] = { - .rx_irq_id = ETS_DMA2D_IN_CH1_INTR_SOURCE, - .tx_irq_id = ETS_DMA2D_OUT_CH1_INTR_SOURCE, - }, - } - } - } -}; +const gdma_signal_conn_t gdma_periph_signals = {}; diff --git a/components/soc/esp32p4/gpio_periph.c b/components/soc/esp32p4/gpio_periph.c index c8158d5e19..c23436882a 100644 --- a/components/soc/esp32p4/gpio_periph.c +++ b/components/soc/esp32p4/gpio_periph.c @@ -7,99 +7,13 @@ #include "soc/gpio_periph.h" const uint32_t GPIO_PIN_MUX_REG[] = { - IO_MUX_GPIO0_REG, - IO_MUX_GPIO1_REG, - IO_MUX_GPIO2_REG, - IO_MUX_GPIO3_REG, - IO_MUX_GPIO4_REG, - IO_MUX_GPIO5_REG, - IO_MUX_GPIO6_REG, - IO_MUX_GPIO7_REG, - IO_MUX_GPIO8_REG, - IO_MUX_GPIO9_REG, - IO_MUX_GPIO10_REG, - IO_MUX_GPIO11_REG, - IO_MUX_GPIO12_REG, - IO_MUX_GPIO13_REG, - IO_MUX_GPIO14_REG, - IO_MUX_GPIO15_REG, - IO_MUX_GPIO16_REG, - IO_MUX_GPIO17_REG, - IO_MUX_GPIO18_REG, - IO_MUX_GPIO19_REG, - IO_MUX_GPIO20_REG, - IO_MUX_GPIO21_REG, - IO_MUX_GPIO22_REG, - IO_MUX_GPIO23_REG, - IO_MUX_GPIO24_REG, - IO_MUX_GPIO25_REG, - IO_MUX_GPIO26_REG, - IO_MUX_GPIO27_REG, - IO_MUX_GPIO28_REG, - IO_MUX_GPIO29_REG, - IO_MUX_GPIO30_REG, - IO_MUX_GPIO31_REG, - IO_MUX_GPIO32_REG, - IO_MUX_GPIO33_REG, - IO_MUX_GPIO34_REG, - IO_MUX_GPIO35_REG, - IO_MUX_GPIO36_REG, - IO_MUX_GPIO37_REG, - IO_MUX_GPIO38_REG, - IO_MUX_GPIO39_REG, - IO_MUX_GPIO40_REG, - IO_MUX_GPIO41_REG, - IO_MUX_GPIO42_REG, - IO_MUX_GPIO43_REG, - IO_MUX_GPIO44_REG, - IO_MUX_GPIO45_REG, - IO_MUX_GPIO46_REG, - IO_MUX_GPIO47_REG, - IO_MUX_GPIO48_REG, - IO_MUX_GPIO49_REG, - IO_MUX_GPIO50_REG, - IO_MUX_GPIO51_REG, - IO_MUX_GPIO52_REG, - IO_MUX_GPIO53_REG, - IO_MUX_GPIO54_REG, - IO_MUX_GPIO55_REG, - IO_MUX_GPIO56_REG, + }; -_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); +// _Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); const uint32_t GPIO_HOLD_MASK[] = { - BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG - BIT(1), //GPIO1 - BIT(2), //GPIO2 - BIT(3), //GPIO3 - BIT(4), //GPIO4 - BIT(5), //GPIO5 - BIT(6), //GPIO6 - BIT(7), //GPIO7 - BIT(8), //GPIO8 - BIT(9), //GPIO9 - BIT(10), //GPIO10 - BIT(11), //GPIO11 - BIT(12), //GPIO12 - BIT(13), //GPIO13 - BIT(14), //GPIO14 - BIT(15), //GPIO15 - BIT(16), //GPIO16 - BIT(17), //GPIO17 - BIT(18), //GPIO18 - BIT(19), //GPIO19 - BIT(20), //GPIO20 - BIT(21), //GPIO21 - BIT(22), //GPIO22 - BIT(23), //GPIO23 - BIT(24), //GPIO24 - BIT(25), //GPIO25 - BIT(26), //GPIO26 - BIT(27), //GPIO27 - BIT(28), //GPIO28 - BIT(29), //GPIO29 - BIT(30), //GPIO30 + }; -_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); +// _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c index dd08f58a60..b444a1255d 100644 --- a/components/soc/esp32p4/i2c_periph.c +++ b/components/soc/esp32p4/i2c_periph.c @@ -11,12 +11,4 @@ Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc */ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { - { - .sda_out_sig = I2CEXT0_SDA_OUT_IDX, - .sda_in_sig = I2CEXT0_SDA_IN_IDX, - .scl_out_sig = I2CEXT0_SCL_OUT_IDX, - .scl_in_sig = I2CEXT0_SCL_IN_IDX, - .irq = ETS_I2C_EXT0_INTR_SOURCE, - .module = PERIPH_I2C0_MODULE, - }, }; diff --git a/components/soc/esp32p4/i2s_periph.c b/components/soc/esp32p4/i2s_periph.c index 15a7ff4fff..1e466a3433 100644 --- a/components/soc/esp32p4/i2s_periph.c +++ b/components/soc/esp32p4/i2s_periph.c @@ -11,24 +11,4 @@ Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc */ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { - { - .mck_out_sig = 0, - - .m_tx_bck_sig = 0, - .m_rx_bck_sig = 0, - .m_tx_ws_sig = 0, - .m_rx_ws_sig = 0, - - .s_tx_bck_sig = 0, - .s_rx_bck_sig = 0, - .s_tx_ws_sig = 0, - .s_rx_ws_sig = 0, - - .data_out_sigs[0] = 0, - .data_out_sigs[1] = 0, - .data_in_sig = 0, - - .irq = -1, - .module = PERIPH_I2S1_MODULE, - } }; diff --git a/components/soc/esp32p4/include/modem/modem_lpcon_reg.h b/components/soc/esp32p4/include/modem/modem_lpcon_reg.h deleted file mode 100644 index 63889d3e68..0000000000 --- a/components/soc/esp32p4/include/modem/modem_lpcon_reg.h +++ /dev/null @@ -1,382 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "modem/reg_base.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) -/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_EN (BIT(0)) -#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S) -#define MODEM_LPCON_CLK_EN_V 0x00000001U -#define MODEM_LPCON_CLK_EN_S 0 -/* MODEM_LPCON_CLK_DEBUG_ENA : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_DEBUG_ENA (BIT(1)) -#define MODEM_LPCON_CLK_DEBUG_ENA_M (MODEM_LPCON_CLK_DEBUG_ENA_V << MODEM_LPCON_CLK_DEBUG_ENA_S) -#define MODEM_LPCON_CLK_DEBUG_ENA_V 0x00000001U -#define MODEM_LPCON_CLK_DEBUG_ENA_S 1 - -#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x00000001U -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x00000001U -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x00000001U -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x00000001U -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFFU -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S) -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0x00000FFFU -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 - -#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S) -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 - -#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc) -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x00000001U -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x00000001U -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x00000001U -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x00000001U -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFFU -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S) -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0x00000FFFU -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 - -#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) -/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_I2C_MST_SEL_160M (BIT(0)) -#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M (MODEM_LPCON_CLK_I2C_MST_SEL_160M_V << MODEM_LPCON_CLK_I2C_MST_SEL_160M_S) -#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V 0x00000001U -#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S 0 - -#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) -/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003U -#define MODEM_LPCON_CLK_MODEM_32K_SEL_M (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S) -#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x00000003U -#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 - -#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) -/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_M (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S) -#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x00000001U -#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 -/* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S) -#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U -#define MODEM_LPCON_CLK_COEX_EN_S 1 -/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S) -#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U -#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_M (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S) -#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x00000001U -#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 - -#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c) -/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_M (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S) -#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x00000001U -#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 -/* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S) -#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U -#define MODEM_LPCON_CLK_COEX_FO_S 1 -/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S) -#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U -#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_M (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S) -#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x00000001U -#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 -/* MODEM_LPCON_CLK_BCMEM_FO : R/W; bitpos: [4]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_BCMEM_FO (BIT(4)) -#define MODEM_LPCON_CLK_BCMEM_FO_M (MODEM_LPCON_CLK_BCMEM_FO_V << MODEM_LPCON_CLK_BCMEM_FO_S) -#define MODEM_LPCON_CLK_BCMEM_FO_V 0x00000001U -#define MODEM_LPCON_CLK_BCMEM_FO_S 4 -/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W; bitpos: [5]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO (BIT(5)) -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M (MODEM_LPCON_CLK_I2C_MST_MEM_FO_V << MODEM_LPCON_CLK_I2C_MST_MEM_FO_S) -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V 0x00000001U -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S 5 -/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W; bitpos: [6]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO (BIT(6)) -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M (MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V << MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S) -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V 0x00000001U -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S 6 -/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W; bitpos: [7]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_PBUS_MEM_FO (BIT(7)) -#define MODEM_LPCON_CLK_PBUS_MEM_FO_M (MODEM_LPCON_CLK_PBUS_MEM_FO_V << MODEM_LPCON_CLK_PBUS_MEM_FO_S) -#define MODEM_LPCON_CLK_PBUS_MEM_FO_V 0x00000001U -#define MODEM_LPCON_CLK_PBUS_MEM_FO_S 7 -/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W; bitpos: [8]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_AGC_MEM_FO (BIT(8)) -#define MODEM_LPCON_CLK_AGC_MEM_FO_M (MODEM_LPCON_CLK_AGC_MEM_FO_V << MODEM_LPCON_CLK_AGC_MEM_FO_S) -#define MODEM_LPCON_CLK_AGC_MEM_FO_V 0x00000001U -#define MODEM_LPCON_CLK_AGC_MEM_FO_S 8 -/* MODEM_LPCON_CLK_DC_MEM_FO : R/W; bitpos: [9]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_DC_MEM_FO (BIT(9)) -#define MODEM_LPCON_CLK_DC_MEM_FO_M (MODEM_LPCON_CLK_DC_MEM_FO_V << MODEM_LPCON_CLK_DC_MEM_FO_S) -#define MODEM_LPCON_CLK_DC_MEM_FO_V 0x00000001U -#define MODEM_LPCON_CLK_DC_MEM_FO_S 9 - -#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) -/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000FU -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S) -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0x0000000FU -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 -/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000FU -#define MODEM_LPCON_CLK_COEX_ST_MAP_M (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S) -#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0x0000000FU -#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 -/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000FU -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S) -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0x0000000FU -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 -/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000FU -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S) -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0x0000000FU -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 - -#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) -/* MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_LPCON_RST_WIFIPWR (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_M (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S) -#define MODEM_LPCON_RST_WIFIPWR_V 0x00000001U -#define MODEM_LPCON_RST_WIFIPWR_S 0 -/* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_RST_COEX (BIT(1)) -#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S) -#define MODEM_LPCON_RST_COEX_V 0x00000001U -#define MODEM_LPCON_RST_COEX_S 1 -/* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_LPCON_RST_I2C_MST (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S) -#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U -#define MODEM_LPCON_RST_I2C_MST_S 2 -/* MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_M (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S) -#define MODEM_LPCON_RST_LP_TIMER_V 0x00000001U -#define MODEM_LPCON_RST_LP_TIMER_S 3 - -#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) -/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1; */ -/*description: */ -#define MODEM_LPCON_DC_MEM_FORCE_PU (BIT(0)) -#define MODEM_LPCON_DC_MEM_FORCE_PU_M (MODEM_LPCON_DC_MEM_FORCE_PU_V << MODEM_LPCON_DC_MEM_FORCE_PU_S) -#define MODEM_LPCON_DC_MEM_FORCE_PU_V 0x00000001U -#define MODEM_LPCON_DC_MEM_FORCE_PU_S 0 -/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_LPCON_DC_MEM_FORCE_PD (BIT(1)) -#define MODEM_LPCON_DC_MEM_FORCE_PD_M (MODEM_LPCON_DC_MEM_FORCE_PD_V << MODEM_LPCON_DC_MEM_FORCE_PD_S) -#define MODEM_LPCON_DC_MEM_FORCE_PD_V 0x00000001U -#define MODEM_LPCON_DC_MEM_FORCE_PD_S 1 -/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; */ -/*description: */ -#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2)) -#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S) -#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x00000001U -#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2 -/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3)) -#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S) -#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x00000001U -#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3 -/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; */ -/*description: */ -#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4)) -#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S) -#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x00000001U -#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4 -/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; */ -/*description: */ -#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5)) -#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S) -#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x00000001U -#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5 -/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W; bitpos: [6]; default: 0; */ -/*description: */ -#define MODEM_LPCON_BC_MEM_FORCE_PU (BIT(6)) -#define MODEM_LPCON_BC_MEM_FORCE_PU_M (MODEM_LPCON_BC_MEM_FORCE_PU_V << MODEM_LPCON_BC_MEM_FORCE_PU_S) -#define MODEM_LPCON_BC_MEM_FORCE_PU_V 0x00000001U -#define MODEM_LPCON_BC_MEM_FORCE_PU_S 6 -/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W; bitpos: [7]; default: 0; */ -/*description: */ -#define MODEM_LPCON_BC_MEM_FORCE_PD (BIT(7)) -#define MODEM_LPCON_BC_MEM_FORCE_PD_M (MODEM_LPCON_BC_MEM_FORCE_PD_V << MODEM_LPCON_BC_MEM_FORCE_PD_S) -#define MODEM_LPCON_BC_MEM_FORCE_PD_V 0x00000001U -#define MODEM_LPCON_BC_MEM_FORCE_PD_S 7 -/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0; */ -/*description: */ -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x00000001U -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8 -/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0; */ -/*description: */ -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x00000001U -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9 -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x00000001U -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10 -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0; */ -/*description: */ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x00000001U -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11 -/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0; */ -/*description: */ -#define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007U -#define MODEM_LPCON_MODEM_PWR_MEM_WP_M (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S) -#define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x00000007U -#define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12 -/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 4; */ -/*description: */ -#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007U -#define MODEM_LPCON_MODEM_PWR_MEM_WA_M (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S) -#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x00000007U -#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15 -/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0; */ -/*description: */ -#define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003U -#define MODEM_LPCON_MODEM_PWR_MEM_RA_M (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S) -#define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x00000003U -#define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18 - -#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x2c) -/* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35676736; */ -/*description: */ -#define MODEM_LPCON_DATE 0x0FFFFFFFU -#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S) -#define MODEM_LPCON_DATE_V 0x0FFFFFFFU -#define MODEM_LPCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/modem/modem_lpcon_struct.h b/components/soc/esp32p4/include/modem/modem_lpcon_struct.h deleted file mode 100644 index f27074fcee..0000000000 --- a/components/soc/esp32p4/include/modem/modem_lpcon_struct.h +++ /dev/null @@ -1,178 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef union { - struct { - uint32_t clk_en:1; - uint32_t clk_debug_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} modem_lpcon_test_conf_reg_t; - -typedef union { - struct { - uint32_t clk_lp_timer_sel_osc_slow:1; - uint32_t clk_lp_timer_sel_osc_fast:1; - uint32_t clk_lp_timer_sel_xtal:1; - uint32_t clk_lp_timer_sel_xtal32k:1; - uint32_t clk_lp_timer_div_num:12; - uint32_t reserved_16:16; - }; - uint32_t val; -} modem_lpcon_lp_timer_conf_reg_t; - -typedef union { - struct { - uint32_t clk_coex_lp_sel_osc_slow:1; - uint32_t clk_coex_lp_sel_osc_fast:1; - uint32_t clk_coex_lp_sel_xtal:1; - uint32_t clk_coex_lp_sel_xtal32k:1; - uint32_t clk_coex_lp_div_num:12; - uint32_t reserved_16:16; - }; - uint32_t val; -} modem_lpcon_coex_lp_clk_conf_reg_t; - -typedef union { - struct { - uint32_t clk_wifipwr_lp_sel_osc_slow:1; - uint32_t clk_wifipwr_lp_sel_osc_fast:1; - uint32_t clk_wifipwr_lp_sel_xtal:1; - uint32_t clk_wifipwr_lp_sel_xtal32k:1; - uint32_t clk_wifipwr_lp_div_num:12; - uint32_t reserved_16:16; - }; - uint32_t val; -} modem_lpcon_wifi_lp_clk_conf_reg_t; - -typedef union { - struct { - uint32_t clk_i2c_mst_sel_160m:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} modem_lpcon_i2c_mst_clk_conf_reg_t; - -typedef union { - struct { - uint32_t clk_modem_32k_sel:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} modem_lpcon_modem_32k_clk_conf_reg_t; - -typedef union { - struct { - uint32_t clk_wifipwr_en:1; - uint32_t clk_coex_en:1; - uint32_t clk_i2c_mst_en:1; - uint32_t clk_lp_timer_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} modem_lpcon_clk_conf_reg_t; - -typedef union { - struct { - uint32_t clk_wifipwr_fo:1; - uint32_t clk_coex_fo:1; - uint32_t clk_i2c_mst_fo:1; - uint32_t clk_lp_timer_fo:1; - uint32_t clk_bcmem_fo:1; - uint32_t clk_i2c_mst_mem_fo:1; - uint32_t clk_chan_freq_mem_fo:1; - uint32_t clk_pbus_mem_fo:1; - uint32_t clk_agc_mem_fo:1; - uint32_t clk_dc_mem_fo:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} modem_lpcon_clk_conf_force_on_reg_t; - -typedef union { - struct { - uint32_t reserved_0:16; - uint32_t clk_wifipwr_st_map:4; - uint32_t clk_coex_st_map:4; - uint32_t clk_i2c_mst_st_map:4; - uint32_t clk_lp_apb_st_map:4; - }; - uint32_t val; -} modem_lpcon_clk_conf_power_st_reg_t; - -typedef union { - struct { - uint32_t rst_wifipwr:1; - uint32_t rst_coex:1; - uint32_t rst_i2c_mst:1; - uint32_t rst_lp_timer:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} modem_lpcon_rst_conf_reg_t; - -typedef union { - struct { - uint32_t dc_mem_force_pu:1; - uint32_t dc_mem_force_pd:1; - uint32_t agc_mem_force_pu:1; - uint32_t agc_mem_force_pd:1; - uint32_t pbus_mem_force_pu:1; - uint32_t pbus_mem_force_pd:1; - uint32_t bc_mem_force_pu:1; - uint32_t bc_mem_force_pd:1; - uint32_t i2c_mst_mem_force_pu:1; - uint32_t i2c_mst_mem_force_pd:1; - uint32_t chan_freq_mem_force_pu:1; - uint32_t chan_freq_mem_force_pd:1; - uint32_t modem_pwr_mem_wp:3; - uint32_t modem_pwr_mem_wa:3; - uint32_t modem_pwr_mem_ra:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} modem_lpcon_mem_conf_reg_t; - -typedef union { - struct { - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} modem_lpcon_date_reg_t; - - -typedef struct { - volatile modem_lpcon_test_conf_reg_t test_conf; - volatile modem_lpcon_lp_timer_conf_reg_t lp_timer_conf; - volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf; - volatile modem_lpcon_wifi_lp_clk_conf_reg_t wifi_lp_clk_conf; - volatile modem_lpcon_i2c_mst_clk_conf_reg_t i2c_mst_clk_conf; - volatile modem_lpcon_modem_32k_clk_conf_reg_t modem_32k_clk_conf; - volatile modem_lpcon_clk_conf_reg_t clk_conf; - volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on; - volatile modem_lpcon_clk_conf_power_st_reg_t clk_conf_power_st; - volatile modem_lpcon_rst_conf_reg_t rst_conf; - volatile modem_lpcon_mem_conf_reg_t mem_conf; - volatile modem_lpcon_date_reg_t date; -} modem_lpcon_dev_t; - -extern modem_lpcon_dev_t MODEM_LPCON; - -#ifndef __cplusplus -_Static_assert(sizeof(modem_lpcon_dev_t) == 0x30, "Invalid size of modem_lpcon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/modem/modem_syscon_reg.h b/components/soc/esp32p4/include/modem/modem_syscon_reg.h deleted file mode 100644 index 2feabbd036..0000000000 --- a/components/soc/esp32p4/include/modem/modem_syscon_reg.h +++ /dev/null @@ -1,612 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - *//*description: */ -#pragma once - -#include -#include "modem/reg_base.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) -/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_EN (BIT(0)) -#define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S) -#define MODEM_SYSCON_CLK_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_EN_S 0 - -#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) -/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 1; */ -/*description: */ -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x00000001U -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 -/* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S) -#define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_ETM_EN_S 22 -/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S) -#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 -/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [24]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(24)) -#define MODEM_SYSCON_CLK_ZB_MAC_EN_M (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S) -#define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_ZB_MAC_EN_S 24 -/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 -/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 -/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 -/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 -/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 -/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 -/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 - -#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) -/* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_ETM_FO (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S) -#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_ETM_FO_S 22 -/* MODEM_SYSCON_CLK_ZB_APB_FO : R/W; bitpos: [23]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_ZB_APB_FO (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_FO_M (MODEM_SYSCON_CLK_ZB_APB_FO_V << MODEM_SYSCON_CLK_ZB_APB_FO_S) -#define MODEM_SYSCON_CLK_ZB_APB_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_ZB_APB_FO_S 23 -/* MODEM_SYSCON_CLK_ZB_MAC_FO : R/W; bitpos: [24]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_ZB_MAC_FO (BIT(24)) -#define MODEM_SYSCON_CLK_ZB_MAC_FO_M (MODEM_SYSCON_CLK_ZB_MAC_FO_V << MODEM_SYSCON_CLK_ZB_MAC_FO_S) -#define MODEM_SYSCON_CLK_ZB_MAC_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_ZB_MAC_FO_S 24 -/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO : R/W; bitpos: [25]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S 25 -/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO : R/W; bitpos: [26]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S 26 -/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO : R/W; bitpos: [27]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S 27 -/* MODEM_SYSCON_CLK_MODEM_SEC_APB_FO : R/W; bitpos: [28]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S 28 -/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 -/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 -/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 - -#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc) -/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000FU -#define MODEM_SYSCON_CLK_ZB_ST_MAP_M (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S) -#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0x0000000FU -#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 -/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000FU -#define MODEM_SYSCON_CLK_FE_ST_MAP_M (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S) -#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0x0000000FU -#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 -/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000FU -#define MODEM_SYSCON_CLK_BT_ST_MAP_M (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S) -#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0x0000000FU -#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 -/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000FU -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S) -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0x0000000FU -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 -/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000FU -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S) -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0x0000000FU -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 -/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000FU -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S) -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0x0000000FU -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 - -#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) -/* MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_WIFIBB (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_M (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S) -#define MODEM_SYSCON_RST_WIFIBB_V 0x00000001U -#define MODEM_SYSCON_RST_WIFIBB_S 8 -/* MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [10]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_WIFIMAC (BIT(10)) -#define MODEM_SYSCON_RST_WIFIMAC_M (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S) -#define MODEM_SYSCON_RST_WIFIMAC_V 0x00000001U -#define MODEM_SYSCON_RST_WIFIMAC_S 10 -/* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_FE (BIT(14)) -#define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S) -#define MODEM_SYSCON_RST_FE_V 0x00000001U -#define MODEM_SYSCON_RST_FE_S 14 -/* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S) -#define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U -#define MODEM_SYSCON_RST_BTMAC_APB_S 15 -/* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_BTMAC (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S) -#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U -#define MODEM_SYSCON_RST_BTMAC_S 16 -/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S) -#define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U -#define MODEM_SYSCON_RST_BTBB_APB_S 17 -/* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_BTBB (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S) -#define MODEM_SYSCON_RST_BTBB_V 0x00000001U -#define MODEM_SYSCON_RST_BTBB_S 18 -/* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_ETM (BIT(22)) -#define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S) -#define MODEM_SYSCON_RST_ETM_V 0x00000001U -#define MODEM_SYSCON_RST_ETM_S 22 -/* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S) -#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U -#define MODEM_SYSCON_RST_ZBMAC_S 24 -/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S) -#define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U -#define MODEM_SYSCON_RST_MODEM_ECB_S 25 -/* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S) -#define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U -#define MODEM_SYSCON_RST_MODEM_CCM_S 26 -/* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S) -#define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U -#define MODEM_SYSCON_RST_MODEM_BAH_S 27 -/* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S) -#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U -#define MODEM_SYSCON_RST_MODEM_SEC_S 29 -/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S) -#define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U -#define MODEM_SYSCON_RST_BLE_TIMER_S 30 -/* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S) -#define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U -#define MODEM_SYSCON_RST_DATA_DUMP_S 31 - -#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) -/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 -/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 -/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 -/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 -/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 -/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 -/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 -/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 -/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 -/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 -/* MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_M (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S) -#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 -/* MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_M (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S) -#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 -/* MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_M (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S) -#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 -/* MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_M (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S) -#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 -/* MODEM_SYSCON_CLK_FE_CAL_160M_EN : R/W; bitpos: [15]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_CAL_160M_EN (BIT(15)) -#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_M (MODEM_SYSCON_CLK_FE_CAL_160M_EN_V << MODEM_SYSCON_CLK_FE_CAL_160M_EN_S) -#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_S 15 -/* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16)) -#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S) -#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_APB_EN_S 16 -/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(17)) -#define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S) -#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_BT_APB_EN_S 17 -/* MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_BT_EN (BIT(18)) -#define MODEM_SYSCON_CLK_BT_EN_M (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S) -#define MODEM_SYSCON_CLK_BT_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_BT_EN_S 18 -/* MODEM_SYSCON_CLK_WIFIBB_480M_EN : R/W; bitpos: [19]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_480M_EN (BIT(19)) -#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_M (MODEM_SYSCON_CLK_WIFIBB_480M_EN_V << MODEM_SYSCON_CLK_WIFIBB_480M_EN_S) -#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_S 19 -/* MODEM_SYSCON_CLK_FE_480M_EN : R/W; bitpos: [20]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_480M_EN (BIT(20)) -#define MODEM_SYSCON_CLK_FE_480M_EN_M (MODEM_SYSCON_CLK_FE_480M_EN_V << MODEM_SYSCON_CLK_FE_480M_EN_S) -#define MODEM_SYSCON_CLK_FE_480M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_480M_EN_S 20 -/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN : R/W; bitpos: [21]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN (BIT(21)) -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S) -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S 21 -/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN : R/W; bitpos: [22]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN (BIT(22)) -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S) -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S 22 -/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN : R/W; bitpos: [23]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN (BIT(23)) -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S) -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S 23 - -#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) -/* MODEM_SYSCON_CLK_WIFIBB_22M_FO : R/W; bitpos: [0]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_22M_FO (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_M (MODEM_SYSCON_CLK_WIFIBB_22M_FO_V << MODEM_SYSCON_CLK_WIFIBB_22M_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_S 0 -/* MODEM_SYSCON_CLK_WIFIBB_40M_FO : R/W; bitpos: [1]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_40M_FO (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_M (MODEM_SYSCON_CLK_WIFIBB_40M_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_44M_FO : R/W; bitpos: [2]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_44M_FO (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_M (MODEM_SYSCON_CLK_WIFIBB_44M_FO_V << MODEM_SYSCON_CLK_WIFIBB_44M_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_S 2 -/* MODEM_SYSCON_CLK_WIFIBB_80M_FO : R/W; bitpos: [3]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_80M_FO (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_M (MODEM_SYSCON_CLK_WIFIBB_80M_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_S 3 -/* MODEM_SYSCON_CLK_WIFIBB_40X_FO : R/W; bitpos: [4]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_40X_FO (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_M (MODEM_SYSCON_CLK_WIFIBB_40X_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_S 4 -/* MODEM_SYSCON_CLK_WIFIBB_80X_FO : R/W; bitpos: [5]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_80X_FO (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_M (MODEM_SYSCON_CLK_WIFIBB_80X_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_S 5 -/* MODEM_SYSCON_CLK_WIFIBB_40X1_FO : R/W; bitpos: [6]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S 6 -/* MODEM_SYSCON_CLK_WIFIBB_80X1_FO : R/W; bitpos: [7]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S 7 -/* MODEM_SYSCON_CLK_WIFIBB_160X1_FO : R/W; bitpos: [8]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S 8 -/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [9]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 9 -/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [10]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 10 -/* MODEM_SYSCON_CLK_FE_20M_FO : R/W; bitpos: [11]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_20M_FO (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_FO_M (MODEM_SYSCON_CLK_FE_20M_FO_V << MODEM_SYSCON_CLK_FE_20M_FO_S) -#define MODEM_SYSCON_CLK_FE_20M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_20M_FO_S 11 -/* MODEM_SYSCON_CLK_FE_40M_FO : R/W; bitpos: [12]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_40M_FO (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_FO_M (MODEM_SYSCON_CLK_FE_40M_FO_V << MODEM_SYSCON_CLK_FE_40M_FO_S) -#define MODEM_SYSCON_CLK_FE_40M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_40M_FO_S 12 -/* MODEM_SYSCON_CLK_FE_80M_FO : R/W; bitpos: [13]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_80M_FO (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_FO_M (MODEM_SYSCON_CLK_FE_80M_FO_V << MODEM_SYSCON_CLK_FE_80M_FO_S) -#define MODEM_SYSCON_CLK_FE_80M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_80M_FO_S 13 -/* MODEM_SYSCON_CLK_FE_160M_FO : R/W; bitpos: [14]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_160M_FO (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_FO_M (MODEM_SYSCON_CLK_FE_160M_FO_V << MODEM_SYSCON_CLK_FE_160M_FO_S) -#define MODEM_SYSCON_CLK_FE_160M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_160M_FO_S 14 -/* MODEM_SYSCON_CLK_FE_CAL_160M_FO : R/W; bitpos: [15]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_CAL_160M_FO (BIT(15)) -#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_M (MODEM_SYSCON_CLK_FE_CAL_160M_FO_V << MODEM_SYSCON_CLK_FE_CAL_160M_FO_S) -#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_S 15 -/* MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [16]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(16)) -#define MODEM_SYSCON_CLK_FE_APB_FO_M (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S) -#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_APB_FO_S 16 -/* MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [17]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(17)) -#define MODEM_SYSCON_CLK_BT_APB_FO_M (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S) -#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_BT_APB_FO_S 17 -/* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_BT_FO (BIT(18)) -#define MODEM_SYSCON_CLK_BT_FO_M (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S) -#define MODEM_SYSCON_CLK_BT_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_BT_FO_S 18 -/* MODEM_SYSCON_CLK_WIFIBB_480M_FO : R/W; bitpos: [19]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_WIFIBB_480M_FO (BIT(19)) -#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_M (MODEM_SYSCON_CLK_WIFIBB_480M_FO_V << MODEM_SYSCON_CLK_WIFIBB_480M_FO_S) -#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_S 19 -/* MODEM_SYSCON_CLK_FE_480M_FO : R/W; bitpos: [20]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_480M_FO (BIT(20)) -#define MODEM_SYSCON_CLK_FE_480M_FO_M (MODEM_SYSCON_CLK_FE_480M_FO_V << MODEM_SYSCON_CLK_FE_480M_FO_S) -#define MODEM_SYSCON_CLK_FE_480M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_480M_FO_S 20 -/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO : R/W; bitpos: [21]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO (BIT(21)) -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S) -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S 21 -/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO : R/W; bitpos: [22]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO (BIT(22)) -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S) -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S 22 -/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO : R/W; bitpos: [23]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO (BIT(23)) -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S) -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V 0x00000001U -#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S 23 - -#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c) -/* MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFFU -#define MODEM_SYSCON_WIFI_BB_CFG_M (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S) -#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFFU -#define MODEM_SYSCON_WIFI_BB_CFG_S 0 - -#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) -/* MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_MODEM_MEM_WP 0x00000007U -#define MODEM_SYSCON_MODEM_MEM_WP_M (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S) -#define MODEM_SYSCON_MODEM_MEM_WP_V 0x00000007U -#define MODEM_SYSCON_MODEM_MEM_WP_S 0 -/* MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 4; */ -/*description: */ -#define MODEM_SYSCON_MODEM_MEM_WA 0x00000007U -#define MODEM_SYSCON_MODEM_MEM_WA_M (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S) -#define MODEM_SYSCON_MODEM_MEM_WA_V 0x00000007U -#define MODEM_SYSCON_MODEM_MEM_WA_S 3 -/* MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0; */ -/*description: */ -#define MODEM_SYSCON_MODEM_MEM_RA 0x00000003U -#define MODEM_SYSCON_MODEM_MEM_RA_M (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S) -#define MODEM_SYSCON_MODEM_MEM_RA_V 0x00000003U -#define MODEM_SYSCON_MODEM_MEM_RA_S 6 - -#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) -/* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 35676928; */ -/*description: */ -#define MODEM_SYSCON_DATE 0x0FFFFFFFU -#define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S) -#define MODEM_SYSCON_DATE_V 0x0FFFFFFFU -#define MODEM_SYSCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/modem/modem_syscon_struct.h b/components/soc/esp32p4/include/modem/modem_syscon_struct.h deleted file mode 100644 index 2635e741b9..0000000000 --- a/components/soc/esp32p4/include/modem/modem_syscon_struct.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef union { - struct { - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} modem_syscon_test_conf_reg_t; - -typedef union { - struct { - uint32_t reserved_0:21; - uint32_t clk_data_dump_mux:1; - uint32_t clk_etm_en:1; - uint32_t clk_zb_apb_en:1; - uint32_t clk_zb_mac_en:1; - uint32_t clk_modem_sec_ecb_en:1; - uint32_t clk_modem_sec_ccm_en:1; - uint32_t clk_modem_sec_bah_en:1; - uint32_t clk_modem_sec_apb_en:1; - uint32_t clk_modem_sec_en:1; - uint32_t clk_ble_timer_en:1; - uint32_t clk_data_dump_en:1; - }; - uint32_t val; -} modem_syscon_clk_conf_reg_t; - -typedef union { - struct { - uint32_t reserved_0:22; - uint32_t clk_etm_fo:1; - uint32_t clk_zb_apb_fo:1; - uint32_t clk_zb_mac_fo:1; - uint32_t clk_modem_sec_ecb_fo:1; - uint32_t clk_modem_sec_ccm_fo:1; - uint32_t clk_modem_sec_bah_fo:1; - uint32_t clk_modem_sec_apb_fo:1; - uint32_t clk_modem_sec_fo:1; - uint32_t clk_ble_timer_fo:1; - uint32_t clk_data_dump_fo:1; - }; - uint32_t val; -} modem_syscon_clk_conf_force_on_reg_t; - -typedef union { - struct { - uint32_t reserved_0:8; - uint32_t clk_zb_st_map:4; - uint32_t clk_fe_st_map:4; - uint32_t clk_bt_st_map:4; - uint32_t clk_wifi_st_map:4; - uint32_t clk_modem_peri_st_map:4; - uint32_t clk_modem_apb_st_map:4; - }; - uint32_t val; -} modem_syscon_clk_conf_power_st_reg_t; - -typedef union { - struct { - uint32_t reserved_0:8; - uint32_t rst_wifibb:1; - uint32_t reserved_9:1; - uint32_t rst_wifimac:1; - uint32_t reserved_11:3; - uint32_t rst_fe:1; - uint32_t rst_btmac_apb:1; - uint32_t rst_btmac:1; - uint32_t rst_btbb_apb:1; - uint32_t rst_btbb:1; - uint32_t reserved_19:3; - uint32_t rst_etm:1; - uint32_t reserved_23:1; - uint32_t rst_zbmac:1; - uint32_t rst_modem_ecb:1; - uint32_t rst_modem_ccm:1; - uint32_t rst_modem_bah:1; - uint32_t reserved_28:1; - uint32_t rst_modem_sec:1; - uint32_t rst_ble_timer:1; - uint32_t rst_data_dump:1; - }; - uint32_t val; -} modem_syscon_modem_rst_conf_reg_t; - -typedef union { - struct { - uint32_t clk_wifibb_22m_en:1; - uint32_t clk_wifibb_40m_en:1; - uint32_t clk_wifibb_44m_en:1; - uint32_t clk_wifibb_80m_en:1; - uint32_t clk_wifibb_40x_en:1; - uint32_t clk_wifibb_80x_en:1; - uint32_t clk_wifibb_40x1_en:1; - uint32_t clk_wifibb_80x1_en:1; - uint32_t clk_wifibb_160x1_en:1; - uint32_t clk_wifimac_en:1; - uint32_t clk_wifi_apb_en:1; - uint32_t clk_fe_20m_en:1; - uint32_t clk_fe_40m_en:1; - uint32_t clk_fe_80m_en:1; - uint32_t clk_fe_160m_en:1; - uint32_t clk_fe_cal_160m_en:1; - uint32_t clk_fe_apb_en:1; - uint32_t clk_bt_apb_en:1; - uint32_t clk_bt_en:1; - uint32_t clk_wifibb_480m_en:1; - uint32_t clk_fe_480m_en:1; - uint32_t clk_fe_anamode_40m_en:1; - uint32_t clk_fe_anamode_80m_en:1; - uint32_t clk_fe_anamode_160m_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} modem_syscon_clk_conf1_reg_t; - -typedef union { - struct { - uint32_t clk_wifibb_22m_fo:1; - uint32_t clk_wifibb_40m_fo:1; - uint32_t clk_wifibb_44m_fo:1; - uint32_t clk_wifibb_80m_fo:1; - uint32_t clk_wifibb_40x_fo:1; - uint32_t clk_wifibb_80x_fo:1; - uint32_t clk_wifibb_40x1_fo:1; - uint32_t clk_wifibb_80x1_fo:1; - uint32_t clk_wifibb_160x1_fo:1; - uint32_t clk_wifimac_fo:1; - uint32_t clk_wifi_apb_fo:1; - uint32_t clk_fe_20m_fo:1; - uint32_t clk_fe_40m_fo:1; - uint32_t clk_fe_80m_fo:1; - uint32_t clk_fe_160m_fo:1; - uint32_t clk_fe_cal_160m_fo:1; - uint32_t clk_fe_apb_fo:1; - uint32_t clk_bt_apb_fo:1; - uint32_t clk_bt_fo:1; - uint32_t clk_wifibb_480m_fo:1; - uint32_t clk_fe_480m_fo:1; - uint32_t clk_fe_anamode_40m_fo:1; - uint32_t clk_fe_anamode_80m_fo:1; - uint32_t clk_fe_anamode_160m_fo:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} modem_syscon_clk_conf1_force_on_reg_t; - -typedef union { - struct { - uint32_t wifi_bb_cfg:32; - }; - uint32_t val; -} modem_syscon_wifi_bb_cfg_reg_t; - -typedef union { - struct { - uint32_t modem_mem_wp:3; - uint32_t modem_mem_wa:3; - uint32_t modem_mem_ra:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} modem_syscon_mem_conf_reg_t; - -typedef union { - struct { - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} modem_syscon_date_reg_t; - - -typedef struct { - volatile modem_syscon_test_conf_reg_t test_conf; - volatile modem_syscon_clk_conf_reg_t clk_conf; - volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on; - volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st; - volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf; - volatile modem_syscon_clk_conf1_reg_t clk_conf1; - volatile modem_syscon_clk_conf1_force_on_reg_t clk_conf1_force_on; - volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg; - volatile modem_syscon_mem_conf_reg_t mem_conf; - volatile modem_syscon_date_reg_t date; -} modem_syscon_dev_t; - -extern modem_syscon_dev_t MODEM_SYSCON; - -#ifndef __cplusplus -_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/modem/reg_base.h b/components/soc/esp32p4/include/modem/reg_base.h deleted file mode 100644 index 7a0254eac0..0000000000 --- a/components/soc/esp32p4/include/modem/reg_base.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once -#define DR_REG_MODEM_SYSCON_BASE 0x600A9800 -#define DR_REG_MODEM_LPCON_BASE 0x600AF000 diff --git a/components/soc/esp32p4/include/soc/adc_channel.h b/components/soc/esp32p4/include/soc/adc_channel.h index dcdfb8633b..d2aa55b41e 100644 --- a/components/soc/esp32p4/include/soc/adc_channel.h +++ b/components/soc/esp32p4/include/soc/adc_channel.h @@ -5,24 +5,3 @@ */ #pragma once - -#define ADC1_GPIO0_CHANNEL 0 -#define ADC1_CHANNEL_0_GPIO_NUM 0 - -#define ADC1_GPIO1_CHANNEL 1 -#define ADC1_CHANNEL_1_GPIO_NUM 1 - -#define ADC1_GPIO2_CHANNEL 2 -#define ADC1_CHANNEL_2_GPIO_NUM 2 - -#define ADC1_GPIO3_CHANNEL 3 -#define ADC1_CHANNEL_3_GPIO_NUM 3 - -#define ADC1_GPIO4_CHANNEL 4 -#define ADC1_CHANNEL_4_GPIO_NUM 4 - -#define ADC1_GPIO5_CHANNEL 5 -#define ADC1_CHANNEL_5_GPIO_NUM 5 - -#define ADC1_GPIO6_CHANNEL 6 -#define ADC1_CHANNEL_6_GPIO_NUM 6 diff --git a/components/soc/esp32p4/include/soc/apb_saradc_reg.h b/components/soc/esp32p4/include/soc/apb_saradc_reg.h deleted file mode 100644 index 933120275b..0000000000 --- a/components/soc/esp32p4/include/soc/apb_saradc_reg.h +++ /dev/null @@ -1,884 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** APB_SARADC_CTRL_REG register - * digital saradc configure register - */ -#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) -/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; - * select software enable saradc sample - */ -#define APB_SARADC_SARADC_START_FORCE (BIT(0)) -#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S) -#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U -#define APB_SARADC_SARADC_START_FORCE_S 0 -/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0; - * software enable saradc sample - */ -#define APB_SARADC_SARADC_START (BIT(1)) -#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S) -#define APB_SARADC_SARADC_START_V 0x00000001U -#define APB_SARADC_SARADC_START_S 1 -/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; - * SAR clock gated - */ -#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6)) -#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S) -#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U -#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6 -/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; - * SAR clock divider - */ -#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU -#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S) -#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU -#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7 -/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; - * 0 ~ 15 means length 1 ~ 16 - */ -#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U -#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S) -#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U -#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15 -/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; - * clear the pointer of pattern table for DIG ADC1 CTRL - */ -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23)) -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S) -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23 -/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; - * force option to xpd sar blocks - */ -#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U -#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S) -#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U -#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27 -/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0; - * enable saradc2 power detect driven func. - */ -#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29)) -#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S) -#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U -#define APB_SARADC_SARADC2_PWDET_DRV_S 29 -/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; - * wait arbit signal stable after sar_done - */ -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S) -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30 - -/** APB_SARADC_CTRL2_REG register - * digital saradc configure register - */ -#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) -/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; - * enable max meas num - */ -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0)) -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S) -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0 -/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; - * max conversion number - */ -#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU -#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S) -#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU -#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1 -/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; - * 1: data to DIG ADC1 CTRL is inverted, otherwise not - */ -#define APB_SARADC_SARADC_SAR1_INV (BIT(9)) -#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S) -#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U -#define APB_SARADC_SARADC_SAR1_INV_S 9 -/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; - * 1: data to DIG ADC2 CTRL is inverted, otherwise not - */ -#define APB_SARADC_SARADC_SAR2_INV (BIT(10)) -#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S) -#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U -#define APB_SARADC_SARADC_SAR2_INV_S 10 -/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; - * to set saradc timer target - */ -#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU -#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S) -#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU -#define APB_SARADC_SARADC_TIMER_TARGET_S 12 -/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; - * to enable saradc timer trigger - */ -#define APB_SARADC_SARADC_TIMER_EN (BIT(24)) -#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S) -#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U -#define APB_SARADC_SARADC_TIMER_EN_S 24 - -/** APB_SARADC_FILTER_CTRL1_REG register - * digital saradc configure register - */ -#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) -/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; - * Factor of saradc filter1 - */ -#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U -#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S) -#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U -#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26 -/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; - * Factor of saradc filter0 - */ -#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U -#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S) -#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U -#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29 - -/** APB_SARADC_FSM_WAIT_REG register - * digital saradc configure register - */ -#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc) -/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; - * saradc_xpd_wait - */ -#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU -#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S) -#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU -#define APB_SARADC_SARADC_XPD_WAIT_S 0 -/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; - * saradc_rstb_wait - */ -#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU -#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S) -#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU -#define APB_SARADC_SARADC_RSTB_WAIT_S 8 -/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; - * saradc_standby_wait - */ -#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU -#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S) -#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU -#define APB_SARADC_SARADC_STANDBY_WAIT_S 16 - -/** APB_SARADC_SAR1_STATUS_REG register - * digital saradc configure register - */ -#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10) -/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912; - * saradc1 status about data and channel - */ -#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S) -#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR1_STATUS_S 0 - -/** APB_SARADC_SAR2_STATUS_REG register - * digital saradc configure register - */ -#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14) -/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912; - * saradc2 status about data and channel - */ -#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S) -#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR2_STATUS_S 0 - -/** APB_SARADC_SAR_PATT_TAB1_REG register - * digital saradc configure register - */ -#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) -/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; - * item 0 ~ 3 for pattern table 1 (each item one byte) - */ -#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S) -#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0 - -/** APB_SARADC_SAR_PATT_TAB2_REG register - * digital saradc configure register - */ -#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c) -/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; - * Item 4 ~ 7 for pattern table 1 (each item one byte) - */ -#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S) -#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0 - -/** APB_SARADC_ONETIME_SAMPLE_REG register - * digital saradc configure register - */ -#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) -/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; - * configure onetime atten - */ -#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U -#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S) -#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U -#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23 -/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; - * configure onetime channel - */ -#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU -#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S) -#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU -#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25 -/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; - * trigger adc onetime sample - */ -#define APB_SARADC_SARADC_ONETIME_START (BIT(29)) -#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S) -#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U -#define APB_SARADC_SARADC_ONETIME_START_S 29 -/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; - * enable adc2 onetime sample - */ -#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) -#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S) -#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U -#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30 -/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; - * enable adc1 onetime sample - */ -#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) -#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S) -#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U -#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31 - -/** APB_SARADC_ARB_CTRL_REG register - * digital saradc configure register - */ -#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) -/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; - * adc2 arbiter force to enableapb controller - */ -#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) -#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S) -#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U -#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 -/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; - * adc2 arbiter force to enable rtc controller - */ -#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) -#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S) -#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U -#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 -/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; - * adc2 arbiter force to enable wifi controller - */ -#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U -#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 -/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; - * adc2 arbiter force grant - */ -#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U -#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 -/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; - * Set adc2 arbiterapb priority - */ -#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U -#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S) -#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U -#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 -/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; - * Set adc2 arbiter rtc priority - */ -#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S) -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 -/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; - * Set adc2 arbiter wifi priority - */ -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S) -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 -/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; - * adc2 arbiter uses fixed priority - */ -#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 - -/** APB_SARADC_FILTER_CTRL0_REG register - * digital saradc configure register - */ -#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) -/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; - * configure filter1 to adc channel - */ -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S) -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18 -/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; - * configure filter0 to adc channel - */ -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S) -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU -#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22 -/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; - * enable apb_adc1_filter - */ -#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31)) -#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S) -#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U -#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31 - -/** APB_SARADC_SAR1DATA_STATUS_REG register - * digital saradc configure register - */ -#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c) -/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; - * saradc1 data - */ -#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU -#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S) -#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU -#define APB_SARADC_APB_SARADC1_DATA_S 0 - -/** APB_SARADC_SAR2DATA_STATUS_REG register - * digital saradc configure register - */ -#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) -/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; - * saradc2 data - */ -#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU -#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S) -#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU -#define APB_SARADC_APB_SARADC2_DATA_S 0 - -/** APB_SARADC_THRES0_CTRL_REG register - * digital saradc configure register - */ -#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) -/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; - * configure thres0 to adc channel - */ -#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU -#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S) -#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU -#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0 -/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; - * saradc thres0 monitor thres - */ -#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5 -/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; - * saradc thres0 monitor thres - */ -#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S) -#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18 - -/** APB_SARADC_THRES1_CTRL_REG register - * digital saradc configure register - */ -#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) -/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; - * configure thres1 to adc channel - */ -#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU -#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S) -#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU -#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0 -/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; - * saradc thres1 monitor thres - */ -#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5 -/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; - * saradc thres1 monitor thres - */ -#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S) -#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU -#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18 - -/** APB_SARADC_THRES_CTRL_REG register - * digital saradc configure register - */ -#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c) -/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; - * enable thres to all channel - */ -#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27)) -#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S) -#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27 -/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; - * enable thres1 - */ -#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30)) -#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S) -#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_EN_S 30 -/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; - * enable thres0 - */ -#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31)) -#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S) -#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_EN_S 31 - -/** APB_SARADC_INT_ENA_REG register - * digital saradc int register - */ -#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) -/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; - * tsens low interrupt enable - */ -#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25)) -#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S) -#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U -#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25 -/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; - * saradc thres1 low interrupt enable - */ -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26 -/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; - * saradc thres0 low interrupt enable - */ -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27 -/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; - * saradc thres1 high interrupt enable - */ -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28 -/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; - * saradc thres0 high interrupt enable - */ -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29 -/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; - * saradc2 done interrupt enable - */ -#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30)) -#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S) -#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U -#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30 -/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; - * saradc1 done interrupt enable - */ -#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31)) -#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S) -#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U -#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31 - -/** APB_SARADC_INT_RAW_REG register - * digital saradc int register - */ -#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) -/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; - * saradc tsens interrupt raw - */ -#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25)) -#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S) -#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U -#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25 -/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; - * saradc thres1 low interrupt raw - */ -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26 -/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; - * saradc thres0 low interrupt raw - */ -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27 -/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * saradc thres1 high interrupt raw - */ -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28 -/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * saradc thres0 high interrupt raw - */ -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29 -/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * saradc2 done interrupt raw - */ -#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30)) -#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S) -#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U -#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30 -/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * saradc1 done interrupt raw - */ -#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31)) -#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S) -#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U -#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31 - -/** APB_SARADC_INT_ST_REG register - * digital saradc int register - */ -#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) -/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; - * saradc tsens interrupt state - */ -#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25)) -#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S) -#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U -#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25 -/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; - * saradc thres1 low interrupt state - */ -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26 -/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; - * saradc thres0 low interrupt state - */ -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27 -/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; - * saradc thres1 high interrupt state - */ -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28 -/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; - * saradc thres0 high interrupt state - */ -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29 -/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; - * saradc2 done interrupt state - */ -#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30)) -#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S) -#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U -#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30 -/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; - * saradc1 done interrupt state - */ -#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31)) -#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S) -#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U -#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31 - -/** APB_SARADC_INT_CLR_REG register - * digital saradc int register - */ -#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c) -/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; - * saradc tsens interrupt clear - */ -#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25)) -#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S) -#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U -#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25 -/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0; - * saradc thres1 low interrupt clear - */ -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S) -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26 -/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0; - * saradc thres0 low interrupt clear - */ -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S) -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27 -/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0; - * saradc thres1 high interrupt clear - */ -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S) -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28 -/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0; - * saradc thres0 high interrupt clear - */ -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S) -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U -#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29 -/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0; - * saradc2 done interrupt clear - */ -#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30)) -#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S) -#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U -#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30 -/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0; - * saradc1 done interrupt clear - */ -#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31)) -#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S) -#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U -#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31 - -/** APB_SARADC_DMA_CONF_REG register - * digital saradc configure register - */ -#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) -/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; - * the dma_in_suc_eof gen when sample cnt = spi_eof_num - */ -#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU -#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S) -#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU -#define APB_SARADC_APB_ADC_EOF_NUM_S 0 -/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; - * reset_apb_adc_state - */ -#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) -#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S) -#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U -#define APB_SARADC_APB_ADC_RESET_FSM_S 30 -/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; - * enable apb_adc use spi_dma - */ -#define APB_SARADC_APB_ADC_TRANS (BIT(31)) -#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S) -#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U -#define APB_SARADC_APB_ADC_TRANS_S 31 - -/** APB_SARADC_CLKM_CONF_REG register - * digital saradc configure register - */ -#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) -/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; - * Integral I2S clock divider value - */ -#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU -#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S) -#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU -#define APB_SARADC_CLKM_DIV_NUM_S 0 -/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; - * Fractional clock divider numerator value - */ -#define APB_SARADC_CLKM_DIV_B 0x0000003FU -#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S) -#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU -#define APB_SARADC_CLKM_DIV_B_S 8 -/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; - * Fractional clock divider denominator value - */ -#define APB_SARADC_CLKM_DIV_A 0x0000003FU -#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S) -#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU -#define APB_SARADC_CLKM_DIV_A_S 14 -/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; - * reg clk en - */ -#define APB_SARADC_CLK_EN (BIT(20)) -#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S) -#define APB_SARADC_CLK_EN_V 0x00000001U -#define APB_SARADC_CLK_EN_S 20 -/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0; - * Set this bit to enable clk_apll - */ -#define APB_SARADC_CLK_SEL 0x00000003U -#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S) -#define APB_SARADC_CLK_SEL_V 0x00000003U -#define APB_SARADC_CLK_SEL_S 21 - -/** APB_SARADC_APB_TSENS_CTRL_REG register - * digital tsens configure register - */ -#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) -/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; - * temperature sensor data out - */ -#define APB_SARADC_TSENS_OUT 0x000000FFU -#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S) -#define APB_SARADC_TSENS_OUT_V 0x000000FFU -#define APB_SARADC_TSENS_OUT_S 0 -/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; - * invert temperature sensor data - */ -#define APB_SARADC_TSENS_IN_INV (BIT(13)) -#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S) -#define APB_SARADC_TSENS_IN_INV_V 0x00000001U -#define APB_SARADC_TSENS_IN_INV_S 13 -/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; - * temperature sensor clock divider - */ -#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU -#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S) -#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU -#define APB_SARADC_TSENS_CLK_DIV_S 14 -/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0; - * temperature sensor power up - */ -#define APB_SARADC_TSENS_PU (BIT(22)) -#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S) -#define APB_SARADC_TSENS_PU_V 0x00000001U -#define APB_SARADC_TSENS_PU_S 22 - -/** APB_SARADC_TSENS_CTRL2_REG register - * digital tsens configure register - */ -#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c) -/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; - * the time that power up tsens need wait - */ -#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFFU -#define APB_SARADC_TSENS_XPD_WAIT_M (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S) -#define APB_SARADC_TSENS_XPD_WAIT_V 0x00000FFFU -#define APB_SARADC_TSENS_XPD_WAIT_S 0 -/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0; - * force power up tsens - */ -#define APB_SARADC_TSENS_XPD_FORCE 0x00000003U -#define APB_SARADC_TSENS_XPD_FORCE_M (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S) -#define APB_SARADC_TSENS_XPD_FORCE_V 0x00000003U -#define APB_SARADC_TSENS_XPD_FORCE_S 12 -/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1; - * inv tsens clk - */ -#define APB_SARADC_TSENS_CLK_INV (BIT(14)) -#define APB_SARADC_TSENS_CLK_INV_M (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S) -#define APB_SARADC_TSENS_CLK_INV_V 0x00000001U -#define APB_SARADC_TSENS_CLK_INV_S 14 -/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; - * tsens clk select - */ -#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) -#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S) -#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U -#define APB_SARADC_TSENS_CLK_SEL_S 15 - -/** APB_SARADC_CALI_REG register - * digital saradc configure register - */ -#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) -/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; - * saradc cali factor - */ -#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU -#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S) -#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU -#define APB_SARADC_APB_SARADC_CALI_CFG_S 0 - -/** APB_TSENS_WAKE_REG register - * digital tsens configure register - */ -#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64) -/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; - * reg_wakeup_th_low - */ -#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU -#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S) -#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU -#define APB_SARADC_WAKEUP_TH_LOW_S 0 -/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255; - * reg_wakeup_th_high - */ -#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU -#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S) -#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU -#define APB_SARADC_WAKEUP_TH_HIGH_S 8 -/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0; - * reg_wakeup_over_upper_th - */ -#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16)) -#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S) -#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U -#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16 -/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0; - * reg_wakeup_mode - */ -#define APB_SARADC_WAKEUP_MODE (BIT(17)) -#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S) -#define APB_SARADC_WAKEUP_MODE_V 0x00000001U -#define APB_SARADC_WAKEUP_MODE_S 17 -/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0; - * reg_wakeup_en - */ -#define APB_SARADC_WAKEUP_EN (BIT(18)) -#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S) -#define APB_SARADC_WAKEUP_EN_V 0x00000001U -#define APB_SARADC_WAKEUP_EN_S 18 - -/** APB_TSENS_SAMPLE_REG register - * digital tsens configure register - */ -#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68) -/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; - * HW sample rate - */ -#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU -#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S) -#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU -#define APB_SARADC_TSENS_SAMPLE_RATE_S 0 -/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0; - * HW sample en - */ -#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16)) -#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S) -#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U -#define APB_SARADC_TSENS_SAMPLE_EN_S 16 - -/** APB_SARADC_CTRL_DATE_REG register - * version - */ -#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) -/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; - * version - */ -#define APB_SARADC_DATE 0xFFFFFFFFU -#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S) -#define APB_SARADC_DATE_V 0xFFFFFFFFU -#define APB_SARADC_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/apb_saradc_struct.h b/components/soc/esp32p4/include/soc/apb_saradc_struct.h deleted file mode 100644 index b76d6cfb5b..0000000000 --- a/components/soc/esp32p4/include/soc/apb_saradc_struct.h +++ /dev/null @@ -1,757 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configure Register */ -/** Type of saradc_ctrl register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0; - * select software enable saradc sample - */ - uint32_t saradc_saradc_start_force:1; - /** saradc_saradc_start : R/W; bitpos: [1]; default: 0; - * software enable saradc sample - */ - uint32_t saradc_saradc_start:1; - uint32_t reserved_2:4; - /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1; - * SAR clock gated - */ - uint32_t saradc_saradc_sar_clk_gated:1; - /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4; - * SAR clock divider - */ - uint32_t saradc_saradc_sar_clk_div:8; - /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7; - * 0 ~ 15 means length 1 ~ 16 - */ - uint32_t saradc_saradc_sar_patt_len:3; - uint32_t reserved_18:5; - /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0; - * clear the pointer of pattern table for DIG ADC1 CTRL - */ - uint32_t saradc_saradc_sar_patt_p_clear:1; - uint32_t reserved_24:3; - /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0; - * force option to xpd sar blocks - */ - uint32_t saradc_saradc_xpd_sar_force:2; - /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0; - * enable saradc2 power detect driven func. - */ - uint32_t saradc_saradc2_pwdet_drv:1; - /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1; - * wait arbit signal stable after sar_done - */ - uint32_t saradc_saradc_wait_arb_cycle:2; - }; - uint32_t val; -} apb_saradc_ctrl_reg_t; - -/** Type of saradc_ctrl2 register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0; - * enable max meas num - */ - uint32_t saradc_saradc_meas_num_limit:1; - /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255; - * max conversion number - */ - uint32_t saradc_saradc_max_meas_num:8; - /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0; - * 1: data to DIG ADC1 CTRL is inverted, otherwise not - */ - uint32_t saradc_saradc_sar1_inv:1; - /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0; - * 1: data to DIG ADC2 CTRL is inverted, otherwise not - */ - uint32_t saradc_saradc_sar2_inv:1; - uint32_t reserved_11:1; - /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10; - * to set saradc timer target - */ - uint32_t saradc_saradc_timer_target:12; - /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0; - * to enable saradc timer trigger - */ - uint32_t saradc_saradc_timer_en:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} apb_saradc_ctrl2_reg_t; - -/** Type of saradc_filter_ctrl1 register - * digital saradc configure register - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0; - * Factor of saradc filter1 - */ - uint32_t saradc_apb_saradc_filter_factor1:3; - /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0; - * Factor of saradc filter0 - */ - uint32_t saradc_apb_saradc_filter_factor0:3; - }; - uint32_t val; -} apb_saradc_filter_ctrl1_reg_t; - -/** Type of saradc_fsm_wait register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8; - * saradc_xpd_wait - */ - uint32_t saradc_saradc_xpd_wait:8; - /** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8; - * saradc_rstb_wait - */ - uint32_t saradc_saradc_rstb_wait:8; - /** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255; - * saradc_standby_wait - */ - uint32_t saradc_saradc_standby_wait:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} apb_saradc_fsm_wait_reg_t; - -/** Type of saradc_sar1_status register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912; - * saradc1 status about data and channel - */ - uint32_t saradc_saradc_sar1_status:32; - }; - uint32_t val; -} apb_saradc_sar1_status_reg_t; - -/** Type of saradc_sar2_status register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912; - * saradc2 status about data and channel - */ - uint32_t saradc_saradc_sar2_status:32; - }; - uint32_t val; -} apb_saradc_sar2_status_reg_t; - -/** Type of saradc_sar_patt_tab1 register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215; - * item 0 ~ 3 for pattern table 1 (each item one byte) - */ - uint32_t saradc_saradc_sar_patt_tab1:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} apb_saradc_sar_patt_tab1_reg_t; - -/** Type of saradc_sar_patt_tab2 register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215; - * Item 4 ~ 7 for pattern table 1 (each item one byte) - */ - uint32_t saradc_saradc_sar_patt_tab2:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} apb_saradc_sar_patt_tab2_reg_t; - -/** Type of saradc_onetime_sample register - * digital saradc configure register - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0; - * configure onetime atten - */ - uint32_t saradc_saradc_onetime_atten:2; - /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13; - * configure onetime channel - */ - uint32_t saradc_saradc_onetime_channel:4; - /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0; - * trigger adc onetime sample - */ - uint32_t saradc_saradc_onetime_start:1; - /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0; - * enable adc2 onetime sample - */ - uint32_t saradc_saradc2_onetime_sample:1; - /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0; - * enable adc1 onetime sample - */ - uint32_t saradc_saradc1_onetime_sample:1; - }; - uint32_t val; -} apb_saradc_onetime_sample_reg_t; - -/** Type of saradc_arb_ctrl register - * digital saradc configure register - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0; - * adc2 arbiter force to enableapb controller - */ - uint32_t saradc_adc_arb_apb_force:1; - /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0; - * adc2 arbiter force to enable rtc controller - */ - uint32_t saradc_adc_arb_rtc_force:1; - /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0; - * adc2 arbiter force to enable wifi controller - */ - uint32_t saradc_adc_arb_wifi_force:1; - /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0; - * adc2 arbiter force grant - */ - uint32_t saradc_adc_arb_grant_force:1; - /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0; - * Set adc2 arbiterapb priority - */ - uint32_t saradc_adc_arb_apb_priority:2; - /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1; - * Set adc2 arbiter rtc priority - */ - uint32_t saradc_adc_arb_rtc_priority:2; - /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2; - * Set adc2 arbiter wifi priority - */ - uint32_t saradc_adc_arb_wifi_priority:2; - /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0; - * adc2 arbiter uses fixed priority - */ - uint32_t saradc_adc_arb_fix_priority:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} apb_saradc_arb_ctrl_reg_t; - -/** Type of saradc_filter_ctrl0 register - * digital saradc configure register - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13; - * configure filter1 to adc channel - */ - uint32_t saradc_apb_saradc_filter_channel1:4; - /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13; - * configure filter0 to adc channel - */ - uint32_t saradc_apb_saradc_filter_channel0:4; - uint32_t reserved_26:5; - /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0; - * enable apb_adc1_filter - */ - uint32_t saradc_apb_saradc_filter_reset:1; - }; - uint32_t val; -} apb_saradc_filter_ctrl0_reg_t; - -/** Type of saradc_sar1data_status register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0; - * saradc1 data - */ - uint32_t saradc_apb_saradc1_data:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} apb_saradc_sar1data_status_reg_t; - -/** Type of saradc_sar2data_status register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0; - * saradc2 data - */ - uint32_t saradc_apb_saradc2_data:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} apb_saradc_sar2data_status_reg_t; - -/** Type of saradc_thres0_ctrl register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13; - * configure thres0 to adc channel - */ - uint32_t saradc_apb_saradc_thres0_channel:4; - uint32_t reserved_4:1; - /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191; - * saradc thres0 monitor thres - */ - uint32_t saradc_apb_saradc_thres0_high:13; - /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0; - * saradc thres0 monitor thres - */ - uint32_t saradc_apb_saradc_thres0_low:13; - uint32_t reserved_31:1; - }; - uint32_t val; -} apb_saradc_thres0_ctrl_reg_t; - -/** Type of saradc_thres1_ctrl register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13; - * configure thres1 to adc channel - */ - uint32_t saradc_apb_saradc_thres1_channel:4; - uint32_t reserved_4:1; - /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191; - * saradc thres1 monitor thres - */ - uint32_t saradc_apb_saradc_thres1_high:13; - /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0; - * saradc thres1 monitor thres - */ - uint32_t saradc_apb_saradc_thres1_low:13; - uint32_t reserved_31:1; - }; - uint32_t val; -} apb_saradc_thres1_ctrl_reg_t; - -/** Type of saradc_thres_ctrl register - * digital saradc configure register - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0; - * enable thres to all channel - */ - uint32_t saradc_apb_saradc_thres_all_en:1; - uint32_t reserved_28:2; - /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0; - * enable thres1 - */ - uint32_t saradc_apb_saradc_thres1_en:1; - /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0; - * enable thres0 - */ - uint32_t saradc_apb_saradc_thres0_en:1; - }; - uint32_t val; -} apb_saradc_thres_ctrl_reg_t; - -/** Type of saradc_int_ena register - * digital saradc int register - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0; - * tsens low interrupt enable - */ - uint32_t saradc_apb_saradc_tsens_int_ena:1; - /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0; - * saradc thres1 low interrupt enable - */ - uint32_t saradc_apb_saradc_thres1_low_int_ena:1; - /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0; - * saradc thres0 low interrupt enable - */ - uint32_t saradc_apb_saradc_thres0_low_int_ena:1; - /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0; - * saradc thres1 high interrupt enable - */ - uint32_t saradc_apb_saradc_thres1_high_int_ena:1; - /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0; - * saradc thres0 high interrupt enable - */ - uint32_t saradc_apb_saradc_thres0_high_int_ena:1; - /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0; - * saradc2 done interrupt enable - */ - uint32_t saradc_apb_saradc2_done_int_ena:1; - /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0; - * saradc1 done interrupt enable - */ - uint32_t saradc_apb_saradc1_done_int_ena:1; - }; - uint32_t val; -} apb_saradc_int_ena_reg_t; - -/** Type of saradc_int_raw register - * digital saradc int register - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * saradc tsens interrupt raw - */ - uint32_t saradc_apb_saradc_tsens_int_raw:1; - /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * saradc thres1 low interrupt raw - */ - uint32_t saradc_apb_saradc_thres1_low_int_raw:1; - /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * saradc thres0 low interrupt raw - */ - uint32_t saradc_apb_saradc_thres0_low_int_raw:1; - /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * saradc thres1 high interrupt raw - */ - uint32_t saradc_apb_saradc_thres1_high_int_raw:1; - /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * saradc thres0 high interrupt raw - */ - uint32_t saradc_apb_saradc_thres0_high_int_raw:1; - /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * saradc2 done interrupt raw - */ - uint32_t saradc_apb_saradc2_done_int_raw:1; - /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * saradc1 done interrupt raw - */ - uint32_t saradc_apb_saradc1_done_int_raw:1; - }; - uint32_t val; -} apb_saradc_int_raw_reg_t; - -/** Type of saradc_int_st register - * digital saradc int register - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0; - * saradc tsens interrupt state - */ - uint32_t saradc_apb_saradc_tsens_int_st:1; - /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0; - * saradc thres1 low interrupt state - */ - uint32_t saradc_apb_saradc_thres1_low_int_st:1; - /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0; - * saradc thres0 low interrupt state - */ - uint32_t saradc_apb_saradc_thres0_low_int_st:1; - /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0; - * saradc thres1 high interrupt state - */ - uint32_t saradc_apb_saradc_thres1_high_int_st:1; - /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0; - * saradc thres0 high interrupt state - */ - uint32_t saradc_apb_saradc_thres0_high_int_st:1; - /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0; - * saradc2 done interrupt state - */ - uint32_t saradc_apb_saradc2_done_int_st:1; - /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0; - * saradc1 done interrupt state - */ - uint32_t saradc_apb_saradc1_done_int_st:1; - }; - uint32_t val; -} apb_saradc_int_st_reg_t; - -/** Type of saradc_int_clr register - * digital saradc int register - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0; - * saradc tsens interrupt clear - */ - uint32_t saradc_apb_saradc_tsens_int_clr:1; - /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0; - * saradc thres1 low interrupt clear - */ - uint32_t saradc_apb_saradc_thres1_low_int_clr:1; - /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0; - * saradc thres0 low interrupt clear - */ - uint32_t saradc_apb_saradc_thres0_low_int_clr:1; - /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0; - * saradc thres1 high interrupt clear - */ - uint32_t saradc_apb_saradc_thres1_high_int_clr:1; - /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0; - * saradc thres0 high interrupt clear - */ - uint32_t saradc_apb_saradc_thres0_high_int_clr:1; - /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0; - * saradc2 done interrupt clear - */ - uint32_t saradc_apb_saradc2_done_int_clr:1; - /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0; - * saradc1 done interrupt clear - */ - uint32_t saradc_apb_saradc1_done_int_clr:1; - }; - uint32_t val; -} apb_saradc_int_clr_reg_t; - -/** Type of saradc_dma_conf register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255; - * the dma_in_suc_eof gen when sample cnt = spi_eof_num - */ - uint32_t saradc_apb_adc_eof_num:16; - uint32_t reserved_16:14; - /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0; - * reset_apb_adc_state - */ - uint32_t saradc_apb_adc_reset_fsm:1; - /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0; - * enable apb_adc use spi_dma - */ - uint32_t saradc_apb_adc_trans:1; - }; - uint32_t val; -} apb_saradc_dma_conf_reg_t; - -/** Type of saradc_clkm_conf register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4; - * Integral I2S clock divider value - */ - uint32_t saradc_clkm_div_num:8; - /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0; - * Fractional clock divider numerator value - */ - uint32_t saradc_clkm_div_b:6; - /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0; - * Fractional clock divider denominator value - */ - uint32_t saradc_clkm_div_a:6; - /** saradc_clk_en : R/W; bitpos: [20]; default: 0; - * reg clk en - */ - uint32_t saradc_clk_en:1; - /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0; - * Set this bit to enable clk_apll - */ - uint32_t saradc_clk_sel:2; - uint32_t reserved_23:9; - }; - uint32_t val; -} apb_saradc_clkm_conf_reg_t; - -/** Type of saradc_apb_tsens_ctrl register - * digital tsens configure register - */ -typedef union { - struct { - /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128; - * temperature sensor data out - */ - uint32_t saradc_tsens_out:8; - uint32_t reserved_8:5; - /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0; - * invert temperature sensor data - */ - uint32_t saradc_tsens_in_inv:1; - /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6; - * temperature sensor clock divider - */ - uint32_t saradc_tsens_clk_div:8; - /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0; - * temperature sensor power up - */ - uint32_t saradc_tsens_pu:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} apb_saradc_apb_tsens_ctrl_reg_t; - -/** Type of saradc_tsens_ctrl2 register - * digital tsens configure register - */ -typedef union { - struct { - /** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2; - * the time that power up tsens need wait - */ - uint32_t saradc_tsens_xpd_wait:12; - /** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0; - * force power up tsens - */ - uint32_t saradc_tsens_xpd_force:2; - /** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1; - * inv tsens clk - */ - uint32_t saradc_tsens_clk_inv:1; - /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0; - * tsens clk select - */ - uint32_t saradc_tsens_clk_sel:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} apb_saradc_tsens_ctrl2_reg_t; - -/** Type of saradc_cali register - * digital saradc configure register - */ -typedef union { - struct { - /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768; - * saradc cali factor - */ - uint32_t saradc_apb_saradc_cali_cfg:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} apb_saradc_cali_reg_t; - -/** Type of tsens_wake register - * digital tsens configure register - */ -typedef union { - struct { - /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0; - * reg_wakeup_th_low - */ - uint32_t saradc_wakeup_th_low:8; - /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255; - * reg_wakeup_th_high - */ - uint32_t saradc_wakeup_th_high:8; - /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0; - * reg_wakeup_over_upper_th - */ - uint32_t saradc_wakeup_over_upper_th:1; - /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0; - * reg_wakeup_mode - */ - uint32_t saradc_wakeup_mode:1; - /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0; - * reg_wakeup_en - */ - uint32_t saradc_wakeup_en:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} apb_tsens_wake_reg_t; - -/** Type of tsens_sample register - * digital tsens configure register - */ -typedef union { - struct { - /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20; - * HW sample rate - */ - uint32_t saradc_tsens_sample_rate:16; - /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0; - * HW sample en - */ - uint32_t saradc_tsens_sample_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} apb_tsens_sample_reg_t; - -/** Type of saradc_ctrl_date register - * version - */ -typedef union { - struct { - /** saradc_date : R/W; bitpos: [31:0]; default: 35676736; - * version - */ - uint32_t saradc_date:32; - }; - uint32_t val; -} apb_saradc_ctrl_date_reg_t; - - -typedef struct apb_dev_t { - volatile apb_saradc_ctrl_reg_t saradc_ctrl; - volatile apb_saradc_ctrl2_reg_t saradc_ctrl2; - volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1; - volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait; - volatile apb_saradc_sar1_status_reg_t saradc_sar1_status; - volatile apb_saradc_sar2_status_reg_t saradc_sar2_status; - volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1; - volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2; - volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample; - volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl; - volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0; - volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status; - volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status; - volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl; - volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl; - volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl; - volatile apb_saradc_int_ena_reg_t saradc_int_ena; - volatile apb_saradc_int_raw_reg_t saradc_int_raw; - volatile apb_saradc_int_st_reg_t saradc_int_st; - volatile apb_saradc_int_clr_reg_t saradc_int_clr; - volatile apb_saradc_dma_conf_reg_t saradc_dma_conf; - volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf; - volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl; - volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2; - volatile apb_saradc_cali_reg_t saradc_cali; - volatile apb_tsens_wake_reg_t tsens_wake; - volatile apb_tsens_sample_reg_t tsens_sample; - uint32_t reserved_06c[228]; - volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date; -} apb_dev_t; - -extern apb_dev_t APB_SARADC; - -#ifndef __cplusplus -_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/clic_reg.h b/components/soc/esp32p4/include/soc/clic_reg.h index 3c170302af..29853d2b5d 100644 --- a/components/soc/esp32p4/include/soc/clic_reg.h +++ b/components/soc/esp32p4/include/soc/clic_reg.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#define _CLIC_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif @@ -106,5 +107,3 @@ extern "C" { #ifdef __cplusplus } #endif - -#endif /*_CLIC_REG_H_ */ diff --git a/components/soc/esp32p4/include/soc/clint_reg.h b/components/soc/esp32p4/include/soc/clint_reg.h deleted file mode 100644 index 5ce015e17f..0000000000 --- a/components/soc/esp32p4/include/soc/clint_reg.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define DR_REG_CLINT_M_BASE(i) ( 0x20001800 + (i) * 0x100 ) -#define DR_REG_CLINT_U_BASE(i) ( 0x20001C00 + (i) * 0x100 ) - -/*CLINT MINT*/ -#define CLINT_MINT_SIP_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x0) -/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define CLINT_CPU_MINT_SIP 0xFFFFFFFF -#define CLINT_CPU_MINT_SIP_M ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S)) -#define CLINT_CPU_MINT_SIP_V 0xFFFFFFFF -#define CLINT_CPU_MINT_SIP_S 0 - -#define CLINT_MINT_TIMECTL_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x4) -/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: .*/ -#define CLINT_MINT_SAMPLING_MODE 0x00000003 -#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S)) -#define CLINT_MINT_SAMPLING_MODE_V 0x3 -#define CLINT_MINT_SAMPLING_MODE_S 4 -/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3)) -#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3)) -#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1 -#define CLINT_MINT_COUNTER_OVERFLOW_S 3 -/* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_MINT_TIMERINT_PENDING (BIT(2)) -#define CLINT_MINT_TIMERINT_PENDING_M (BIT(2)) -#define CLINT_MINT_TIMERINT_PENDING_V 0x1 -#define CLINT_MINT_TIMERINT_PENDING_S 2 -/* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_MINT_TIMERINT_EN (BIT(1)) -#define CLINT_MINT_TIMERINT_EN_M (BIT(1)) -#define CLINT_MINT_TIMERINT_EN_V 0x1 -#define CLINT_MINT_TIMERINT_EN_S 1 -/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_MINT_COUNTER_EN (BIT(0)) -#define CLINT_MINT_COUNTER_EN_M (BIT(0)) -#define CLINT_MINT_COUNTER_EN_V 0x1 -#define CLINT_MINT_COUNTER_EN_S 0 - -#define CLINT_MINT_MTIME_L_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x8) -/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S)) -#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIME_L_S 0 - -#define CLINT_MINT_MTIME_H_REG(i) (DR_REG_CLINT_M_BASE(i) + 0xC) -/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S)) -#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIME_H_S 0 - -#define CLINT_MINT_MTIMECMP_L_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x10) -/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S)) -#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIMECMP_L_S 0 - -#define CLINT_MINT_MTIMECMP_H_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x14) -/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S)) -#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF -#define CLINT_CPU_MINT_MTIMECMP_H_S 0 - -/*CLINT UINT*/ -#define CLINT_UINT_SIP_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x0) -/* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define CLINT_CPU_UINT_SIP 0xFFFFFFFF -#define CLINT_CPU_UINT_SIP_M ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S)) -#define CLINT_CPU_UINT_SIP_V 0xFFFFFFFF -#define CLINT_CPU_UINT_SIP_S 0 - -#define CLINT_UINT_TIMECTL_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x4) -/* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: .*/ -#define CLINT_UINT_SAMPLING_MODE 0x00000003 -#define CLINT_UINT_SAMPLING_MODE_M ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S)) -#define CLINT_UINT_SAMPLING_MODE_V 0x3 -#define CLINT_UINT_SAMPLING_MODE_S 4 -/* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_UINT_COUNTER_OVERFLOW (BIT(3)) -#define CLINT_UINT_COUNTER_OVERFLOW_M (BIT(3)) -#define CLINT_UINT_COUNTER_OVERFLOW_V 0x1 -#define CLINT_UINT_COUNTER_OVERFLOW_S 3 -/* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_UINT_TIMERINT_PENDING (BIT(2)) -#define CLINT_UINT_TIMERINT_PENDING_M (BIT(2)) -#define CLINT_UINT_TIMERINT_PENDING_V 0x1 -#define CLINT_UINT_TIMERINT_PENDING_S 2 -/* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_UINT_TIMERINT_EN (BIT(1)) -#define CLINT_UINT_TIMERINT_EN_M (BIT(1)) -#define CLINT_UINT_TIMERINT_EN_V 0x1 -#define CLINT_UINT_TIMERINT_EN_S 1 -/* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define CLINT_UINT_COUNTER_EN (BIT(0)) -#define CLINT_UINT_COUNTER_EN_M (BIT(0)) -#define CLINT_UINT_COUNTER_EN_V 0x1 -#define CLINT_UINT_COUNTER_EN_S 0 - -#define CLINT_UINT_UTIME_L_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x8) -/* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S)) -#define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIME_L_S 0 - -#define CLINT_UINT_UTIME_H_REG(i) (DR_REG_CLINT_U_BASE(i) + 0xC) -/* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_UINT_UTIME_H 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIME_H_M ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S)) -#define CLINT_CPU_UINT_UTIME_H_V 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIME_H_S 0 - -#define CLINT_UINT_UTIMECMP_L_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x10) -/* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_UINT_UTIMECMP_L 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIMECMP_L_M ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S)) -#define CLINT_CPU_UINT_UTIMECMP_L_V 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIMECMP_L_S 0 - -#define CLINT_UINT_UTIMECMP_H_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x14) -/* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S)) -#define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF -#define CLINT_CPU_UINT_UTIMECMP_H_S 0 -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index 6e421b6437..e6a690eb8b 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -10,7 +10,7 @@ extern "C" { #endif /* - ************************* ESP32C6 Root Clock Source **************************** + ************************* ESP32P4 Root Clock Source **************************** * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) * * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. @@ -126,6 +126,7 @@ typedef enum { //////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// +//TODO: IDF-7486 /** * @brief Type of SYSTIMER clock source */ @@ -137,83 +138,19 @@ typedef enum { //////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of GPTimer - * - * The following code can be used to iterate all possible clocks: - * @code{c} - * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; - * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { - * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; - * // Test GPTimer with the clock `clk` - * } - * @endcode - */ -#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} -/** - * @brief Type of GPTimer clock source - */ -typedef enum { - GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ - GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ -} soc_periph_gptimer_clk_src_t; - -/** - * @brief Type of Timer Group clock source, reserved for the legacy timer group driver - */ -typedef enum { - TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ - TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ - TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ -} soc_periph_tg_clk_src_legacy_t; //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of RMT - */ -#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} -/** - * @brief Type of RMT clock source - */ -typedef enum { - RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ - RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ -} soc_periph_rmt_clk_src_t; - -/** - * @brief Type of RMT clock source, reserved for the legacy RMT driver - */ -typedef enum { - RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */ - RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ - RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */ -} soc_periph_rmt_clk_src_legacy_t; //////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of Temperature Sensor - */ -#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} -/** - * @brief Type of Temp Sensor clock source - */ -typedef enum { - TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ -} soc_periph_temperature_sensor_clk_src_t; ///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// +//TODO: IDF-6511 /** * @brief Type of UART clock source, reserved for the legacy UART driver */ @@ -226,69 +163,19 @@ typedef enum { //////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of MCPWM Timer - */ -#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} -/** - * @brief Type of MCPWM timer clock source - */ -typedef enum { - MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ - MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ -} soc_periph_mcpwm_timer_clk_src_t; -/** - * @brief Array initializer for all supported clock sources of MCPWM Capture Timer - */ -#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} +///////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// -/** - * @brief Type of MCPWM capture clock source - */ -typedef enum { - MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ - MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ -} soc_periph_mcpwm_capture_clk_src_t; -///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of I2S - */ -#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} - -/** - * @brief I2S clock source enum - */ -typedef enum { - I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ - I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ - I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ -} soc_periph_i2s_clk_src_t; /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of I2C - */ -#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} - -/** - * @brief Type of I2C clock source. - */ -typedef enum { - I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ -} soc_periph_i2c_clk_src_t; /////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// +//TODO: IDF-7502 /** * @brief Array initializer for all supported clock sources of SPI */ @@ -306,71 +193,19 @@ typedef enum { //////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of SDM - */ -#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} - -/** - * @brief Sigma Delta Modulator clock source - */ -typedef enum { - SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ - SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ - SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ -} soc_periph_sdm_clk_src_t; //////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of Glitch Filter - */ -#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} - -/** - * @brief Glitch filter clock source - */ - -typedef enum { - GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ - GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ - GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ -} soc_periph_glitch_filter_clk_src_t; //////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of TWAI - */ -#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} - -/** - * @brief TWAI clock source - */ -typedef enum { - TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ -} soc_periph_twai_clk_src_t; //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of ADC digital controller - */ -#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} - -/** - * @brief ADC digital controller clock source - */ -typedef enum { - ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ - ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ -} soc_periph_adc_digi_clk_src_t; //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// +//TODO: IDF-6516 /** * @brief Array initializer for all supported clock sources of MWDT */ @@ -388,38 +223,9 @@ typedef enum { //////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of LEDC - */ -#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} - -/** - * @brief Type of LEDC clock source, reserved for the legacy LEDC driver - */ -typedef enum { - LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ - LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ - LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - - LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ -} soc_periph_ledc_clk_src_legacy_t; //////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of PARLIO - */ -#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M} - -/** - * @brief PARLIO clock source - */ -typedef enum { - PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ - PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ -} soc_periph_parlio_clk_src_t; #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h index 035248b78d..d3ba233faa 100644 --- a/components/soc/esp32p4/include/soc/clkout_channel.h +++ b/components/soc/esp32p4/include/soc/clkout_channel.h @@ -5,4 +5,5 @@ */ #pragma once -// ESP32C6 CLKOUT signals has no corresponding iomux pins +//Copied from C6, please check. TODO: IDF-7526 +// ESP32P4 CLKOUT signals has no corresponding iomux pins diff --git a/components/soc/esp32p4/include/soc/core0_interrupt_reg.h b/components/soc/esp32p4/include/soc/core0_interrupt_reg.h deleted file mode 100644 index a71a12b423..0000000000 --- a/components/soc/esp32p4/include/soc/core0_interrupt_reg.h +++ /dev/null @@ -1,1624 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** CORE0_LP_RTC_INT_MAP_REG register - * NA - */ -#define CORE0_LP_RTC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x0) -/** CORE0_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_RTC_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_RTC_INT_MAP_M (CORE0_CORE0_LP_RTC_INT_MAP_V << CORE0_CORE0_LP_RTC_INT_MAP_S) -#define CORE0_CORE0_LP_RTC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_RTC_INT_MAP_S 0 - -/** CORE0_LP_WDT_INT_MAP_REG register - * NA - */ -#define CORE0_LP_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x4) -/** CORE0_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_WDT_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_WDT_INT_MAP_M (CORE0_CORE0_LP_WDT_INT_MAP_V << CORE0_CORE0_LP_WDT_INT_MAP_S) -#define CORE0_CORE0_LP_WDT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_WDT_INT_MAP_S 0 - -/** CORE0_LP_TIMER_REG_0_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x8) -/** CORE0_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_M (CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S) -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S 0 - -/** CORE0_LP_TIMER_REG_1_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc) -/** CORE0_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_M (CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S) -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S 0 - -/** CORE0_MB_HP_INT_MAP_REG register - * NA - */ -#define CORE0_MB_HP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x10) -/** CORE0_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_MB_HP_INT_MAP 0x0000003FU -#define CORE0_CORE0_MB_HP_INT_MAP_M (CORE0_CORE0_MB_HP_INT_MAP_V << CORE0_CORE0_MB_HP_INT_MAP_S) -#define CORE0_CORE0_MB_HP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_MB_HP_INT_MAP_S 0 - -/** CORE0_MB_LP_INT_MAP_REG register - * NA - */ -#define CORE0_MB_LP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x14) -/** CORE0_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_MB_LP_INT_MAP 0x0000003FU -#define CORE0_CORE0_MB_LP_INT_MAP_M (CORE0_CORE0_MB_LP_INT_MAP_V << CORE0_CORE0_MB_LP_INT_MAP_S) -#define CORE0_CORE0_MB_LP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_MB_LP_INT_MAP_S 0 - -/** CORE0_PMU_REG_0_INT_MAP_REG register - * NA - */ -#define CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x18) -/** CORE0_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PMU_REG_0_INT_MAP 0x0000003FU -#define CORE0_CORE0_PMU_REG_0_INT_MAP_M (CORE0_CORE0_PMU_REG_0_INT_MAP_V << CORE0_CORE0_PMU_REG_0_INT_MAP_S) -#define CORE0_CORE0_PMU_REG_0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PMU_REG_0_INT_MAP_S 0 - -/** CORE0_PMU_REG_1_INT_MAP_REG register - * NA - */ -#define CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c) -/** CORE0_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PMU_REG_1_INT_MAP 0x0000003FU -#define CORE0_CORE0_PMU_REG_1_INT_MAP_M (CORE0_CORE0_PMU_REG_1_INT_MAP_V << CORE0_CORE0_PMU_REG_1_INT_MAP_S) -#define CORE0_CORE0_PMU_REG_1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PMU_REG_1_INT_MAP_S 0 - -/** CORE0_LP_ANAPERI_INT_MAP_REG register - * NA - */ -#define CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x20) -/** CORE0_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_ANAPERI_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_ANAPERI_INT_MAP_M (CORE0_CORE0_LP_ANAPERI_INT_MAP_V << CORE0_CORE0_LP_ANAPERI_INT_MAP_S) -#define CORE0_CORE0_LP_ANAPERI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_ANAPERI_INT_MAP_S 0 - -/** CORE0_LP_ADC_INT_MAP_REG register - * NA - */ -#define CORE0_LP_ADC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x24) -/** CORE0_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_ADC_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_ADC_INT_MAP_M (CORE0_CORE0_LP_ADC_INT_MAP_V << CORE0_CORE0_LP_ADC_INT_MAP_S) -#define CORE0_CORE0_LP_ADC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_ADC_INT_MAP_S 0 - -/** CORE0_LP_GPIO_INT_MAP_REG register - * NA - */ -#define CORE0_LP_GPIO_INT_MAP_REG (DR_REG_CORE0_BASE + 0x28) -/** CORE0_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_GPIO_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_GPIO_INT_MAP_M (CORE0_CORE0_LP_GPIO_INT_MAP_V << CORE0_CORE0_LP_GPIO_INT_MAP_S) -#define CORE0_CORE0_LP_GPIO_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_GPIO_INT_MAP_S 0 - -/** CORE0_LP_I2C_INT_MAP_REG register - * NA - */ -#define CORE0_LP_I2C_INT_MAP_REG (DR_REG_CORE0_BASE + 0x2c) -/** CORE0_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_I2C_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_I2C_INT_MAP_M (CORE0_CORE0_LP_I2C_INT_MAP_V << CORE0_CORE0_LP_I2C_INT_MAP_S) -#define CORE0_CORE0_LP_I2C_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_I2C_INT_MAP_S 0 - -/** CORE0_LP_I2S_INT_MAP_REG register - * NA - */ -#define CORE0_LP_I2S_INT_MAP_REG (DR_REG_CORE0_BASE + 0x30) -/** CORE0_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_I2S_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_I2S_INT_MAP_M (CORE0_CORE0_LP_I2S_INT_MAP_V << CORE0_CORE0_LP_I2S_INT_MAP_S) -#define CORE0_CORE0_LP_I2S_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_I2S_INT_MAP_S 0 - -/** CORE0_LP_SPI_INT_MAP_REG register - * NA - */ -#define CORE0_LP_SPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x34) -/** CORE0_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_SPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_SPI_INT_MAP_M (CORE0_CORE0_LP_SPI_INT_MAP_V << CORE0_CORE0_LP_SPI_INT_MAP_S) -#define CORE0_CORE0_LP_SPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_SPI_INT_MAP_S 0 - -/** CORE0_LP_TOUCH_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_CORE0_BASE + 0x38) -/** CORE0_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TOUCH_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TOUCH_INT_MAP_M (CORE0_CORE0_LP_TOUCH_INT_MAP_V << CORE0_CORE0_LP_TOUCH_INT_MAP_S) -#define CORE0_CORE0_LP_TOUCH_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TOUCH_INT_MAP_S 0 - -/** CORE0_LP_TSENS_INT_MAP_REG register - * NA - */ -#define CORE0_LP_TSENS_INT_MAP_REG (DR_REG_CORE0_BASE + 0x3c) -/** CORE0_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_TSENS_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_TSENS_INT_MAP_M (CORE0_CORE0_LP_TSENS_INT_MAP_V << CORE0_CORE0_LP_TSENS_INT_MAP_S) -#define CORE0_CORE0_LP_TSENS_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_TSENS_INT_MAP_S 0 - -/** CORE0_LP_UART_INT_MAP_REG register - * NA - */ -#define CORE0_LP_UART_INT_MAP_REG (DR_REG_CORE0_BASE + 0x40) -/** CORE0_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_UART_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_UART_INT_MAP_M (CORE0_CORE0_LP_UART_INT_MAP_V << CORE0_CORE0_LP_UART_INT_MAP_S) -#define CORE0_CORE0_LP_UART_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_UART_INT_MAP_S 0 - -/** CORE0_LP_EFUSE_INT_MAP_REG register - * NA - */ -#define CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x44) -/** CORE0_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_EFUSE_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_EFUSE_INT_MAP_M (CORE0_CORE0_LP_EFUSE_INT_MAP_V << CORE0_CORE0_LP_EFUSE_INT_MAP_S) -#define CORE0_CORE0_LP_EFUSE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_EFUSE_INT_MAP_S 0 - -/** CORE0_LP_SW_INT_MAP_REG register - * NA - */ -#define CORE0_LP_SW_INT_MAP_REG (DR_REG_CORE0_BASE + 0x48) -/** CORE0_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_SW_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_SW_INT_MAP_M (CORE0_CORE0_LP_SW_INT_MAP_V << CORE0_CORE0_LP_SW_INT_MAP_S) -#define CORE0_CORE0_LP_SW_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_SW_INT_MAP_S 0 - -/** CORE0_LP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x4c) -/** CORE0_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_SYSREG_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_SYSREG_INT_MAP_M (CORE0_CORE0_LP_SYSREG_INT_MAP_V << CORE0_CORE0_LP_SYSREG_INT_MAP_S) -#define CORE0_CORE0_LP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_SYSREG_INT_MAP_S 0 - -/** CORE0_LP_HUK_INT_MAP_REG register - * NA - */ -#define CORE0_LP_HUK_INT_MAP_REG (DR_REG_CORE0_BASE + 0x50) -/** CORE0_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LP_HUK_INT_MAP 0x0000003FU -#define CORE0_CORE0_LP_HUK_INT_MAP_M (CORE0_CORE0_LP_HUK_INT_MAP_V << CORE0_CORE0_LP_HUK_INT_MAP_S) -#define CORE0_CORE0_LP_HUK_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LP_HUK_INT_MAP_S 0 - -/** CORE0_SYS_ICM_INT_MAP_REG register - * NA - */ -#define CORE0_SYS_ICM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x54) -/** CORE0_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYS_ICM_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYS_ICM_INT_MAP_M (CORE0_CORE0_SYS_ICM_INT_MAP_V << CORE0_CORE0_SYS_ICM_INT_MAP_S) -#define CORE0_CORE0_SYS_ICM_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYS_ICM_INT_MAP_S 0 - -/** CORE0_USB_DEVICE_INT_MAP_REG register - * NA - */ -#define CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x58) -/** CORE0_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_DEVICE_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_DEVICE_INT_MAP_M (CORE0_CORE0_USB_DEVICE_INT_MAP_V << CORE0_CORE0_USB_DEVICE_INT_MAP_S) -#define CORE0_CORE0_USB_DEVICE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_DEVICE_INT_MAP_S 0 - -/** CORE0_SDIO_HOST_INT_MAP_REG register - * NA - */ -#define CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_CORE0_BASE + 0x5c) -/** CORE0_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SDIO_HOST_INT_MAP 0x0000003FU -#define CORE0_CORE0_SDIO_HOST_INT_MAP_M (CORE0_CORE0_SDIO_HOST_INT_MAP_V << CORE0_CORE0_SDIO_HOST_INT_MAP_S) -#define CORE0_CORE0_SDIO_HOST_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SDIO_HOST_INT_MAP_S 0 - -/** CORE0_GDMA_INT_MAP_REG register - * NA - */ -#define CORE0_GDMA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x60) -/** CORE0_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GDMA_INT_MAP 0x0000003FU -#define CORE0_CORE0_GDMA_INT_MAP_M (CORE0_CORE0_GDMA_INT_MAP_V << CORE0_CORE0_GDMA_INT_MAP_S) -#define CORE0_CORE0_GDMA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_GDMA_INT_MAP_S 0 - -/** CORE0_SPI2_INT_MAP_REG register - * NA - */ -#define CORE0_SPI2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x64) -/** CORE0_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SPI2_INT_MAP 0x0000003FU -#define CORE0_CORE0_SPI2_INT_MAP_M (CORE0_CORE0_SPI2_INT_MAP_V << CORE0_CORE0_SPI2_INT_MAP_S) -#define CORE0_CORE0_SPI2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SPI2_INT_MAP_S 0 - -/** CORE0_SPI3_INT_MAP_REG register - * NA - */ -#define CORE0_SPI3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x68) -/** CORE0_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SPI3_INT_MAP 0x0000003FU -#define CORE0_CORE0_SPI3_INT_MAP_M (CORE0_CORE0_SPI3_INT_MAP_V << CORE0_CORE0_SPI3_INT_MAP_S) -#define CORE0_CORE0_SPI3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SPI3_INT_MAP_S 0 - -/** CORE0_I2S0_INT_MAP_REG register - * NA - */ -#define CORE0_I2S0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x6c) -/** CORE0_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2S0_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2S0_INT_MAP_M (CORE0_CORE0_I2S0_INT_MAP_V << CORE0_CORE0_I2S0_INT_MAP_S) -#define CORE0_CORE0_I2S0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2S0_INT_MAP_S 0 - -/** CORE0_I2S1_INT_MAP_REG register - * NA - */ -#define CORE0_I2S1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x70) -/** CORE0_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2S1_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2S1_INT_MAP_M (CORE0_CORE0_I2S1_INT_MAP_V << CORE0_CORE0_I2S1_INT_MAP_S) -#define CORE0_CORE0_I2S1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2S1_INT_MAP_S 0 - -/** CORE0_I2S2_INT_MAP_REG register - * NA - */ -#define CORE0_I2S2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x74) -/** CORE0_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2S2_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2S2_INT_MAP_M (CORE0_CORE0_I2S2_INT_MAP_V << CORE0_CORE0_I2S2_INT_MAP_S) -#define CORE0_CORE0_I2S2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2S2_INT_MAP_S 0 - -/** CORE0_UHCI0_INT_MAP_REG register - * NA - */ -#define CORE0_UHCI0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x78) -/** CORE0_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UHCI0_INT_MAP 0x0000003FU -#define CORE0_CORE0_UHCI0_INT_MAP_M (CORE0_CORE0_UHCI0_INT_MAP_V << CORE0_CORE0_UHCI0_INT_MAP_S) -#define CORE0_CORE0_UHCI0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UHCI0_INT_MAP_S 0 - -/** CORE0_UART0_INT_MAP_REG register - * NA - */ -#define CORE0_UART0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x7c) -/** CORE0_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART0_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART0_INT_MAP_M (CORE0_CORE0_UART0_INT_MAP_V << CORE0_CORE0_UART0_INT_MAP_S) -#define CORE0_CORE0_UART0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART0_INT_MAP_S 0 - -/** CORE0_UART1_INT_MAP_REG register - * NA - */ -#define CORE0_UART1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x80) -/** CORE0_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART1_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART1_INT_MAP_M (CORE0_CORE0_UART1_INT_MAP_V << CORE0_CORE0_UART1_INT_MAP_S) -#define CORE0_CORE0_UART1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART1_INT_MAP_S 0 - -/** CORE0_UART2_INT_MAP_REG register - * NA - */ -#define CORE0_UART2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x84) -/** CORE0_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART2_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART2_INT_MAP_M (CORE0_CORE0_UART2_INT_MAP_V << CORE0_CORE0_UART2_INT_MAP_S) -#define CORE0_CORE0_UART2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART2_INT_MAP_S 0 - -/** CORE0_UART3_INT_MAP_REG register - * NA - */ -#define CORE0_UART3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x88) -/** CORE0_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART3_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART3_INT_MAP_M (CORE0_CORE0_UART3_INT_MAP_V << CORE0_CORE0_UART3_INT_MAP_S) -#define CORE0_CORE0_UART3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART3_INT_MAP_S 0 - -/** CORE0_UART4_INT_MAP_REG register - * NA - */ -#define CORE0_UART4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x8c) -/** CORE0_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_UART4_INT_MAP 0x0000003FU -#define CORE0_CORE0_UART4_INT_MAP_M (CORE0_CORE0_UART4_INT_MAP_V << CORE0_CORE0_UART4_INT_MAP_S) -#define CORE0_CORE0_UART4_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_UART4_INT_MAP_S 0 - -/** CORE0_LCD_CAM_INT_MAP_REG register - * NA - */ -#define CORE0_LCD_CAM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x90) -/** CORE0_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LCD_CAM_INT_MAP 0x0000003FU -#define CORE0_CORE0_LCD_CAM_INT_MAP_M (CORE0_CORE0_LCD_CAM_INT_MAP_V << CORE0_CORE0_LCD_CAM_INT_MAP_S) -#define CORE0_CORE0_LCD_CAM_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LCD_CAM_INT_MAP_S 0 - -/** CORE0_ADC_INT_MAP_REG register - * NA - */ -#define CORE0_ADC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x94) -/** CORE0_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ADC_INT_MAP 0x0000003FU -#define CORE0_CORE0_ADC_INT_MAP_M (CORE0_CORE0_ADC_INT_MAP_V << CORE0_CORE0_ADC_INT_MAP_S) -#define CORE0_CORE0_ADC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ADC_INT_MAP_S 0 - -/** CORE0_PWM0_INT_MAP_REG register - * NA - */ -#define CORE0_PWM0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x98) -/** CORE0_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PWM0_INT_MAP 0x0000003FU -#define CORE0_CORE0_PWM0_INT_MAP_M (CORE0_CORE0_PWM0_INT_MAP_V << CORE0_CORE0_PWM0_INT_MAP_S) -#define CORE0_CORE0_PWM0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PWM0_INT_MAP_S 0 - -/** CORE0_PWM1_INT_MAP_REG register - * NA - */ -#define CORE0_PWM1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x9c) -/** CORE0_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PWM1_INT_MAP 0x0000003FU -#define CORE0_CORE0_PWM1_INT_MAP_M (CORE0_CORE0_PWM1_INT_MAP_V << CORE0_CORE0_PWM1_INT_MAP_S) -#define CORE0_CORE0_PWM1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PWM1_INT_MAP_S 0 - -/** CORE0_CAN0_INT_MAP_REG register - * NA - */ -#define CORE0_CAN0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa0) -/** CORE0_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CAN0_INT_MAP 0x0000003FU -#define CORE0_CORE0_CAN0_INT_MAP_M (CORE0_CORE0_CAN0_INT_MAP_V << CORE0_CORE0_CAN0_INT_MAP_S) -#define CORE0_CORE0_CAN0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CAN0_INT_MAP_S 0 - -/** CORE0_CAN1_INT_MAP_REG register - * NA - */ -#define CORE0_CAN1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa4) -/** CORE0_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CAN1_INT_MAP 0x0000003FU -#define CORE0_CORE0_CAN1_INT_MAP_M (CORE0_CORE0_CAN1_INT_MAP_V << CORE0_CORE0_CAN1_INT_MAP_S) -#define CORE0_CORE0_CAN1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CAN1_INT_MAP_S 0 - -/** CORE0_CAN2_INT_MAP_REG register - * NA - */ -#define CORE0_CAN2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xa8) -/** CORE0_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CAN2_INT_MAP 0x0000003FU -#define CORE0_CORE0_CAN2_INT_MAP_M (CORE0_CORE0_CAN2_INT_MAP_V << CORE0_CORE0_CAN2_INT_MAP_S) -#define CORE0_CORE0_CAN2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CAN2_INT_MAP_S 0 - -/** CORE0_RMT_INT_MAP_REG register - * NA - */ -#define CORE0_RMT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xac) -/** CORE0_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_RMT_INT_MAP 0x0000003FU -#define CORE0_CORE0_RMT_INT_MAP_M (CORE0_CORE0_RMT_INT_MAP_V << CORE0_CORE0_RMT_INT_MAP_S) -#define CORE0_CORE0_RMT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_RMT_INT_MAP_S 0 - -/** CORE0_I2C0_INT_MAP_REG register - * NA - */ -#define CORE0_I2C0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb0) -/** CORE0_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2C0_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2C0_INT_MAP_M (CORE0_CORE0_I2C0_INT_MAP_V << CORE0_CORE0_I2C0_INT_MAP_S) -#define CORE0_CORE0_I2C0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2C0_INT_MAP_S 0 - -/** CORE0_I2C1_INT_MAP_REG register - * NA - */ -#define CORE0_I2C1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb4) -/** CORE0_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I2C1_INT_MAP 0x0000003FU -#define CORE0_CORE0_I2C1_INT_MAP_M (CORE0_CORE0_I2C1_INT_MAP_V << CORE0_CORE0_I2C1_INT_MAP_S) -#define CORE0_CORE0_I2C1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I2C1_INT_MAP_S 0 - -/** CORE0_TIMERGRP0_T0_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xb8) -/** CORE0_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_M (CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S 0 - -/** CORE0_TIMERGRP0_T1_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xbc) -/** CORE0_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_M (CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S 0 - -/** CORE0_TIMERGRP0_WDT_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc0) -/** CORE0_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_M (CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S 0 - -/** CORE0_TIMERGRP1_T0_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc4) -/** CORE0_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_M (CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S 0 - -/** CORE0_TIMERGRP1_T1_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xc8) -/** CORE0_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_M (CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S 0 - -/** CORE0_TIMERGRP1_WDT_INT_MAP_REG register - * NA - */ -#define CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_CORE0_BASE + 0xcc) -/** CORE0_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_M (CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S) -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S 0 - -/** CORE0_LEDC_INT_MAP_REG register - * NA - */ -#define CORE0_LEDC_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd0) -/** CORE0_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LEDC_INT_MAP 0x0000003FU -#define CORE0_CORE0_LEDC_INT_MAP_M (CORE0_CORE0_LEDC_INT_MAP_V << CORE0_CORE0_LEDC_INT_MAP_S) -#define CORE0_CORE0_LEDC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LEDC_INT_MAP_S 0 - -/** CORE0_SYSTIMER_TARGET0_INT_MAP_REG register - * NA - */ -#define CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd4) -/** CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_M (CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S) -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 - -/** CORE0_SYSTIMER_TARGET1_INT_MAP_REG register - * NA - */ -#define CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xd8) -/** CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_M (CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S) -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 - -/** CORE0_SYSTIMER_TARGET2_INT_MAP_REG register - * NA - */ -#define CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xdc) -/** CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_M (CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S) -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe0) -/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe4) -/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xe8) -/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xec) -/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf0) -/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf4) -/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0xf8) -/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0xfc) -/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x100) -/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x104) -/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x108) -/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x10c) -/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE0_RSA_INT_MAP_REG register - * NA - */ -#define CORE0_RSA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x110) -/** CORE0_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_RSA_INT_MAP 0x0000003FU -#define CORE0_CORE0_RSA_INT_MAP_M (CORE0_CORE0_RSA_INT_MAP_V << CORE0_CORE0_RSA_INT_MAP_S) -#define CORE0_CORE0_RSA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_RSA_INT_MAP_S 0 - -/** CORE0_AES_INT_MAP_REG register - * NA - */ -#define CORE0_AES_INT_MAP_REG (DR_REG_CORE0_BASE + 0x114) -/** CORE0_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_AES_INT_MAP 0x0000003FU -#define CORE0_CORE0_AES_INT_MAP_M (CORE0_CORE0_AES_INT_MAP_V << CORE0_CORE0_AES_INT_MAP_S) -#define CORE0_CORE0_AES_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_AES_INT_MAP_S 0 - -/** CORE0_SHA_INT_MAP_REG register - * NA - */ -#define CORE0_SHA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x118) -/** CORE0_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SHA_INT_MAP 0x0000003FU -#define CORE0_CORE0_SHA_INT_MAP_M (CORE0_CORE0_SHA_INT_MAP_V << CORE0_CORE0_SHA_INT_MAP_S) -#define CORE0_CORE0_SHA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SHA_INT_MAP_S 0 - -/** CORE0_ECC_INT_MAP_REG register - * NA - */ -#define CORE0_ECC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x11c) -/** CORE0_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ECC_INT_MAP 0x0000003FU -#define CORE0_CORE0_ECC_INT_MAP_M (CORE0_CORE0_ECC_INT_MAP_V << CORE0_CORE0_ECC_INT_MAP_S) -#define CORE0_CORE0_ECC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ECC_INT_MAP_S 0 - -/** CORE0_ECDSA_INT_MAP_REG register - * NA - */ -#define CORE0_ECDSA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x120) -/** CORE0_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ECDSA_INT_MAP 0x0000003FU -#define CORE0_CORE0_ECDSA_INT_MAP_M (CORE0_CORE0_ECDSA_INT_MAP_V << CORE0_CORE0_ECDSA_INT_MAP_S) -#define CORE0_CORE0_ECDSA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ECDSA_INT_MAP_S 0 - -/** CORE0_KM_INT_MAP_REG register - * NA - */ -#define CORE0_KM_INT_MAP_REG (DR_REG_CORE0_BASE + 0x124) -/** CORE0_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_KM_INT_MAP 0x0000003FU -#define CORE0_CORE0_KM_INT_MAP_M (CORE0_CORE0_KM_INT_MAP_V << CORE0_CORE0_KM_INT_MAP_S) -#define CORE0_CORE0_KM_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_KM_INT_MAP_S 0 - -/** CORE0_GPIO_INT0_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT0_MAP_REG (DR_REG_CORE0_BASE + 0x128) -/** CORE0_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT0_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT0_MAP_M (CORE0_CORE0_GPIO_INT0_MAP_V << CORE0_CORE0_GPIO_INT0_MAP_S) -#define CORE0_CORE0_GPIO_INT0_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT0_MAP_S 0 - -/** CORE0_GPIO_INT1_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT1_MAP_REG (DR_REG_CORE0_BASE + 0x12c) -/** CORE0_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT1_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT1_MAP_M (CORE0_CORE0_GPIO_INT1_MAP_V << CORE0_CORE0_GPIO_INT1_MAP_S) -#define CORE0_CORE0_GPIO_INT1_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT1_MAP_S 0 - -/** CORE0_GPIO_INT2_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT2_MAP_REG (DR_REG_CORE0_BASE + 0x130) -/** CORE0_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT2_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT2_MAP_M (CORE0_CORE0_GPIO_INT2_MAP_V << CORE0_CORE0_GPIO_INT2_MAP_S) -#define CORE0_CORE0_GPIO_INT2_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT2_MAP_S 0 - -/** CORE0_GPIO_INT3_MAP_REG register - * NA - */ -#define CORE0_GPIO_INT3_MAP_REG (DR_REG_CORE0_BASE + 0x134) -/** CORE0_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_INT3_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_INT3_MAP_M (CORE0_CORE0_GPIO_INT3_MAP_V << CORE0_CORE0_GPIO_INT3_MAP_S) -#define CORE0_CORE0_GPIO_INT3_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_INT3_MAP_S 0 - -/** CORE0_GPIO_PAD_COMP_INT_MAP_REG register - * NA - */ -#define CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x138) -/** CORE0_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP 0x0000003FU -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_M (CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S) -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_0_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_CORE0_BASE + 0x13c) -/** CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_1_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_CORE0_BASE + 0x140) -/** CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_2_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_CORE0_BASE + 0x144) -/** CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S 0 - -/** CORE0_CPU_INT_FROM_CPU_3_MAP_REG register - * NA - */ -#define CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_CORE0_BASE + 0x148) -/** CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_M (CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S) -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU -#define CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S 0 - -/** CORE0_CACHE_INT_MAP_REG register - * NA - */ -#define CORE0_CACHE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x14c) -/** CORE0_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CACHE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CACHE_INT_MAP_M (CORE0_CORE0_CACHE_INT_MAP_V << CORE0_CORE0_CACHE_INT_MAP_S) -#define CORE0_CORE0_CACHE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CACHE_INT_MAP_S 0 - -/** CORE0_FLASH_MSPI_INT_MAP_REG register - * NA - */ -#define CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x150) -/** CORE0_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_FLASH_MSPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_FLASH_MSPI_INT_MAP_M (CORE0_CORE0_FLASH_MSPI_INT_MAP_V << CORE0_CORE0_FLASH_MSPI_INT_MAP_S) -#define CORE0_CORE0_FLASH_MSPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_FLASH_MSPI_INT_MAP_S 0 - -/** CORE0_CSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x154) -/** CORE0_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_M (CORE0_CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CORE0_CSI_BRIDGE_INT_MAP_S) -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CSI_BRIDGE_INT_MAP_S 0 - -/** CORE0_DSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x158) -/** CORE0_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_M (CORE0_CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_CORE0_DSI_BRIDGE_INT_MAP_S) -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DSI_BRIDGE_INT_MAP_S 0 - -/** CORE0_CSI_INT_MAP_REG register - * NA - */ -#define CORE0_CSI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x15c) -/** CORE0_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CSI_INT_MAP 0x0000003FU -#define CORE0_CORE0_CSI_INT_MAP_M (CORE0_CORE0_CSI_INT_MAP_V << CORE0_CORE0_CSI_INT_MAP_S) -#define CORE0_CORE0_CSI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CSI_INT_MAP_S 0 - -/** CORE0_DSI_INT_MAP_REG register - * NA - */ -#define CORE0_DSI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x160) -/** CORE0_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DSI_INT_MAP 0x0000003FU -#define CORE0_CORE0_DSI_INT_MAP_M (CORE0_CORE0_DSI_INT_MAP_V << CORE0_CORE0_DSI_INT_MAP_S) -#define CORE0_CORE0_DSI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DSI_INT_MAP_S 0 - -/** CORE0_GMII_PHY_INT_MAP_REG register - * NA - */ -#define CORE0_GMII_PHY_INT_MAP_REG (DR_REG_CORE0_BASE + 0x164) -/** CORE0_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_GMII_PHY_INT_MAP 0x0000003FU -#define CORE0_CORE0_GMII_PHY_INT_MAP_M (CORE0_CORE0_GMII_PHY_INT_MAP_V << CORE0_CORE0_GMII_PHY_INT_MAP_S) -#define CORE0_CORE0_GMII_PHY_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_GMII_PHY_INT_MAP_S 0 - -/** CORE0_LPI_INT_MAP_REG register - * NA - */ -#define CORE0_LPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x168) -/** CORE0_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_LPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_LPI_INT_MAP_M (CORE0_CORE0_LPI_INT_MAP_V << CORE0_CORE0_LPI_INT_MAP_S) -#define CORE0_CORE0_LPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_LPI_INT_MAP_S 0 - -/** CORE0_PMT_INT_MAP_REG register - * NA - */ -#define CORE0_PMT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x16c) -/** CORE0_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PMT_INT_MAP 0x0000003FU -#define CORE0_CORE0_PMT_INT_MAP_M (CORE0_CORE0_PMT_INT_MAP_V << CORE0_CORE0_PMT_INT_MAP_S) -#define CORE0_CORE0_PMT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PMT_INT_MAP_S 0 - -/** CORE0_SBD_INT_MAP_REG register - * NA - */ -#define CORE0_SBD_INT_MAP_REG (DR_REG_CORE0_BASE + 0x170) -/** CORE0_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_SBD_INT_MAP 0x0000003FU -#define CORE0_CORE0_SBD_INT_MAP_M (CORE0_CORE0_SBD_INT_MAP_V << CORE0_CORE0_SBD_INT_MAP_S) -#define CORE0_CORE0_SBD_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_SBD_INT_MAP_S 0 - -/** CORE0_USB_OTG_INT_MAP_REG register - * NA - */ -#define CORE0_USB_OTG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x174) -/** CORE0_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_OTG_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_OTG_INT_MAP_M (CORE0_CORE0_USB_OTG_INT_MAP_V << CORE0_CORE0_USB_OTG_INT_MAP_S) -#define CORE0_CORE0_USB_OTG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_OTG_INT_MAP_S 0 - -/** CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register - * NA - */ -#define CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_CORE0_BASE + 0x178) -/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 - -/** CORE0_JPEG_INT_MAP_REG register - * NA - */ -#define CORE0_JPEG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x17c) -/** CORE0_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_JPEG_INT_MAP 0x0000003FU -#define CORE0_CORE0_JPEG_INT_MAP_M (CORE0_CORE0_JPEG_INT_MAP_V << CORE0_CORE0_JPEG_INT_MAP_S) -#define CORE0_CORE0_JPEG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_JPEG_INT_MAP_S 0 - -/** CORE0_PPA_INT_MAP_REG register - * NA - */ -#define CORE0_PPA_INT_MAP_REG (DR_REG_CORE0_BASE + 0x180) -/** CORE0_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PPA_INT_MAP 0x0000003FU -#define CORE0_CORE0_PPA_INT_MAP_M (CORE0_CORE0_PPA_INT_MAP_V << CORE0_CORE0_PPA_INT_MAP_S) -#define CORE0_CORE0_PPA_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PPA_INT_MAP_S 0 - -/** CORE0_CORE0_TRACE_INT_MAP_REG register - * NA - */ -#define CORE0_CORE0_TRACE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x184) -/** CORE0_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CORE0_TRACE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CORE0_TRACE_INT_MAP_M (CORE0_CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_CORE0_TRACE_INT_MAP_S) -#define CORE0_CORE0_CORE0_TRACE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CORE0_TRACE_INT_MAP_S 0 - -/** CORE0_CORE1_TRACE_INT_MAP_REG register - * NA - */ -#define CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_CORE0_BASE + 0x188) -/** CORE0_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_CORE1_TRACE_INT_MAP 0x0000003FU -#define CORE0_CORE0_CORE1_TRACE_INT_MAP_M (CORE0_CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE0_CORE1_TRACE_INT_MAP_S) -#define CORE0_CORE0_CORE1_TRACE_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_CORE1_TRACE_INT_MAP_S 0 - -/** CORE0_HP_CORE_CTRL_INT_MAP_REG register - * NA - */ -#define CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_CORE0_BASE + 0x18c) -/** CORE0_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_M (CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S) -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S 0 - -/** CORE0_ISP_INT_MAP_REG register - * NA - */ -#define CORE0_ISP_INT_MAP_REG (DR_REG_CORE0_BASE + 0x190) -/** CORE0_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ISP_INT_MAP 0x0000003FU -#define CORE0_CORE0_ISP_INT_MAP_M (CORE0_CORE0_ISP_INT_MAP_V << CORE0_CORE0_ISP_INT_MAP_S) -#define CORE0_CORE0_ISP_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ISP_INT_MAP_S 0 - -/** CORE0_I3C_MST_INT_MAP_REG register - * NA - */ -#define CORE0_I3C_MST_INT_MAP_REG (DR_REG_CORE0_BASE + 0x194) -/** CORE0_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I3C_MST_INT_MAP 0x0000003FU -#define CORE0_CORE0_I3C_MST_INT_MAP_M (CORE0_CORE0_I3C_MST_INT_MAP_V << CORE0_CORE0_I3C_MST_INT_MAP_S) -#define CORE0_CORE0_I3C_MST_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I3C_MST_INT_MAP_S 0 - -/** CORE0_I3C_SLV_INT_MAP_REG register - * NA - */ -#define CORE0_I3C_SLV_INT_MAP_REG (DR_REG_CORE0_BASE + 0x198) -/** CORE0_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_I3C_SLV_INT_MAP 0x0000003FU -#define CORE0_CORE0_I3C_SLV_INT_MAP_M (CORE0_CORE0_I3C_SLV_INT_MAP_V << CORE0_CORE0_I3C_SLV_INT_MAP_S) -#define CORE0_CORE0_I3C_SLV_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_I3C_SLV_INT_MAP_S 0 - -/** CORE0_USB_OTG11_INT_MAP_REG register - * NA - */ -#define CORE0_USB_OTG11_INT_MAP_REG (DR_REG_CORE0_BASE + 0x19c) -/** CORE0_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_USB_OTG11_INT_MAP 0x0000003FU -#define CORE0_CORE0_USB_OTG11_INT_MAP_M (CORE0_CORE0_USB_OTG11_INT_MAP_V << CORE0_CORE0_USB_OTG11_INT_MAP_S) -#define CORE0_CORE0_USB_OTG11_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_USB_OTG11_INT_MAP_S 0 - -/** CORE0_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a0) -/** CORE0_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_M (CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE0_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a4) -/** CORE0_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_M (CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE0_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1a8) -/** CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_M (CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE0_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1ac) -/** CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_M (CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE0_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b0) -/** CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_M (CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE0_PSRAM_MSPI_INT_MAP_REG register - * NA - */ -#define CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b4) -/** CORE0_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP 0x0000003FU -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_M (CORE0_CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_CORE0_PSRAM_MSPI_INT_MAP_S) -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PSRAM_MSPI_INT_MAP_S 0 - -/** CORE0_HP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1b8) -/** CORE0_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_SYSREG_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_SYSREG_INT_MAP_M (CORE0_CORE0_HP_SYSREG_INT_MAP_V << CORE0_CORE0_HP_SYSREG_INT_MAP_S) -#define CORE0_CORE0_HP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_SYSREG_INT_MAP_S 0 - -/** CORE0_PCNT_INT_MAP_REG register - * NA - */ -#define CORE0_PCNT_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1bc) -/** CORE0_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_PCNT_INT_MAP 0x0000003FU -#define CORE0_CORE0_PCNT_INT_MAP_M (CORE0_CORE0_PCNT_INT_MAP_V << CORE0_CORE0_PCNT_INT_MAP_S) -#define CORE0_CORE0_PCNT_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_PCNT_INT_MAP_S 0 - -/** CORE0_HP_PAU_INT_MAP_REG register - * NA - */ -#define CORE0_HP_PAU_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c0) -/** CORE0_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_PAU_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_PAU_INT_MAP_M (CORE0_CORE0_HP_PAU_INT_MAP_V << CORE0_CORE0_HP_PAU_INT_MAP_S) -#define CORE0_CORE0_HP_PAU_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_PAU_INT_MAP_S 0 - -/** CORE0_HP_PARLIO_RX_INT_MAP_REG register - * NA - */ -#define CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c4) -/** CORE0_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_M (CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S) -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S 0 - -/** CORE0_HP_PARLIO_TX_INT_MAP_REG register - * NA - */ -#define CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1c8) -/** CORE0_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_M (CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S) -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1cc) -/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d0) -/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d4) -/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1d8) -/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1dc) -/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e0) -/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e4) -/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1e8) -/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1ec) -/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f0) -/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S 0 - -/** CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register - * NA - */ -#define CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f4) -/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S) -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S 0 - -/** CORE0_H264_REG_INT_MAP_REG register - * NA - */ -#define CORE0_H264_REG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1f8) -/** CORE0_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_H264_REG_INT_MAP 0x0000003FU -#define CORE0_CORE0_H264_REG_INT_MAP_M (CORE0_CORE0_H264_REG_INT_MAP_V << CORE0_CORE0_H264_REG_INT_MAP_S) -#define CORE0_CORE0_H264_REG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_H264_REG_INT_MAP_S 0 - -/** CORE0_ASSIST_DEBUG_INT_MAP_REG register - * NA - */ -#define CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_CORE0_BASE + 0x1fc) -/** CORE0_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP 0x0000003FU -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_M (CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S) -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V 0x0000003FU -#define CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S 0 - -/** CORE0_INTR_STATUS_REG_0_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_0_REG (DR_REG_CORE0_BASE + 0x200) -/** CORE0_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_0 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_0_M (CORE0_CORE0_INTR_STATUS_0_V << CORE0_CORE0_INTR_STATUS_0_S) -#define CORE0_CORE0_INTR_STATUS_0_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_0_S 0 - -/** CORE0_INTR_STATUS_REG_1_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_1_REG (DR_REG_CORE0_BASE + 0x204) -/** CORE0_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_1 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_1_M (CORE0_CORE0_INTR_STATUS_1_V << CORE0_CORE0_INTR_STATUS_1_S) -#define CORE0_CORE0_INTR_STATUS_1_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_1_S 0 - -/** CORE0_INTR_STATUS_REG_2_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_2_REG (DR_REG_CORE0_BASE + 0x208) -/** CORE0_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_2 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_2_M (CORE0_CORE0_INTR_STATUS_2_V << CORE0_CORE0_INTR_STATUS_2_S) -#define CORE0_CORE0_INTR_STATUS_2_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_2_S 0 - -/** CORE0_INTR_STATUS_REG_3_REG register - * NA - */ -#define CORE0_INTR_STATUS_REG_3_REG (DR_REG_CORE0_BASE + 0x20c) -/** CORE0_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE0_CORE0_INTR_STATUS_3 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_3_M (CORE0_CORE0_INTR_STATUS_3_V << CORE0_CORE0_INTR_STATUS_3_S) -#define CORE0_CORE0_INTR_STATUS_3_V 0xFFFFFFFFU -#define CORE0_CORE0_INTR_STATUS_3_S 0 - -/** CORE0_CLOCK_GATE_REG register - * NA - */ -#define CORE0_CLOCK_GATE_REG (DR_REG_CORE0_BASE + 0x210) -/** CORE0_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define CORE0_CORE0_REG_CLK_EN (BIT(0)) -#define CORE0_CORE0_REG_CLK_EN_M (CORE0_CORE0_REG_CLK_EN_V << CORE0_CORE0_REG_CLK_EN_S) -#define CORE0_CORE0_REG_CLK_EN_V 0x00000001U -#define CORE0_CORE0_REG_CLK_EN_S 0 - -/** CORE0_INTERRUPT_REG_DATE_REG register - * NA - */ -#define CORE0_INTERRUPT_REG_DATE_REG (DR_REG_CORE0_BASE + 0x3fc) -/** CORE0_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ -#define CORE0_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU -#define CORE0_CORE0_INTERRUPT_REG_DATE_M (CORE0_CORE0_INTERRUPT_REG_DATE_V << CORE0_CORE0_INTERRUPT_REG_DATE_S) -#define CORE0_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU -#define CORE0_CORE0_INTERRUPT_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/core0_interrupt_struct.h b/components/soc/esp32p4/include/soc/core0_interrupt_struct.h deleted file mode 100644 index 0fc7cf301c..0000000000 --- a/components/soc/esp32p4/include/soc/core0_interrupt_struct.h +++ /dev/null @@ -1,2298 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: CORE0 LP RTC INT MAP REG */ -/** Type of lp_rtc_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_rtc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_rtc_int_map_reg_t; - - -/** Group: CORE0 LP WDT INT MAP REG */ -/** Type of lp_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_wdt_int_map_reg_t; - - -/** Group: CORE0 LP TIMER REG 0 INT MAP REG */ -/** Type of lp_timer_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_timer_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_timer_reg_0_int_map_reg_t; - - -/** Group: CORE0 LP TIMER REG 1 INT MAP REG */ -/** Type of lp_timer_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_timer_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_timer_reg_1_int_map_reg_t; - - -/** Group: CORE0 MB HP INT MAP REG */ -/** Type of mb_hp_int_map register - * NA - */ -typedef union { - struct { - /** core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_mb_hp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_mb_hp_int_map_reg_t; - - -/** Group: CORE0 MB LP INT MAP REG */ -/** Type of mb_lp_int_map register - * NA - */ -typedef union { - struct { - /** core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_mb_lp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_mb_lp_int_map_reg_t; - - -/** Group: CORE0 PMU REG 0 INT MAP REG */ -/** Type of pmu_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pmu_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pmu_reg_0_int_map_reg_t; - - -/** Group: CORE0 PMU REG 1 INT MAP REG */ -/** Type of pmu_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pmu_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pmu_reg_1_int_map_reg_t; - - -/** Group: CORE0 LP ANAPERI INT MAP REG */ -/** Type of lp_anaperi_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_anaperi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_anaperi_int_map_reg_t; - - -/** Group: CORE0 LP ADC INT MAP REG */ -/** Type of lp_adc_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_adc_int_map_reg_t; - - -/** Group: CORE0 LP GPIO INT MAP REG */ -/** Type of lp_gpio_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_gpio_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_gpio_int_map_reg_t; - - -/** Group: CORE0 LP I2C INT MAP REG */ -/** Type of lp_i2c_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_i2c_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_i2c_int_map_reg_t; - - -/** Group: CORE0 LP I2S INT MAP REG */ -/** Type of lp_i2s_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_i2s_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_i2s_int_map_reg_t; - - -/** Group: CORE0 LP SPI INT MAP REG */ -/** Type of lp_spi_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_spi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_spi_int_map_reg_t; - - -/** Group: CORE0 LP TOUCH INT MAP REG */ -/** Type of lp_touch_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_touch_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_touch_int_map_reg_t; - - -/** Group: CORE0 LP TSENS INT MAP REG */ -/** Type of lp_tsens_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_tsens_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_tsens_int_map_reg_t; - - -/** Group: CORE0 LP UART INT MAP REG */ -/** Type of lp_uart_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_uart_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_uart_int_map_reg_t; - - -/** Group: CORE0 LP EFUSE INT MAP REG */ -/** Type of lp_efuse_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_efuse_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_efuse_int_map_reg_t; - - -/** Group: CORE0 LP SW INT MAP REG */ -/** Type of lp_sw_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_sw_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_sw_int_map_reg_t; - - -/** Group: CORE0 LP SYSREG INT MAP REG */ -/** Type of lp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_sysreg_int_map_reg_t; - - -/** Group: CORE0 LP HUK INT MAP REG */ -/** Type of lp_huk_int_map register - * NA - */ -typedef union { - struct { - /** core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lp_huk_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lp_huk_int_map_reg_t; - - -/** Group: CORE0 SYS ICM INT MAP REG */ -/** Type of sys_icm_int_map register - * NA - */ -typedef union { - struct { - /** core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sys_icm_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sys_icm_int_map_reg_t; - - -/** Group: CORE0 USB DEVICE INT MAP REG */ -/** Type of usb_device_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_device_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_device_int_map_reg_t; - - -/** Group: CORE0 SDIO HOST INT MAP REG */ -/** Type of sdio_host_int_map register - * NA - */ -typedef union { - struct { - /** core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sdio_host_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sdio_host_int_map_reg_t; - - -/** Group: CORE0 GDMA INT MAP REG */ -/** Type of gdma_int_map register - * NA - */ -typedef union { - struct { - /** core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gdma_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gdma_int_map_reg_t; - - -/** Group: CORE0 SPI2 INT MAP REG */ -/** Type of spi2_int_map register - * NA - */ -typedef union { - struct { - /** core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_spi2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_spi2_int_map_reg_t; - - -/** Group: CORE0 SPI3 INT MAP REG */ -/** Type of spi3_int_map register - * NA - */ -typedef union { - struct { - /** core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_spi3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_spi3_int_map_reg_t; - - -/** Group: CORE0 I2S0 INT MAP REG */ -/** Type of i2s0_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2s0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2s0_int_map_reg_t; - - -/** Group: CORE0 I2S1 INT MAP REG */ -/** Type of i2s1_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2s1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2s1_int_map_reg_t; - - -/** Group: CORE0 I2S2 INT MAP REG */ -/** Type of i2s2_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2s2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2s2_int_map_reg_t; - - -/** Group: CORE0 UHCI0 INT MAP REG */ -/** Type of uhci0_int_map register - * NA - */ -typedef union { - struct { - /** core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uhci0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uhci0_int_map_reg_t; - - -/** Group: CORE0 UART0 INT MAP REG */ -/** Type of uart0_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart0_int_map_reg_t; - - -/** Group: CORE0 UART1 INT MAP REG */ -/** Type of uart1_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart1_int_map_reg_t; - - -/** Group: CORE0 UART2 INT MAP REG */ -/** Type of uart2_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart2_int_map_reg_t; - - -/** Group: CORE0 UART3 INT MAP REG */ -/** Type of uart3_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart3_int_map_reg_t; - - -/** Group: CORE0 UART4 INT MAP REG */ -/** Type of uart4_int_map register - * NA - */ -typedef union { - struct { - /** core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_uart4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_uart4_int_map_reg_t; - - -/** Group: CORE0 LCD CAM INT MAP REG */ -/** Type of lcd_cam_int_map register - * NA - */ -typedef union { - struct { - /** core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lcd_cam_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lcd_cam_int_map_reg_t; - - -/** Group: CORE0 ADC INT MAP REG */ -/** Type of adc_int_map register - * NA - */ -typedef union { - struct { - /** core0_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_adc_int_map_reg_t; - - -/** Group: CORE0 PWM0 INT MAP REG */ -/** Type of pwm0_int_map register - * NA - */ -typedef union { - struct { - /** core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pwm0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pwm0_int_map_reg_t; - - -/** Group: CORE0 PWM1 INT MAP REG */ -/** Type of pwm1_int_map register - * NA - */ -typedef union { - struct { - /** core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pwm1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pwm1_int_map_reg_t; - - -/** Group: CORE0 CAN0 INT MAP REG */ -/** Type of can0_int_map register - * NA - */ -typedef union { - struct { - /** core0_can0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_can0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_can0_int_map_reg_t; - - -/** Group: CORE0 CAN1 INT MAP REG */ -/** Type of can1_int_map register - * NA - */ -typedef union { - struct { - /** core0_can1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_can1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_can1_int_map_reg_t; - - -/** Group: CORE0 CAN2 INT MAP REG */ -/** Type of can2_int_map register - * NA - */ -typedef union { - struct { - /** core0_can2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_can2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_can2_int_map_reg_t; - - -/** Group: CORE0 RMT INT MAP REG */ -/** Type of rmt_int_map register - * NA - */ -typedef union { - struct { - /** core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_rmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_rmt_int_map_reg_t; - - -/** Group: CORE0 I2C0 INT MAP REG */ -/** Type of i2c0_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2c0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2c0_int_map_reg_t; - - -/** Group: CORE0 I2C1 INT MAP REG */ -/** Type of i2c1_int_map register - * NA - */ -typedef union { - struct { - /** core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i2c1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i2c1_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP0 T0 INT MAP REG */ -/** Type of timergrp0_t0_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp0_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp0_t0_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP0 T1 INT MAP REG */ -/** Type of timergrp0_t1_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp0_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp0_t1_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP0 WDT INT MAP REG */ -/** Type of timergrp0_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp0_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp0_wdt_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP1 T0 INT MAP REG */ -/** Type of timergrp1_t0_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp1_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp1_t0_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP1 T1 INT MAP REG */ -/** Type of timergrp1_t1_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp1_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp1_t1_int_map_reg_t; - - -/** Group: CORE0 TIMERGRP1 WDT INT MAP REG */ -/** Type of timergrp1_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_timergrp1_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_timergrp1_wdt_int_map_reg_t; - - -/** Group: CORE0 LEDC INT MAP REG */ -/** Type of ledc_int_map register - * NA - */ -typedef union { - struct { - /** core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ledc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ledc_int_map_reg_t; - - -/** Group: CORE0 SYSTIMER TARGET0 INT MAP REG */ -/** Type of systimer_target0_int_map register - * NA - */ -typedef union { - struct { - /** core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_systimer_target0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_systimer_target0_int_map_reg_t; - - -/** Group: CORE0 SYSTIMER TARGET1 INT MAP REG */ -/** Type of systimer_target1_int_map register - * NA - */ -typedef union { - struct { - /** core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_systimer_target1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_systimer_target1_int_map_reg_t; - - -/** Group: CORE0 SYSTIMER TARGET2 INT MAP REG */ -/** Type of systimer_target2_int_map register - * NA - */ -typedef union { - struct { - /** core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_systimer_target2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_systimer_target2_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA IN CH0 INT MAP REG */ -/** Type of ahb_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA IN CH1 INT MAP REG */ -/** Type of ahb_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA IN CH2 INT MAP REG */ -/** Type of ahb_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA OUT CH0 INT MAP REG */ -/** Type of ahb_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA OUT CH1 INT MAP REG */ -/** Type of ahb_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE0 AHB PDMA OUT CH2 INT MAP REG */ -/** Type of ahb_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ahb_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ahb_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA IN CH0 INT MAP REG */ -/** Type of axi_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA IN CH1 INT MAP REG */ -/** Type of axi_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA IN CH2 INT MAP REG */ -/** Type of axi_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA OUT CH0 INT MAP REG */ -/** Type of axi_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA OUT CH1 INT MAP REG */ -/** Type of axi_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE0 AXI PDMA OUT CH2 INT MAP REG */ -/** Type of axi_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_axi_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_axi_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE0 RSA INT MAP REG */ -/** Type of rsa_int_map register - * NA - */ -typedef union { - struct { - /** core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_rsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_rsa_int_map_reg_t; - - -/** Group: CORE0 AES INT MAP REG */ -/** Type of aes_int_map register - * NA - */ -typedef union { - struct { - /** core0_aes_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_aes_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_aes_int_map_reg_t; - - -/** Group: CORE0 SHA INT MAP REG */ -/** Type of sha_int_map register - * NA - */ -typedef union { - struct { - /** core0_sha_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sha_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sha_int_map_reg_t; - - -/** Group: CORE0 ECC INT MAP REG */ -/** Type of ecc_int_map register - * NA - */ -typedef union { - struct { - /** core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ecc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ecc_int_map_reg_t; - - -/** Group: CORE0 ECDSA INT MAP REG */ -/** Type of ecdsa_int_map register - * NA - */ -typedef union { - struct { - /** core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ecdsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ecdsa_int_map_reg_t; - - -/** Group: CORE0 KM INT MAP REG */ -/** Type of km_int_map register - * NA - */ -typedef union { - struct { - /** core0_km_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_km_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_km_int_map_reg_t; - - -/** Group: CORE0 GPIO INT0 MAP REG */ -/** Type of gpio_int0_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int0_map_reg_t; - - -/** Group: CORE0 GPIO INT1 MAP REG */ -/** Type of gpio_int1_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int1_map_reg_t; - - -/** Group: CORE0 GPIO INT2 MAP REG */ -/** Type of gpio_int2_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int2_map_reg_t; - - -/** Group: CORE0 GPIO INT3 MAP REG */ -/** Type of gpio_int3_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_int3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_int3_map_reg_t; - - -/** Group: CORE0 GPIO PAD COMP INT MAP REG */ -/** Type of gpio_pad_comp_int_map register - * NA - */ -typedef union { - struct { - /** core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gpio_pad_comp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gpio_pad_comp_int_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 0 MAP REG */ -/** Type of cpu_int_from_cpu_0_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_0_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 1 MAP REG */ -/** Type of cpu_int_from_cpu_1_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_1_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 2 MAP REG */ -/** Type of cpu_int_from_cpu_2_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_2_map_reg_t; - - -/** Group: CORE0 CPU INT FROM CPU 3 MAP REG */ -/** Type of cpu_int_from_cpu_3_map register - * NA - */ -typedef union { - struct { - /** core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cpu_int_from_cpu_3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cpu_int_from_cpu_3_map_reg_t; - - -/** Group: CORE0 CACHE INT MAP REG */ -/** Type of cache_int_map register - * NA - */ -typedef union { - struct { - /** core0_cache_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_cache_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_cache_int_map_reg_t; - - -/** Group: CORE0 FLASH MSPI INT MAP REG */ -/** Type of flash_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_flash_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_flash_mspi_int_map_reg_t; - - -/** Group: CORE0 CSI BRIDGE INT MAP REG */ -/** Type of csi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_csi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_csi_bridge_int_map_reg_t; - - -/** Group: CORE0 DSI BRIDGE INT MAP REG */ -/** Type of dsi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dsi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dsi_bridge_int_map_reg_t; - - -/** Group: CORE0 CSI INT MAP REG */ -/** Type of csi_int_map register - * NA - */ -typedef union { - struct { - /** core0_csi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_csi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_csi_int_map_reg_t; - - -/** Group: CORE0 DSI INT MAP REG */ -/** Type of dsi_int_map register - * NA - */ -typedef union { - struct { - /** core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dsi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dsi_int_map_reg_t; - - -/** Group: CORE0 GMII PHY INT MAP REG */ -/** Type of gmii_phy_int_map register - * NA - */ -typedef union { - struct { - /** core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_gmii_phy_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_gmii_phy_int_map_reg_t; - - -/** Group: CORE0 LPI INT MAP REG */ -/** Type of lpi_int_map register - * NA - */ -typedef union { - struct { - /** core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_lpi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_lpi_int_map_reg_t; - - -/** Group: CORE0 PMT INT MAP REG */ -/** Type of pmt_int_map register - * NA - */ -typedef union { - struct { - /** core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pmt_int_map_reg_t; - - -/** Group: CORE0 SBD INT MAP REG */ -/** Type of sbd_int_map register - * NA - */ -typedef union { - struct { - /** core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_sbd_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_sbd_int_map_reg_t; - - -/** Group: CORE0 USB OTG INT MAP REG */ -/** Type of usb_otg_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_otg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_otg_int_map_reg_t; - - -/** Group: CORE0 USB OTG ENDP MULTI PROC INT MAP REG */ -/** Type of usb_otg_endp_multi_proc_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_otg_endp_multi_proc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_otg_endp_multi_proc_int_map_reg_t; - - -/** Group: CORE0 JPEG INT MAP REG */ -/** Type of jpeg_int_map register - * NA - */ -typedef union { - struct { - /** core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_jpeg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_jpeg_int_map_reg_t; - - -/** Group: CORE0 PPA INT MAP REG */ -/** Type of ppa_int_map register - * NA - */ -typedef union { - struct { - /** core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_ppa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_ppa_int_map_reg_t; - - -/** Group: CORE0 CORE0 TRACE INT MAP REG */ -/** Type of core0_trace_int_map register - * NA - */ -typedef union { - struct { - /** core0_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_core0_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_core0_trace_int_map_reg_t; - - -/** Group: CORE0 CORE1 TRACE INT MAP REG */ -/** Type of core1_trace_int_map register - * NA - */ -typedef union { - struct { - /** core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_core1_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_core1_trace_int_map_reg_t; - - -/** Group: CORE0 HP CORE CTRL INT MAP REG */ -/** Type of hp_core_ctrl_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_core_ctrl_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_core_ctrl_int_map_reg_t; - - -/** Group: CORE0 ISP INT MAP REG */ -/** Type of isp_int_map register - * NA - */ -typedef union { - struct { - /** core0_isp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_isp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_isp_int_map_reg_t; - - -/** Group: CORE0 I3C MST INT MAP REG */ -/** Type of i3c_mst_int_map register - * NA - */ -typedef union { - struct { - /** core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i3c_mst_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i3c_mst_int_map_reg_t; - - -/** Group: CORE0 I3C SLV INT MAP REG */ -/** Type of i3c_slv_int_map register - * NA - */ -typedef union { - struct { - /** core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_i3c_slv_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_i3c_slv_int_map_reg_t; - - -/** Group: CORE0 USB OTG11 INT MAP REG */ -/** Type of usb_otg11_int_map register - * NA - */ -typedef union { - struct { - /** core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_usb_otg11_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_usb_otg11_int_map_reg_t; - - -/** Group: CORE0 DMA2D IN CH0 INT MAP REG */ -/** Type of dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE0 DMA2D IN CH1 INT MAP REG */ -/** Type of dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE0 DMA2D OUT CH0 INT MAP REG */ -/** Type of dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE0 DMA2D OUT CH1 INT MAP REG */ -/** Type of dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE0 DMA2D OUT CH2 INT MAP REG */ -/** Type of dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE0 PSRAM MSPI INT MAP REG */ -/** Type of psram_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_psram_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_psram_mspi_int_map_reg_t; - - -/** Group: CORE0 HP SYSREG INT MAP REG */ -/** Type of hp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_sysreg_int_map_reg_t; - - -/** Group: CORE0 PCNT INT MAP REG */ -/** Type of pcnt_int_map register - * NA - */ -typedef union { - struct { - /** core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_pcnt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_pcnt_int_map_reg_t; - - -/** Group: CORE0 HP PAU INT MAP REG */ -/** Type of hp_pau_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_pau_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_pau_int_map_reg_t; - - -/** Group: CORE0 HP PARLIO RX INT MAP REG */ -/** Type of hp_parlio_rx_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_parlio_rx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_parlio_rx_int_map_reg_t; - - -/** Group: CORE0 HP PARLIO TX INT MAP REG */ -/** Type of hp_parlio_tx_int_map register - * NA - */ -typedef union { - struct { - /** core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_hp_parlio_tx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_hp_parlio_tx_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH0 INT MAP REG */ -/** Type of h264_dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH1 INT MAP REG */ -/** Type of h264_dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH2 INT MAP REG */ -/** Type of h264_dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH3 INT MAP REG */ -/** Type of h264_dma2d_out_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch3_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D OUT CH4 INT MAP REG */ -/** Type of h264_dma2d_out_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_out_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_out_ch4_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH0 INT MAP REG */ -/** Type of h264_dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH1 INT MAP REG */ -/** Type of h264_dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH2 INT MAP REG */ -/** Type of h264_dma2d_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch2_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH3 INT MAP REG */ -/** Type of h264_dma2d_in_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch3_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH4 INT MAP REG */ -/** Type of h264_dma2d_in_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch4_int_map_reg_t; - - -/** Group: CORE0 H264 DMA2D IN CH5 INT MAP REG */ -/** Type of h264_dma2d_in_ch5_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_dma2d_in_ch5_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_dma2d_in_ch5_int_map_reg_t; - - -/** Group: CORE0 H264 REG INT MAP REG */ -/** Type of h264_reg_int_map register - * NA - */ -typedef union { - struct { - /** core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_h264_reg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_h264_reg_int_map_reg_t; - - -/** Group: CORE0 ASSIST DEBUG INT MAP REG */ -/** Type of assist_debug_int_map register - * NA - */ -typedef union { - struct { - /** core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core0_assist_debug_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core0_assist_debug_int_map_reg_t; - - -/** Group: CORE0 INTR STATUS REG 0 REG */ -/** Type of intr_status_reg_0 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_0:32; - }; - uint32_t val; -} core0_intr_status_reg_0_reg_t; - - -/** Group: CORE0 INTR STATUS REG 1 REG */ -/** Type of intr_status_reg_1 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_1:32; - }; - uint32_t val; -} core0_intr_status_reg_1_reg_t; - - -/** Group: CORE0 INTR STATUS REG 2 REG */ -/** Type of intr_status_reg_2 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_2:32; - }; - uint32_t val; -} core0_intr_status_reg_2_reg_t; - - -/** Group: CORE0 INTR STATUS REG 3 REG */ -/** Type of intr_status_reg_3 register - * NA - */ -typedef union { - struct { - /** core0_intr_status_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core0_intr_status_3:32; - }; - uint32_t val; -} core0_intr_status_reg_3_reg_t; - - -/** Group: CORE0 CLOCK GATE REG */ -/** Type of clock_gate register - * NA - */ -typedef union { - struct { - /** core0_reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t core0_reg_clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} core0_clock_gate_reg_t; - - -/** Group: CORE0 INTERRUPT REG DATE REG */ -/** Type of interrupt_reg_date register - * NA - */ -typedef union { - struct { - /** core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ - uint32_t core0_interrupt_reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} core0_interrupt_reg_date_reg_t; - - -typedef struct { - volatile core0_lp_rtc_int_map_reg_t lp_rtc_int_map; - volatile core0_lp_wdt_int_map_reg_t lp_wdt_int_map; - volatile core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; - volatile core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; - volatile core0_mb_hp_int_map_reg_t mb_hp_int_map; - volatile core0_mb_lp_int_map_reg_t mb_lp_int_map; - volatile core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; - volatile core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; - volatile core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map; - volatile core0_lp_adc_int_map_reg_t lp_adc_int_map; - volatile core0_lp_gpio_int_map_reg_t lp_gpio_int_map; - volatile core0_lp_i2c_int_map_reg_t lp_i2c_int_map; - volatile core0_lp_i2s_int_map_reg_t lp_i2s_int_map; - volatile core0_lp_spi_int_map_reg_t lp_spi_int_map; - volatile core0_lp_touch_int_map_reg_t lp_touch_int_map; - volatile core0_lp_tsens_int_map_reg_t lp_tsens_int_map; - volatile core0_lp_uart_int_map_reg_t lp_uart_int_map; - volatile core0_lp_efuse_int_map_reg_t lp_efuse_int_map; - volatile core0_lp_sw_int_map_reg_t lp_sw_int_map; - volatile core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map; - volatile core0_lp_huk_int_map_reg_t lp_huk_int_map; - volatile core0_sys_icm_int_map_reg_t sys_icm_int_map; - volatile core0_usb_device_int_map_reg_t usb_device_int_map; - volatile core0_sdio_host_int_map_reg_t sdio_host_int_map; - volatile core0_gdma_int_map_reg_t gdma_int_map; - volatile core0_spi2_int_map_reg_t spi2_int_map; - volatile core0_spi3_int_map_reg_t spi3_int_map; - volatile core0_i2s0_int_map_reg_t i2s0_int_map; - volatile core0_i2s1_int_map_reg_t i2s1_int_map; - volatile core0_i2s2_int_map_reg_t i2s2_int_map; - volatile core0_uhci0_int_map_reg_t uhci0_int_map; - volatile core0_uart0_int_map_reg_t uart0_int_map; - volatile core0_uart1_int_map_reg_t uart1_int_map; - volatile core0_uart2_int_map_reg_t uart2_int_map; - volatile core0_uart3_int_map_reg_t uart3_int_map; - volatile core0_uart4_int_map_reg_t uart4_int_map; - volatile core0_lcd_cam_int_map_reg_t lcd_cam_int_map; - volatile core0_adc_int_map_reg_t adc_int_map; - volatile core0_pwm0_int_map_reg_t pwm0_int_map; - volatile core0_pwm1_int_map_reg_t pwm1_int_map; - volatile core0_can0_int_map_reg_t can0_int_map; - volatile core0_can1_int_map_reg_t can1_int_map; - volatile core0_can2_int_map_reg_t can2_int_map; - volatile core0_rmt_int_map_reg_t rmt_int_map; - volatile core0_i2c0_int_map_reg_t i2c0_int_map; - volatile core0_i2c1_int_map_reg_t i2c1_int_map; - volatile core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; - volatile core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; - volatile core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; - volatile core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; - volatile core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; - volatile core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; - volatile core0_ledc_int_map_reg_t ledc_int_map; - volatile core0_systimer_target0_int_map_reg_t systimer_target0_int_map; - volatile core0_systimer_target1_int_map_reg_t systimer_target1_int_map; - volatile core0_systimer_target2_int_map_reg_t systimer_target2_int_map; - volatile core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; - volatile core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; - volatile core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; - volatile core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; - volatile core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; - volatile core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; - volatile core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; - volatile core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; - volatile core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; - volatile core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; - volatile core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; - volatile core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; - volatile core0_rsa_int_map_reg_t rsa_int_map; - volatile core0_aes_int_map_reg_t aes_int_map; - volatile core0_sha_int_map_reg_t sha_int_map; - volatile core0_ecc_int_map_reg_t ecc_int_map; - volatile core0_ecdsa_int_map_reg_t ecdsa_int_map; - volatile core0_km_int_map_reg_t km_int_map; - volatile core0_gpio_int0_map_reg_t gpio_int0_map; - volatile core0_gpio_int1_map_reg_t gpio_int1_map; - volatile core0_gpio_int2_map_reg_t gpio_int2_map; - volatile core0_gpio_int3_map_reg_t gpio_int3_map; - volatile core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; - volatile core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; - volatile core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; - volatile core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; - volatile core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; - volatile core0_cache_int_map_reg_t cache_int_map; - volatile core0_flash_mspi_int_map_reg_t flash_mspi_int_map; - volatile core0_csi_bridge_int_map_reg_t csi_bridge_int_map; - volatile core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map; - volatile core0_csi_int_map_reg_t csi_int_map; - volatile core0_dsi_int_map_reg_t dsi_int_map; - volatile core0_gmii_phy_int_map_reg_t gmii_phy_int_map; - volatile core0_lpi_int_map_reg_t lpi_int_map; - volatile core0_pmt_int_map_reg_t pmt_int_map; - volatile core0_sbd_int_map_reg_t sbd_int_map; - volatile core0_usb_otg_int_map_reg_t usb_otg_int_map; - volatile core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; - volatile core0_jpeg_int_map_reg_t jpeg_int_map; - volatile core0_ppa_int_map_reg_t ppa_int_map; - volatile core0_core0_trace_int_map_reg_t core0_trace_int_map; - volatile core0_core1_trace_int_map_reg_t core1_trace_int_map; - volatile core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; - volatile core0_isp_int_map_reg_t isp_int_map; - volatile core0_i3c_mst_int_map_reg_t i3c_mst_int_map; - volatile core0_i3c_slv_int_map_reg_t i3c_slv_int_map; - volatile core0_usb_otg11_int_map_reg_t usb_otg11_int_map; - volatile core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; - volatile core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; - volatile core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; - volatile core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; - volatile core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; - volatile core0_psram_mspi_int_map_reg_t psram_mspi_int_map; - volatile core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map; - volatile core0_pcnt_int_map_reg_t pcnt_int_map; - volatile core0_hp_pau_int_map_reg_t hp_pau_int_map; - volatile core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; - volatile core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; - volatile core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; - volatile core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; - volatile core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; - volatile core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; - volatile core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; - volatile core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; - volatile core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; - volatile core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; - volatile core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; - volatile core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; - volatile core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; - volatile core0_h264_reg_int_map_reg_t h264_reg_int_map; - volatile core0_assist_debug_int_map_reg_t assist_debug_int_map; - volatile core0_intr_status_reg_0_reg_t intr_status_reg_0; - volatile core0_intr_status_reg_1_reg_t intr_status_reg_1; - volatile core0_intr_status_reg_2_reg_t intr_status_reg_2; - volatile core0_intr_status_reg_3_reg_t intr_status_reg_3; - volatile core0_clock_gate_reg_t clock_gate; - uint32_t reserved_214[122]; - volatile core0_interrupt_reg_date_reg_t interrupt_reg_date; -} core0_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(core0_dev_t) == 0x400, "Invalid size of core0_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/core1_interrupt_reg.h b/components/soc/esp32p4/include/soc/core1_interrupt_reg.h deleted file mode 100644 index f7a6bd5409..0000000000 --- a/components/soc/esp32p4/include/soc/core1_interrupt_reg.h +++ /dev/null @@ -1,1624 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** CORE1_LP_RTC_INT_MAP_REG register - * NA - */ -#define CORE1_LP_RTC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x0) -/** CORE1_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_RTC_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_RTC_INT_MAP_M (CORE1_CORE1_LP_RTC_INT_MAP_V << CORE1_CORE1_LP_RTC_INT_MAP_S) -#define CORE1_CORE1_LP_RTC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_RTC_INT_MAP_S 0 - -/** CORE1_LP_WDT_INT_MAP_REG register - * NA - */ -#define CORE1_LP_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x4) -/** CORE1_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_WDT_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_WDT_INT_MAP_M (CORE1_CORE1_LP_WDT_INT_MAP_V << CORE1_CORE1_LP_WDT_INT_MAP_S) -#define CORE1_CORE1_LP_WDT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_WDT_INT_MAP_S 0 - -/** CORE1_LP_TIMER_REG_0_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x8) -/** CORE1_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_M (CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S) -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S 0 - -/** CORE1_LP_TIMER_REG_1_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc) -/** CORE1_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_M (CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S) -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S 0 - -/** CORE1_MB_HP_INT_MAP_REG register - * NA - */ -#define CORE1_MB_HP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x10) -/** CORE1_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_MB_HP_INT_MAP 0x0000003FU -#define CORE1_CORE1_MB_HP_INT_MAP_M (CORE1_CORE1_MB_HP_INT_MAP_V << CORE1_CORE1_MB_HP_INT_MAP_S) -#define CORE1_CORE1_MB_HP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_MB_HP_INT_MAP_S 0 - -/** CORE1_MB_LP_INT_MAP_REG register - * NA - */ -#define CORE1_MB_LP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x14) -/** CORE1_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_MB_LP_INT_MAP 0x0000003FU -#define CORE1_CORE1_MB_LP_INT_MAP_M (CORE1_CORE1_MB_LP_INT_MAP_V << CORE1_CORE1_MB_LP_INT_MAP_S) -#define CORE1_CORE1_MB_LP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_MB_LP_INT_MAP_S 0 - -/** CORE1_PMU_REG_0_INT_MAP_REG register - * NA - */ -#define CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x18) -/** CORE1_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PMU_REG_0_INT_MAP 0x0000003FU -#define CORE1_CORE1_PMU_REG_0_INT_MAP_M (CORE1_CORE1_PMU_REG_0_INT_MAP_V << CORE1_CORE1_PMU_REG_0_INT_MAP_S) -#define CORE1_CORE1_PMU_REG_0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PMU_REG_0_INT_MAP_S 0 - -/** CORE1_PMU_REG_1_INT_MAP_REG register - * NA - */ -#define CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c) -/** CORE1_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PMU_REG_1_INT_MAP 0x0000003FU -#define CORE1_CORE1_PMU_REG_1_INT_MAP_M (CORE1_CORE1_PMU_REG_1_INT_MAP_V << CORE1_CORE1_PMU_REG_1_INT_MAP_S) -#define CORE1_CORE1_PMU_REG_1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PMU_REG_1_INT_MAP_S 0 - -/** CORE1_LP_ANAPERI_INT_MAP_REG register - * NA - */ -#define CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x20) -/** CORE1_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_ANAPERI_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_ANAPERI_INT_MAP_M (CORE1_CORE1_LP_ANAPERI_INT_MAP_V << CORE1_CORE1_LP_ANAPERI_INT_MAP_S) -#define CORE1_CORE1_LP_ANAPERI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_ANAPERI_INT_MAP_S 0 - -/** CORE1_LP_ADC_INT_MAP_REG register - * NA - */ -#define CORE1_LP_ADC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x24) -/** CORE1_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_ADC_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_ADC_INT_MAP_M (CORE1_CORE1_LP_ADC_INT_MAP_V << CORE1_CORE1_LP_ADC_INT_MAP_S) -#define CORE1_CORE1_LP_ADC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_ADC_INT_MAP_S 0 - -/** CORE1_LP_GPIO_INT_MAP_REG register - * NA - */ -#define CORE1_LP_GPIO_INT_MAP_REG (DR_REG_CORE1_BASE + 0x28) -/** CORE1_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_GPIO_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_GPIO_INT_MAP_M (CORE1_CORE1_LP_GPIO_INT_MAP_V << CORE1_CORE1_LP_GPIO_INT_MAP_S) -#define CORE1_CORE1_LP_GPIO_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_GPIO_INT_MAP_S 0 - -/** CORE1_LP_I2C_INT_MAP_REG register - * NA - */ -#define CORE1_LP_I2C_INT_MAP_REG (DR_REG_CORE1_BASE + 0x2c) -/** CORE1_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_I2C_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_I2C_INT_MAP_M (CORE1_CORE1_LP_I2C_INT_MAP_V << CORE1_CORE1_LP_I2C_INT_MAP_S) -#define CORE1_CORE1_LP_I2C_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_I2C_INT_MAP_S 0 - -/** CORE1_LP_I2S_INT_MAP_REG register - * NA - */ -#define CORE1_LP_I2S_INT_MAP_REG (DR_REG_CORE1_BASE + 0x30) -/** CORE1_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_I2S_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_I2S_INT_MAP_M (CORE1_CORE1_LP_I2S_INT_MAP_V << CORE1_CORE1_LP_I2S_INT_MAP_S) -#define CORE1_CORE1_LP_I2S_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_I2S_INT_MAP_S 0 - -/** CORE1_LP_SPI_INT_MAP_REG register - * NA - */ -#define CORE1_LP_SPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x34) -/** CORE1_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_SPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_SPI_INT_MAP_M (CORE1_CORE1_LP_SPI_INT_MAP_V << CORE1_CORE1_LP_SPI_INT_MAP_S) -#define CORE1_CORE1_LP_SPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_SPI_INT_MAP_S 0 - -/** CORE1_LP_TOUCH_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_CORE1_BASE + 0x38) -/** CORE1_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TOUCH_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TOUCH_INT_MAP_M (CORE1_CORE1_LP_TOUCH_INT_MAP_V << CORE1_CORE1_LP_TOUCH_INT_MAP_S) -#define CORE1_CORE1_LP_TOUCH_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TOUCH_INT_MAP_S 0 - -/** CORE1_LP_TSENS_INT_MAP_REG register - * NA - */ -#define CORE1_LP_TSENS_INT_MAP_REG (DR_REG_CORE1_BASE + 0x3c) -/** CORE1_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_TSENS_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_TSENS_INT_MAP_M (CORE1_CORE1_LP_TSENS_INT_MAP_V << CORE1_CORE1_LP_TSENS_INT_MAP_S) -#define CORE1_CORE1_LP_TSENS_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_TSENS_INT_MAP_S 0 - -/** CORE1_LP_UART_INT_MAP_REG register - * NA - */ -#define CORE1_LP_UART_INT_MAP_REG (DR_REG_CORE1_BASE + 0x40) -/** CORE1_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_UART_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_UART_INT_MAP_M (CORE1_CORE1_LP_UART_INT_MAP_V << CORE1_CORE1_LP_UART_INT_MAP_S) -#define CORE1_CORE1_LP_UART_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_UART_INT_MAP_S 0 - -/** CORE1_LP_EFUSE_INT_MAP_REG register - * NA - */ -#define CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x44) -/** CORE1_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_EFUSE_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_EFUSE_INT_MAP_M (CORE1_CORE1_LP_EFUSE_INT_MAP_V << CORE1_CORE1_LP_EFUSE_INT_MAP_S) -#define CORE1_CORE1_LP_EFUSE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_EFUSE_INT_MAP_S 0 - -/** CORE1_LP_SW_INT_MAP_REG register - * NA - */ -#define CORE1_LP_SW_INT_MAP_REG (DR_REG_CORE1_BASE + 0x48) -/** CORE1_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_SW_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_SW_INT_MAP_M (CORE1_CORE1_LP_SW_INT_MAP_V << CORE1_CORE1_LP_SW_INT_MAP_S) -#define CORE1_CORE1_LP_SW_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_SW_INT_MAP_S 0 - -/** CORE1_LP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x4c) -/** CORE1_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_SYSREG_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_SYSREG_INT_MAP_M (CORE1_CORE1_LP_SYSREG_INT_MAP_V << CORE1_CORE1_LP_SYSREG_INT_MAP_S) -#define CORE1_CORE1_LP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_SYSREG_INT_MAP_S 0 - -/** CORE1_LP_HUK_INT_MAP_REG register - * NA - */ -#define CORE1_LP_HUK_INT_MAP_REG (DR_REG_CORE1_BASE + 0x50) -/** CORE1_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LP_HUK_INT_MAP 0x0000003FU -#define CORE1_CORE1_LP_HUK_INT_MAP_M (CORE1_CORE1_LP_HUK_INT_MAP_V << CORE1_CORE1_LP_HUK_INT_MAP_S) -#define CORE1_CORE1_LP_HUK_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LP_HUK_INT_MAP_S 0 - -/** CORE1_SYS_ICM_INT_MAP_REG register - * NA - */ -#define CORE1_SYS_ICM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x54) -/** CORE1_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYS_ICM_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYS_ICM_INT_MAP_M (CORE1_CORE1_SYS_ICM_INT_MAP_V << CORE1_CORE1_SYS_ICM_INT_MAP_S) -#define CORE1_CORE1_SYS_ICM_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYS_ICM_INT_MAP_S 0 - -/** CORE1_USB_DEVICE_INT_MAP_REG register - * NA - */ -#define CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x58) -/** CORE1_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_DEVICE_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_DEVICE_INT_MAP_M (CORE1_CORE1_USB_DEVICE_INT_MAP_V << CORE1_CORE1_USB_DEVICE_INT_MAP_S) -#define CORE1_CORE1_USB_DEVICE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_DEVICE_INT_MAP_S 0 - -/** CORE1_SDIO_HOST_INT_MAP_REG register - * NA - */ -#define CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_CORE1_BASE + 0x5c) -/** CORE1_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SDIO_HOST_INT_MAP 0x0000003FU -#define CORE1_CORE1_SDIO_HOST_INT_MAP_M (CORE1_CORE1_SDIO_HOST_INT_MAP_V << CORE1_CORE1_SDIO_HOST_INT_MAP_S) -#define CORE1_CORE1_SDIO_HOST_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SDIO_HOST_INT_MAP_S 0 - -/** CORE1_GDMA_INT_MAP_REG register - * NA - */ -#define CORE1_GDMA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x60) -/** CORE1_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GDMA_INT_MAP 0x0000003FU -#define CORE1_CORE1_GDMA_INT_MAP_M (CORE1_CORE1_GDMA_INT_MAP_V << CORE1_CORE1_GDMA_INT_MAP_S) -#define CORE1_CORE1_GDMA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_GDMA_INT_MAP_S 0 - -/** CORE1_SPI2_INT_MAP_REG register - * NA - */ -#define CORE1_SPI2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x64) -/** CORE1_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SPI2_INT_MAP 0x0000003FU -#define CORE1_CORE1_SPI2_INT_MAP_M (CORE1_CORE1_SPI2_INT_MAP_V << CORE1_CORE1_SPI2_INT_MAP_S) -#define CORE1_CORE1_SPI2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SPI2_INT_MAP_S 0 - -/** CORE1_SPI3_INT_MAP_REG register - * NA - */ -#define CORE1_SPI3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x68) -/** CORE1_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SPI3_INT_MAP 0x0000003FU -#define CORE1_CORE1_SPI3_INT_MAP_M (CORE1_CORE1_SPI3_INT_MAP_V << CORE1_CORE1_SPI3_INT_MAP_S) -#define CORE1_CORE1_SPI3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SPI3_INT_MAP_S 0 - -/** CORE1_I2S0_INT_MAP_REG register - * NA - */ -#define CORE1_I2S0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x6c) -/** CORE1_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2S0_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2S0_INT_MAP_M (CORE1_CORE1_I2S0_INT_MAP_V << CORE1_CORE1_I2S0_INT_MAP_S) -#define CORE1_CORE1_I2S0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2S0_INT_MAP_S 0 - -/** CORE1_I2S1_INT_MAP_REG register - * NA - */ -#define CORE1_I2S1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x70) -/** CORE1_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2S1_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2S1_INT_MAP_M (CORE1_CORE1_I2S1_INT_MAP_V << CORE1_CORE1_I2S1_INT_MAP_S) -#define CORE1_CORE1_I2S1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2S1_INT_MAP_S 0 - -/** CORE1_I2S2_INT_MAP_REG register - * NA - */ -#define CORE1_I2S2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x74) -/** CORE1_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2S2_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2S2_INT_MAP_M (CORE1_CORE1_I2S2_INT_MAP_V << CORE1_CORE1_I2S2_INT_MAP_S) -#define CORE1_CORE1_I2S2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2S2_INT_MAP_S 0 - -/** CORE1_UHCI0_INT_MAP_REG register - * NA - */ -#define CORE1_UHCI0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x78) -/** CORE1_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UHCI0_INT_MAP 0x0000003FU -#define CORE1_CORE1_UHCI0_INT_MAP_M (CORE1_CORE1_UHCI0_INT_MAP_V << CORE1_CORE1_UHCI0_INT_MAP_S) -#define CORE1_CORE1_UHCI0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UHCI0_INT_MAP_S 0 - -/** CORE1_UART0_INT_MAP_REG register - * NA - */ -#define CORE1_UART0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x7c) -/** CORE1_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART0_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART0_INT_MAP_M (CORE1_CORE1_UART0_INT_MAP_V << CORE1_CORE1_UART0_INT_MAP_S) -#define CORE1_CORE1_UART0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART0_INT_MAP_S 0 - -/** CORE1_UART1_INT_MAP_REG register - * NA - */ -#define CORE1_UART1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x80) -/** CORE1_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART1_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART1_INT_MAP_M (CORE1_CORE1_UART1_INT_MAP_V << CORE1_CORE1_UART1_INT_MAP_S) -#define CORE1_CORE1_UART1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART1_INT_MAP_S 0 - -/** CORE1_UART2_INT_MAP_REG register - * NA - */ -#define CORE1_UART2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x84) -/** CORE1_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART2_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART2_INT_MAP_M (CORE1_CORE1_UART2_INT_MAP_V << CORE1_CORE1_UART2_INT_MAP_S) -#define CORE1_CORE1_UART2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART2_INT_MAP_S 0 - -/** CORE1_UART3_INT_MAP_REG register - * NA - */ -#define CORE1_UART3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x88) -/** CORE1_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART3_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART3_INT_MAP_M (CORE1_CORE1_UART3_INT_MAP_V << CORE1_CORE1_UART3_INT_MAP_S) -#define CORE1_CORE1_UART3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART3_INT_MAP_S 0 - -/** CORE1_UART4_INT_MAP_REG register - * NA - */ -#define CORE1_UART4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x8c) -/** CORE1_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_UART4_INT_MAP 0x0000003FU -#define CORE1_CORE1_UART4_INT_MAP_M (CORE1_CORE1_UART4_INT_MAP_V << CORE1_CORE1_UART4_INT_MAP_S) -#define CORE1_CORE1_UART4_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_UART4_INT_MAP_S 0 - -/** CORE1_LCD_CAM_INT_MAP_REG register - * NA - */ -#define CORE1_LCD_CAM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x90) -/** CORE1_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LCD_CAM_INT_MAP 0x0000003FU -#define CORE1_CORE1_LCD_CAM_INT_MAP_M (CORE1_CORE1_LCD_CAM_INT_MAP_V << CORE1_CORE1_LCD_CAM_INT_MAP_S) -#define CORE1_CORE1_LCD_CAM_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LCD_CAM_INT_MAP_S 0 - -/** CORE1_ADC_INT_MAP_REG register - * NA - */ -#define CORE1_ADC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x94) -/** CORE1_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ADC_INT_MAP 0x0000003FU -#define CORE1_CORE1_ADC_INT_MAP_M (CORE1_CORE1_ADC_INT_MAP_V << CORE1_CORE1_ADC_INT_MAP_S) -#define CORE1_CORE1_ADC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ADC_INT_MAP_S 0 - -/** CORE1_PWM0_INT_MAP_REG register - * NA - */ -#define CORE1_PWM0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x98) -/** CORE1_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PWM0_INT_MAP 0x0000003FU -#define CORE1_CORE1_PWM0_INT_MAP_M (CORE1_CORE1_PWM0_INT_MAP_V << CORE1_CORE1_PWM0_INT_MAP_S) -#define CORE1_CORE1_PWM0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PWM0_INT_MAP_S 0 - -/** CORE1_PWM1_INT_MAP_REG register - * NA - */ -#define CORE1_PWM1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x9c) -/** CORE1_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PWM1_INT_MAP 0x0000003FU -#define CORE1_CORE1_PWM1_INT_MAP_M (CORE1_CORE1_PWM1_INT_MAP_V << CORE1_CORE1_PWM1_INT_MAP_S) -#define CORE1_CORE1_PWM1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PWM1_INT_MAP_S 0 - -/** CORE1_CAN0_INT_MAP_REG register - * NA - */ -#define CORE1_CAN0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa0) -/** CORE1_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CAN0_INT_MAP 0x0000003FU -#define CORE1_CORE1_CAN0_INT_MAP_M (CORE1_CORE1_CAN0_INT_MAP_V << CORE1_CORE1_CAN0_INT_MAP_S) -#define CORE1_CORE1_CAN0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CAN0_INT_MAP_S 0 - -/** CORE1_CAN1_INT_MAP_REG register - * NA - */ -#define CORE1_CAN1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa4) -/** CORE1_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CAN1_INT_MAP 0x0000003FU -#define CORE1_CORE1_CAN1_INT_MAP_M (CORE1_CORE1_CAN1_INT_MAP_V << CORE1_CORE1_CAN1_INT_MAP_S) -#define CORE1_CORE1_CAN1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CAN1_INT_MAP_S 0 - -/** CORE1_CAN2_INT_MAP_REG register - * NA - */ -#define CORE1_CAN2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xa8) -/** CORE1_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CAN2_INT_MAP 0x0000003FU -#define CORE1_CORE1_CAN2_INT_MAP_M (CORE1_CORE1_CAN2_INT_MAP_V << CORE1_CORE1_CAN2_INT_MAP_S) -#define CORE1_CORE1_CAN2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CAN2_INT_MAP_S 0 - -/** CORE1_RMT_INT_MAP_REG register - * NA - */ -#define CORE1_RMT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xac) -/** CORE1_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_RMT_INT_MAP 0x0000003FU -#define CORE1_CORE1_RMT_INT_MAP_M (CORE1_CORE1_RMT_INT_MAP_V << CORE1_CORE1_RMT_INT_MAP_S) -#define CORE1_CORE1_RMT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_RMT_INT_MAP_S 0 - -/** CORE1_I2C0_INT_MAP_REG register - * NA - */ -#define CORE1_I2C0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb0) -/** CORE1_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2C0_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2C0_INT_MAP_M (CORE1_CORE1_I2C0_INT_MAP_V << CORE1_CORE1_I2C0_INT_MAP_S) -#define CORE1_CORE1_I2C0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2C0_INT_MAP_S 0 - -/** CORE1_I2C1_INT_MAP_REG register - * NA - */ -#define CORE1_I2C1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb4) -/** CORE1_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I2C1_INT_MAP 0x0000003FU -#define CORE1_CORE1_I2C1_INT_MAP_M (CORE1_CORE1_I2C1_INT_MAP_V << CORE1_CORE1_I2C1_INT_MAP_S) -#define CORE1_CORE1_I2C1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I2C1_INT_MAP_S 0 - -/** CORE1_TIMERGRP0_T0_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xb8) -/** CORE1_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_M (CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S 0 - -/** CORE1_TIMERGRP0_T1_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xbc) -/** CORE1_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_M (CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S 0 - -/** CORE1_TIMERGRP0_WDT_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc0) -/** CORE1_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_M (CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S 0 - -/** CORE1_TIMERGRP1_T0_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc4) -/** CORE1_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_M (CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S 0 - -/** CORE1_TIMERGRP1_T1_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xc8) -/** CORE1_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_M (CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S 0 - -/** CORE1_TIMERGRP1_WDT_INT_MAP_REG register - * NA - */ -#define CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_CORE1_BASE + 0xcc) -/** CORE1_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_M (CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S) -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S 0 - -/** CORE1_LEDC_INT_MAP_REG register - * NA - */ -#define CORE1_LEDC_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd0) -/** CORE1_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LEDC_INT_MAP 0x0000003FU -#define CORE1_CORE1_LEDC_INT_MAP_M (CORE1_CORE1_LEDC_INT_MAP_V << CORE1_CORE1_LEDC_INT_MAP_S) -#define CORE1_CORE1_LEDC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LEDC_INT_MAP_S 0 - -/** CORE1_SYSTIMER_TARGET0_INT_MAP_REG register - * NA - */ -#define CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd4) -/** CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S) -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 - -/** CORE1_SYSTIMER_TARGET1_INT_MAP_REG register - * NA - */ -#define CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xd8) -/** CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S) -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 - -/** CORE1_SYSTIMER_TARGET2_INT_MAP_REG register - * NA - */ -#define CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xdc) -/** CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S) -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe0) -/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe4) -/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xe8) -/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xec) -/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf0) -/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf4) -/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0xf8) -/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0xfc) -/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x100) -/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x104) -/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x108) -/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S 0 - -/** CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x10c) -/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S 0 - -/** CORE1_RSA_INT_MAP_REG register - * NA - */ -#define CORE1_RSA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x110) -/** CORE1_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_RSA_INT_MAP 0x0000003FU -#define CORE1_CORE1_RSA_INT_MAP_M (CORE1_CORE1_RSA_INT_MAP_V << CORE1_CORE1_RSA_INT_MAP_S) -#define CORE1_CORE1_RSA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_RSA_INT_MAP_S 0 - -/** CORE1_AES_INT_MAP_REG register - * NA - */ -#define CORE1_AES_INT_MAP_REG (DR_REG_CORE1_BASE + 0x114) -/** CORE1_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_AES_INT_MAP 0x0000003FU -#define CORE1_CORE1_AES_INT_MAP_M (CORE1_CORE1_AES_INT_MAP_V << CORE1_CORE1_AES_INT_MAP_S) -#define CORE1_CORE1_AES_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_AES_INT_MAP_S 0 - -/** CORE1_SHA_INT_MAP_REG register - * NA - */ -#define CORE1_SHA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x118) -/** CORE1_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SHA_INT_MAP 0x0000003FU -#define CORE1_CORE1_SHA_INT_MAP_M (CORE1_CORE1_SHA_INT_MAP_V << CORE1_CORE1_SHA_INT_MAP_S) -#define CORE1_CORE1_SHA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SHA_INT_MAP_S 0 - -/** CORE1_ECC_INT_MAP_REG register - * NA - */ -#define CORE1_ECC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x11c) -/** CORE1_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ECC_INT_MAP 0x0000003FU -#define CORE1_CORE1_ECC_INT_MAP_M (CORE1_CORE1_ECC_INT_MAP_V << CORE1_CORE1_ECC_INT_MAP_S) -#define CORE1_CORE1_ECC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ECC_INT_MAP_S 0 - -/** CORE1_ECDSA_INT_MAP_REG register - * NA - */ -#define CORE1_ECDSA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x120) -/** CORE1_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ECDSA_INT_MAP 0x0000003FU -#define CORE1_CORE1_ECDSA_INT_MAP_M (CORE1_CORE1_ECDSA_INT_MAP_V << CORE1_CORE1_ECDSA_INT_MAP_S) -#define CORE1_CORE1_ECDSA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ECDSA_INT_MAP_S 0 - -/** CORE1_KM_INT_MAP_REG register - * NA - */ -#define CORE1_KM_INT_MAP_REG (DR_REG_CORE1_BASE + 0x124) -/** CORE1_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_KM_INT_MAP 0x0000003FU -#define CORE1_CORE1_KM_INT_MAP_M (CORE1_CORE1_KM_INT_MAP_V << CORE1_CORE1_KM_INT_MAP_S) -#define CORE1_CORE1_KM_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_KM_INT_MAP_S 0 - -/** CORE1_GPIO_INT0_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT0_MAP_REG (DR_REG_CORE1_BASE + 0x128) -/** CORE1_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT0_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT0_MAP_M (CORE1_CORE1_GPIO_INT0_MAP_V << CORE1_CORE1_GPIO_INT0_MAP_S) -#define CORE1_CORE1_GPIO_INT0_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT0_MAP_S 0 - -/** CORE1_GPIO_INT1_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT1_MAP_REG (DR_REG_CORE1_BASE + 0x12c) -/** CORE1_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT1_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT1_MAP_M (CORE1_CORE1_GPIO_INT1_MAP_V << CORE1_CORE1_GPIO_INT1_MAP_S) -#define CORE1_CORE1_GPIO_INT1_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT1_MAP_S 0 - -/** CORE1_GPIO_INT2_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT2_MAP_REG (DR_REG_CORE1_BASE + 0x130) -/** CORE1_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT2_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT2_MAP_M (CORE1_CORE1_GPIO_INT2_MAP_V << CORE1_CORE1_GPIO_INT2_MAP_S) -#define CORE1_CORE1_GPIO_INT2_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT2_MAP_S 0 - -/** CORE1_GPIO_INT3_MAP_REG register - * NA - */ -#define CORE1_GPIO_INT3_MAP_REG (DR_REG_CORE1_BASE + 0x134) -/** CORE1_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_INT3_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_INT3_MAP_M (CORE1_CORE1_GPIO_INT3_MAP_V << CORE1_CORE1_GPIO_INT3_MAP_S) -#define CORE1_CORE1_GPIO_INT3_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_INT3_MAP_S 0 - -/** CORE1_GPIO_PAD_COMP_INT_MAP_REG register - * NA - */ -#define CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x138) -/** CORE1_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP 0x0000003FU -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_M (CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V << CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S) -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_0_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_CORE1_BASE + 0x13c) -/** CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_1_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_CORE1_BASE + 0x140) -/** CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_2_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_CORE1_BASE + 0x144) -/** CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S 0 - -/** CORE1_CPU_INT_FROM_CPU_3_MAP_REG register - * NA - */ -#define CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_CORE1_BASE + 0x148) -/** CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S) -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU -#define CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S 0 - -/** CORE1_CACHE_INT_MAP_REG register - * NA - */ -#define CORE1_CACHE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x14c) -/** CORE1_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CACHE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CACHE_INT_MAP_M (CORE1_CORE1_CACHE_INT_MAP_V << CORE1_CORE1_CACHE_INT_MAP_S) -#define CORE1_CORE1_CACHE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CACHE_INT_MAP_S 0 - -/** CORE1_FLASH_MSPI_INT_MAP_REG register - * NA - */ -#define CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x150) -/** CORE1_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_FLASH_MSPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_FLASH_MSPI_INT_MAP_M (CORE1_CORE1_FLASH_MSPI_INT_MAP_V << CORE1_CORE1_FLASH_MSPI_INT_MAP_S) -#define CORE1_CORE1_FLASH_MSPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_FLASH_MSPI_INT_MAP_S 0 - -/** CORE1_CSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x154) -/** CORE1_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_M (CORE1_CORE1_CSI_BRIDGE_INT_MAP_V << CORE1_CORE1_CSI_BRIDGE_INT_MAP_S) -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CSI_BRIDGE_INT_MAP_S 0 - -/** CORE1_DSI_BRIDGE_INT_MAP_REG register - * NA - */ -#define CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x158) -/** CORE1_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP 0x0000003FU -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_M (CORE1_CORE1_DSI_BRIDGE_INT_MAP_V << CORE1_CORE1_DSI_BRIDGE_INT_MAP_S) -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DSI_BRIDGE_INT_MAP_S 0 - -/** CORE1_CSI_INT_MAP_REG register - * NA - */ -#define CORE1_CSI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x15c) -/** CORE1_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CSI_INT_MAP 0x0000003FU -#define CORE1_CORE1_CSI_INT_MAP_M (CORE1_CORE1_CSI_INT_MAP_V << CORE1_CORE1_CSI_INT_MAP_S) -#define CORE1_CORE1_CSI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CSI_INT_MAP_S 0 - -/** CORE1_DSI_INT_MAP_REG register - * NA - */ -#define CORE1_DSI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x160) -/** CORE1_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DSI_INT_MAP 0x0000003FU -#define CORE1_CORE1_DSI_INT_MAP_M (CORE1_CORE1_DSI_INT_MAP_V << CORE1_CORE1_DSI_INT_MAP_S) -#define CORE1_CORE1_DSI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DSI_INT_MAP_S 0 - -/** CORE1_GMII_PHY_INT_MAP_REG register - * NA - */ -#define CORE1_GMII_PHY_INT_MAP_REG (DR_REG_CORE1_BASE + 0x164) -/** CORE1_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_GMII_PHY_INT_MAP 0x0000003FU -#define CORE1_CORE1_GMII_PHY_INT_MAP_M (CORE1_CORE1_GMII_PHY_INT_MAP_V << CORE1_CORE1_GMII_PHY_INT_MAP_S) -#define CORE1_CORE1_GMII_PHY_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_GMII_PHY_INT_MAP_S 0 - -/** CORE1_LPI_INT_MAP_REG register - * NA - */ -#define CORE1_LPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x168) -/** CORE1_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_LPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_LPI_INT_MAP_M (CORE1_CORE1_LPI_INT_MAP_V << CORE1_CORE1_LPI_INT_MAP_S) -#define CORE1_CORE1_LPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_LPI_INT_MAP_S 0 - -/** CORE1_PMT_INT_MAP_REG register - * NA - */ -#define CORE1_PMT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x16c) -/** CORE1_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PMT_INT_MAP 0x0000003FU -#define CORE1_CORE1_PMT_INT_MAP_M (CORE1_CORE1_PMT_INT_MAP_V << CORE1_CORE1_PMT_INT_MAP_S) -#define CORE1_CORE1_PMT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PMT_INT_MAP_S 0 - -/** CORE1_SBD_INT_MAP_REG register - * NA - */ -#define CORE1_SBD_INT_MAP_REG (DR_REG_CORE1_BASE + 0x170) -/** CORE1_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_SBD_INT_MAP 0x0000003FU -#define CORE1_CORE1_SBD_INT_MAP_M (CORE1_CORE1_SBD_INT_MAP_V << CORE1_CORE1_SBD_INT_MAP_S) -#define CORE1_CORE1_SBD_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_SBD_INT_MAP_S 0 - -/** CORE1_USB_OTG_INT_MAP_REG register - * NA - */ -#define CORE1_USB_OTG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x174) -/** CORE1_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_OTG_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_OTG_INT_MAP_M (CORE1_CORE1_USB_OTG_INT_MAP_V << CORE1_CORE1_USB_OTG_INT_MAP_S) -#define CORE1_CORE1_USB_OTG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_OTG_INT_MAP_S 0 - -/** CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register - * NA - */ -#define CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_CORE1_BASE + 0x178) -/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 - -/** CORE1_JPEG_INT_MAP_REG register - * NA - */ -#define CORE1_JPEG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x17c) -/** CORE1_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_JPEG_INT_MAP 0x0000003FU -#define CORE1_CORE1_JPEG_INT_MAP_M (CORE1_CORE1_JPEG_INT_MAP_V << CORE1_CORE1_JPEG_INT_MAP_S) -#define CORE1_CORE1_JPEG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_JPEG_INT_MAP_S 0 - -/** CORE1_PPA_INT_MAP_REG register - * NA - */ -#define CORE1_PPA_INT_MAP_REG (DR_REG_CORE1_BASE + 0x180) -/** CORE1_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PPA_INT_MAP 0x0000003FU -#define CORE1_CORE1_PPA_INT_MAP_M (CORE1_CORE1_PPA_INT_MAP_V << CORE1_CORE1_PPA_INT_MAP_S) -#define CORE1_CORE1_PPA_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PPA_INT_MAP_S 0 - -/** CORE1_CORE0_TRACE_INT_MAP_REG register - * NA - */ -#define CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x184) -/** CORE1_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CORE0_TRACE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CORE0_TRACE_INT_MAP_M (CORE1_CORE1_CORE0_TRACE_INT_MAP_V << CORE1_CORE1_CORE0_TRACE_INT_MAP_S) -#define CORE1_CORE1_CORE0_TRACE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CORE0_TRACE_INT_MAP_S 0 - -/** CORE1_CORE1_TRACE_INT_MAP_REG register - * NA - */ -#define CORE1_CORE1_TRACE_INT_MAP_REG (DR_REG_CORE1_BASE + 0x188) -/** CORE1_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_CORE1_TRACE_INT_MAP 0x0000003FU -#define CORE1_CORE1_CORE1_TRACE_INT_MAP_M (CORE1_CORE1_CORE1_TRACE_INT_MAP_V << CORE1_CORE1_CORE1_TRACE_INT_MAP_S) -#define CORE1_CORE1_CORE1_TRACE_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_CORE1_TRACE_INT_MAP_S 0 - -/** CORE1_HP_CORE_CTRL_INT_MAP_REG register - * NA - */ -#define CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_CORE1_BASE + 0x18c) -/** CORE1_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_M (CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V << CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S) -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S 0 - -/** CORE1_ISP_INT_MAP_REG register - * NA - */ -#define CORE1_ISP_INT_MAP_REG (DR_REG_CORE1_BASE + 0x190) -/** CORE1_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ISP_INT_MAP 0x0000003FU -#define CORE1_CORE1_ISP_INT_MAP_M (CORE1_CORE1_ISP_INT_MAP_V << CORE1_CORE1_ISP_INT_MAP_S) -#define CORE1_CORE1_ISP_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ISP_INT_MAP_S 0 - -/** CORE1_I3C_MST_INT_MAP_REG register - * NA - */ -#define CORE1_I3C_MST_INT_MAP_REG (DR_REG_CORE1_BASE + 0x194) -/** CORE1_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I3C_MST_INT_MAP 0x0000003FU -#define CORE1_CORE1_I3C_MST_INT_MAP_M (CORE1_CORE1_I3C_MST_INT_MAP_V << CORE1_CORE1_I3C_MST_INT_MAP_S) -#define CORE1_CORE1_I3C_MST_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I3C_MST_INT_MAP_S 0 - -/** CORE1_I3C_SLV_INT_MAP_REG register - * NA - */ -#define CORE1_I3C_SLV_INT_MAP_REG (DR_REG_CORE1_BASE + 0x198) -/** CORE1_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_I3C_SLV_INT_MAP 0x0000003FU -#define CORE1_CORE1_I3C_SLV_INT_MAP_M (CORE1_CORE1_I3C_SLV_INT_MAP_V << CORE1_CORE1_I3C_SLV_INT_MAP_S) -#define CORE1_CORE1_I3C_SLV_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_I3C_SLV_INT_MAP_S 0 - -/** CORE1_USB_OTG11_INT_MAP_REG register - * NA - */ -#define CORE1_USB_OTG11_INT_MAP_REG (DR_REG_CORE1_BASE + 0x19c) -/** CORE1_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_USB_OTG11_INT_MAP 0x0000003FU -#define CORE1_CORE1_USB_OTG11_INT_MAP_M (CORE1_CORE1_USB_OTG11_INT_MAP_V << CORE1_CORE1_USB_OTG11_INT_MAP_S) -#define CORE1_CORE1_USB_OTG11_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_USB_OTG11_INT_MAP_S 0 - -/** CORE1_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a0) -/** CORE1_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_M (CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE1_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a4) -/** CORE1_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_M (CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE1_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1a8) -/** CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE1_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1ac) -/** CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE1_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b0) -/** CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE1_PSRAM_MSPI_INT_MAP_REG register - * NA - */ -#define CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b4) -/** CORE1_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP 0x0000003FU -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_M (CORE1_CORE1_PSRAM_MSPI_INT_MAP_V << CORE1_CORE1_PSRAM_MSPI_INT_MAP_S) -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PSRAM_MSPI_INT_MAP_S 0 - -/** CORE1_HP_SYSREG_INT_MAP_REG register - * NA - */ -#define CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1b8) -/** CORE1_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_SYSREG_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_SYSREG_INT_MAP_M (CORE1_CORE1_HP_SYSREG_INT_MAP_V << CORE1_CORE1_HP_SYSREG_INT_MAP_S) -#define CORE1_CORE1_HP_SYSREG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_SYSREG_INT_MAP_S 0 - -/** CORE1_PCNT_INT_MAP_REG register - * NA - */ -#define CORE1_PCNT_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1bc) -/** CORE1_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_PCNT_INT_MAP 0x0000003FU -#define CORE1_CORE1_PCNT_INT_MAP_M (CORE1_CORE1_PCNT_INT_MAP_V << CORE1_CORE1_PCNT_INT_MAP_S) -#define CORE1_CORE1_PCNT_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_PCNT_INT_MAP_S 0 - -/** CORE1_HP_PAU_INT_MAP_REG register - * NA - */ -#define CORE1_HP_PAU_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c0) -/** CORE1_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_PAU_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_PAU_INT_MAP_M (CORE1_CORE1_HP_PAU_INT_MAP_V << CORE1_CORE1_HP_PAU_INT_MAP_S) -#define CORE1_CORE1_HP_PAU_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_PAU_INT_MAP_S 0 - -/** CORE1_HP_PARLIO_RX_INT_MAP_REG register - * NA - */ -#define CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c4) -/** CORE1_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_M (CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S) -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S 0 - -/** CORE1_HP_PARLIO_TX_INT_MAP_REG register - * NA - */ -#define CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1c8) -/** CORE1_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_M (CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S) -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1cc) -/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d0) -/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d4) -/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1d8) -/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1dc) -/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e0) -/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e4) -/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1e8) -/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1ec) -/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f0) -/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S 0 - -/** CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register - * NA - */ -#define CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f4) -/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S) -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S 0 - -/** CORE1_H264_REG_INT_MAP_REG register - * NA - */ -#define CORE1_H264_REG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1f8) -/** CORE1_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_H264_REG_INT_MAP 0x0000003FU -#define CORE1_CORE1_H264_REG_INT_MAP_M (CORE1_CORE1_H264_REG_INT_MAP_V << CORE1_CORE1_H264_REG_INT_MAP_S) -#define CORE1_CORE1_H264_REG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_H264_REG_INT_MAP_S 0 - -/** CORE1_ASSIST_DEBUG_INT_MAP_REG register - * NA - */ -#define CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_CORE1_BASE + 0x1fc) -/** CORE1_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; - * NA - */ -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP 0x0000003FU -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_M (CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V << CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S) -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V 0x0000003FU -#define CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S 0 - -/** CORE1_INTR_STATUS_REG_0_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_0_REG (DR_REG_CORE1_BASE + 0x200) -/** CORE1_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_0 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_0_M (CORE1_CORE1_INTR_STATUS_0_V << CORE1_CORE1_INTR_STATUS_0_S) -#define CORE1_CORE1_INTR_STATUS_0_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_0_S 0 - -/** CORE1_INTR_STATUS_REG_1_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_1_REG (DR_REG_CORE1_BASE + 0x204) -/** CORE1_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_1 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_1_M (CORE1_CORE1_INTR_STATUS_1_V << CORE1_CORE1_INTR_STATUS_1_S) -#define CORE1_CORE1_INTR_STATUS_1_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_1_S 0 - -/** CORE1_INTR_STATUS_REG_2_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_2_REG (DR_REG_CORE1_BASE + 0x208) -/** CORE1_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_2 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_2_M (CORE1_CORE1_INTR_STATUS_2_V << CORE1_CORE1_INTR_STATUS_2_S) -#define CORE1_CORE1_INTR_STATUS_2_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_2_S 0 - -/** CORE1_INTR_STATUS_REG_3_REG register - * NA - */ -#define CORE1_INTR_STATUS_REG_3_REG (DR_REG_CORE1_BASE + 0x20c) -/** CORE1_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ -#define CORE1_CORE1_INTR_STATUS_3 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_3_M (CORE1_CORE1_INTR_STATUS_3_V << CORE1_CORE1_INTR_STATUS_3_S) -#define CORE1_CORE1_INTR_STATUS_3_V 0xFFFFFFFFU -#define CORE1_CORE1_INTR_STATUS_3_S 0 - -/** CORE1_CLOCK_GATE_REG register - * NA - */ -#define CORE1_CLOCK_GATE_REG (DR_REG_CORE1_BASE + 0x210) -/** CORE1_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * NA - */ -#define CORE1_CORE1_REG_CLK_EN (BIT(0)) -#define CORE1_CORE1_REG_CLK_EN_M (CORE1_CORE1_REG_CLK_EN_V << CORE1_CORE1_REG_CLK_EN_S) -#define CORE1_CORE1_REG_CLK_EN_V 0x00000001U -#define CORE1_CORE1_REG_CLK_EN_S 0 - -/** CORE1_INTERRUPT_REG_DATE_REG register - * NA - */ -#define CORE1_INTERRUPT_REG_DATE_REG (DR_REG_CORE1_BASE + 0x3fc) -/** CORE1_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ -#define CORE1_CORE1_INTERRUPT_REG_DATE 0x0FFFFFFFU -#define CORE1_CORE1_INTERRUPT_REG_DATE_M (CORE1_CORE1_INTERRUPT_REG_DATE_V << CORE1_CORE1_INTERRUPT_REG_DATE_S) -#define CORE1_CORE1_INTERRUPT_REG_DATE_V 0x0FFFFFFFU -#define CORE1_CORE1_INTERRUPT_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/core1_interrupt_struct.h b/components/soc/esp32p4/include/soc/core1_interrupt_struct.h deleted file mode 100644 index 38dbda26b3..0000000000 --- a/components/soc/esp32p4/include/soc/core1_interrupt_struct.h +++ /dev/null @@ -1,2298 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: CORE1 LP RTC INT MAP REG */ -/** Type of lp_rtc_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_rtc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_rtc_int_map_reg_t; - - -/** Group: CORE1 LP WDT INT MAP REG */ -/** Type of lp_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_wdt_int_map_reg_t; - - -/** Group: CORE1 LP TIMER REG 0 INT MAP REG */ -/** Type of lp_timer_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_timer_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_timer_reg_0_int_map_reg_t; - - -/** Group: CORE1 LP TIMER REG 1 INT MAP REG */ -/** Type of lp_timer_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_timer_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_timer_reg_1_int_map_reg_t; - - -/** Group: CORE1 MB HP INT MAP REG */ -/** Type of mb_hp_int_map register - * NA - */ -typedef union { - struct { - /** core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_mb_hp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_mb_hp_int_map_reg_t; - - -/** Group: CORE1 MB LP INT MAP REG */ -/** Type of mb_lp_int_map register - * NA - */ -typedef union { - struct { - /** core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_mb_lp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_mb_lp_int_map_reg_t; - - -/** Group: CORE1 PMU REG 0 INT MAP REG */ -/** Type of pmu_reg_0_int_map register - * NA - */ -typedef union { - struct { - /** core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pmu_reg_0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pmu_reg_0_int_map_reg_t; - - -/** Group: CORE1 PMU REG 1 INT MAP REG */ -/** Type of pmu_reg_1_int_map register - * NA - */ -typedef union { - struct { - /** core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pmu_reg_1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pmu_reg_1_int_map_reg_t; - - -/** Group: CORE1 LP ANAPERI INT MAP REG */ -/** Type of lp_anaperi_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_anaperi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_anaperi_int_map_reg_t; - - -/** Group: CORE1 LP ADC INT MAP REG */ -/** Type of lp_adc_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_adc_int_map_reg_t; - - -/** Group: CORE1 LP GPIO INT MAP REG */ -/** Type of lp_gpio_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_gpio_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_gpio_int_map_reg_t; - - -/** Group: CORE1 LP I2C INT MAP REG */ -/** Type of lp_i2c_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_i2c_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_i2c_int_map_reg_t; - - -/** Group: CORE1 LP I2S INT MAP REG */ -/** Type of lp_i2s_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_i2s_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_i2s_int_map_reg_t; - - -/** Group: CORE1 LP SPI INT MAP REG */ -/** Type of lp_spi_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_spi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_spi_int_map_reg_t; - - -/** Group: CORE1 LP TOUCH INT MAP REG */ -/** Type of lp_touch_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_touch_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_touch_int_map_reg_t; - - -/** Group: CORE1 LP TSENS INT MAP REG */ -/** Type of lp_tsens_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_tsens_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_tsens_int_map_reg_t; - - -/** Group: CORE1 LP UART INT MAP REG */ -/** Type of lp_uart_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_uart_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_uart_int_map_reg_t; - - -/** Group: CORE1 LP EFUSE INT MAP REG */ -/** Type of lp_efuse_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_efuse_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_efuse_int_map_reg_t; - - -/** Group: CORE1 LP SW INT MAP REG */ -/** Type of lp_sw_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_sw_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_sw_int_map_reg_t; - - -/** Group: CORE1 LP SYSREG INT MAP REG */ -/** Type of lp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_sysreg_int_map_reg_t; - - -/** Group: CORE1 LP HUK INT MAP REG */ -/** Type of lp_huk_int_map register - * NA - */ -typedef union { - struct { - /** core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lp_huk_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lp_huk_int_map_reg_t; - - -/** Group: CORE1 SYS ICM INT MAP REG */ -/** Type of sys_icm_int_map register - * NA - */ -typedef union { - struct { - /** core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sys_icm_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sys_icm_int_map_reg_t; - - -/** Group: CORE1 USB DEVICE INT MAP REG */ -/** Type of usb_device_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_device_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_device_int_map_reg_t; - - -/** Group: CORE1 SDIO HOST INT MAP REG */ -/** Type of sdio_host_int_map register - * NA - */ -typedef union { - struct { - /** core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sdio_host_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sdio_host_int_map_reg_t; - - -/** Group: CORE1 GDMA INT MAP REG */ -/** Type of gdma_int_map register - * NA - */ -typedef union { - struct { - /** core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gdma_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gdma_int_map_reg_t; - - -/** Group: CORE1 SPI2 INT MAP REG */ -/** Type of spi2_int_map register - * NA - */ -typedef union { - struct { - /** core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_spi2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_spi2_int_map_reg_t; - - -/** Group: CORE1 SPI3 INT MAP REG */ -/** Type of spi3_int_map register - * NA - */ -typedef union { - struct { - /** core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_spi3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_spi3_int_map_reg_t; - - -/** Group: CORE1 I2S0 INT MAP REG */ -/** Type of i2s0_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2s0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2s0_int_map_reg_t; - - -/** Group: CORE1 I2S1 INT MAP REG */ -/** Type of i2s1_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2s1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2s1_int_map_reg_t; - - -/** Group: CORE1 I2S2 INT MAP REG */ -/** Type of i2s2_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2s2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2s2_int_map_reg_t; - - -/** Group: CORE1 UHCI0 INT MAP REG */ -/** Type of uhci0_int_map register - * NA - */ -typedef union { - struct { - /** core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uhci0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uhci0_int_map_reg_t; - - -/** Group: CORE1 UART0 INT MAP REG */ -/** Type of uart0_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart0_int_map_reg_t; - - -/** Group: CORE1 UART1 INT MAP REG */ -/** Type of uart1_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart1_int_map_reg_t; - - -/** Group: CORE1 UART2 INT MAP REG */ -/** Type of uart2_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart2_int_map_reg_t; - - -/** Group: CORE1 UART3 INT MAP REG */ -/** Type of uart3_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart3_int_map_reg_t; - - -/** Group: CORE1 UART4 INT MAP REG */ -/** Type of uart4_int_map register - * NA - */ -typedef union { - struct { - /** core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_uart4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_uart4_int_map_reg_t; - - -/** Group: CORE1 LCD CAM INT MAP REG */ -/** Type of lcd_cam_int_map register - * NA - */ -typedef union { - struct { - /** core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lcd_cam_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lcd_cam_int_map_reg_t; - - -/** Group: CORE1 ADC INT MAP REG */ -/** Type of adc_int_map register - * NA - */ -typedef union { - struct { - /** core1_adc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_adc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_adc_int_map_reg_t; - - -/** Group: CORE1 PWM0 INT MAP REG */ -/** Type of pwm0_int_map register - * NA - */ -typedef union { - struct { - /** core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pwm0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pwm0_int_map_reg_t; - - -/** Group: CORE1 PWM1 INT MAP REG */ -/** Type of pwm1_int_map register - * NA - */ -typedef union { - struct { - /** core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pwm1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pwm1_int_map_reg_t; - - -/** Group: CORE1 CAN0 INT MAP REG */ -/** Type of can0_int_map register - * NA - */ -typedef union { - struct { - /** core1_can0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_can0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_can0_int_map_reg_t; - - -/** Group: CORE1 CAN1 INT MAP REG */ -/** Type of can1_int_map register - * NA - */ -typedef union { - struct { - /** core1_can1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_can1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_can1_int_map_reg_t; - - -/** Group: CORE1 CAN2 INT MAP REG */ -/** Type of can2_int_map register - * NA - */ -typedef union { - struct { - /** core1_can2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_can2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_can2_int_map_reg_t; - - -/** Group: CORE1 RMT INT MAP REG */ -/** Type of rmt_int_map register - * NA - */ -typedef union { - struct { - /** core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_rmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_rmt_int_map_reg_t; - - -/** Group: CORE1 I2C0 INT MAP REG */ -/** Type of i2c0_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2c0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2c0_int_map_reg_t; - - -/** Group: CORE1 I2C1 INT MAP REG */ -/** Type of i2c1_int_map register - * NA - */ -typedef union { - struct { - /** core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i2c1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i2c1_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP0 T0 INT MAP REG */ -/** Type of timergrp0_t0_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp0_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp0_t0_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP0 T1 INT MAP REG */ -/** Type of timergrp0_t1_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp0_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp0_t1_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP0 WDT INT MAP REG */ -/** Type of timergrp0_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp0_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp0_wdt_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP1 T0 INT MAP REG */ -/** Type of timergrp1_t0_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp1_t0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp1_t0_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP1 T1 INT MAP REG */ -/** Type of timergrp1_t1_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp1_t1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp1_t1_int_map_reg_t; - - -/** Group: CORE1 TIMERGRP1 WDT INT MAP REG */ -/** Type of timergrp1_wdt_int_map register - * NA - */ -typedef union { - struct { - /** core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_timergrp1_wdt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_timergrp1_wdt_int_map_reg_t; - - -/** Group: CORE1 LEDC INT MAP REG */ -/** Type of ledc_int_map register - * NA - */ -typedef union { - struct { - /** core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ledc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ledc_int_map_reg_t; - - -/** Group: CORE1 SYSTIMER TARGET0 INT MAP REG */ -/** Type of systimer_target0_int_map register - * NA - */ -typedef union { - struct { - /** core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_systimer_target0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_systimer_target0_int_map_reg_t; - - -/** Group: CORE1 SYSTIMER TARGET1 INT MAP REG */ -/** Type of systimer_target1_int_map register - * NA - */ -typedef union { - struct { - /** core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_systimer_target1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_systimer_target1_int_map_reg_t; - - -/** Group: CORE1 SYSTIMER TARGET2 INT MAP REG */ -/** Type of systimer_target2_int_map register - * NA - */ -typedef union { - struct { - /** core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_systimer_target2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_systimer_target2_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA IN CH0 INT MAP REG */ -/** Type of ahb_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA IN CH1 INT MAP REG */ -/** Type of ahb_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA IN CH2 INT MAP REG */ -/** Type of ahb_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA OUT CH0 INT MAP REG */ -/** Type of ahb_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA OUT CH1 INT MAP REG */ -/** Type of ahb_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE1 AHB PDMA OUT CH2 INT MAP REG */ -/** Type of ahb_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ahb_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ahb_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA IN CH0 INT MAP REG */ -/** Type of axi_pdma_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_in_ch0_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA IN CH1 INT MAP REG */ -/** Type of axi_pdma_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_in_ch1_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA IN CH2 INT MAP REG */ -/** Type of axi_pdma_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_in_ch2_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA OUT CH0 INT MAP REG */ -/** Type of axi_pdma_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_out_ch0_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA OUT CH1 INT MAP REG */ -/** Type of axi_pdma_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_out_ch1_int_map_reg_t; - - -/** Group: CORE1 AXI PDMA OUT CH2 INT MAP REG */ -/** Type of axi_pdma_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_axi_pdma_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_axi_pdma_out_ch2_int_map_reg_t; - - -/** Group: CORE1 RSA INT MAP REG */ -/** Type of rsa_int_map register - * NA - */ -typedef union { - struct { - /** core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_rsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_rsa_int_map_reg_t; - - -/** Group: CORE1 AES INT MAP REG */ -/** Type of aes_int_map register - * NA - */ -typedef union { - struct { - /** core1_aes_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_aes_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_aes_int_map_reg_t; - - -/** Group: CORE1 SHA INT MAP REG */ -/** Type of sha_int_map register - * NA - */ -typedef union { - struct { - /** core1_sha_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sha_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sha_int_map_reg_t; - - -/** Group: CORE1 ECC INT MAP REG */ -/** Type of ecc_int_map register - * NA - */ -typedef union { - struct { - /** core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ecc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ecc_int_map_reg_t; - - -/** Group: CORE1 ECDSA INT MAP REG */ -/** Type of ecdsa_int_map register - * NA - */ -typedef union { - struct { - /** core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ecdsa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ecdsa_int_map_reg_t; - - -/** Group: CORE1 KM INT MAP REG */ -/** Type of km_int_map register - * NA - */ -typedef union { - struct { - /** core1_km_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_km_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_km_int_map_reg_t; - - -/** Group: CORE1 GPIO INT0 MAP REG */ -/** Type of gpio_int0_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int0_map_reg_t; - - -/** Group: CORE1 GPIO INT1 MAP REG */ -/** Type of gpio_int1_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int1_map_reg_t; - - -/** Group: CORE1 GPIO INT2 MAP REG */ -/** Type of gpio_int2_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int2_map_reg_t; - - -/** Group: CORE1 GPIO INT3 MAP REG */ -/** Type of gpio_int3_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_int3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_int3_map_reg_t; - - -/** Group: CORE1 GPIO PAD COMP INT MAP REG */ -/** Type of gpio_pad_comp_int_map register - * NA - */ -typedef union { - struct { - /** core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gpio_pad_comp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gpio_pad_comp_int_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 0 MAP REG */ -/** Type of cpu_int_from_cpu_0_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_0_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_0_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 1 MAP REG */ -/** Type of cpu_int_from_cpu_1_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_1_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_1_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 2 MAP REG */ -/** Type of cpu_int_from_cpu_2_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_2_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_2_map_reg_t; - - -/** Group: CORE1 CPU INT FROM CPU 3 MAP REG */ -/** Type of cpu_int_from_cpu_3_map register - * NA - */ -typedef union { - struct { - /** core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cpu_int_from_cpu_3_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cpu_int_from_cpu_3_map_reg_t; - - -/** Group: CORE1 CACHE INT MAP REG */ -/** Type of cache_int_map register - * NA - */ -typedef union { - struct { - /** core1_cache_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_cache_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_cache_int_map_reg_t; - - -/** Group: CORE1 FLASH MSPI INT MAP REG */ -/** Type of flash_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_flash_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_flash_mspi_int_map_reg_t; - - -/** Group: CORE1 CSI BRIDGE INT MAP REG */ -/** Type of csi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_csi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_csi_bridge_int_map_reg_t; - - -/** Group: CORE1 DSI BRIDGE INT MAP REG */ -/** Type of dsi_bridge_int_map register - * NA - */ -typedef union { - struct { - /** core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dsi_bridge_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dsi_bridge_int_map_reg_t; - - -/** Group: CORE1 CSI INT MAP REG */ -/** Type of csi_int_map register - * NA - */ -typedef union { - struct { - /** core1_csi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_csi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_csi_int_map_reg_t; - - -/** Group: CORE1 DSI INT MAP REG */ -/** Type of dsi_int_map register - * NA - */ -typedef union { - struct { - /** core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dsi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dsi_int_map_reg_t; - - -/** Group: CORE1 GMII PHY INT MAP REG */ -/** Type of gmii_phy_int_map register - * NA - */ -typedef union { - struct { - /** core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_gmii_phy_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_gmii_phy_int_map_reg_t; - - -/** Group: CORE1 LPI INT MAP REG */ -/** Type of lpi_int_map register - * NA - */ -typedef union { - struct { - /** core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_lpi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_lpi_int_map_reg_t; - - -/** Group: CORE1 PMT INT MAP REG */ -/** Type of pmt_int_map register - * NA - */ -typedef union { - struct { - /** core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pmt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pmt_int_map_reg_t; - - -/** Group: CORE1 SBD INT MAP REG */ -/** Type of sbd_int_map register - * NA - */ -typedef union { - struct { - /** core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_sbd_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_sbd_int_map_reg_t; - - -/** Group: CORE1 USB OTG INT MAP REG */ -/** Type of usb_otg_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_otg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_otg_int_map_reg_t; - - -/** Group: CORE1 USB OTG ENDP MULTI PROC INT MAP REG */ -/** Type of usb_otg_endp_multi_proc_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_otg_endp_multi_proc_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_otg_endp_multi_proc_int_map_reg_t; - - -/** Group: CORE1 JPEG INT MAP REG */ -/** Type of jpeg_int_map register - * NA - */ -typedef union { - struct { - /** core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_jpeg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_jpeg_int_map_reg_t; - - -/** Group: CORE1 PPA INT MAP REG */ -/** Type of ppa_int_map register - * NA - */ -typedef union { - struct { - /** core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_ppa_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_ppa_int_map_reg_t; - - -/** Group: CORE1 CORE0 TRACE INT MAP REG */ -/** Type of core0_trace_int_map register - * NA - */ -typedef union { - struct { - /** core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_core0_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_core0_trace_int_map_reg_t; - - -/** Group: CORE1 CORE1 TRACE INT MAP REG */ -/** Type of core1_trace_int_map register - * NA - */ -typedef union { - struct { - /** core1_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_core1_trace_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_core1_trace_int_map_reg_t; - - -/** Group: CORE1 HP CORE CTRL INT MAP REG */ -/** Type of hp_core_ctrl_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_core_ctrl_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_core_ctrl_int_map_reg_t; - - -/** Group: CORE1 ISP INT MAP REG */ -/** Type of isp_int_map register - * NA - */ -typedef union { - struct { - /** core1_isp_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_isp_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_isp_int_map_reg_t; - - -/** Group: CORE1 I3C MST INT MAP REG */ -/** Type of i3c_mst_int_map register - * NA - */ -typedef union { - struct { - /** core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i3c_mst_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i3c_mst_int_map_reg_t; - - -/** Group: CORE1 I3C SLV INT MAP REG */ -/** Type of i3c_slv_int_map register - * NA - */ -typedef union { - struct { - /** core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_i3c_slv_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_i3c_slv_int_map_reg_t; - - -/** Group: CORE1 USB OTG11 INT MAP REG */ -/** Type of usb_otg11_int_map register - * NA - */ -typedef union { - struct { - /** core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_usb_otg11_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_usb_otg11_int_map_reg_t; - - -/** Group: CORE1 DMA2D IN CH0 INT MAP REG */ -/** Type of dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE1 DMA2D IN CH1 INT MAP REG */ -/** Type of dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE1 DMA2D OUT CH0 INT MAP REG */ -/** Type of dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE1 DMA2D OUT CH1 INT MAP REG */ -/** Type of dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE1 DMA2D OUT CH2 INT MAP REG */ -/** Type of dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE1 PSRAM MSPI INT MAP REG */ -/** Type of psram_mspi_int_map register - * NA - */ -typedef union { - struct { - /** core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_psram_mspi_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_psram_mspi_int_map_reg_t; - - -/** Group: CORE1 HP SYSREG INT MAP REG */ -/** Type of hp_sysreg_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_sysreg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_sysreg_int_map_reg_t; - - -/** Group: CORE1 PCNT INT MAP REG */ -/** Type of pcnt_int_map register - * NA - */ -typedef union { - struct { - /** core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_pcnt_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_pcnt_int_map_reg_t; - - -/** Group: CORE1 HP PAU INT MAP REG */ -/** Type of hp_pau_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_pau_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_pau_int_map_reg_t; - - -/** Group: CORE1 HP PARLIO RX INT MAP REG */ -/** Type of hp_parlio_rx_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_parlio_rx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_parlio_rx_int_map_reg_t; - - -/** Group: CORE1 HP PARLIO TX INT MAP REG */ -/** Type of hp_parlio_tx_int_map register - * NA - */ -typedef union { - struct { - /** core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_hp_parlio_tx_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_hp_parlio_tx_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH0 INT MAP REG */ -/** Type of h264_dma2d_out_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch0_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH1 INT MAP REG */ -/** Type of h264_dma2d_out_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch1_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH2 INT MAP REG */ -/** Type of h264_dma2d_out_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch2_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH3 INT MAP REG */ -/** Type of h264_dma2d_out_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch3_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D OUT CH4 INT MAP REG */ -/** Type of h264_dma2d_out_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_out_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_out_ch4_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH0 INT MAP REG */ -/** Type of h264_dma2d_in_ch0_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch0_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch0_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH1 INT MAP REG */ -/** Type of h264_dma2d_in_ch1_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch1_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch1_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH2 INT MAP REG */ -/** Type of h264_dma2d_in_ch2_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch2_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch2_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH3 INT MAP REG */ -/** Type of h264_dma2d_in_ch3_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch3_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch3_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH4 INT MAP REG */ -/** Type of h264_dma2d_in_ch4_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch4_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch4_int_map_reg_t; - - -/** Group: CORE1 H264 DMA2D IN CH5 INT MAP REG */ -/** Type of h264_dma2d_in_ch5_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_dma2d_in_ch5_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_dma2d_in_ch5_int_map_reg_t; - - -/** Group: CORE1 H264 REG INT MAP REG */ -/** Type of h264_reg_int_map register - * NA - */ -typedef union { - struct { - /** core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_h264_reg_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_h264_reg_int_map_reg_t; - - -/** Group: CORE1 ASSIST DEBUG INT MAP REG */ -/** Type of assist_debug_int_map register - * NA - */ -typedef union { - struct { - /** core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t core1_assist_debug_int_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} core1_assist_debug_int_map_reg_t; - - -/** Group: CORE1 INTR STATUS REG 0 REG */ -/** Type of intr_status_reg_0 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_0 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_0:32; - }; - uint32_t val; -} core1_intr_status_reg_0_reg_t; - - -/** Group: CORE1 INTR STATUS REG 1 REG */ -/** Type of intr_status_reg_1 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_1 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_1:32; - }; - uint32_t val; -} core1_intr_status_reg_1_reg_t; - - -/** Group: CORE1 INTR STATUS REG 2 REG */ -/** Type of intr_status_reg_2 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_2 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_2:32; - }; - uint32_t val; -} core1_intr_status_reg_2_reg_t; - - -/** Group: CORE1 INTR STATUS REG 3 REG */ -/** Type of intr_status_reg_3 register - * NA - */ -typedef union { - struct { - /** core1_intr_status_3 : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t core1_intr_status_3:32; - }; - uint32_t val; -} core1_intr_status_reg_3_reg_t; - - -/** Group: CORE1 CLOCK GATE REG */ -/** Type of clock_gate register - * NA - */ -typedef union { - struct { - /** core1_reg_clk_en : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t core1_reg_clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} core1_clock_gate_reg_t; - - -/** Group: CORE1 INTERRUPT REG DATE REG */ -/** Type of interrupt_reg_date register - * NA - */ -typedef union { - struct { - /** core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; - * NA - */ - uint32_t core1_interrupt_reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} core1_interrupt_reg_date_reg_t; - - -typedef struct { - volatile core1_lp_rtc_int_map_reg_t lp_rtc_int_map; - volatile core1_lp_wdt_int_map_reg_t lp_wdt_int_map; - volatile core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; - volatile core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; - volatile core1_mb_hp_int_map_reg_t mb_hp_int_map; - volatile core1_mb_lp_int_map_reg_t mb_lp_int_map; - volatile core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; - volatile core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; - volatile core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map; - volatile core1_lp_adc_int_map_reg_t lp_adc_int_map; - volatile core1_lp_gpio_int_map_reg_t lp_gpio_int_map; - volatile core1_lp_i2c_int_map_reg_t lp_i2c_int_map; - volatile core1_lp_i2s_int_map_reg_t lp_i2s_int_map; - volatile core1_lp_spi_int_map_reg_t lp_spi_int_map; - volatile core1_lp_touch_int_map_reg_t lp_touch_int_map; - volatile core1_lp_tsens_int_map_reg_t lp_tsens_int_map; - volatile core1_lp_uart_int_map_reg_t lp_uart_int_map; - volatile core1_lp_efuse_int_map_reg_t lp_efuse_int_map; - volatile core1_lp_sw_int_map_reg_t lp_sw_int_map; - volatile core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map; - volatile core1_lp_huk_int_map_reg_t lp_huk_int_map; - volatile core1_sys_icm_int_map_reg_t sys_icm_int_map; - volatile core1_usb_device_int_map_reg_t usb_device_int_map; - volatile core1_sdio_host_int_map_reg_t sdio_host_int_map; - volatile core1_gdma_int_map_reg_t gdma_int_map; - volatile core1_spi2_int_map_reg_t spi2_int_map; - volatile core1_spi3_int_map_reg_t spi3_int_map; - volatile core1_i2s0_int_map_reg_t i2s0_int_map; - volatile core1_i2s1_int_map_reg_t i2s1_int_map; - volatile core1_i2s2_int_map_reg_t i2s2_int_map; - volatile core1_uhci0_int_map_reg_t uhci0_int_map; - volatile core1_uart0_int_map_reg_t uart0_int_map; - volatile core1_uart1_int_map_reg_t uart1_int_map; - volatile core1_uart2_int_map_reg_t uart2_int_map; - volatile core1_uart3_int_map_reg_t uart3_int_map; - volatile core1_uart4_int_map_reg_t uart4_int_map; - volatile core1_lcd_cam_int_map_reg_t lcd_cam_int_map; - volatile core1_adc_int_map_reg_t adc_int_map; - volatile core1_pwm0_int_map_reg_t pwm0_int_map; - volatile core1_pwm1_int_map_reg_t pwm1_int_map; - volatile core1_can0_int_map_reg_t can0_int_map; - volatile core1_can1_int_map_reg_t can1_int_map; - volatile core1_can2_int_map_reg_t can2_int_map; - volatile core1_rmt_int_map_reg_t rmt_int_map; - volatile core1_i2c0_int_map_reg_t i2c0_int_map; - volatile core1_i2c1_int_map_reg_t i2c1_int_map; - volatile core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; - volatile core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; - volatile core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; - volatile core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; - volatile core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; - volatile core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; - volatile core1_ledc_int_map_reg_t ledc_int_map; - volatile core1_systimer_target0_int_map_reg_t systimer_target0_int_map; - volatile core1_systimer_target1_int_map_reg_t systimer_target1_int_map; - volatile core1_systimer_target2_int_map_reg_t systimer_target2_int_map; - volatile core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; - volatile core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; - volatile core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; - volatile core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; - volatile core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; - volatile core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; - volatile core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; - volatile core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; - volatile core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; - volatile core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; - volatile core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; - volatile core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; - volatile core1_rsa_int_map_reg_t rsa_int_map; - volatile core1_aes_int_map_reg_t aes_int_map; - volatile core1_sha_int_map_reg_t sha_int_map; - volatile core1_ecc_int_map_reg_t ecc_int_map; - volatile core1_ecdsa_int_map_reg_t ecdsa_int_map; - volatile core1_km_int_map_reg_t km_int_map; - volatile core1_gpio_int0_map_reg_t gpio_int0_map; - volatile core1_gpio_int1_map_reg_t gpio_int1_map; - volatile core1_gpio_int2_map_reg_t gpio_int2_map; - volatile core1_gpio_int3_map_reg_t gpio_int3_map; - volatile core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; - volatile core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; - volatile core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; - volatile core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; - volatile core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; - volatile core1_cache_int_map_reg_t cache_int_map; - volatile core1_flash_mspi_int_map_reg_t flash_mspi_int_map; - volatile core1_csi_bridge_int_map_reg_t csi_bridge_int_map; - volatile core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map; - volatile core1_csi_int_map_reg_t csi_int_map; - volatile core1_dsi_int_map_reg_t dsi_int_map; - volatile core1_gmii_phy_int_map_reg_t gmii_phy_int_map; - volatile core1_lpi_int_map_reg_t lpi_int_map; - volatile core1_pmt_int_map_reg_t pmt_int_map; - volatile core1_sbd_int_map_reg_t sbd_int_map; - volatile core1_usb_otg_int_map_reg_t usb_otg_int_map; - volatile core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; - volatile core1_jpeg_int_map_reg_t jpeg_int_map; - volatile core1_ppa_int_map_reg_t ppa_int_map; - volatile core1_core0_trace_int_map_reg_t core0_trace_int_map; - volatile core1_core1_trace_int_map_reg_t core1_trace_int_map; - volatile core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; - volatile core1_isp_int_map_reg_t isp_int_map; - volatile core1_i3c_mst_int_map_reg_t i3c_mst_int_map; - volatile core1_i3c_slv_int_map_reg_t i3c_slv_int_map; - volatile core1_usb_otg11_int_map_reg_t usb_otg11_int_map; - volatile core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; - volatile core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; - volatile core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; - volatile core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; - volatile core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; - volatile core1_psram_mspi_int_map_reg_t psram_mspi_int_map; - volatile core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map; - volatile core1_pcnt_int_map_reg_t pcnt_int_map; - volatile core1_hp_pau_int_map_reg_t hp_pau_int_map; - volatile core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; - volatile core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; - volatile core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; - volatile core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; - volatile core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; - volatile core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; - volatile core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; - volatile core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; - volatile core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; - volatile core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; - volatile core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; - volatile core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; - volatile core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; - volatile core1_h264_reg_int_map_reg_t h264_reg_int_map; - volatile core1_assist_debug_int_map_reg_t assist_debug_int_map; - volatile core1_intr_status_reg_0_reg_t intr_status_reg_0; - volatile core1_intr_status_reg_1_reg_t intr_status_reg_1; - volatile core1_intr_status_reg_2_reg_t intr_status_reg_2; - volatile core1_intr_status_reg_3_reg_t intr_status_reg_3; - volatile core1_clock_gate_reg_t clock_gate; - uint32_t reserved_214[122]; - volatile core1_interrupt_reg_date_reg_t interrupt_reg_date; -} core1_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(core1_dev_t) == 0x400, "Invalid size of core1_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/extmem_reg.h b/components/soc/esp32p4/include/soc/extmem_reg.h deleted file mode 100644 index a9cb693586..0000000000 --- a/components/soc/esp32p4/include/soc/extmem_reg.h +++ /dev/null @@ -1,871 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define EXTMEM_L1_CACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4) -/* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/ -#define EXTMEM_L1_CACHE_SHUT_DBUS (BIT(1)) -#define EXTMEM_L1_CACHE_SHUT_DBUS_M (BIT(1)) -#define EXTMEM_L1_CACHE_SHUT_DBUS_V 0x1 -#define EXTMEM_L1_CACHE_SHUT_DBUS_S 1 -/* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/ -#define EXTMEM_L1_CACHE_SHUT_IBUS (BIT(0)) -#define EXTMEM_L1_CACHE_SHUT_IBUS_M (BIT(0)) -#define EXTMEM_L1_CACHE_SHUT_IBUS_V 0x1 -#define EXTMEM_L1_CACHE_SHUT_IBUS_S 0 - -#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20) -/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/ -#define EXTMEM_L1_CACHE_WRAP (BIT(4)) -#define EXTMEM_L1_CACHE_WRAP_M (BIT(4)) -#define EXTMEM_L1_CACHE_WRAP_V 0x1 -#define EXTMEM_L1_CACHE_WRAP_S 4 - -#define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24) -/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ -/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/ -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18)) -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M (BIT(18)) -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V 0x1 -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S 18 -/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power -down.*/ -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17)) -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M (BIT(17)) -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V 0x1 -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S 17 -/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, -0: open clock gating..*/ -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16)) -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M (BIT(16)) -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V 0x1 -#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S 16 - -#define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) -/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ -/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u -p.*/ -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18)) -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M (BIT(18)) -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V 0x1 -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S 18 -/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power - down.*/ -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17)) -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M (BIT(17)) -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V 0x1 -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S 17 -/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to close clock gating of L1-Cache data memory. 1: close gating, - 0: open clock gating..*/ -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16)) -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M (BIT(16)) -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V 0x1 -#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S 16 - -#define EXTMEM_L1_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C) -/* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ -/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or -not. 0: not finished. 1: finished..*/ -#define EXTMEM_L1_CACHE_FREEZE_DONE (BIT(18)) -#define EXTMEM_L1_CACHE_FREEZE_DONE_M (BIT(18)) -#define EXTMEM_L1_CACHE_FREEZE_DONE_V 0x1 -#define EXTMEM_L1_CACHE_FREEZE_DONE_S 18 -/* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access - will not stuck. 1: a miss-access will stuck..*/ -#define EXTMEM_L1_CACHE_FREEZE_MODE (BIT(17)) -#define EXTMEM_L1_CACHE_FREEZE_MODE_M (BIT(17)) -#define EXTMEM_L1_CACHE_FREEZE_MODE_V 0x1 -#define EXTMEM_L1_CACHE_FREEZE_MODE_S 17 -/* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof -tware..*/ -#define EXTMEM_L1_CACHE_FREEZE_EN (BIT(16)) -#define EXTMEM_L1_CACHE_FREEZE_EN_M (BIT(16)) -#define EXTMEM_L1_CACHE_FREEZE_EN_V 0x1 -#define EXTMEM_L1_CACHE_FREEZE_EN_S 16 - -#define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30) -/* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, -1: enable..*/ -#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) -#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M (BIT(17)) -#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V 0x1 -#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S 17 -/* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1 -: enable..*/ -#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) -#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M (BIT(16)) -#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V 0x1 -#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S 16 - -#define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34) -/* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1 -: enable..*/ -#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) -#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M (BIT(17)) -#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V 0x1 -#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S 17 -/* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: - enable..*/ -#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) -#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M (BIT(16)) -#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V 0x1 -#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S 16 - -#define EXTMEM_L1_CACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78) -/* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/ -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M (BIT(1)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V 0x1 -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S 1 -/* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/ -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M (BIT(0)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V 0x1 -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S 0 - -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C) -/* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of the first section -of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0 -_SIZE_REG.*/ -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 - -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) -/* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of the second section - of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT -1_SIZE_REG.*/ -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 - -#define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) -/* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ -/*description: Those bits are used to configure the size of the second section of prelock on L1 --Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/ -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x3FFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 -/* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ -/*description: Those bits are used to configure the size of the first section of prelock on L1- -Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/ -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S)) -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x3FFF -#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 - -#define EXTMEM_L1_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) -/* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ -/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0: - not finished. 1: finished..*/ -#define EXTMEM_L1_CACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_L1_CACHE_LOCK_DONE_M (BIT(2)) -#define EXTMEM_L1_CACHE_LOCK_DONE_V 0x1 -#define EXTMEM_L1_CACHE_LOCK_DONE_S 2 -/* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable unlock operation. It will be cleared by hardware after - unlock operation done.*/ -#define EXTMEM_L1_CACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_L1_CACHE_UNLOCK_ENA_M (BIT(1)) -#define EXTMEM_L1_CACHE_UNLOCK_ENA_V 0x1 -#define EXTMEM_L1_CACHE_UNLOCK_ENA_S 1 -/* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable lock operation. It will be cleared by hardware after l -ock operation done.*/ -#define EXTMEM_L1_CACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_L1_CACHE_LOCK_ENA_M (BIT(0)) -#define EXTMEM_L1_CACHE_LOCK_ENA_V 0x1 -#define EXTMEM_L1_CACHE_LOCK_ENA_S 0 - -#define EXTMEM_L1_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C) -/* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: Those bits are used to indicate which caches in the two-level cache structure wi -ll apply this lock/unlock operation. [4]: L1-Cache.*/ -#define EXTMEM_L1_CACHE_LOCK_MAP 0x0000003F -#define EXTMEM_L1_CACHE_LOCK_MAP_M ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S)) -#define EXTMEM_L1_CACHE_LOCK_MAP_V 0x3F -#define EXTMEM_L1_CACHE_LOCK_MAP_S 0 - -#define EXTMEM_L1_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90) -/* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of the lock/unlock op -eration, which should be used together with CACHE_LOCK_SIZE_REG.*/ -#define EXTMEM_L1_CACHE_LOCK_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_LOCK_ADDR_M ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S)) -#define EXTMEM_L1_CACHE_LOCK_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_LOCK_ADDR_S 0 - -#define EXTMEM_L1_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94) -/* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Those bits are used to configure the size of the lock/unlock operation, which sh -ould be used together with CACHE_LOCK_ADDR_REG.*/ -#define EXTMEM_L1_CACHE_LOCK_SIZE 0x0000FFFF -#define EXTMEM_L1_CACHE_LOCK_SIZE_M ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S)) -#define EXTMEM_L1_CACHE_LOCK_SIZE_V 0xFFFF -#define EXTMEM_L1_CACHE_LOCK_SIZE_S 0 - -#define EXTMEM_L1_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98) -/* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback -, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/ -#define EXTMEM_L1_CACHE_SYNC_DONE (BIT(4)) -#define EXTMEM_L1_CACHE_SYNC_DONE_M (BIT(4)) -#define EXTMEM_L1_CACHE_SYNC_DONE_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_DONE_S 4 -/* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ -/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by -hardware after writeback-invalidate operation done. Note that this bit and the o -ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive -, that is, those bits can not be set to 1 at the same time..*/ -#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) -#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) -#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 -#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S 3 -/* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The bit is used to enable writeback operation. It will be cleared by hardware af -ter writeback operation done. Note that this bit and the other sync-bits (invali -date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, -those bits can not be set to 1 at the same time..*/ -#define EXTMEM_L1_CACHE_WRITEBACK_ENA (BIT(2)) -#define EXTMEM_L1_CACHE_WRITEBACK_ENA_M (BIT(2)) -#define EXTMEM_L1_CACHE_WRITEBACK_ENA_V 0x1 -#define EXTMEM_L1_CACHE_WRITEBACK_ENA_S 2 -/* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable clean operation. It will be cleared by hardware after -clean operation done. Note that this bit and the other sync-bits (invalidate_ena -, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos -e bits can not be set to 1 at the same time..*/ -#define EXTMEM_L1_CACHE_CLEAN_ENA (BIT(1)) -#define EXTMEM_L1_CACHE_CLEAN_ENA_M (BIT(1)) -#define EXTMEM_L1_CACHE_CLEAN_ENA_V 0x1 -#define EXTMEM_L1_CACHE_CLEAN_ENA_S 1 -/* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ -/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a -fter invalidate operation done. Note that this bit and the other sync-bits (clea -n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, - those bits can not be set to 1 at the same time..*/ -#define EXTMEM_L1_CACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_L1_CACHE_INVALIDATE_ENA_M (BIT(0)) -#define EXTMEM_L1_CACHE_INVALIDATE_ENA_V 0x1 -#define EXTMEM_L1_CACHE_INVALIDATE_ENA_S 0 - -#define EXTMEM_L1_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C) -/* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ -/*description: Those bits are used to indicate which caches in the two-level cache structure wi -ll apply the sync operation. [4]: L1-Cache.*/ -#define EXTMEM_L1_CACHE_SYNC_MAP 0x0000003F -#define EXTMEM_L1_CACHE_SYNC_MAP_M ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S)) -#define EXTMEM_L1_CACHE_SYNC_MAP_V 0x3F -#define EXTMEM_L1_CACHE_SYNC_MAP_S 0 - -#define EXTMEM_L1_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0) -/* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of the sync operation -, which should be used together with CACHE_SYNC_SIZE_REG.*/ -#define EXTMEM_L1_CACHE_SYNC_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_SYNC_ADDR_M ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S)) -#define EXTMEM_L1_CACHE_SYNC_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_SYNC_ADDR_S 0 - -#define EXTMEM_L1_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4) -/* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Those bits are used to configure the size of the sync operation, which should be - used together with CACHE_SYNC_ADDR_REG.*/ -#define EXTMEM_L1_CACHE_SYNC_SIZE 0x00FFFFFF -#define EXTMEM_L1_CACHE_SYNC_SIZE_M ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S)) -#define EXTMEM_L1_CACHE_SYNC_SIZE_V 0xFFFFFF -#define EXTMEM_L1_CACHE_SYNC_SIZE_S 0 - -#define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8) -/* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of l1 cache preload..*/ -#define EXTMEM_L1_CACHE_PRELOAD_RGID 0x0000000F -#define EXTMEM_L1_CACHE_PRELOAD_RGID_M ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S)) -#define EXTMEM_L1_CACHE_PRELOAD_RGID_V 0xF -#define EXTMEM_L1_CACHE_PRELOAD_RGID_S 3 -/* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1 -: descending..*/ -#define EXTMEM_L1_CACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_L1_CACHE_PRELOAD_ORDER_M (BIT(2)) -#define EXTMEM_L1_CACHE_PRELOAD_ORDER_V 0x1 -#define EXTMEM_L1_CACHE_PRELOAD_ORDER_S 2 -/* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ -/*description: The bit is used to indicate whether preload operation is finished or not. 0: not - finished. 1: finished..*/ -#define EXTMEM_L1_CACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_L1_CACHE_PRELOAD_DONE_M (BIT(1)) -#define EXTMEM_L1_CACHE_PRELOAD_DONE_V 0x1 -#define EXTMEM_L1_CACHE_PRELOAD_DONE_S 1 -/* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h -ardware automatically after preload operation is done..*/ -#define EXTMEM_L1_CACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_L1_CACHE_PRELOAD_ENA_M (BIT(0)) -#define EXTMEM_L1_CACHE_PRELOAD_ENA_V 0x1 -#define EXTMEM_L1_CACHE_PRELOAD_ENA_S 0 - -#define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC) -/* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of preload on L1-Cach -e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/ -#define EXTMEM_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_PRELOAD_ADDR_M ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S)) -#define EXTMEM_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_PRELOAD_ADDR_S 0 - -#define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0) -/* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: Those bits are used to configure the size of the first section of prelock on L1- -Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/ -#define EXTMEM_L1_CACHE_PRELOAD_SIZE 0x00003FFF -#define EXTMEM_L1_CACHE_PRELOAD_SIZE_M ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S)) -#define EXTMEM_L1_CACHE_PRELOAD_SIZE_V 0x3FFF -#define EXTMEM_L1_CACHE_PRELOAD_SIZE_S 0 - -#define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) -/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x1 -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 -/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x1 -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 -/* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0 -/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 -#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)) -#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 -#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 -/* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0: - ascending. 1: descending..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) -#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M (BIT(2)) -#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V 0x1 -#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S 2 -/* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ -/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o -r not. 0: not finished. 1: finished..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_DONE (BIT(1)) -#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M (BIT(1)) -#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V 0x1 -#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S 1 -/* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable and disable autoload operation on L1-Cache. 1: enable -, 0: disable..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_ENA (BIT(0)) -#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M (BIT(0)) -#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V 0x1 -#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S 0 - -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138) -/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of the first section -for autoload operation on L1-Cache. Note that it should be used together with L1 -_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 - -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C) -/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ -/*description: Those bits are used to configure the size of the first section for autoload oper -ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S -CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 - -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140) -/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of the second section - for autoload operation on L1-Cache. Note that it should be used together with L -1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 - -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144) -/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ -/*description: Those bits are used to configure the size of the second section for autoload ope -ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_ -SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)) -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF -#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 - -#define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) -/* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L -1-DCache due to bus1 accesses L1-DCache..*/ -#define EXTMEM_L1_DBUS_OVF_INT_ENA (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_ENA_M (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_ENA_V 0x1 -#define EXTMEM_L1_DBUS_OVF_INT_ENA_S 5 -/* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L -1-DCache due to bus0 accesses L1-DCache..*/ -#define EXTMEM_L1_IBUS_OVF_INT_ENA (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_ENA_M (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_ENA_V 0x1 -#define EXTMEM_L1_IBUS_OVF_INT_ENA_S 4 - -#define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) -/* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d -ue to bus1 accesses L1-DCache..*/ -#define EXTMEM_L1_DBUS_OVF_INT_CLR (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_CLR_M (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_CLR_V 0x1 -#define EXTMEM_L1_DBUS_OVF_INT_CLR_S 5 -/* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d -ue to bus0 accesses L1-DCache..*/ -#define EXTMEM_L1_IBUS_OVF_INT_CLR (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_CLR_M (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_CLR_V 0x1 -#define EXTMEM_L1_IBUS_OVF_INT_CLR_S 4 - -#define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160) -/* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach -e due to bus1 accesses L1-DCache..*/ -#define EXTMEM_L1_DBUS_OVF_INT_RAW (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_RAW_M (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_RAW_V 0x1 -#define EXTMEM_L1_DBUS_OVF_INT_RAW_S 5 -/* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach -e due to bus0 accesses L1-DCache..*/ -#define EXTMEM_L1_IBUS_OVF_INT_RAW (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_RAW_M (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_RAW_V 0x1 -#define EXTMEM_L1_IBUS_OVF_INT_RAW_S 4 - -#define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164) -/* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit indicates the interrupt status of one of counters overflow that occurs i -n L1-DCache due to bus1 accesses L1-DCache..*/ -#define EXTMEM_L1_DBUS_OVF_INT_ST (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_ST_M (BIT(5)) -#define EXTMEM_L1_DBUS_OVF_INT_ST_V 0x1 -#define EXTMEM_L1_DBUS_OVF_INT_ST_S 5 -/* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit indicates the interrupt status of one of counters overflow that occurs i -n L1-DCache due to bus0 accesses L1-DCache..*/ -#define EXTMEM_L1_IBUS_OVF_INT_ST (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_ST_M (BIT(4)) -#define EXTMEM_L1_IBUS_OVF_INT_ST_V 0x1 -#define EXTMEM_L1_IBUS_OVF_INT_ST_S 4 - -#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168) -/* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due -to cpu accesses L1-DCache..*/ -#define EXTMEM_L1_CACHE_FAIL_INT_ENA (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_ENA_M (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_ENA_V 0x1 -#define EXTMEM_L1_CACHE_FAIL_INT_ENA_S 4 - -#define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C) -/* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t -o cpu accesses L1-DCache..*/ -#define EXTMEM_L1_CACHE_FAIL_INT_CLR (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_CLR_M (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_CLR_V 0x1 -#define EXTMEM_L1_CACHE_FAIL_INT_CLR_S 4 - -#define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170) -/* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/ -#define EXTMEM_L1_CACHE_FAIL_INT_RAW (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_RAW_M (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_RAW_V 0x1 -#define EXTMEM_L1_CACHE_FAIL_INT_RAW_S 4 - -#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) -/* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d -ue to cpu accesses L1-DCache..*/ -#define EXTMEM_L1_CACHE_FAIL_INT_ST (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_ST_M (BIT(4)) -#define EXTMEM_L1_CACHE_FAIL_INT_ST_V 0x1 -#define EXTMEM_L1_CACHE_FAIL_INT_ST_S 4 - -#define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178) -/* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The bit is used to clear dbus1 counter in L1-DCache..*/ -#define EXTMEM_L1_DBUS_CNT_CLR (BIT(21)) -#define EXTMEM_L1_DBUS_CNT_CLR_M (BIT(21)) -#define EXTMEM_L1_DBUS_CNT_CLR_V 0x1 -#define EXTMEM_L1_DBUS_CNT_CLR_S 21 -/* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The bit is used to clear dbus0 counter in L1-DCache..*/ -#define EXTMEM_L1_IBUS_CNT_CLR (BIT(20)) -#define EXTMEM_L1_IBUS_CNT_CLR_M (BIT(20)) -#define EXTMEM_L1_IBUS_CNT_CLR_V 0x1 -#define EXTMEM_L1_IBUS_CNT_CLR_S 20 -/* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to enable dbus1 counter in L1-DCache..*/ -#define EXTMEM_L1_DBUS_CNT_ENA (BIT(5)) -#define EXTMEM_L1_DBUS_CNT_ENA_M (BIT(5)) -#define EXTMEM_L1_DBUS_CNT_ENA_V 0x1 -#define EXTMEM_L1_DBUS_CNT_ENA_S 5 -/* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable dbus0 counter in L1-DCache..*/ -#define EXTMEM_L1_IBUS_CNT_ENA (BIT(4)) -#define EXTMEM_L1_IBUS_CNT_ENA_M (BIT(4)) -#define EXTMEM_L1_IBUS_CNT_ENA_V 0x1 -#define EXTMEM_L1_IBUS_CNT_ENA_S 4 - -#define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC) -/* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of hits when bus0 accesses L1-Cache..*/ -#define EXTMEM_L1_IBUS_HIT_CNT 0xFFFFFFFF -#define EXTMEM_L1_IBUS_HIT_CNT_M ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S)) -#define EXTMEM_L1_IBUS_HIT_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_IBUS_HIT_CNT_S 0 - -#define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0) -/* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of missing when bus0 accesses L1-Cache..*/ -#define EXTMEM_L1_IBUS_MISS_CNT 0xFFFFFFFF -#define EXTMEM_L1_IBUS_MISS_CNT_M ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S)) -#define EXTMEM_L1_IBUS_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_IBUS_MISS_CNT_S 0 - -#define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4) -/* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/ -#define EXTMEM_L1_IBUS_CONFLICT_CNT 0xFFFFFFFF -#define EXTMEM_L1_IBUS_CONFLICT_CNT_M ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S)) -#define EXTMEM_L1_IBUS_CONFLICT_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_IBUS_CONFLICT_CNT_S 0 - -#define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8) -/* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of times that L1-Cache accesses L2-Cache due to -bus0 accessing L1-Cache..*/ -#define EXTMEM_L1_IBUS_NXTLVL_CNT 0xFFFFFFFF -#define EXTMEM_L1_IBUS_NXTLVL_CNT_M ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S)) -#define EXTMEM_L1_IBUS_NXTLVL_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_IBUS_NXTLVL_CNT_S 0 - -#define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC) -/* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of hits when bus1 accesses L1-Cache..*/ -#define EXTMEM_L1_DBUS_HIT_CNT 0xFFFFFFFF -#define EXTMEM_L1_DBUS_HIT_CNT_M ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S)) -#define EXTMEM_L1_DBUS_HIT_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_DBUS_HIT_CNT_S 0 - -#define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0) -/* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of missing when bus1 accesses L1-Cache..*/ -#define EXTMEM_L1_DBUS_MISS_CNT 0xFFFFFFFF -#define EXTMEM_L1_DBUS_MISS_CNT_M ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S)) -#define EXTMEM_L1_DBUS_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_DBUS_MISS_CNT_S 0 - -#define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4) -/* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/ -#define EXTMEM_L1_DBUS_CONFLICT_CNT 0xFFFFFFFF -#define EXTMEM_L1_DBUS_CONFLICT_CNT_M ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S)) -#define EXTMEM_L1_DBUS_CONFLICT_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_DBUS_CONFLICT_CNT_S 0 - -#define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8) -/* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of times that L1-Cache accesses L2-Cache due to -bus1 accessing L1-Cache..*/ -#define EXTMEM_L1_DBUS_NXTLVL_CNT 0xFFFFFFFF -#define EXTMEM_L1_DBUS_NXTLVL_CNT_M ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S)) -#define EXTMEM_L1_DBUS_NXTLVL_CNT_V 0xFFFFFFFF -#define EXTMEM_L1_DBUS_NXTLVL_CNT_S 0 - -#define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C) -/* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The register records the attribution of fail-access when cache accesses L1-Cache -..*/ -#define EXTMEM_L1_CACHE_FAIL_ATTR 0x0000FFFF -#define EXTMEM_L1_CACHE_FAIL_ATTR_M ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S)) -#define EXTMEM_L1_CACHE_FAIL_ATTR_V 0xFFFF -#define EXTMEM_L1_CACHE_FAIL_ATTR_S 16 -/* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/ -#define EXTMEM_L1_CACHE_FAIL_ID 0x0000FFFF -#define EXTMEM_L1_CACHE_FAIL_ID_M ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S)) -#define EXTMEM_L1_CACHE_FAIL_ID_V 0xFFFF -#define EXTMEM_L1_CACHE_FAIL_ID_S 0 - -#define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220) -/* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the address of fail-access when cache accesses L1-Cache..*/ -#define EXTMEM_L1_CACHE_FAIL_ADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_FAIL_ADDR_M ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S)) -#define EXTMEM_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_FAIL_ADDR_S 0 - -#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224) -/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of Cache sync-operation error..*/ -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S 13 -/* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/ -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V 0x1 -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S 11 -/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of Cache sync-operation done..*/ -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S 6 -/* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op -eration is done, interrupt occurs..*/ -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V 0x1 -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S 4 - -#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228) -/* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt of Cache sync-operation error..*/ -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S 13 -/* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/ -#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V 0x1 -#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S 11 -/* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is - done..*/ -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S 6 -/* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat -ion is done..*/ -#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V 0x1 -#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S 4 - -#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C) -/* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc -curs..*/ -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S 13 -/* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er -ror occurs..*/ -#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V 0x1 -#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S 11 -/* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/ -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S 6 -/* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is - done..*/ -#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V 0x1 -#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S 4 - -#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230) -/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/ -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M (BIT(13)) -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S 13 -/* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro -r..*/ -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11)) -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V 0x1 -#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S 11 -/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o -peration is done..*/ -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M (BIT(6)) -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S 6 -/* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre -load-operation is done..*/ -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V 0x1 -#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S 4 - -#define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234) -/* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The values 0-2 are available which means sync map, command conflict and size are - error in Cache System..*/ -#define EXTMEM_L1_CACHE_SYNC_ERR_CODE 0x00000003 -#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S)) -#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V 0x3 -#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S 12 -/* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/ -#define EXTMEM_L1_CACHE_PLD_ERR_CODE 0x00000003 -#define EXTMEM_L1_CACHE_PLD_ERR_CODE_M ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S)) -#define EXTMEM_L1_CACHE_PLD_ERR_CODE_V 0x3 -#define EXTMEM_L1_CACHE_PLD_ERR_CODE_S 8 - -#define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) -/* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl -y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ -#define EXTMEM_L1_CACHE_SYNC_RST (BIT(4)) -#define EXTMEM_L1_CACHE_SYNC_RST_M (BIT(4)) -#define EXTMEM_L1_CACHE_SYNC_RST_V 0x1 -#define EXTMEM_L1_CACHE_SYNC_RST_S 4 - -#define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C) -/* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should -only be used to initialize preload-logic when some fatal error of preload-logic -occurs..*/ -#define EXTMEM_L1_CACHE_PLD_RST (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_RST_M (BIT(4)) -#define EXTMEM_L1_CACHE_PLD_RST_V 0x1 -#define EXTMEM_L1_CACHE_PLD_RST_S 4 - -#define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240) -/* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au -toload will not work in L1-Cache. This bit should not be active when autoload wo -rks in L1-Cache..*/ -#define EXTMEM_L1_CACHE_ALD_BUF_CLR (BIT(4)) -#define EXTMEM_L1_CACHE_ALD_BUF_CLR_M (BIT(4)) -#define EXTMEM_L1_CACHE_ALD_BUF_CLR_V 0x1 -#define EXTMEM_L1_CACHE_ALD_BUF_CLR_S 4 - -#define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) -/* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una -llocate request is responsed but not completed..*/ -#define EXTMEM_L1_CACHE_UNALLOC_CLR (BIT(4)) -#define EXTMEM_L1_CACHE_UNALLOC_CLR_M (BIT(4)) -#define EXTMEM_L1_CACHE_UNALLOC_CLR_V 0x1 -#define EXTMEM_L1_CACHE_UNALLOC_CLR_S 4 - -#define EXTMEM_L1_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248) -/* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi -th the others fields inside this register..*/ -#define EXTMEM_L1_CACHE_MEM_OBJECT (BIT(10)) -#define EXTMEM_L1_CACHE_MEM_OBJECT_M (BIT(10)) -#define EXTMEM_L1_CACHE_MEM_OBJECT_V 0x1 -#define EXTMEM_L1_CACHE_MEM_OBJECT_S 10 -/* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit -h the others fields inside this register..*/ -#define EXTMEM_L1_CACHE_TAG_OBJECT (BIT(4)) -#define EXTMEM_L1_CACHE_TAG_OBJECT_M (BIT(4)) -#define EXTMEM_L1_CACHE_TAG_OBJECT_V 0x1 -#define EXTMEM_L1_CACHE_TAG_OBJECT_S 4 - -#define EXTMEM_L1_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C) -/* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 -: way1, 2: way2, 3: way3, ?, 7: way7..*/ -#define EXTMEM_L1_CACHE_WAY_OBJECT 0x00000007 -#define EXTMEM_L1_CACHE_WAY_OBJECT_M ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S)) -#define EXTMEM_L1_CACHE_WAY_OBJECT_V 0x7 -#define EXTMEM_L1_CACHE_WAY_OBJECT_S 0 - -#define EXTMEM_L1_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) -/* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ -/*description: Those bits stores the virtual address which will decide where inside the specifi -ed tag memory object will be accessed..*/ -#define EXTMEM_L1_CACHE_VADDR 0xFFFFFFFF -#define EXTMEM_L1_CACHE_VADDR_M ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S)) -#define EXTMEM_L1_CACHE_VADDR_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_VADDR_S 0 - -#define EXTMEM_L1_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254) -/* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ -/*description: This is a constant place where we can write data to or read data from the tag/da -ta memory on the specified cache..*/ -#define EXTMEM_L1_CACHE_DEBUG_BUS 0xFFFFFFFF -#define EXTMEM_L1_CACHE_DEBUG_BUS_M ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S)) -#define EXTMEM_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFF -#define EXTMEM_L1_CACHE_DEBUG_BUS_S 0 - -#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) -/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */ -/*description: version control register. Note that this default value stored is the latest date - when the hardware logic was updated..*/ -#define EXTMEM_DATE 0x0FFFFFFF -#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) -#define EXTMEM_DATE_V 0xFFFFFFF -#define EXTMEM_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/extmem_struct.h b/components/soc/esp32p4/include/soc/extmem_struct.h deleted file mode 100644 index dbd90f719a..0000000000 --- a/components/soc/esp32p4/include/soc/extmem_struct.h +++ /dev/null @@ -1,5747 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Control and configuration registers */ -/** Type of l1_icache_ctrl register - * L1 instruction Cache(L1-ICache) control register - */ -typedef union { - struct { - /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0; - * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable - */ - uint32_t l1_icache_shut_ibus0:1; - /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0; - * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable - */ - uint32_t l1_icache_shut_ibus1:1; - /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache_shut_ibus2:1; - /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache_shut_ibus3:1; - /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0; - * Reserved - */ - uint32_t l1_icache_undef_op:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} extmem_l1_icache_ctrl_reg_t; - -/** Type of l1_cache_ctrl register - * L1 data Cache(L1-Cache) control register - */ -typedef union { - struct { - /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable - */ - uint32_t l1_cache_shut_bus0:1; - /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable - */ - uint32_t l1_cache_shut_bus1:1; - /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_cache_shut_dbus2:1; - /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_cache_shut_dbus3:1; - /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable - */ - uint32_t l1_cache_shut_dma:1; - uint32_t reserved_5:3; - /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0; - * Reserved - */ - uint32_t l1_cache_undef_op:4; - uint32_t reserved_12:20; - }; - uint32_t val; -} extmem_l1_cache_ctrl_reg_t; - -/** Type of l2_cache_ctrl register - * L2 Cache(L2-Cache) control register - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable - */ - uint32_t l2_cache_shut_dma:1; - /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0; - * Reserved - */ - uint32_t l2_cache_undef_op:4; - uint32_t reserved_9:23; - }; - uint32_t val; -} extmem_l2_cache_ctrl_reg_t; - - -/** Group: Bypass Cache Control and configuration registers */ -/** Type of l1_bypass_cache_conf register - * Bypass Cache configure register - */ -typedef union { - struct { - /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_icache0_en:1; - /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_icache1_en:1; - /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t bypass_l1_icache2_en:1; - /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t bypass_l1_icache3_en:1; - /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_dcache_en:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_bypass_cache_conf_reg_t; - -/** Type of l2_bypass_cache_conf register - * Bypass Cache configure register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0; - * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l2_cache_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_bypass_cache_conf_reg_t; - - -/** Group: Cache Atomic Control and configuration registers */ -/** Type of l1_cache_atomic_conf register - * L1 Cache atomic feature configure register - */ -typedef union { - struct { - /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable atomic feature on L1-Cache when multiple cores access - * L1-Cache. 1: disable, 1: enable. - */ - uint32_t l1_cache_atomic_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} extmem_l1_cache_atomic_conf_reg_t; - - -/** Group: Cache Mode Control and configuration registers */ -/** Type of l1_icache_cachesize_conf register - * L1 instruction Cache CacheSize mode configure register - */ -typedef union { - struct { - /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_1k:1; - /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_2k:1; - /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_4k:1; - /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_8k:1; - /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_16k:1; - /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_32k:1; - /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_64k:1; - /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_128k:1; - /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_256k:1; - /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_512k:1; - /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_1024k:1; - /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-ICache as 2048k bytes. This field - * and all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_2048k:1; - /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-ICache as 4096k bytes. This field - * and all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_4096k:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} extmem_l1_icache_cachesize_conf_reg_t; - -/** Type of l1_icache_blocksize_conf register - * L1 instruction Cache BlockSize mode configure register - */ -typedef union { - struct { - /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_8:1; - /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_16:1; - /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_32:1; - /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_64:1; - /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_128:1; - /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_256:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l1_icache_blocksize_conf_reg_t; - -/** Type of l1_cache_cachesize_conf register - * L1 data Cache CacheSize mode configure register - */ -typedef union { - struct { - /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-Cache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_1k:1; - /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-Cache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_2k:1; - /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-Cache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_4k:1; - /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-Cache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_8k:1; - /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-Cache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_16k:1; - /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1; - * The field is used to configure cachesize of L1-Cache as 32k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_32k:1; - /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-Cache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_64k:1; - /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L1-Cache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_128k:1; - /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-Cache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_256k:1; - /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-Cache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_512k:1; - /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_1024k:1; - /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_2048k:1; - /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_4096k:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} extmem_l1_cache_cachesize_conf_reg_t; - -/** Type of l1_cache_blocksize_conf register - * L1 data Cache BlockSize mode configure register - */ -typedef union { - struct { - /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_8:1; - /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_16:1; - /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1; - * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_32:1; - /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_64:1; - /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_128:1; - /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_256:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l1_cache_blocksize_conf_reg_t; - -/** Type of l2_cache_cachesize_conf register - * L2 Cache CacheSize mode configure register - */ -typedef union { - struct { - /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_1k:1; - /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_2k:1; - /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_4k:1; - /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_8k:1; - /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_16k:1; - /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_32k:1; - /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_64k:1; - /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_128k:1; - /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_256k:1; - /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_512k:1; - /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_1024k:1; - /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_2048k:1; - /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_4096k:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} extmem_l2_cache_cachesize_conf_reg_t; - -/** Type of l2_cache_blocksize_conf register - * L2 Cache BlockSize mode configure register - */ -typedef union { - struct { - /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_8:1; - /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_16:1; - /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_32:1; - /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_64:1; - /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_128:1; - /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_256:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_blocksize_conf_reg_t; - - -/** Group: Wrap Mode Control and configuration registers */ -/** Type of l1_cache_wrap_around_ctrl register - * Cache wrap around control register - */ -typedef union { - struct { - /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to enable L1-ICache0 wrap around mode. - */ - uint32_t l1_icache0_wrap:1; - /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to enable L1-ICache1 wrap around mode. - */ - uint32_t l1_icache1_wrap:1; - /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_wrap:1; - /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_wrap:1; - /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to enable L1-DCache wrap around mode. - */ - uint32_t l1_cache_wrap:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_wrap_around_ctrl_reg_t; - -/** Type of l2_cache_wrap_around_ctrl register - * Cache wrap around control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_wrap : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to enable L2-Cache wrap around mode. - */ - uint32_t l2_cache_wrap:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_wrap_around_ctrl_reg_t; - - -/** Group: Cache Tag Memory Power Control registers */ -/** Type of l1_cache_tag_mem_power_ctrl register - * Cache tag memory power control register - */ -typedef union { - struct { - /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1; - * The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, - * 0: open clock gating. - */ - uint32_t l1_icache0_tag_mem_force_on:1; - /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0; - * The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power - * down - */ - uint32_t l1_icache0_tag_mem_force_pd:1; - /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1; - * The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l1_icache0_tag_mem_force_pu:1; - uint32_t reserved_3:1; - /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1; - * The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, - * 0: open clock gating. - */ - uint32_t l1_icache1_tag_mem_force_on:1; - /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0; - * The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power - * down - */ - uint32_t l1_icache1_tag_mem_force_pd:1; - /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1; - * The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l1_icache1_tag_mem_force_pu:1; - uint32_t reserved_7:1; - /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1; - * Reserved - */ - uint32_t l1_icache2_tag_mem_force_on:1; - /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_mem_force_pd:1; - /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1; - * Reserved - */ - uint32_t l1_icache2_tag_mem_force_pu:1; - uint32_t reserved_11:1; - /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1; - * Reserved - */ - uint32_t l1_icache3_tag_mem_force_on:1; - /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_mem_force_pd:1; - /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1; - * Reserved - */ - uint32_t l1_icache3_tag_mem_force_pu:1; - uint32_t reserved_15:1; - /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1; - * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: - * open clock gating. - */ - uint32_t l1_cache_tag_mem_force_on:1; - /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0; - * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down - */ - uint32_t l1_cache_tag_mem_force_pd:1; - /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1; - * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l1_cache_tag_mem_force_pu:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} extmem_l1_cache_tag_mem_power_ctrl_reg_t; - -/** Type of l2_cache_tag_mem_power_ctrl register - * Cache tag memory power control register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0; - * The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: - * open clock gating. - */ - uint32_t l2_cache_tag_mem_force_on:1; - /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0; - * The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down - */ - uint32_t l2_cache_tag_mem_force_pd:1; - /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0; - * The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l2_cache_tag_mem_force_pu:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} extmem_l2_cache_tag_mem_power_ctrl_reg_t; - - -/** Group: Cache Data Memory Power Control registers */ -/** Type of l1_cache_data_mem_power_ctrl register - * Cache data memory power control register - */ -typedef union { - struct { - /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1; - * The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, - * 0: open clock gating. - */ - uint32_t l1_icache0_data_mem_force_on:1; - /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0; - * The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power - * down - */ - uint32_t l1_icache0_data_mem_force_pd:1; - /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1; - * The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l1_icache0_data_mem_force_pu:1; - uint32_t reserved_3:1; - /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1; - * The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, - * 0: open clock gating. - */ - uint32_t l1_icache1_data_mem_force_on:1; - /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0; - * The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power - * down - */ - uint32_t l1_icache1_data_mem_force_pd:1; - /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1; - * The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l1_icache1_data_mem_force_pu:1; - uint32_t reserved_7:1; - /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1; - * Reserved - */ - uint32_t l1_icache2_data_mem_force_on:1; - /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_data_mem_force_pd:1; - /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1; - * Reserved - */ - uint32_t l1_icache2_data_mem_force_pu:1; - uint32_t reserved_11:1; - /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1; - * Reserved - */ - uint32_t l1_icache3_data_mem_force_on:1; - /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_data_mem_force_pd:1; - /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1; - * Reserved - */ - uint32_t l1_icache3_data_mem_force_pu:1; - uint32_t reserved_15:1; - /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1; - * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: - * open clock gating. - */ - uint32_t l1_cache_data_mem_force_on:1; - /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0; - * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power - * down - */ - uint32_t l1_cache_data_mem_force_pd:1; - /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1; - * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l1_cache_data_mem_force_pu:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} extmem_l1_cache_data_mem_power_ctrl_reg_t; - -/** Type of l2_cache_data_mem_power_ctrl register - * Cache data memory power control register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0; - * The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: - * open clock gating. - */ - uint32_t l2_cache_data_mem_force_on:1; - /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0; - * The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power - * down - */ - uint32_t l2_cache_data_mem_force_pd:1; - /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0; - * The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up - */ - uint32_t l2_cache_data_mem_force_pu:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} extmem_l2_cache_data_mem_power_ctrl_reg_t; - - -/** Group: Cache Freeze Control registers */ -/** Type of l1_cache_freeze_ctrl register - * Cache Freeze control register - */ -typedef union { - struct { - /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by - * software. - */ - uint32_t l1_icache0_freeze_en:1; - /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l1_icache0_freeze_mode:1; - /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache0_freeze_done:1; - uint32_t reserved_3:1; - /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by - * software. - */ - uint32_t l1_icache1_freeze_en:1; - /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l1_icache1_freeze_mode:1; - /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache1_freeze_done:1; - uint32_t reserved_7:1; - /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_en:1; - /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_mode:1; - /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_done:1; - uint32_t reserved_11:1; - /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_en:1; - /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_mode:1; - /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_done:1; - uint32_t reserved_15:1; - /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; - * The bit is used to enable freeze operation on L1-Cache. It can be cleared by - * software. - */ - uint32_t l1_cache_freeze_en:1; - /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; - * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l1_cache_freeze_mode:1; - /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; - * The bit is used to indicate whether freeze operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_cache_freeze_done:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} extmem_l1_cache_freeze_ctrl_reg_t; - -/** Type of l2_cache_freeze_ctrl register - * Cache Freeze control register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable freeze operation on L2-Cache. It can be cleared by - * software. - */ - uint32_t l2_cache_freeze_en:1; - /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0; - * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l2_cache_freeze_mode:1; - /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0; - * The bit is used to indicate whether freeze operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l2_cache_freeze_done:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} extmem_l2_cache_freeze_ctrl_reg_t; - - -/** Group: Cache Data Memory Access Control and Configuration registers */ -/** Type of l1_cache_data_mem_acs_conf register - * Cache data memory access configure register - */ -typedef union { - struct { - /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1; - * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_data_mem_rd_en:1; - /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1; - * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, - * 1: enable. - */ - uint32_t l1_icache0_data_mem_wr_en:1; - uint32_t reserved_2:2; - /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1; - * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_data_mem_rd_en:1; - /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1; - * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, - * 1: enable. - */ - uint32_t l1_icache1_data_mem_wr_en:1; - uint32_t reserved_6:2; - /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1; - * Reserved - */ - uint32_t l1_icache2_data_mem_rd_en:1; - /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1; - * Reserved - */ - uint32_t l1_icache2_data_mem_wr_en:1; - uint32_t reserved_10:2; - /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1; - * Reserved - */ - uint32_t l1_icache3_data_mem_rd_en:1; - /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1; - * Reserved - */ - uint32_t l1_icache3_data_mem_wr_en:1; - uint32_t reserved_14:2; - /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1; - * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_cache_data_mem_rd_en:1; - /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1; - * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_cache_data_mem_wr_en:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} extmem_l1_cache_data_mem_acs_conf_reg_t; - -/** Type of l2_cache_data_mem_acs_conf register - * Cache data memory access configure register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_data_mem_rd_en:1; - /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_data_mem_wr_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} extmem_l2_cache_data_mem_acs_conf_reg_t; - - -/** Group: Cache Tag Memory Access Control and Configuration registers */ -/** Type of l1_cache_tag_mem_acs_conf register - * Cache tag memory access configure register - */ -typedef union { - struct { - /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1; - * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_tag_mem_rd_en:1; - /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1; - * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_tag_mem_wr_en:1; - uint32_t reserved_2:2; - /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1; - * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_tag_mem_rd_en:1; - /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1; - * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_tag_mem_wr_en:1; - uint32_t reserved_6:2; - /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1; - * Reserved - */ - uint32_t l1_icache2_tag_mem_rd_en:1; - /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1; - * Reserved - */ - uint32_t l1_icache2_tag_mem_wr_en:1; - uint32_t reserved_10:2; - /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1; - * Reserved - */ - uint32_t l1_icache3_tag_mem_rd_en:1; - /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1; - * Reserved - */ - uint32_t l1_icache3_tag_mem_wr_en:1; - uint32_t reserved_14:2; - /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1; - * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_cache_tag_mem_rd_en:1; - /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1; - * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_cache_tag_mem_wr_en:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} extmem_l1_cache_tag_mem_acs_conf_reg_t; - -/** Type of l2_cache_tag_mem_acs_conf register - * Cache tag memory access configure register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_tag_mem_rd_en:1; - /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_tag_mem_wr_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} extmem_l2_cache_tag_mem_acs_conf_reg_t; - - -/** Group: Prelock Control and configuration registers */ -/** Type of l1_icache0_prelock_conf register - * L1 instruction Cache 0 prelock configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache0. - */ - uint32_t l1_icache0_prelock_sct0_en:1; - /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache0. - */ - uint32_t l1_icache0_prelock_sct1_en:1; - /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache0 prelock. - */ - uint32_t l1_icache0_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l1_icache0_prelock_conf_reg_t; - -/** Type of l1_icache0_prelock_sct0_addr register - * L1 instruction Cache 0 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section of - * prelock on L1-ICache0, which should be used together with - * L1_ICACHE0_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache0_prelock_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache0_prelock_sct0_addr_reg_t; - -/** Type of l1_icache0_prelock_sct1_addr register - * L1 instruction Cache 0 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section of - * prelock on L1-ICache0, which should be used together with - * L1_ICACHE0_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache0_prelock_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache0_prelock_sct1_addr_reg_t; - -/** Type of l1_icache0_prelock_sct_size register - * L1 instruction Cache 0 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache0_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache0_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} extmem_l1_icache0_prelock_sct_size_reg_t; - -/** Type of l1_icache1_prelock_conf register - * L1 instruction Cache 1 prelock configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache1. - */ - uint32_t l1_icache1_prelock_sct0_en:1; - /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache1. - */ - uint32_t l1_icache1_prelock_sct1_en:1; - /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache1 prelock. - */ - uint32_t l1_icache1_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l1_icache1_prelock_conf_reg_t; - -/** Type of l1_icache1_prelock_sct0_addr register - * L1 instruction Cache 1 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section of - * prelock on L1-ICache1, which should be used together with - * L1_ICACHE1_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache1_prelock_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache1_prelock_sct0_addr_reg_t; - -/** Type of l1_icache1_prelock_sct1_addr register - * L1 instruction Cache 1 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section of - * prelock on L1-ICache1, which should be used together with - * L1_ICACHE1_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache1_prelock_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache1_prelock_sct1_addr_reg_t; - -/** Type of l1_icache1_prelock_sct_size register - * L1 instruction Cache 1 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache1_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache1_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} extmem_l1_icache1_prelock_sct_size_reg_t; - -/** Type of l1_icache2_prelock_conf register - * L1 instruction Cache 2 prelock configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache2. - */ - uint32_t l1_icache2_prelock_sct0_en:1; - /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache2. - */ - uint32_t l1_icache2_prelock_sct1_en:1; - /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache2 prelock. - */ - uint32_t l1_icache2_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l1_icache2_prelock_conf_reg_t; - -/** Type of l1_icache2_prelock_sct0_addr register - * L1 instruction Cache 2 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section of - * prelock on L1-ICache2, which should be used together with - * L1_ICACHE2_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache2_prelock_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache2_prelock_sct0_addr_reg_t; - -/** Type of l1_icache2_prelock_sct1_addr register - * L1 instruction Cache 2 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section of - * prelock on L1-ICache2, which should be used together with - * L1_ICACHE2_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache2_prelock_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache2_prelock_sct1_addr_reg_t; - -/** Type of l1_icache2_prelock_sct_size register - * L1 instruction Cache 2 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache2_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache2_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} extmem_l1_icache2_prelock_sct_size_reg_t; - -/** Type of l1_icache3_prelock_conf register - * L1 instruction Cache 3 prelock configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache3. - */ - uint32_t l1_icache3_prelock_sct0_en:1; - /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache3. - */ - uint32_t l1_icache3_prelock_sct1_en:1; - /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache3 prelock. - */ - uint32_t l1_icache3_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l1_icache3_prelock_conf_reg_t; - -/** Type of l1_icache3_prelock_sct0_addr register - * L1 instruction Cache 3 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section of - * prelock on L1-ICache3, which should be used together with - * L1_ICACHE3_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache3_prelock_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache3_prelock_sct0_addr_reg_t; - -/** Type of l1_icache3_prelock_sct1_addr register - * L1 instruction Cache 3 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section of - * prelock on L1-ICache3, which should be used together with - * L1_ICACHE3_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache3_prelock_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache3_prelock_sct1_addr_reg_t; - -/** Type of l1_icache3_prelock_sct_size register - * L1 instruction Cache 3 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache3_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache3_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} extmem_l1_icache3_prelock_sct_size_reg_t; - -/** Type of l1_cache_prelock_conf register - * L1 Cache prelock configure register - */ -typedef union { - struct { - /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-Cache. - */ - uint32_t l1_cache_prelock_sct0_en:1; - /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-Cache. - */ - uint32_t l1_cache_prelock_sct1_en:1; - /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 cache prelock. - */ - uint32_t l1_cache_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l1_cache_prelock_conf_reg_t; - -/** Type of l1_cache_prelock_sct0_addr register - * L1 Cache prelock section0 address configure register - */ -typedef union { - struct { - /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section of - * prelock on L1-Cache, which should be used together with - * L1_CACHE_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_cache_prelock_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_cache_prelock_sct0_addr_reg_t; - -/** Type of l1_dcache_prelock_sct1_addr register - * L1 Cache prelock section1 address configure register - */ -typedef union { - struct { - /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section of - * prelock on L1-Cache, which should be used together with - * L1_CACHE_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_cache_prelock_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_dcache_prelock_sct1_addr_reg_t; - -/** Type of l1_dcache_prelock_sct_size register - * L1 Cache prelock section size configure register - */ -typedef union { - struct { - /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_cache_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_cache_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} extmem_l1_dcache_prelock_sct_size_reg_t; - -/** Type of l2_cache_prelock_conf register - * L2 Cache prelock configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L2-Cache. - */ - uint32_t l2_cache_prelock_sct0_en:1; - /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L2-Cache. - */ - uint32_t l2_cache_prelock_sct1_en:1; - /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l2 cache prelock. - */ - uint32_t l2_cache_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_prelock_conf_reg_t; - -/** Type of l2_cache_prelock_sct0_addr register - * L2 Cache prelock section0 address configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section of - * prelock on L2-Cache, which should be used together with - * L2_CACHE_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l2_cache_prelock_sct0_addr:32; - }; - uint32_t val; -} extmem_l2_cache_prelock_sct0_addr_reg_t; - -/** Type of l2_cache_prelock_sct1_addr register - * L2 Cache prelock section1 address configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section of - * prelock on L2-Cache, which should be used together with - * L2_CACHE_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l2_cache_prelock_sct1_addr:32; - }; - uint32_t val; -} extmem_l2_cache_prelock_sct1_addr_reg_t; - -/** Type of l2_cache_prelock_sct_size register - * L2 Cache prelock section size configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l2_cache_prelock_sct0_size:16; - /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535; - * Those bits are used to configure the size of the second section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l2_cache_prelock_sct1_size:16; - }; - uint32_t val; -} extmem_l2_cache_prelock_sct_size_reg_t; - - -/** Group: Lock Control and configuration registers */ -/** Type of cache_lock_ctrl register - * Lock-class (manual lock) operation control register - */ -typedef union { - struct { - /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware after lock - * operation done - */ - uint32_t cache_lock_ena:1; - /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by hardware after - * unlock operation done - */ - uint32_t cache_unlock_ena:1; - /** cache_lock_done : RO; bitpos: [2]; default: 1; - * The bit is used to indicate whether unlock/lock operation is finished or not. 0: - * not finished. 1: finished. - */ - uint32_t cache_lock_done:1; - /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of cache lock/unlock. - */ - uint32_t cache_lock_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} extmem_cache_lock_ctrl_reg_t; - -/** Type of cache_lock_map register - * Lock (manual lock) map configure register - */ -typedef union { - struct { - /** cache_lock_map : R/W; bitpos: [5:0]; default: 0; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply this lock/unlock operation. [4]: L1-Cache - */ - uint32_t cache_lock_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_cache_lock_map_reg_t; - -/** Type of cache_lock_addr register - * Lock (manual lock) address configure register - */ -typedef union { - struct { - /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the lock/unlock - * operation, which should be used together with CACHE_LOCK_SIZE_REG - */ - uint32_t cache_lock_addr:32; - }; - uint32_t val; -} extmem_cache_lock_addr_reg_t; - -/** Type of cache_lock_size register - * Lock (manual lock) size configure register - */ -typedef union { - struct { - /** cache_lock_size : R/W; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the lock/unlock operation, which - * should be used together with CACHE_LOCK_ADDR_REG - */ - uint32_t cache_lock_size:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_cache_lock_size_reg_t; - - -/** Group: Sync Control and configuration registers */ -/** Type of cache_sync_ctrl register - * Sync-class operation control register - */ -typedef union { - struct { - /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by hardware - * after invalidate operation done. Note that this bit and the other sync-bits - * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. - */ - uint32_t cache_invalidate_ena:1; - /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable clean operation. It will be cleared by hardware after - * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, - * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those - * bits can not be set to 1 at the same time. - */ - uint32_t cache_clean_ena:1; - /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0; - * The bit is used to enable writeback operation. It will be cleared by hardware after - * writeback operation done. Note that this bit and the other sync-bits - * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. - */ - uint32_t cache_writeback_ena:1; - /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; - * The bit is used to enable writeback-invalidate operation. It will be cleared by - * hardware after writeback-invalidate operation done. Note that this bit and the - * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, - * that is, those bits can not be set to 1 at the same time. - */ - uint32_t cache_writeback_invalidate_ena:1; - /** cache_sync_done : RO; bitpos: [4]; default: 0; - * The bit is used to indicate whether sync operation (invalidate, clean, writeback, - * writeback_invalidate) is finished or not. 0: not finished. 1: finished. - */ - uint32_t cache_sync_done:1; - /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0; - * The bit is used to set the gid of cache sync operation (invalidate, clean, - * writeback, writeback_invalidate) - */ - uint32_t cache_sync_rgid:4; - uint32_t reserved_9:23; - }; - uint32_t val; -} extmem_cache_sync_ctrl_reg_t; - -/** Type of cache_sync_map register - * Sync map configure register - */ -typedef union { - struct { - /** cache_sync_map : R/W; bitpos: [5:0]; default: 63; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply the sync operation. [4]: L1-Cache - */ - uint32_t cache_sync_map:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_cache_sync_map_reg_t; - -/** Type of cache_sync_addr register - * Sync address configure register - */ -typedef union { - struct { - /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the sync operation, - * which should be used together with CACHE_SYNC_SIZE_REG - */ - uint32_t cache_sync_addr:32; - }; - uint32_t val; -} extmem_cache_sync_addr_reg_t; - -/** Type of cache_sync_size register - * Sync size configure register - */ -typedef union { - struct { - /** cache_sync_size : R/W; bitpos: [23:0]; default: 0; - * Those bits are used to configure the size of the sync operation, which should be - * used together with CACHE_SYNC_ADDR_REG - */ - uint32_t cache_sync_size:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} extmem_cache_sync_size_reg_t; - - -/** Group: Preload Control and configuration registers */ -/** Type of l1_icache0_preload_ctrl register - * L1 instruction Cache 0 preload-operation control register - */ -typedef union { - struct { - /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache0. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache0_preload_ena:1; - /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache0_preload_done:1; - /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache0_preload_order:1; - /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache0 preload. - */ - uint32_t l1_icache0_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} extmem_l1_icache0_preload_ctrl_reg_t; - -/** Type of l1_icache0_preload_addr register - * L1 instruction Cache 0 preload address configure register - */ -typedef union { - struct { - /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of preload on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG - */ - uint32_t l1_icache0_preload_addr:32; - }; - uint32_t val; -} extmem_l1_icache0_preload_addr_reg_t; - -/** Type of l1_icache0_preload_size register - * L1 instruction Cache 0 preload size configure register - */ -typedef union { - struct { - /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG - */ - uint32_t l1_icache0_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache0_preload_size_reg_t; - -/** Type of l1_icache1_preload_ctrl register - * L1 instruction Cache 1 preload-operation control register - */ -typedef union { - struct { - /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache1. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache1_preload_ena:1; - /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache1_preload_done:1; - /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache1_preload_order:1; - /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache1 preload. - */ - uint32_t l1_icache1_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} extmem_l1_icache1_preload_ctrl_reg_t; - -/** Type of l1_icache1_preload_addr register - * L1 instruction Cache 1 preload address configure register - */ -typedef union { - struct { - /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of preload on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG - */ - uint32_t l1_icache1_preload_addr:32; - }; - uint32_t val; -} extmem_l1_icache1_preload_addr_reg_t; - -/** Type of l1_icache1_preload_size register - * L1 instruction Cache 1 preload size configure register - */ -typedef union { - struct { - /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG - */ - uint32_t l1_icache1_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache1_preload_size_reg_t; - -/** Type of l1_icache2_preload_ctrl register - * L1 instruction Cache 2 preload-operation control register - */ -typedef union { - struct { - /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache2. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache2_preload_ena:1; - /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache2_preload_done:1; - /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache2_preload_order:1; - /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache2 preload. - */ - uint32_t l1_icache2_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} extmem_l1_icache2_preload_ctrl_reg_t; - -/** Type of l1_icache2_preload_addr register - * L1 instruction Cache 2 preload address configure register - */ -typedef union { - struct { - /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of preload on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG - */ - uint32_t l1_icache2_preload_addr:32; - }; - uint32_t val; -} extmem_l1_icache2_preload_addr_reg_t; - -/** Type of l1_icache2_preload_size register - * L1 instruction Cache 2 preload size configure register - */ -typedef union { - struct { - /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG - */ - uint32_t l1_icache2_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache2_preload_size_reg_t; - -/** Type of l1_icache3_preload_ctrl register - * L1 instruction Cache 3 preload-operation control register - */ -typedef union { - struct { - /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache3. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache3_preload_ena:1; - /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache3_preload_done:1; - /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache3_preload_order:1; - /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache3 preload. - */ - uint32_t l1_icache3_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} extmem_l1_icache3_preload_ctrl_reg_t; - -/** Type of l1_icache3_preload_addr register - * L1 instruction Cache 3 preload address configure register - */ -typedef union { - struct { - /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of preload on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG - */ - uint32_t l1_icache3_preload_addr:32; - }; - uint32_t val; -} extmem_l1_icache3_preload_addr_reg_t; - -/** Type of l1_icache3_preload_size register - * L1 instruction Cache 3 preload size configure register - */ -typedef union { - struct { - /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG - */ - uint32_t l1_icache3_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache3_preload_size_reg_t; - -/** Type of l1_cache_preload_ctrl register - * L1 Cache preload-operation control register - */ -typedef union { - struct { - /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-Cache. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_cache_preload_ena:1; - /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_cache_preload_done:1; - /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_cache_preload_order:1; - /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 cache preload. - */ - uint32_t l1_cache_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} extmem_l1_cache_preload_ctrl_reg_t; - -/** Type of l1_dcache_preload_addr register - * L1 Cache preload address configure register - */ -typedef union { - struct { - /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of preload on L1-Cache, - * which should be used together with L1_CACHE_PRELOAD_SIZE_REG - */ - uint32_t l1_cache_preload_addr:32; - }; - uint32_t val; -} extmem_l1_dcache_preload_addr_reg_t; - -/** Type of l1_dcache_preload_size register - * L1 Cache preload size configure register - */ -typedef union { - struct { - /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG - */ - uint32_t l1_cache_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_dcache_preload_size_reg_t; - -/** Type of l2_cache_preload_ctrl register - * L2 Cache preload-operation control register - */ -typedef union { - struct { - /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L2-Cache. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l2_cache_preload_ena:1; - /** l2_cache_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l2_cache_preload_done:1; - /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l2_cache_preload_order:1; - /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l2 cache preload. - */ - uint32_t l2_cache_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} extmem_l2_cache_preload_ctrl_reg_t; - -/** Type of l2_cache_preload_addr register - * L2 Cache preload address configure register - */ -typedef union { - struct { - /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of preload on L2-Cache, - * which should be used together with L2_CACHE_PRELOAD_SIZE_REG - */ - uint32_t l2_cache_preload_addr:32; - }; - uint32_t val; -} extmem_l2_cache_preload_addr_reg_t; - -/** Type of l2_cache_preload_size register - * L2 Cache preload size configure register - */ -typedef union { - struct { - /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG - */ - uint32_t l2_cache_preload_size:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_l2_cache_preload_size_reg_t; - - -/** Group: Autoload Control and configuration registers */ -/** Type of l1_icache0_autoload_ctrl register - * L1 instruction Cache 0 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, - * 0: disable. - */ - uint32_t l1_icache0_autoload_ena:1; - /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache0_autoload_done:1; - /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache0_autoload_order:1; - /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache0. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache0_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache0. - */ - uint32_t l1_icache0_autoload_sct0_ena:1; - /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache0. - */ - uint32_t l1_icache0_autoload_sct1_ena:1; - /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache0 autoload. - */ - uint32_t l1_icache0_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache0_autoload_ctrl_reg_t; - -/** Type of l1_icache0_autoload_sct0_addr register - * L1 instruction Cache 0 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache0_autoload_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache0_autoload_sct0_addr_reg_t; - -/** Type of l1_icache0_autoload_sct0_size register - * L1 instruction Cache 0 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache0_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache0_autoload_sct0_size_reg_t; - -/** Type of l1_icache0_autoload_sct1_addr register - * L1 instruction Cache 0 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section - * for autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache0_autoload_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache0_autoload_sct1_addr_reg_t; - -/** Type of l1_icache0_autoload_sct1_size register - * L1 instruction Cache 0 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache0_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache0_autoload_sct1_size_reg_t; - -/** Type of l1_icache1_autoload_ctrl register - * L1 instruction Cache 1 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, - * 0: disable. - */ - uint32_t l1_icache1_autoload_ena:1; - /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache1_autoload_done:1; - /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache1_autoload_order:1; - /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache1. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache1_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache1. - */ - uint32_t l1_icache1_autoload_sct0_ena:1; - /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache1. - */ - uint32_t l1_icache1_autoload_sct1_ena:1; - /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache1 autoload. - */ - uint32_t l1_icache1_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache1_autoload_ctrl_reg_t; - -/** Type of l1_icache1_autoload_sct0_addr register - * L1 instruction Cache 1 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache1_autoload_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache1_autoload_sct0_addr_reg_t; - -/** Type of l1_icache1_autoload_sct0_size register - * L1 instruction Cache 1 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache1_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache1_autoload_sct0_size_reg_t; - -/** Type of l1_icache1_autoload_sct1_addr register - * L1 instruction Cache 1 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section - * for autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache1_autoload_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache1_autoload_sct1_addr_reg_t; - -/** Type of l1_icache1_autoload_sct1_size register - * L1 instruction Cache 1 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache1_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache1_autoload_sct1_size_reg_t; - -/** Type of l1_icache2_autoload_ctrl register - * L1 instruction Cache 2 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, - * 0: disable. - */ - uint32_t l1_icache2_autoload_ena:1; - /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache2_autoload_done:1; - /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache2_autoload_order:1; - /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache2. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache2_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache2. - */ - uint32_t l1_icache2_autoload_sct0_ena:1; - /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache2. - */ - uint32_t l1_icache2_autoload_sct1_ena:1; - /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache2 autoload. - */ - uint32_t l1_icache2_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache2_autoload_ctrl_reg_t; - -/** Type of l1_icache2_autoload_sct0_addr register - * L1 instruction Cache 2 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache2_autoload_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache2_autoload_sct0_addr_reg_t; - -/** Type of l1_icache2_autoload_sct0_size register - * L1 instruction Cache 2 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache2_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache2_autoload_sct0_size_reg_t; - -/** Type of l1_icache2_autoload_sct1_addr register - * L1 instruction Cache 2 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section - * for autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache2_autoload_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache2_autoload_sct1_addr_reg_t; - -/** Type of l1_icache2_autoload_sct1_size register - * L1 instruction Cache 2 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache2_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache2_autoload_sct1_size_reg_t; - -/** Type of l1_icache3_autoload_ctrl register - * L1 instruction Cache 3 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, - * 0: disable. - */ - uint32_t l1_icache3_autoload_ena:1; - /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache3_autoload_done:1; - /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache3_autoload_order:1; - /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache3. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache3_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache3. - */ - uint32_t l1_icache3_autoload_sct0_ena:1; - /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache3. - */ - uint32_t l1_icache3_autoload_sct1_ena:1; - /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache3 autoload. - */ - uint32_t l1_icache3_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_icache3_autoload_ctrl_reg_t; - -/** Type of l1_icache3_autoload_sct0_addr register - * L1 instruction Cache 3 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache3_autoload_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_icache3_autoload_sct0_addr_reg_t; - -/** Type of l1_icache3_autoload_sct0_size register - * L1 instruction Cache 3 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache3_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache3_autoload_sct0_size_reg_t; - -/** Type of l1_icache3_autoload_sct1_addr register - * L1 instruction Cache 3 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section - * for autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache3_autoload_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_icache3_autoload_sct1_addr_reg_t; - -/** Type of l1_icache3_autoload_sct1_size register - * L1 instruction Cache 3 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Reserved - */ - uint32_t l1_icache3_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_icache3_autoload_sct1_size_reg_t; - -/** Type of l1_cache_autoload_ctrl register - * L1 Cache autoload-operation control register - */ -typedef union { - struct { - /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, - * 0: disable. - */ - uint32_t l1_cache_autoload_ena:1; - /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_cache_autoload_done:1; - /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-Cache. 0: - * ascending. 1: descending. - */ - uint32_t l1_cache_autoload_order:1; - /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_cache_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct0_ena:1; - /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct1_ena:1; - /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct2_ena:1; - /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct3_ena:1; - /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l1 cache autoload. - */ - uint32_t l1_cache_autoload_rgid:4; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_l1_cache_autoload_ctrl_reg_t; - -/** Type of l1_cache_autoload_sct0_addr register - * L1 Cache autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_cache_autoload_sct0_addr:32; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct0_addr_reg_t; - -/** Type of l1_cache_autoload_sct0_size register - * L1 Cache autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_cache_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct0_size_reg_t; - -/** Type of l1_cache_autoload_sct1_addr register - * L1 Cache autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section - * for autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_cache_autoload_sct1_addr:32; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct1_addr_reg_t; - -/** Type of l1_cache_autoload_sct1_size register - * L1 Cache autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_cache_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct1_size_reg_t; - -/** Type of l1_cache_autoload_sct2_addr register - * L1 Cache autoload section 2 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the third section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l1_cache_autoload_sct2_addr:32; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct2_addr_reg_t; - -/** Type of l1_cache_autoload_sct2_size register - * L1 Cache autoload section 2 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l1_cache_autoload_sct2_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct2_size_reg_t; - -/** Type of l1_cache_autoload_sct3_addr register - * L1 Cache autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the fourth section - * for autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l1_cache_autoload_sct3_addr:32; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct3_addr_reg_t; - -/** Type of l1_cache_autoload_sct3_size register - * L1 Cache autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l1_cache_autoload_sct3_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l1_cache_autoload_sct3_size_reg_t; - -/** Type of l2_cache_autoload_ctrl register - * L2 Cache autoload-operation control register - */ -typedef union { - struct { - /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, - * 0: disable. - */ - uint32_t l2_cache_autoload_ena:1; - /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l2_cache_autoload_done:1; - /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L2-Cache. 0: - * ascending. 1: descending. - */ - uint32_t l2_cache_autoload_order:1; - /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l2_cache_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct0_ena:1; - /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct1_ena:1; - /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct2_ena:1; - /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct3_ena:1; - /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l2 cache autoload. - */ - uint32_t l2_cache_autoload_rgid:4; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_l2_cache_autoload_ctrl_reg_t; - -/** Type of l2_cache_autoload_sct0_addr register - * L2 Cache autoload section 0 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the first section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l2_cache_autoload_sct0_addr:32; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct0_addr_reg_t; - -/** Type of l2_cache_autoload_sct0_size register - * L2 Cache autoload section 0 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l2_cache_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct0_size_reg_t; - -/** Type of l2_cache_autoload_sct1_addr register - * L2 Cache autoload section 1 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the second section - * for autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l2_cache_autoload_sct1_addr:32; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct1_addr_reg_t; - -/** Type of l2_cache_autoload_sct1_size register - * L2 Cache autoload section 1 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l2_cache_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct1_size_reg_t; - -/** Type of l2_cache_autoload_sct2_addr register - * L2 Cache autoload section 2 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the third section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l2_cache_autoload_sct2_addr:32; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct2_addr_reg_t; - -/** Type of l2_cache_autoload_sct2_size register - * L2 Cache autoload section 2 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l2_cache_autoload_sct2_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct2_size_reg_t; - -/** Type of l2_cache_autoload_sct3_addr register - * L2 Cache autoload section 3 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start virtual address of the fourth section - * for autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l2_cache_autoload_sct3_addr:32; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct3_addr_reg_t; - -/** Type of l2_cache_autoload_sct3_size register - * L2 Cache autoload section 3 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l2_cache_autoload_sct3_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_l2_cache_autoload_sct3_size_reg_t; - - -/** Group: Interrupt registers */ -/** Type of l1_cache_acs_cnt_int_ena register - * Cache Access Counter Interrupt enable register - */ -typedef union { - struct { - /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_ena:1; - /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_ena:1; - /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_ena:1; - /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_ena:1; - /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. - */ - uint32_t l1_bus0_ovf_int_ena:1; - /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. - */ - uint32_t l1_bus1_ovf_int_ena:1; - /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_ena:1; - /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} extmem_l1_cache_acs_cnt_int_ena_reg_t; - -/** Type of l1_cache_acs_cnt_int_clr register - * Cache Access Counter Interrupt clear register - */ -typedef union { - struct { - /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due - * to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_clr:1; - /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due - * to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_clr:1; - /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_clr:1; - /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_clr:1; - /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus0 accesses L1-DCache. - */ - uint32_t l1_bus0_ovf_int_clr:1; - /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus1 accesses L1-DCache. - */ - uint32_t l1_bus1_ovf_int_clr:1; - /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_clr:1; - /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_clr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} extmem_l1_cache_acs_cnt_int_clr_reg_t; - -/** Type of l1_cache_acs_cnt_int_raw register - * Cache Access Counter Interrupt raw register - */ -typedef union { - struct { - /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 - * due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_raw:1; - /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 - * due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_raw:1; - /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 - * due to bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_ovf_int_raw:1; - /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 - * due to bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_ovf_int_raw:1; - /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus0 accesses L1-DCache. - */ - uint32_t l1_bus0_ovf_int_raw:1; - /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus1 accesses L1-DCache. - */ - uint32_t l1_bus1_ovf_int_raw:1; - /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_ovf_int_raw:1; - /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_ovf_int_raw:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} extmem_l1_cache_acs_cnt_int_raw_reg_t; - -/** Type of l1_cache_acs_cnt_int_st register - * Cache Access Counter Interrupt status register - */ -typedef union { - struct { - /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_st:1; - /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_st:1; - /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_st:1; - /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_st:1; - /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. - */ - uint32_t l1_bus0_ovf_int_st:1; - /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. - */ - uint32_t l1_bus1_ovf_int_st:1; - /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_st:1; - /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_st:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} extmem_l1_cache_acs_cnt_int_st_reg_t; - -/** Type of l1_cache_acs_fail_int_ena register - * Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ - uint32_t l1_icache0_fail_int_ena:1; - /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ - uint32_t l1_icache1_fail_int_ena:1; - /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_ena:1; - /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_ena:1; - /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. - */ - uint32_t l1_cache_fail_int_ena:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_acs_fail_int_ena_reg_t; - -/** Type of l1_cache_acs_fail_int_clr register - * L1-Cache Access Fail Interrupt clear register - */ -typedef union { - struct { - /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ - uint32_t l1_icache0_fail_int_clr:1; - /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ - uint32_t l1_icache1_fail_int_clr:1; - /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_clr:1; - /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_clr:1; - /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. - */ - uint32_t l1_cache_fail_int_clr:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_acs_fail_int_clr_reg_t; - -/** Type of l1_cache_acs_fail_int_raw register - * Cache Access Fail Interrupt raw register - */ -typedef union { - struct { - /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache0. - */ - uint32_t l1_icache0_fail_int_raw:1; - /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache1. - */ - uint32_t l1_icache1_fail_int_raw:1; - /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache2. - */ - uint32_t l1_icache2_fail_int_raw:1; - /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache3. - */ - uint32_t l1_icache3_fail_int_raw:1; - /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-DCache. - */ - uint32_t l1_cache_fail_int_raw:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_acs_fail_int_raw_reg_t; - -/** Type of l1_cache_acs_fail_int_st register - * Cache Access Fail Interrupt status register - */ -typedef union { - struct { - /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due - * to cpu accesses L1-ICache. - */ - uint32_t l1_icache0_fail_int_st:1; - /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due - * to cpu accesses L1-ICache. - */ - uint32_t l1_icache1_fail_int_st:1; - /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_st:1; - /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_st:1; - /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-DCache due - * to cpu accesses L1-DCache. - */ - uint32_t l1_cache_fail_int_st:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_acs_fail_int_st_reg_t; - -/** Type of l1_cache_sync_preload_int_ena register - * L1-Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload - * operation is done, interrupt occurs. - */ - uint32_t l1_icache0_pld_done_int_ena:1; - /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload - * operation is done, interrupt occurs. - */ - uint32_t l1_icache1_pld_done_int_ena:1; - /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_ena:1; - /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_ena:1; - /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation. If preload - * operation is done, interrupt occurs. - */ - uint32_t l1_cache_pld_done_int_ena:1; - uint32_t reserved_5:1; - /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation done. - */ - uint32_t cache_sync_done_int_ena:1; - /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_ena:1; - /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_ena:1; - /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_ena:1; - /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_ena:1; - /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation error. - */ - uint32_t l1_cache_pld_err_int_ena:1; - uint32_t reserved_12:1; - /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation error. - */ - uint32_t cache_sync_err_int_ena:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_cache_sync_preload_int_ena_reg_t; - -/** Type of l1_cache_sync_preload_int_clr register - * Sync Preload operation Interrupt clear register - */ -typedef union { - struct { - /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ - uint32_t l1_icache0_pld_done_int_clr:1; - /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ - uint32_t l1_icache1_pld_done_int_clr:1; - /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_clr:1; - /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_clr:1; - /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation - * is done. - */ - uint32_t l1_cache_pld_done_int_clr:1; - uint32_t reserved_5:1; - /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0; - * The bit is used to clear interrupt that occurs only when Cache sync-operation is - * done. - */ - uint32_t cache_sync_done_int_clr:1; - /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0; - * The bit is used to clear interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_clr:1; - /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0; - * The bit is used to clear interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_clr:1; - /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_clr:1; - /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_clr:1; - /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; - * The bit is used to clear interrupt of L1-Cache preload-operation error. - */ - uint32_t l1_cache_pld_err_int_clr:1; - uint32_t reserved_12:1; - /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0; - * The bit is used to clear interrupt of Cache sync-operation error. - */ - uint32_t cache_sync_err_int_clr:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_cache_sync_preload_int_clr_reg_t; - -/** Type of l1_cache_sync_preload_int_raw register - * Sync Preload operation Interrupt raw register - */ -typedef union { - struct { - /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is - * done. - */ - uint32_t l1_icache0_pld_done_int_raw:1; - /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is - * done. - */ - uint32_t l1_icache1_pld_done_int_raw:1; - /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_raw:1; - /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_raw:1; - /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is - * done. - */ - uint32_t l1_cache_pld_done_int_raw:1; - uint32_t reserved_5:1; - /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation is done. - */ - uint32_t cache_sync_done_int_raw:1; - /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation - * error occurs. - */ - uint32_t l1_icache0_pld_err_int_raw:1; - /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation - * error occurs. - */ - uint32_t l1_icache1_pld_err_int_raw:1; - /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_raw:1; - /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_raw:1; - /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error - * occurs. - */ - uint32_t l1_cache_pld_err_int_raw:1; - uint32_t reserved_12:1; - /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation error - * occurs. - */ - uint32_t cache_sync_err_int_raw:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_cache_sync_preload_int_raw_reg_t; - -/** Type of l1_cache_sync_preload_int_st register - * L1-Cache Access Fail Interrupt status register - */ -typedef union { - struct { - /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ - uint32_t l1_icache0_pld_done_int_st:1; - /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ - uint32_t l1_icache1_pld_done_int_st:1; - /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_st:1; - /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_st:1; - /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-Cache - * preload-operation is done. - */ - uint32_t l1_cache_pld_done_int_st:1; - uint32_t reserved_5:1; - /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0; - * The bit indicates the status of the interrupt that occurs only when Cache - * sync-operation is done. - */ - uint32_t cache_sync_done_int_st:1; - /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_st:1; - /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_st:1; - /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_st:1; - /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_st:1; - /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; - * The bit indicates the status of the interrupt of L1-Cache preload-operation error. - */ - uint32_t l1_cache_pld_err_int_st:1; - uint32_t reserved_12:1; - /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0; - * The bit indicates the status of the interrupt of Cache sync-operation error. - */ - uint32_t cache_sync_err_int_st:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_cache_sync_preload_int_st_reg_t; - -/** Type of l2_cache_acs_cnt_int_ena register - * Cache Access Counter Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_ena:1; - /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_ena:1; - /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_ena:1; - /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_ena:1; - /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_ena:1; - /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_ena:1; - /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_ena:1; - /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_ena:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_l2_cache_acs_cnt_int_ena_reg_t; - -/** Type of l2_cache_acs_cnt_int_clr register - * Cache Access Counter Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_clr:1; - /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_clr:1; - /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_clr:1; - /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_clr:1; - /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_clr:1; - /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_clr:1; - /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_clr:1; - /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_clr:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_l2_cache_acs_cnt_int_clr_reg_t; - -/** Type of l2_cache_acs_cnt_int_raw register - * Cache Access Counter Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-ICache0. - */ - uint32_t l2_ibus0_ovf_int_raw:1; - /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-ICache1. - */ - uint32_t l2_ibus1_ovf_int_raw:1; - /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-ICache2. - */ - uint32_t l2_ibus2_ovf_int_raw:1; - /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-ICache3. - */ - uint32_t l2_ibus3_ovf_int_raw:1; - /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-DCache. - */ - uint32_t l2_dbus0_ovf_int_raw:1; - /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-DCache. - */ - uint32_t l2_dbus1_ovf_int_raw:1; - /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-DCache. - */ - uint32_t l2_dbus2_ovf_int_raw:1; - /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-DCache. - */ - uint32_t l2_dbus3_ovf_int_raw:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_l2_cache_acs_cnt_int_raw_reg_t; - -/** Type of l2_cache_acs_cnt_int_st register - * Cache Access Counter Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_st:1; - /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_st:1; - /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_st:1; - /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_st:1; - /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_st:1; - /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_st:1; - /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_st:1; - /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_st:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} extmem_l2_cache_acs_cnt_int_st_reg_t; - -/** Type of l2_cache_acs_fail_int_ena register - * Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to - * l1 cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_ena:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_acs_fail_int_ena_reg_t; - -/** Type of l2_cache_acs_fail_int_clr register - * L1-Cache Access Fail Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 - * cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_acs_fail_int_clr_reg_t; - -/** Type of l2_cache_acs_fail_int_raw register - * Cache Access Fail Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L2-Cache. - */ - uint32_t l2_cache_fail_int_raw:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_acs_fail_int_raw_reg_t; - -/** Type of l2_cache_acs_fail_int_st register - * Cache Access Fail Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L2-Cache due - * to l1 cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_st:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_acs_fail_int_st_reg_t; - -/** Type of l2_cache_sync_preload_int_ena register - * L1-Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation done. - */ - uint32_t l2_cache_pld_done_int_ena:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_ena:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} extmem_l2_cache_sync_preload_int_ena_reg_t; - -/** Type of l2_cache_sync_preload_int_clr register - * Sync Preload operation Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation - * is done. - */ - uint32_t l2_cache_pld_done_int_clr:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0; - * The bit is used to clear interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_clr:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} extmem_l2_cache_sync_preload_int_clr_reg_t; - -/** Type of l2_cache_sync_preload_int_raw register - * Sync Preload operation Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is - * done. - */ - uint32_t l2_cache_pld_done_int_raw:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error - * occurs. - */ - uint32_t l2_cache_pld_err_int_raw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} extmem_l2_cache_sync_preload_int_raw_reg_t; - -/** Type of l2_cache_sync_preload_int_st register - * L1-Cache Access Fail Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L2-Cache - * preload-operation is done. - */ - uint32_t l2_cache_pld_done_int_st:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0; - * The bit indicates the status of the interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_st:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} extmem_l2_cache_sync_preload_int_st_reg_t; - - -/** Group: Access Statistics registers */ -/** Type of l1_cache_acs_cnt_ctrl register - * Cache Access Counter enable and clear register - */ -typedef union { - struct { - /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable ibus0 counter in L1-ICache0. - */ - uint32_t l1_ibus0_cnt_ena:1; - /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable ibus1 counter in L1-ICache1. - */ - uint32_t l1_ibus1_cnt_ena:1; - /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_cnt_ena:1; - /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_cnt_ena:1; - /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable dbus0 counter in L1-DCache. - */ - uint32_t l1_bus0_cnt_ena:1; - /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; - * The bit is used to enable dbus1 counter in L1-DCache. - */ - uint32_t l1_bus1_cnt_ena:1; - /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_cnt_ena:1; - /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_cnt_ena:1; - uint32_t reserved_8:8; - /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0; - * The bit is used to clear ibus0 counter in L1-ICache0. - */ - uint32_t l1_ibus0_cnt_clr:1; - /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0; - * The bit is used to clear ibus1 counter in L1-ICache1. - */ - uint32_t l1_ibus1_cnt_clr:1; - /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_cnt_clr:1; - /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_cnt_clr:1; - /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; - * The bit is used to clear dbus0 counter in L1-DCache. - */ - uint32_t l1_bus0_cnt_clr:1; - /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; - * The bit is used to clear dbus1 counter in L1-DCache. - */ - uint32_t l1_bus1_cnt_clr:1; - /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_cnt_clr:1; - /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_cnt_clr:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} extmem_l1_cache_acs_cnt_ctrl_reg_t; - -/** Type of l1_ibus0_acs_hit_cnt register - * L1-ICache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus0_acs_hit_cnt_reg_t; - -/** Type of l1_ibus0_acs_miss_cnt register - * L1-ICache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus0_acs_miss_cnt_reg_t; - -/** Type of l1_ibus0_acs_conflict_cnt register - * L1-ICache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus0_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus0_acs_nxtlvl_cnt register - * L1-ICache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l1_ibus0_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t; - -/** Type of l1_ibus1_acs_hit_cnt register - * L1-ICache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus1_acs_hit_cnt_reg_t; - -/** Type of l1_ibus1_acs_miss_cnt register - * L1-ICache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus1_acs_miss_cnt_reg_t; - -/** Type of l1_ibus1_acs_conflict_cnt register - * L1-ICache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus1_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus1_acs_nxtlvl_cnt register - * L1-ICache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l1_ibus1_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t; - -/** Type of l1_ibus2_acs_hit_cnt register - * L1-ICache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus2_acs_hit_cnt_reg_t; - -/** Type of l1_ibus2_acs_miss_cnt register - * L1-ICache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus2_acs_miss_cnt_reg_t; - -/** Type of l1_ibus2_acs_conflict_cnt register - * L1-ICache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus2_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus2_acs_nxtlvl_cnt register - * L1-ICache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l1_ibus2_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t; - -/** Type of l1_ibus3_acs_hit_cnt register - * L1-ICache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus3_acs_hit_cnt_reg_t; - -/** Type of l1_ibus3_acs_miss_cnt register - * L1-ICache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus3_acs_miss_cnt_reg_t; - -/** Type of l1_ibus3_acs_conflict_cnt register - * L1-ICache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus3_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus3_acs_nxtlvl_cnt register - * L1-ICache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l1_ibus3_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t; - -/** Type of l1_bus0_acs_hit_cnt register - * L1-Cache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-Cache. - */ - uint32_t l1_bus0_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_bus0_acs_hit_cnt_reg_t; - -/** Type of l1_bus0_acs_miss_cnt register - * L1-Cache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-Cache. - */ - uint32_t l1_bus0_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_bus0_acs_miss_cnt_reg_t; - -/** Type of l1_bus0_acs_conflict_cnt register - * L1-Cache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-Cache. - */ - uint32_t l1_bus0_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_bus0_acs_conflict_cnt_reg_t; - -/** Type of l1_bus0_acs_nxtlvl_cnt register - * L1-Cache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus0 accessing L1-Cache. - */ - uint32_t l1_bus0_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t; - -/** Type of l1_bus1_acs_hit_cnt register - * L1-Cache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-Cache. - */ - uint32_t l1_bus1_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_bus1_acs_hit_cnt_reg_t; - -/** Type of l1_bus1_acs_miss_cnt register - * L1-Cache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-Cache. - */ - uint32_t l1_bus1_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_bus1_acs_miss_cnt_reg_t; - -/** Type of l1_bus1_acs_conflict_cnt register - * L1-Cache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-Cache. - */ - uint32_t l1_bus1_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_bus1_acs_conflict_cnt_reg_t; - -/** Type of l1_bus1_acs_nxtlvl_cnt register - * L1-Cache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus1 accessing L1-Cache. - */ - uint32_t l1_bus1_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t; - -/** Type of l1_dbus2_acs_hit_cnt register - * L1-DCache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus2_acs_hit_cnt_reg_t; - -/** Type of l1_dbus2_acs_miss_cnt register - * L1-DCache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus2_acs_miss_cnt_reg_t; - -/** Type of l1_dbus2_acs_conflict_cnt register - * L1-DCache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus2_acs_conflict_cnt_reg_t; - -/** Type of l1_dbus2_acs_nxtlvl_cnt register - * L1-DCache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ - uint32_t l1_dbus2_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t; - -/** Type of l1_dbus3_acs_hit_cnt register - * L1-DCache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_hit_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus3_acs_hit_cnt_reg_t; - -/** Type of l1_dbus3_acs_miss_cnt register - * L1-DCache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_miss_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus3_acs_miss_cnt_reg_t; - -/** Type of l1_dbus3_acs_conflict_cnt register - * L1-DCache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_conflict_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus3_acs_conflict_cnt_reg_t; - -/** Type of l1_dbus3_acs_nxtlvl_cnt register - * L1-DCache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ - uint32_t l1_dbus3_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_cache_acs_cnt_ctrl register - * Cache Access Counter enable and clear register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable ibus0 counter in L2-Cache. - */ - uint32_t l2_ibus0_cnt_ena:1; - /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable ibus1 counter in L2-Cache. - */ - uint32_t l2_ibus1_cnt_ena:1; - /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_cnt_ena:1; - /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_cnt_ena:1; - /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable dbus0 counter in L2-Cache. - */ - uint32_t l2_dbus0_cnt_ena:1; - /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0; - * The bit is used to enable dbus1 counter in L2-Cache. - */ - uint32_t l2_dbus1_cnt_ena:1; - /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_cnt_ena:1; - /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_cnt_ena:1; - uint32_t reserved_16:8; - /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0; - * The bit is used to clear ibus0 counter in L2-Cache. - */ - uint32_t l2_ibus0_cnt_clr:1; - /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0; - * The bit is used to clear ibus1 counter in L2-Cache. - */ - uint32_t l2_ibus1_cnt_clr:1; - /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_cnt_clr:1; - /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_cnt_clr:1; - /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0; - * The bit is used to clear dbus0 counter in L2-Cache. - */ - uint32_t l2_dbus0_cnt_clr:1; - /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0; - * The bit is used to clear dbus1 counter in L2-Cache. - */ - uint32_t l2_dbus1_cnt_clr:1; - /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_cnt_clr:1; - /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_cnt_clr:1; - }; - uint32_t val; -} extmem_l2_cache_acs_cnt_ctrl_reg_t; - -/** Type of l2_ibus0_acs_hit_cnt register - * L2-Cache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus0_acs_hit_cnt_reg_t; - -/** Type of l2_ibus0_acs_miss_cnt register - * L2-Cache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus0_acs_miss_cnt_reg_t; - -/** Type of l2_ibus0_acs_conflict_cnt register - * L2-Cache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache0 accesses - * L2-Cache due to bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus0_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus0_acs_nxtlvl_cnt register - * L2-Cache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_ibus1_acs_hit_cnt register - * L2-Cache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus1_acs_hit_cnt_reg_t; - -/** Type of l2_ibus1_acs_miss_cnt register - * L2-Cache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus1_acs_miss_cnt_reg_t; - -/** Type of l2_ibus1_acs_conflict_cnt register - * L2-Cache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache1 accesses - * L2-Cache due to bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus1_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus1_acs_nxtlvl_cnt register - * L2-Cache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_ibus2_acs_hit_cnt register - * L2-Cache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus2_acs_hit_cnt_reg_t; - -/** Type of l2_ibus2_acs_miss_cnt register - * L2-Cache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus2_acs_miss_cnt_reg_t; - -/** Type of l2_ibus2_acs_conflict_cnt register - * L2-Cache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache2 accesses - * L2-Cache due to bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus2_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus2_acs_nxtlvl_cnt register - * L2-Cache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_ibus3_acs_hit_cnt register - * L2-Cache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus3_acs_hit_cnt_reg_t; - -/** Type of l2_ibus3_acs_miss_cnt register - * L2-Cache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus3_acs_miss_cnt_reg_t; - -/** Type of l2_ibus3_acs_conflict_cnt register - * L2-Cache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache3 accesses - * L2-Cache due to bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus3_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus3_acs_nxtlvl_cnt register - * L2-Cache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_dbus0_acs_hit_cnt register - * L2-Cache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus0_acs_hit_cnt_reg_t; - -/** Type of l2_dbus0_acs_miss_cnt register - * L2-Cache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus0_acs_miss_cnt_reg_t; - -/** Type of l2_dbus0_acs_conflict_cnt register - * L2-Cache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus0_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus0_acs_nxtlvl_cnt register - * L2-Cache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_dbus1_acs_hit_cnt register - * L2-Cache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus1_acs_hit_cnt_reg_t; - -/** Type of l2_dbus1_acs_miss_cnt register - * L2-Cache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus1_acs_miss_cnt_reg_t; - -/** Type of l2_dbus1_acs_conflict_cnt register - * L2-Cache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus1_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus1_acs_nxtlvl_cnt register - * L2-Cache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_dbus2_acs_hit_cnt register - * L2-Cache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus2_acs_hit_cnt_reg_t; - -/** Type of l2_dbus2_acs_miss_cnt register - * L2-Cache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus2_acs_miss_cnt_reg_t; - -/** Type of l2_dbus2_acs_conflict_cnt register - * L2-Cache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus2_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus2_acs_nxtlvl_cnt register - * L2-Cache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t; - -/** Type of l2_dbus3_acs_hit_cnt register - * L2-Cache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_hit_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus3_acs_hit_cnt_reg_t; - -/** Type of l2_dbus3_acs_miss_cnt register - * L2-Cache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_miss_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus3_acs_miss_cnt_reg_t; - -/** Type of l2_dbus3_acs_conflict_cnt register - * L2-Cache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_conflict_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus3_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus3_acs_nxtlvl_cnt register - * L2-Cache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_nxtlvl_cnt:32; - }; - uint32_t val; -} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t; - - -/** Group: Access Fail Debug registers */ -/** Type of l1_icache0_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_id:16; - /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_attr:16; - }; - uint32_t val; -} extmem_l1_icache0_acs_fail_id_attr_reg_t; - -/** Type of l1_icache0_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_addr:32; - }; - uint32_t val; -} extmem_l1_icache0_acs_fail_addr_reg_t; - -/** Type of l1_icache1_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_id:16; - /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_attr:16; - }; - uint32_t val; -} extmem_l1_icache1_acs_fail_id_attr_reg_t; - -/** Type of l1_icache1_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_addr:32; - }; - uint32_t val; -} extmem_l1_icache1_acs_fail_addr_reg_t; - -/** Type of l1_icache2_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_id:16; - /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_attr:16; - }; - uint32_t val; -} extmem_l1_icache2_acs_fail_id_attr_reg_t; - -/** Type of l1_icache2_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_addr:32; - }; - uint32_t val; -} extmem_l1_icache2_acs_fail_addr_reg_t; - -/** Type of l1_icache3_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_id:16; - /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_attr:16; - }; - uint32_t val; -} extmem_l1_icache3_acs_fail_id_attr_reg_t; - -/** Type of l1_icache3_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_addr:32; - }; - uint32_t val; -} extmem_l1_icache3_acs_fail_addr_reg_t; - -/** Type of l1_cache_acs_fail_id_attr register - * L1-Cache Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache accesses L1-Cache. - */ - uint32_t l1_cache_fail_id:16; - /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache accesses L1-Cache. - */ - uint32_t l1_cache_fail_attr:16; - }; - uint32_t val; -} extmem_l1_cache_acs_fail_id_attr_reg_t; - -/** Type of l1_dcache_acs_fail_addr register - * L1-Cache Access Fail Address information register - */ -typedef union { - struct { - /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache accesses L1-Cache. - */ - uint32_t l1_cache_fail_addr:32; - }; - uint32_t val; -} extmem_l1_dcache_acs_fail_addr_reg_t; - -/** Type of l2_cache_acs_fail_id_attr register - * L2-Cache Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when L1-Cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_id:16; - /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when L1-Cache accesses L2-Cache - * due to cache accessing L1-Cache. - */ - uint32_t l2_cache_fail_attr:16; - }; - uint32_t val; -} extmem_l2_cache_acs_fail_id_attr_reg_t; - -/** Type of l2_cache_acs_fail_addr register - * L2-Cache Access Fail Address information register - */ -typedef union { - struct { - /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when L1-Cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_addr:32; - }; - uint32_t val; -} extmem_l2_cache_acs_fail_addr_reg_t; - - -/** Group: Operation Exception registers */ -/** Type of l1_cache_sync_preload_exception register - * Cache Sync/Preload Operation exception register - */ -typedef union { - struct { - /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache0. - */ - uint32_t l1_icache0_pld_err_code:2; - /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache1. - */ - uint32_t l1_icache1_pld_err_code:2; - /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_code:2; - /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_code:2; - /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; - * The value 2 is Only available which means preload size is error in L1-Cache. - */ - uint32_t l1_cache_pld_err_code:2; - uint32_t reserved_10:2; - /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0; - * The values 0-2 are available which means sync map, command conflict and size are - * error in Cache System. - */ - uint32_t cache_sync_err_code:2; - uint32_t reserved_14:18; - }; - uint32_t val; -} extmem_l1_cache_sync_preload_exception_reg_t; - -/** Type of l2_cache_sync_preload_exception register - * Cache Sync/Preload Operation exception register - */ -typedef union { - struct { - uint32_t reserved_0:10; - /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0; - * The value 2 is Only available which means preload size is error in L2-Cache. - */ - uint32_t l2_cache_pld_err_code:2; - uint32_t reserved_12:20; - }; - uint32_t val; -} extmem_l2_cache_sync_preload_exception_reg_t; - - -/** Group: Sync Reset control and configuration registers */ -/** Type of l1_cache_sync_rst_ctrl register - * Cache Sync Reset control register - */ -typedef union { - struct { - /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0; - * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l1_icache0_sync_rst:1; - /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0; - * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l1_icache1_sync_rst:1; - /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_sync_rst:1; - /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_sync_rst:1; - /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; - * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l1_cache_sync_rst:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_sync_rst_ctrl_reg_t; - -/** Type of l2_cache_sync_rst_ctrl register - * Cache Sync Reset control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0; - * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l2_cache_sync_rst:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_sync_rst_ctrl_reg_t; - - -/** Group: Preload Reset control and configuration registers */ -/** Type of l1_cache_preload_rst_ctrl register - * Cache Preload Reset control register - */ -typedef union { - struct { - /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0; - * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l1_icache0_pld_rst:1; - /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0; - * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l1_icache1_pld_rst:1; - /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_rst:1; - /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_rst:1; - /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; - * set this bit to reset preload-logic inside L1-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l1_cache_pld_rst:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_preload_rst_ctrl_reg_t; - -/** Type of l2_cache_preload_rst_ctrl register - * Cache Preload Reset control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0; - * set this bit to reset preload-logic inside L2-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l2_cache_pld_rst:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_preload_rst_ctrl_reg_t; - - -/** Group: Autoload buffer clear control and configuration registers */ -/** Type of l1_cache_autoload_buf_clr_ctrl register - * Cache Autoload buffer clear control register - */ -typedef union { - struct { - /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, - * autoload will not work in L1-ICache0. This bit should not be active when autoload - * works in L1-ICache0. - */ - uint32_t l1_icache0_ald_buf_clr:1; - /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, - * autoload will not work in L1-ICache1. This bit should not be active when autoload - * works in L1-ICache1. - */ - uint32_t l1_icache1_ald_buf_clr:1; - /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_ald_buf_clr:1; - /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_ald_buf_clr:1; - /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; - * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, - * autoload will not work in L1-Cache. This bit should not be active when autoload - * works in L1-Cache. - */ - uint32_t l1_cache_ald_buf_clr:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t; - -/** Type of l2_cache_autoload_buf_clr_ctrl register - * Cache Autoload buffer clear control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0; - * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, - * autoload will not work in L2-Cache. This bit should not be active when autoload - * works in L2-Cache. - */ - uint32_t l2_cache_ald_buf_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t; - - -/** Group: Unallocate request buffer clear registers */ -/** Type of l1_unallocate_buffer_clear register - * Unallocate request buffer clear registers - */ -typedef union { - struct { - /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responsed but not completed. - */ - uint32_t l1_icache0_unalloc_clr:1; - /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responsed but not completed. - */ - uint32_t l1_icache1_unalloc_clr:1; - /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_unalloc_clr:1; - /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_unalloc_clr:1; - /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responsed but not completed. - */ - uint32_t l1_cache_unalloc_clr:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} extmem_l1_unallocate_buffer_clear_reg_t; - -/** Type of l2_unallocate_buffer_clear register - * Unallocate request buffer clear registers - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responsed but not completed. - */ - uint32_t l2_cache_unalloc_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} extmem_l2_unallocate_buffer_clear_reg_t; - - -/** Group: Tag and Data Memory Access Control and configuration register */ -/** Type of l1_cache_object_ctrl register - * Cache Tag and Data memory Object control register - */ -typedef union { - struct { - /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0; - * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_icache0_tag_object:1; - /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0; - * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_icache1_tag_object:1; - /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_object:1; - /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_object:1; - /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; - * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_cache_tag_object:1; - uint32_t reserved_5:1; - /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0; - * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ - uint32_t l1_icache0_mem_object:1; - /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0; - * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ - uint32_t l1_icache1_mem_object:1; - /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_mem_object:1; - /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache3_mem_object:1; - /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; - * Set this bit to set L1-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_cache_mem_object:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} extmem_l1_cache_object_ctrl_reg_t; - -/** Type of l1_cache_way_object register - * Cache Tag and Data memory way register - */ -typedef union { - struct { - /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. - */ - uint32_t l1_cache_way_object:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} extmem_l1_cache_way_object_reg_t; - -/** Type of l1_cache_vaddr register - * Cache Vaddr register - */ -typedef union { - struct { - /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824; - * Those bits stores the virtual address which will decide where inside the specified - * tag memory object will be accessed. - */ - uint32_t l1_cache_vaddr:32; - }; - uint32_t val; -} extmem_l1_cache_vaddr_reg_t; - -/** Type of l1_cache_debug_bus register - * Cache Tag/data memory content register - */ -typedef union { - struct { - /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. - */ - uint32_t l1_cache_debug_bus:32; - }; - uint32_t val; -} extmem_l1_cache_debug_bus_reg_t; - -/** Type of l2_cache_object_ctrl register - * Cache Tag and Data memory Object control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0; - * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l2_cache_tag_object:1; - uint32_t reserved_6:5; - /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0; - * Set this bit to set L2-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l2_cache_mem_object:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} extmem_l2_cache_object_ctrl_reg_t; - -/** Type of l2_cache_way_object register - * Cache Tag and Data memory way register - */ -typedef union { - struct { - /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. - */ - uint32_t l2_cache_way_object:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} extmem_l2_cache_way_object_reg_t; - -/** Type of l2_cache_vaddr register - * Cache Vaddr register - */ -typedef union { - struct { - /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824; - * Those bits stores the virtual address which will decide where inside the specified - * tag memory object will be accessed. - */ - uint32_t l2_cache_vaddr:32; - }; - uint32_t val; -} extmem_l2_cache_vaddr_reg_t; - -/** Type of l2_cache_debug_bus register - * Cache Tag/data memory content register - */ -typedef union { - struct { - /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. - */ - uint32_t l2_cache_debug_bus:32; - }; - uint32_t val; -} extmem_l2_cache_debug_bus_reg_t; - - -/** Group: Split L1 and L2 registers */ -/** Type of level_split0 register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -typedef union { - struct { - /** level_split0 : HRO; bitpos: [31:0]; default: 600; - * Reserved - */ - uint32_t level_split0:32; - }; - uint32_t val; -} extmem_level_split0_reg_t; - -/** Type of level_split1 register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -typedef union { - struct { - /** level_split1 : HRO; bitpos: [31:0]; default: 936; - * Reserved - */ - uint32_t level_split1:32; - }; - uint32_t val; -} extmem_level_split1_reg_t; - - -/** Group: L2 cache access attribute control register */ -/** Type of l2_cache_access_attr_ctrl register - * L1 Cache access Attribute propagation control register - */ -typedef union { - struct { - /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1; - * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and - * non-cacheable. - */ - uint32_t l2_cache_access_force_cc:1; - /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1; - * Set this bit to force the request to l2 cache with write-back attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of write-back and - * write-through. - */ - uint32_t l2_cache_access_force_wb:1; - /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1; - * Set this bit to force the request to l2 cache with write-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * write-miss-allocate and write-miss-no-allocate. - */ - uint32_t l2_cache_access_force_wma:1; - /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1; - * Set this bit to force the request to l2 cache with read-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * read-miss-allocate and read-miss-no-allocate. - */ - uint32_t l2_cache_access_force_rma:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} extmem_l2_cache_access_attr_ctrl_reg_t; - - -/** Group: Clock Gate Control and configuration register */ -/** Type of clock_gate register - * Clock gate control register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * The bit is used to enable clock gate when access all registers in this module. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} extmem_clock_gate_reg_t; - - -/** Group: Redundancy register (Prepare for ECO) */ -/** Type of redundancy_sig0 register - * Cache redundancy signal 0 register - */ -typedef union { - struct { - /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t cache_redcy_sig0:32; - }; - uint32_t val; -} extmem_redundancy_sig0_reg_t; - -/** Type of redundancy_sig1 register - * Cache redundancy signal 1 register - */ -typedef union { - struct { - /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t cache_redcy_sig1:32; - }; - uint32_t val; -} extmem_redundancy_sig1_reg_t; - -/** Type of redundancy_sig2 register - * Cache redundancy signal 2 register - */ -typedef union { - struct { - /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t cache_redcy_sig2:32; - }; - uint32_t val; -} extmem_redundancy_sig2_reg_t; - -/** Type of redundancy_sig3 register - * Cache redundancy signal 3 register - */ -typedef union { - struct { - /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t cache_redcy_sig3:32; - }; - uint32_t val; -} extmem_redundancy_sig3_reg_t; - -/** Type of redundancy_sig4 register - * Cache redundancy signal 0 register - */ -typedef union { - struct { - /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t cache_redcy_sig4:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} extmem_redundancy_sig4_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35659904; - * version control register. Note that this default value stored is the latest date - * when the hardware logic was updated. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} extmem_date_reg_t; - - -typedef struct extmem_dev_s { - volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl; - volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl; - volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf; - volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf; - volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf; - volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf; - volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf; - volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf; - volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; - volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl; - volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl; - volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; - volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; - volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; - volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf; - volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr; - volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr; - volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size; - volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf; - volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr; - volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr; - volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size; - volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf; - volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr; - volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr; - volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size; - volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf; - volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr; - volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr; - volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size; - volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; - volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; - volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; - volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; - volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl; - volatile extmem_cache_lock_map_reg_t cache_lock_map; - volatile extmem_cache_lock_addr_reg_t cache_lock_addr; - volatile extmem_cache_lock_size_reg_t cache_lock_size; - volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl; - volatile extmem_cache_sync_map_reg_t cache_sync_map; - volatile extmem_cache_sync_addr_reg_t cache_sync_addr; - volatile extmem_cache_sync_size_reg_t cache_sync_size; - volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl; - volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr; - volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size; - volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl; - volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr; - volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size; - volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl; - volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr; - volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size; - volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl; - volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr; - volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size; - volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; - volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; - volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size; - volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl; - volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr; - volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size; - volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr; - volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size; - volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl; - volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr; - volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size; - volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr; - volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size; - volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl; - volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr; - volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size; - volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr; - volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size; - volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl; - volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr; - volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size; - volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr; - volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size; - volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; - volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; - volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; - volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; - volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; - volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr; - volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size; - volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr; - volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size; - volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; - volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; - volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; - volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st; - volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena; - volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr; - volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; - volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; - volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; - volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt; - volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt; - volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt; - volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt; - volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt; - volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt; - volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt; - volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt; - volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt; - volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt; - volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt; - volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt; - volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt; - volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt; - volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt; - volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt; - volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; - volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; - volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; - volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt; - volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; - volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; - volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; - volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt; - volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt; - volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt; - volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt; - volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt; - volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt; - volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt; - volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt; - volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt; - volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; - volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; - volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; - volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; - volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr; - volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr; - volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr; - volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr; - volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr; - volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; - volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena; - volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr; - volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw; - volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st; - volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception; - volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; - volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; - volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; - volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; - volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; - volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object; - volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr; - volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus; - volatile extmem_level_split0_reg_t level_split0; - volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl; - volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf; - volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf; - volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf; - volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl; - volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl; - volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl; - volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl; - volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf; - volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf; - volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf; - volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr; - volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr; - volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size; - volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl; - volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr; - volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size; - volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl; - volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr; - volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size; - volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr; - volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size; - volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr; - volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size; - volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr; - volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size; - volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena; - volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr; - volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw; - volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st; - volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena; - volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr; - volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw; - volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st; - volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl; - volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt; - volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt; - volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt; - volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt; - volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt; - volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt; - volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt; - volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt; - volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt; - volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt; - volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt; - volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt; - volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt; - volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt; - volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt; - volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt; - volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt; - volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt; - volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt; - volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt; - volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt; - volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt; - volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt; - volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt; - volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt; - volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt; - volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt; - volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt; - volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt; - volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt; - volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt; - volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt; - volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr; - volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr; - volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena; - volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr; - volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw; - volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st; - volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception; - volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl; - volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl; - volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl; - volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear; - volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl; - volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl; - volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object; - volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr; - volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus; - volatile extmem_level_split1_reg_t level_split1; - volatile extmem_clock_gate_reg_t clock_gate; - volatile extmem_redundancy_sig0_reg_t redundancy_sig0; - volatile extmem_redundancy_sig1_reg_t redundancy_sig1; - volatile extmem_redundancy_sig2_reg_t redundancy_sig2; - volatile extmem_redundancy_sig3_reg_t redundancy_sig3; - volatile extmem_redundancy_sig4_reg_t redundancy_sig4; - uint32_t reserved_3c4[14]; - volatile extmem_date_reg_t date; -} extmem_dev_t; - -extern extmem_dev_t EXTMEM; - -#ifndef __cplusplus -_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/gdma_channel.h b/components/soc/esp32p4/include/soc/gdma_channel.h index 785d920785..d2aa55b41e 100644 --- a/components/soc/esp32p4/include/soc/gdma_channel.h +++ b/components/soc/esp32p4/include/soc/gdma_channel.h @@ -5,13 +5,3 @@ */ #pragma once - -// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` -#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) -#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) -#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) -#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) -#define SOC_GDMA_TRIG_PERIPH_AES0 (6) -#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) -#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) -#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9) diff --git a/components/soc/esp32p4/include/soc/gpio_pins.h b/components/soc/esp32p4/include/soc/gpio_pins.h index 7731c871b0..6238eeffbb 100644 --- a/components/soc/esp32p4/include/soc/gpio_pins.h +++ b/components/soc/esp32p4/include/soc/gpio_pins.h @@ -11,8 +11,6 @@ extern "C" { #endif -#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) -#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C) #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/gpio_sd_reg.h b/components/soc/esp32p4/include/soc/gpio_sd_reg.h deleted file mode 100644 index 3173778fda..0000000000 --- a/components/soc/esp32p4/include/soc/gpio_sd_reg.h +++ /dev/null @@ -1,1455 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** GPIOSD_SIGMADELTA0_REG register - * Duty Cycle Configure Register of SDM0 - */ -#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA1_REG register - * Duty Cycle Configure Register of SDM1 - */ -#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA2_REG register - * Duty Cycle Configure Register of SDM2 - */ -#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA3_REG register - * Duty Cycle Configure Register of SDM3 - */ -#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA4_REG register - * Duty Cycle Configure Register of SDM4 - */ -#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA5_REG register - * Duty Cycle Configure Register of SDM5 - */ -#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA6_REG register - * Duty Cycle Configure Register of SDM6 - */ -#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA7_REG register - * Duty Cycle Configure Register of SDM7 - */ -#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 - -/** GPIOSD_SIGMADELTA_MISC_REG register - * MISC Register - */ -#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24) -/** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; - * Clock enable bit of sigma delta modulation. - */ -#define GPIOSD_FUNCTION_CLK_EN (BIT(30)) -#define GPIOSD_FUNCTION_CLK_EN_M (GPIOSD_FUNCTION_CLK_EN_V << GPIOSD_FUNCTION_CLK_EN_S) -#define GPIOSD_FUNCTION_CLK_EN_V 0x00000001U -#define GPIOSD_FUNCTION_CLK_EN_S 30 -/** GPIOSD_SPI_SWAP : R/W; bitpos: [31]; default: 0; - * Reserved. - */ -#define GPIOSD_SPI_SWAP (BIT(31)) -#define GPIOSD_SPI_SWAP_M (GPIOSD_SPI_SWAP_V << GPIOSD_SPI_SWAP_S) -#define GPIOSD_SPI_SWAP_V 0x00000001U -#define GPIOSD_SPI_SWAP_S 31 - -/** GPIOSD_GLITCH_FILTER_CH0_REG register - * Glitch Filter Configure Register of Channel0 - */ -#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_GLITCH_FILTER_CH1_REG register - * Glitch Filter Configure Register of Channel1 - */ -#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_GLITCH_FILTER_CH2_REG register - * Glitch Filter Configure Register of Channel2 - */ -#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_GLITCH_FILTER_CH3_REG register - * Glitch Filter Configure Register of Channel3 - */ -#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_GLITCH_FILTER_CH4_REG register - * Glitch Filter Configure Register of Channel4 - */ -#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_GLITCH_FILTER_CH5_REG register - * Glitch Filter Configure Register of Channel5 - */ -#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_GLITCH_FILTER_CH6_REG register - * Glitch Filter Configure Register of Channel6 - */ -#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_GLITCH_FILTER_CH7_REG register - * Glitch Filter Configure Register of Channel7 - */ -#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 - -/** GPIOSD_ETM_EVENT_CH0_CFG_REG register - * Etm Config register of Channel0 - */ -#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_EVENT_CH1_CFG_REG register - * Etm Config register of Channel1 - */ -#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_EVENT_CH2_CFG_REG register - * Etm Config register of Channel2 - */ -#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_EVENT_CH3_CFG_REG register - * Etm Config register of Channel3 - */ -#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_EVENT_CH4_CFG_REG register - * Etm Config register of Channel4 - */ -#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_EVENT_CH5_CFG_REG register - * Etm Config register of Channel5 - */ -#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_EVENT_CH6_CFG_REG register - * Etm Config register of Channel6 - */ -#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_EVENT_CH7_CFG_REG register - * Etm Config register of Channel7 - */ -#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 - -/** GPIOSD_ETM_TASK_P0_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0) -/** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO0_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO0_EN_M (GPIOSD_ETM_TASK_GPIO0_EN_V << GPIOSD_ETM_TASK_GPIO0_EN_S) -#define GPIOSD_ETM_TASK_GPIO0_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO0_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO0_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO0_SEL_M (GPIOSD_ETM_TASK_GPIO0_SEL_V << GPIOSD_ETM_TASK_GPIO0_SEL_S) -#define GPIOSD_ETM_TASK_GPIO0_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO0_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO1_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO1_EN_M (GPIOSD_ETM_TASK_GPIO1_EN_V << GPIOSD_ETM_TASK_GPIO1_EN_S) -#define GPIOSD_ETM_TASK_GPIO1_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO1_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO1_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO1_SEL_M (GPIOSD_ETM_TASK_GPIO1_SEL_V << GPIOSD_ETM_TASK_GPIO1_SEL_S) -#define GPIOSD_ETM_TASK_GPIO1_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO1_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO2_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO2_EN_M (GPIOSD_ETM_TASK_GPIO2_EN_V << GPIOSD_ETM_TASK_GPIO2_EN_S) -#define GPIOSD_ETM_TASK_GPIO2_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO2_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO2_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO2_SEL_M (GPIOSD_ETM_TASK_GPIO2_SEL_V << GPIOSD_ETM_TASK_GPIO2_SEL_S) -#define GPIOSD_ETM_TASK_GPIO2_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO2_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO3_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO3_EN_M (GPIOSD_ETM_TASK_GPIO3_EN_V << GPIOSD_ETM_TASK_GPIO3_EN_S) -#define GPIOSD_ETM_TASK_GPIO3_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO3_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO3_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO3_SEL_M (GPIOSD_ETM_TASK_GPIO3_SEL_V << GPIOSD_ETM_TASK_GPIO3_SEL_S) -#define GPIOSD_ETM_TASK_GPIO3_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO3_SEL_S 25 - -/** GPIOSD_ETM_TASK_P1_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4) -/** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO4_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO4_EN_M (GPIOSD_ETM_TASK_GPIO4_EN_V << GPIOSD_ETM_TASK_GPIO4_EN_S) -#define GPIOSD_ETM_TASK_GPIO4_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO4_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO4_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO4_SEL_M (GPIOSD_ETM_TASK_GPIO4_SEL_V << GPIOSD_ETM_TASK_GPIO4_SEL_S) -#define GPIOSD_ETM_TASK_GPIO4_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO4_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO5_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO5_EN_M (GPIOSD_ETM_TASK_GPIO5_EN_V << GPIOSD_ETM_TASK_GPIO5_EN_S) -#define GPIOSD_ETM_TASK_GPIO5_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO5_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO5_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO5_SEL_M (GPIOSD_ETM_TASK_GPIO5_SEL_V << GPIOSD_ETM_TASK_GPIO5_SEL_S) -#define GPIOSD_ETM_TASK_GPIO5_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO5_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO6_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO6_EN_M (GPIOSD_ETM_TASK_GPIO6_EN_V << GPIOSD_ETM_TASK_GPIO6_EN_S) -#define GPIOSD_ETM_TASK_GPIO6_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO6_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO6_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO6_SEL_M (GPIOSD_ETM_TASK_GPIO6_SEL_V << GPIOSD_ETM_TASK_GPIO6_SEL_S) -#define GPIOSD_ETM_TASK_GPIO6_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO6_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO7_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO7_EN_M (GPIOSD_ETM_TASK_GPIO7_EN_V << GPIOSD_ETM_TASK_GPIO7_EN_S) -#define GPIOSD_ETM_TASK_GPIO7_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO7_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO7_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO7_SEL_M (GPIOSD_ETM_TASK_GPIO7_SEL_V << GPIOSD_ETM_TASK_GPIO7_SEL_S) -#define GPIOSD_ETM_TASK_GPIO7_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO7_SEL_S 25 - -/** GPIOSD_ETM_TASK_P2_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8) -/** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO8_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO8_EN_M (GPIOSD_ETM_TASK_GPIO8_EN_V << GPIOSD_ETM_TASK_GPIO8_EN_S) -#define GPIOSD_ETM_TASK_GPIO8_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO8_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO8_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO8_SEL_M (GPIOSD_ETM_TASK_GPIO8_SEL_V << GPIOSD_ETM_TASK_GPIO8_SEL_S) -#define GPIOSD_ETM_TASK_GPIO8_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO8_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO9_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO9_EN_M (GPIOSD_ETM_TASK_GPIO9_EN_V << GPIOSD_ETM_TASK_GPIO9_EN_S) -#define GPIOSD_ETM_TASK_GPIO9_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO9_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO9_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO9_SEL_M (GPIOSD_ETM_TASK_GPIO9_SEL_V << GPIOSD_ETM_TASK_GPIO9_SEL_S) -#define GPIOSD_ETM_TASK_GPIO9_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO9_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO10_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO10_EN_M (GPIOSD_ETM_TASK_GPIO10_EN_V << GPIOSD_ETM_TASK_GPIO10_EN_S) -#define GPIOSD_ETM_TASK_GPIO10_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO10_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO10_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO10_SEL_M (GPIOSD_ETM_TASK_GPIO10_SEL_V << GPIOSD_ETM_TASK_GPIO10_SEL_S) -#define GPIOSD_ETM_TASK_GPIO10_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO10_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO11_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO11_EN_M (GPIOSD_ETM_TASK_GPIO11_EN_V << GPIOSD_ETM_TASK_GPIO11_EN_S) -#define GPIOSD_ETM_TASK_GPIO11_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO11_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO11_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO11_SEL_M (GPIOSD_ETM_TASK_GPIO11_SEL_V << GPIOSD_ETM_TASK_GPIO11_SEL_S) -#define GPIOSD_ETM_TASK_GPIO11_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO11_SEL_S 25 - -/** GPIOSD_ETM_TASK_P3_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac) -/** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO12_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO12_EN_M (GPIOSD_ETM_TASK_GPIO12_EN_V << GPIOSD_ETM_TASK_GPIO12_EN_S) -#define GPIOSD_ETM_TASK_GPIO12_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO12_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO12_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO12_SEL_M (GPIOSD_ETM_TASK_GPIO12_SEL_V << GPIOSD_ETM_TASK_GPIO12_SEL_S) -#define GPIOSD_ETM_TASK_GPIO12_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO12_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO13_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO13_EN_M (GPIOSD_ETM_TASK_GPIO13_EN_V << GPIOSD_ETM_TASK_GPIO13_EN_S) -#define GPIOSD_ETM_TASK_GPIO13_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO13_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO13_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO13_SEL_M (GPIOSD_ETM_TASK_GPIO13_SEL_V << GPIOSD_ETM_TASK_GPIO13_SEL_S) -#define GPIOSD_ETM_TASK_GPIO13_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO13_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO14_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO14_EN_M (GPIOSD_ETM_TASK_GPIO14_EN_V << GPIOSD_ETM_TASK_GPIO14_EN_S) -#define GPIOSD_ETM_TASK_GPIO14_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO14_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO14_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO14_SEL_M (GPIOSD_ETM_TASK_GPIO14_SEL_V << GPIOSD_ETM_TASK_GPIO14_SEL_S) -#define GPIOSD_ETM_TASK_GPIO14_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO14_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO15_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO15_EN_M (GPIOSD_ETM_TASK_GPIO15_EN_V << GPIOSD_ETM_TASK_GPIO15_EN_S) -#define GPIOSD_ETM_TASK_GPIO15_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO15_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO15_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO15_SEL_M (GPIOSD_ETM_TASK_GPIO15_SEL_V << GPIOSD_ETM_TASK_GPIO15_SEL_S) -#define GPIOSD_ETM_TASK_GPIO15_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO15_SEL_S 25 - -/** GPIOSD_ETM_TASK_P4_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0) -/** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO16_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO16_EN_M (GPIOSD_ETM_TASK_GPIO16_EN_V << GPIOSD_ETM_TASK_GPIO16_EN_S) -#define GPIOSD_ETM_TASK_GPIO16_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO16_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO16_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO16_SEL_M (GPIOSD_ETM_TASK_GPIO16_SEL_V << GPIOSD_ETM_TASK_GPIO16_SEL_S) -#define GPIOSD_ETM_TASK_GPIO16_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO16_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO17_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO17_EN_M (GPIOSD_ETM_TASK_GPIO17_EN_V << GPIOSD_ETM_TASK_GPIO17_EN_S) -#define GPIOSD_ETM_TASK_GPIO17_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO17_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO17_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO17_SEL_M (GPIOSD_ETM_TASK_GPIO17_SEL_V << GPIOSD_ETM_TASK_GPIO17_SEL_S) -#define GPIOSD_ETM_TASK_GPIO17_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO17_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO18_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO18_EN_M (GPIOSD_ETM_TASK_GPIO18_EN_V << GPIOSD_ETM_TASK_GPIO18_EN_S) -#define GPIOSD_ETM_TASK_GPIO18_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO18_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO18_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO18_SEL_M (GPIOSD_ETM_TASK_GPIO18_SEL_V << GPIOSD_ETM_TASK_GPIO18_SEL_S) -#define GPIOSD_ETM_TASK_GPIO18_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO18_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO19_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO19_EN_M (GPIOSD_ETM_TASK_GPIO19_EN_V << GPIOSD_ETM_TASK_GPIO19_EN_S) -#define GPIOSD_ETM_TASK_GPIO19_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO19_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO19_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO19_SEL_M (GPIOSD_ETM_TASK_GPIO19_SEL_V << GPIOSD_ETM_TASK_GPIO19_SEL_S) -#define GPIOSD_ETM_TASK_GPIO19_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO19_SEL_S 25 - -/** GPIOSD_ETM_TASK_P5_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4) -/** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO20_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO20_EN_M (GPIOSD_ETM_TASK_GPIO20_EN_V << GPIOSD_ETM_TASK_GPIO20_EN_S) -#define GPIOSD_ETM_TASK_GPIO20_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO20_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO20_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO20_SEL_M (GPIOSD_ETM_TASK_GPIO20_SEL_V << GPIOSD_ETM_TASK_GPIO20_SEL_S) -#define GPIOSD_ETM_TASK_GPIO20_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO20_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO21_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO21_EN_M (GPIOSD_ETM_TASK_GPIO21_EN_V << GPIOSD_ETM_TASK_GPIO21_EN_S) -#define GPIOSD_ETM_TASK_GPIO21_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO21_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO21_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO21_SEL_M (GPIOSD_ETM_TASK_GPIO21_SEL_V << GPIOSD_ETM_TASK_GPIO21_SEL_S) -#define GPIOSD_ETM_TASK_GPIO21_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO21_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO22_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO22_EN_M (GPIOSD_ETM_TASK_GPIO22_EN_V << GPIOSD_ETM_TASK_GPIO22_EN_S) -#define GPIOSD_ETM_TASK_GPIO22_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO22_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO22_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO22_SEL_M (GPIOSD_ETM_TASK_GPIO22_SEL_V << GPIOSD_ETM_TASK_GPIO22_SEL_S) -#define GPIOSD_ETM_TASK_GPIO22_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO22_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO23_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO23_EN_M (GPIOSD_ETM_TASK_GPIO23_EN_V << GPIOSD_ETM_TASK_GPIO23_EN_S) -#define GPIOSD_ETM_TASK_GPIO23_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO23_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO23_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO23_SEL_M (GPIOSD_ETM_TASK_GPIO23_SEL_V << GPIOSD_ETM_TASK_GPIO23_SEL_S) -#define GPIOSD_ETM_TASK_GPIO23_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO23_SEL_S 25 - -/** GPIOSD_ETM_TASK_P6_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8) -/** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO24_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO24_EN_M (GPIOSD_ETM_TASK_GPIO24_EN_V << GPIOSD_ETM_TASK_GPIO24_EN_S) -#define GPIOSD_ETM_TASK_GPIO24_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO24_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO24_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO24_SEL_M (GPIOSD_ETM_TASK_GPIO24_SEL_V << GPIOSD_ETM_TASK_GPIO24_SEL_S) -#define GPIOSD_ETM_TASK_GPIO24_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO24_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO25_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO25_EN_M (GPIOSD_ETM_TASK_GPIO25_EN_V << GPIOSD_ETM_TASK_GPIO25_EN_S) -#define GPIOSD_ETM_TASK_GPIO25_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO25_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO25_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO25_SEL_M (GPIOSD_ETM_TASK_GPIO25_SEL_V << GPIOSD_ETM_TASK_GPIO25_SEL_S) -#define GPIOSD_ETM_TASK_GPIO25_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO25_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO26_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO26_EN_M (GPIOSD_ETM_TASK_GPIO26_EN_V << GPIOSD_ETM_TASK_GPIO26_EN_S) -#define GPIOSD_ETM_TASK_GPIO26_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO26_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO26_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO26_SEL_M (GPIOSD_ETM_TASK_GPIO26_SEL_V << GPIOSD_ETM_TASK_GPIO26_SEL_S) -#define GPIOSD_ETM_TASK_GPIO26_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO26_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO27_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO27_EN_M (GPIOSD_ETM_TASK_GPIO27_EN_V << GPIOSD_ETM_TASK_GPIO27_EN_S) -#define GPIOSD_ETM_TASK_GPIO27_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO27_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO27_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO27_SEL_M (GPIOSD_ETM_TASK_GPIO27_SEL_V << GPIOSD_ETM_TASK_GPIO27_SEL_S) -#define GPIOSD_ETM_TASK_GPIO27_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO27_SEL_S 25 - -/** GPIOSD_ETM_TASK_P7_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc) -/** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO28_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO28_EN_M (GPIOSD_ETM_TASK_GPIO28_EN_V << GPIOSD_ETM_TASK_GPIO28_EN_S) -#define GPIOSD_ETM_TASK_GPIO28_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO28_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO28_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO28_SEL_M (GPIOSD_ETM_TASK_GPIO28_SEL_V << GPIOSD_ETM_TASK_GPIO28_SEL_S) -#define GPIOSD_ETM_TASK_GPIO28_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO28_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO29_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO29_EN_M (GPIOSD_ETM_TASK_GPIO29_EN_V << GPIOSD_ETM_TASK_GPIO29_EN_S) -#define GPIOSD_ETM_TASK_GPIO29_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO29_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO29_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO29_SEL_M (GPIOSD_ETM_TASK_GPIO29_SEL_V << GPIOSD_ETM_TASK_GPIO29_SEL_S) -#define GPIOSD_ETM_TASK_GPIO29_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO29_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO30_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO30_EN_M (GPIOSD_ETM_TASK_GPIO30_EN_V << GPIOSD_ETM_TASK_GPIO30_EN_S) -#define GPIOSD_ETM_TASK_GPIO30_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO30_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO30_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO30_SEL_M (GPIOSD_ETM_TASK_GPIO30_SEL_V << GPIOSD_ETM_TASK_GPIO30_SEL_S) -#define GPIOSD_ETM_TASK_GPIO30_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO30_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO31_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO31_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO31_EN_M (GPIOSD_ETM_TASK_GPIO31_EN_V << GPIOSD_ETM_TASK_GPIO31_EN_S) -#define GPIOSD_ETM_TASK_GPIO31_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO31_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO31_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO31_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO31_SEL_M (GPIOSD_ETM_TASK_GPIO31_SEL_V << GPIOSD_ETM_TASK_GPIO31_SEL_S) -#define GPIOSD_ETM_TASK_GPIO31_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO31_SEL_S 25 - -/** GPIOSD_ETM_TASK_P8_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0) -/** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO32_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO32_EN_M (GPIOSD_ETM_TASK_GPIO32_EN_V << GPIOSD_ETM_TASK_GPIO32_EN_S) -#define GPIOSD_ETM_TASK_GPIO32_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO32_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO32_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO32_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO32_SEL_M (GPIOSD_ETM_TASK_GPIO32_SEL_V << GPIOSD_ETM_TASK_GPIO32_SEL_S) -#define GPIOSD_ETM_TASK_GPIO32_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO32_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO33_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO33_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO33_EN_M (GPIOSD_ETM_TASK_GPIO33_EN_V << GPIOSD_ETM_TASK_GPIO33_EN_S) -#define GPIOSD_ETM_TASK_GPIO33_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO33_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO33_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO33_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO33_SEL_M (GPIOSD_ETM_TASK_GPIO33_SEL_V << GPIOSD_ETM_TASK_GPIO33_SEL_S) -#define GPIOSD_ETM_TASK_GPIO33_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO33_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO34_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO34_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO34_EN_M (GPIOSD_ETM_TASK_GPIO34_EN_V << GPIOSD_ETM_TASK_GPIO34_EN_S) -#define GPIOSD_ETM_TASK_GPIO34_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO34_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO34_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO34_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO34_SEL_M (GPIOSD_ETM_TASK_GPIO34_SEL_V << GPIOSD_ETM_TASK_GPIO34_SEL_S) -#define GPIOSD_ETM_TASK_GPIO34_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO34_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO35_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO35_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO35_EN_M (GPIOSD_ETM_TASK_GPIO35_EN_V << GPIOSD_ETM_TASK_GPIO35_EN_S) -#define GPIOSD_ETM_TASK_GPIO35_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO35_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO35_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO35_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO35_SEL_M (GPIOSD_ETM_TASK_GPIO35_SEL_V << GPIOSD_ETM_TASK_GPIO35_SEL_S) -#define GPIOSD_ETM_TASK_GPIO35_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO35_SEL_S 25 - -/** GPIOSD_ETM_TASK_P9_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4) -/** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO36_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO36_EN_M (GPIOSD_ETM_TASK_GPIO36_EN_V << GPIOSD_ETM_TASK_GPIO36_EN_S) -#define GPIOSD_ETM_TASK_GPIO36_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO36_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO36_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO36_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO36_SEL_M (GPIOSD_ETM_TASK_GPIO36_SEL_V << GPIOSD_ETM_TASK_GPIO36_SEL_S) -#define GPIOSD_ETM_TASK_GPIO36_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO36_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO37_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO37_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO37_EN_M (GPIOSD_ETM_TASK_GPIO37_EN_V << GPIOSD_ETM_TASK_GPIO37_EN_S) -#define GPIOSD_ETM_TASK_GPIO37_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO37_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO37_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO37_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO37_SEL_M (GPIOSD_ETM_TASK_GPIO37_SEL_V << GPIOSD_ETM_TASK_GPIO37_SEL_S) -#define GPIOSD_ETM_TASK_GPIO37_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO37_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO38_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO38_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO38_EN_M (GPIOSD_ETM_TASK_GPIO38_EN_V << GPIOSD_ETM_TASK_GPIO38_EN_S) -#define GPIOSD_ETM_TASK_GPIO38_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO38_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO38_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO38_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO38_SEL_M (GPIOSD_ETM_TASK_GPIO38_SEL_V << GPIOSD_ETM_TASK_GPIO38_SEL_S) -#define GPIOSD_ETM_TASK_GPIO38_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO38_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO39_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO39_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO39_EN_M (GPIOSD_ETM_TASK_GPIO39_EN_V << GPIOSD_ETM_TASK_GPIO39_EN_S) -#define GPIOSD_ETM_TASK_GPIO39_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO39_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO39_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO39_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO39_SEL_M (GPIOSD_ETM_TASK_GPIO39_SEL_V << GPIOSD_ETM_TASK_GPIO39_SEL_S) -#define GPIOSD_ETM_TASK_GPIO39_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO39_SEL_S 25 - -/** GPIOSD_ETM_TASK_P10_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8) -/** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO40_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO40_EN_M (GPIOSD_ETM_TASK_GPIO40_EN_V << GPIOSD_ETM_TASK_GPIO40_EN_S) -#define GPIOSD_ETM_TASK_GPIO40_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO40_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO40_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO40_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO40_SEL_M (GPIOSD_ETM_TASK_GPIO40_SEL_V << GPIOSD_ETM_TASK_GPIO40_SEL_S) -#define GPIOSD_ETM_TASK_GPIO40_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO40_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO41_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO41_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO41_EN_M (GPIOSD_ETM_TASK_GPIO41_EN_V << GPIOSD_ETM_TASK_GPIO41_EN_S) -#define GPIOSD_ETM_TASK_GPIO41_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO41_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO41_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO41_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO41_SEL_M (GPIOSD_ETM_TASK_GPIO41_SEL_V << GPIOSD_ETM_TASK_GPIO41_SEL_S) -#define GPIOSD_ETM_TASK_GPIO41_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO41_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO42_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO42_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO42_EN_M (GPIOSD_ETM_TASK_GPIO42_EN_V << GPIOSD_ETM_TASK_GPIO42_EN_S) -#define GPIOSD_ETM_TASK_GPIO42_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO42_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO42_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO42_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO42_SEL_M (GPIOSD_ETM_TASK_GPIO42_SEL_V << GPIOSD_ETM_TASK_GPIO42_SEL_S) -#define GPIOSD_ETM_TASK_GPIO42_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO42_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO43_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO43_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO43_EN_M (GPIOSD_ETM_TASK_GPIO43_EN_V << GPIOSD_ETM_TASK_GPIO43_EN_S) -#define GPIOSD_ETM_TASK_GPIO43_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO43_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO43_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO43_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO43_SEL_M (GPIOSD_ETM_TASK_GPIO43_SEL_V << GPIOSD_ETM_TASK_GPIO43_SEL_S) -#define GPIOSD_ETM_TASK_GPIO43_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO43_SEL_S 25 - -/** GPIOSD_ETM_TASK_P11_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc) -/** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO44_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO44_EN_M (GPIOSD_ETM_TASK_GPIO44_EN_V << GPIOSD_ETM_TASK_GPIO44_EN_S) -#define GPIOSD_ETM_TASK_GPIO44_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO44_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO44_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO44_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO44_SEL_M (GPIOSD_ETM_TASK_GPIO44_SEL_V << GPIOSD_ETM_TASK_GPIO44_SEL_S) -#define GPIOSD_ETM_TASK_GPIO44_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO44_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO45_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO45_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO45_EN_M (GPIOSD_ETM_TASK_GPIO45_EN_V << GPIOSD_ETM_TASK_GPIO45_EN_S) -#define GPIOSD_ETM_TASK_GPIO45_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO45_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO45_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO45_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO45_SEL_M (GPIOSD_ETM_TASK_GPIO45_SEL_V << GPIOSD_ETM_TASK_GPIO45_SEL_S) -#define GPIOSD_ETM_TASK_GPIO45_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO45_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO46_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO46_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO46_EN_M (GPIOSD_ETM_TASK_GPIO46_EN_V << GPIOSD_ETM_TASK_GPIO46_EN_S) -#define GPIOSD_ETM_TASK_GPIO46_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO46_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO46_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO46_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO46_SEL_M (GPIOSD_ETM_TASK_GPIO46_SEL_V << GPIOSD_ETM_TASK_GPIO46_SEL_S) -#define GPIOSD_ETM_TASK_GPIO46_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO46_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO47_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO47_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO47_EN_M (GPIOSD_ETM_TASK_GPIO47_EN_V << GPIOSD_ETM_TASK_GPIO47_EN_S) -#define GPIOSD_ETM_TASK_GPIO47_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO47_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO47_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO47_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO47_SEL_M (GPIOSD_ETM_TASK_GPIO47_SEL_V << GPIOSD_ETM_TASK_GPIO47_SEL_S) -#define GPIOSD_ETM_TASK_GPIO47_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO47_SEL_S 25 - -/** GPIOSD_ETM_TASK_P12_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0) -/** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO48_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO48_EN_M (GPIOSD_ETM_TASK_GPIO48_EN_V << GPIOSD_ETM_TASK_GPIO48_EN_S) -#define GPIOSD_ETM_TASK_GPIO48_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO48_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO48_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO48_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO48_SEL_M (GPIOSD_ETM_TASK_GPIO48_SEL_V << GPIOSD_ETM_TASK_GPIO48_SEL_S) -#define GPIOSD_ETM_TASK_GPIO48_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO48_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO49_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO49_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO49_EN_M (GPIOSD_ETM_TASK_GPIO49_EN_V << GPIOSD_ETM_TASK_GPIO49_EN_S) -#define GPIOSD_ETM_TASK_GPIO49_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO49_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO49_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO49_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO49_SEL_M (GPIOSD_ETM_TASK_GPIO49_SEL_V << GPIOSD_ETM_TASK_GPIO49_SEL_S) -#define GPIOSD_ETM_TASK_GPIO49_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO49_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO50_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO50_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO50_EN_M (GPIOSD_ETM_TASK_GPIO50_EN_V << GPIOSD_ETM_TASK_GPIO50_EN_S) -#define GPIOSD_ETM_TASK_GPIO50_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO50_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO50_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO50_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO50_SEL_M (GPIOSD_ETM_TASK_GPIO50_SEL_V << GPIOSD_ETM_TASK_GPIO50_SEL_S) -#define GPIOSD_ETM_TASK_GPIO50_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO50_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO51_EN : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO51_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO51_EN_M (GPIOSD_ETM_TASK_GPIO51_EN_V << GPIOSD_ETM_TASK_GPIO51_EN_S) -#define GPIOSD_ETM_TASK_GPIO51_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO51_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO51_SEL : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO51_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO51_SEL_M (GPIOSD_ETM_TASK_GPIO51_SEL_V << GPIOSD_ETM_TASK_GPIO51_SEL_S) -#define GPIOSD_ETM_TASK_GPIO51_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO51_SEL_S 25 - -/** GPIOSD_ETM_TASK_P13_CFG_REG register - * Etm Configure Register to decide which GPIO been chosen - */ -#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4) -/** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO52_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO52_EN_M (GPIOSD_ETM_TASK_GPIO52_EN_V << GPIOSD_ETM_TASK_GPIO52_EN_S) -#define GPIOSD_ETM_TASK_GPIO52_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO52_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO52_SEL : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO52_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO52_SEL_M (GPIOSD_ETM_TASK_GPIO52_SEL_V << GPIOSD_ETM_TASK_GPIO52_SEL_S) -#define GPIOSD_ETM_TASK_GPIO52_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO52_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO53_EN : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO53_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO53_EN_M (GPIOSD_ETM_TASK_GPIO53_EN_V << GPIOSD_ETM_TASK_GPIO53_EN_S) -#define GPIOSD_ETM_TASK_GPIO53_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO53_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO53_SEL : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO53_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO53_SEL_M (GPIOSD_ETM_TASK_GPIO53_SEL_V << GPIOSD_ETM_TASK_GPIO53_SEL_S) -#define GPIOSD_ETM_TASK_GPIO53_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO53_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO54_EN : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ -#define GPIOSD_ETM_TASK_GPIO54_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO54_EN_M (GPIOSD_ETM_TASK_GPIO54_EN_V << GPIOSD_ETM_TASK_GPIO54_EN_S) -#define GPIOSD_ETM_TASK_GPIO54_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO54_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO54_SEL : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ -#define GPIOSD_ETM_TASK_GPIO54_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO54_SEL_M (GPIOSD_ETM_TASK_GPIO54_SEL_V << GPIOSD_ETM_TASK_GPIO54_SEL_S) -#define GPIOSD_ETM_TASK_GPIO54_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO54_SEL_S 17 - -/** GPIOSD_VERSION_REG register - * Version Control Register - */ -#define GPIOSD_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc) -/** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952; - * Version control register. - */ -#define GPIOSD_GPIO_SD_DATE 0x0FFFFFFFU -#define GPIOSD_GPIO_SD_DATE_M (GPIOSD_GPIO_SD_DATE_V << GPIOSD_GPIO_SD_DATE_S) -#define GPIOSD_GPIO_SD_DATE_V 0x0FFFFFFFU -#define GPIOSD_GPIO_SD_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/gpio_sd_struct.h b/components/soc/esp32p4/include/soc/gpio_sd_struct.h deleted file mode 100644 index 54e9030a97..0000000000 --- a/components/soc/esp32p4/include/soc/gpio_sd_struct.h +++ /dev/null @@ -1,771 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: SDM Configure Registers */ -/** Type of sigmadeltan register - * Duty Cycle Configure Register of SDMn - */ -typedef union { - struct { - /** sd0_in : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ - uint32_t sd0_in:8; - /** sd0_prescale : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ - uint32_t sd0_prescale:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} gpiosd_sigmadeltan_reg_t; - -/** Type of sigmadelta_misc register - * MISC Register - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** function_clk_en : R/W; bitpos: [30]; default: 0; - * Clock enable bit of sigma delta modulation. - */ - uint32_t function_clk_en:1; - /** spi_swap : R/W; bitpos: [31]; default: 0; - * Reserved. - */ - uint32_t spi_swap:1; - }; - uint32_t val; -} gpiosd_sigmadelta_misc_reg_t; - - -/** Group: Glitch filter Configure Registers */ -/** Type of glitch_filter_chn register - * Glitch Filter Configure Register of Channeln - */ -typedef union { - struct { - /** filter_ch0_en : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ - uint32_t filter_ch0_en:1; - /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ - uint32_t filter_ch0_input_io_num:6; - /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ - uint32_t filter_ch0_window_thres:6; - /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ - uint32_t filter_ch0_window_width:6; - uint32_t reserved_19:13; - }; - uint32_t val; -} gpiosd_glitch_filter_chn_reg_t; - - -/** Group: Etm Configure Registers */ -/** Type of etm_event_chn_cfg register - * Etm Config register of Channeln - */ -typedef union { - struct { - /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ - uint32_t etm_ch0_event_sel:6; - uint32_t reserved_6:1; - /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ - uint32_t etm_ch0_event_en:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpiosd_etm_event_chn_cfg_reg_t; - -/** Type of etm_task_p0_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio0_en:1; - /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio0_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio1_en:1; - /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio1_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio2_en:1; - /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio2_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio3_en:1; - /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio3_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p0_cfg_reg_t; - -/** Type of etm_task_p1_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio4_en:1; - /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio4_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio5_en:1; - /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio5_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio6_en:1; - /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio6_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio7_en:1; - /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio7_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p1_cfg_reg_t; - -/** Type of etm_task_p2_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio8_en:1; - /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio8_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio9_en:1; - /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio9_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio10_en:1; - /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio10_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio11_en:1; - /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio11_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p2_cfg_reg_t; - -/** Type of etm_task_p3_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio12_en:1; - /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio12_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio13_en:1; - /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio13_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio14_en:1; - /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio14_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio15_en:1; - /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio15_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p3_cfg_reg_t; - -/** Type of etm_task_p4_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio16_en:1; - /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio16_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio17_en:1; - /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio17_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio18_en:1; - /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio18_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio19_en:1; - /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio19_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p4_cfg_reg_t; - -/** Type of etm_task_p5_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio20_en:1; - /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio20_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio21_en:1; - /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio21_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio22_en:1; - /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio22_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio23_en:1; - /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio23_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p5_cfg_reg_t; - -/** Type of etm_task_p6_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio24_en:1; - /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio24_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio25_en:1; - /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio25_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio26_en:1; - /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio26_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio27_en:1; - /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio27_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p6_cfg_reg_t; - -/** Type of etm_task_p7_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio28_en:1; - /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio28_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio29_en:1; - /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio29_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio30_en:1; - /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio30_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio31_en:1; - /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio31_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p7_cfg_reg_t; - -/** Type of etm_task_p8_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio32_en:1; - /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio32_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio33_en:1; - /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio33_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio34_en:1; - /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio34_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio35_en:1; - /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio35_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p8_cfg_reg_t; - -/** Type of etm_task_p9_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio36_en:1; - /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio36_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio37_en:1; - /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio37_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio38_en:1; - /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio38_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio39_en:1; - /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio39_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p9_cfg_reg_t; - -/** Type of etm_task_p10_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio40_en:1; - /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio40_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio41_en:1; - /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio41_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio42_en:1; - /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio42_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio43_en:1; - /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio43_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p10_cfg_reg_t; - -/** Type of etm_task_p11_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio44_en:1; - /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio44_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio45_en:1; - /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio45_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio46_en:1; - /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio46_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio47_en:1; - /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio47_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p11_cfg_reg_t; - -/** Type of etm_task_p12_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio48_en:1; - /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio48_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio49_en:1; - /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio49_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio50_en:1; - /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio50_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio51_en:1; - /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio51_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p12_cfg_reg_t; - -/** Type of etm_task_p13_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio52_en:1; - /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio52_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio53_en:1; - /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio53_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio54_en:1; - /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio54_sel:3; - uint32_t reserved_20:12; - }; - uint32_t val; -} gpiosd_etm_task_p13_cfg_reg_t; - - -/** Group: Version Register */ -/** Type of version register - * Version Control Register - */ -typedef union { - struct { - /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952; - * Version control register. - */ - uint32_t gpio_sd_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_version_reg_t; - - -typedef struct { - volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8]; - uint32_t reserved_020; - volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc; - uint32_t reserved_028[2]; - volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8]; - uint32_t reserved_050[4]; - volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_080[8]; - volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg; - volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg; - volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg; - volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg; - volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg; - volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg; - volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg; - volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg; - volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg; - volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg; - uint32_t reserved_0d8[9]; - volatile gpiosd_version_reg_t version; -} gpiosd_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h index 92d76b0086..cdb82686cc 100644 --- a/components/soc/esp32p4/include/soc/gpio_sig_map.h +++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h @@ -1,10 +1,9 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_GPIO_SIG_MAP_H_ -#define _SOC_GPIO_SIG_MAP_H_ +#pragma once #define SD_CARD_CCLK_2_PAD_OUT_IDX 0 #define SD_CARD_CCMD_2_PAD_IN_IDX 1 @@ -486,4 +485,3 @@ #define SIG_IN_FUNC254_IDX 254 #define SIG_IN_FUNC255_IDX 255 #define SIG_IN_FUNC255_IDX 255 -#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32p4/include/soc/hardware_lock_reg.h b/components/soc/esp32p4/include/soc/hardware_lock_reg.h deleted file mode 100644 index 87faa416d5..0000000000 --- a/components/soc/esp32p4/include/soc/hardware_lock_reg.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** ATOMIC_ADDR_LOCK_REG register - * hardware lock regsiter - */ -#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0) -/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0; - * read to acquire hardware lock, write to release hardware lock - */ -#define ATOMIC_LOCK 0x00000003U -#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S) -#define ATOMIC_LOCK_V 0x00000003U -#define ATOMIC_LOCK_S 0 - -/** ATOMIC_LR_ADDR_REG register - * gloable lr address regsiter - */ -#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4) -/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0; - * backup gloable address - */ -#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU -#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S) -#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU -#define ATOMIC_GLOABLE_LR_ADDR_S 0 - -/** ATOMIC_LR_VALUE_REG register - * gloable lr value regsiter - */ -#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8) -/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0; - * backup gloable value - */ -#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU -#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S) -#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU -#define ATOMIC_GLOABLE_LR_VALUE_S 0 - -/** ATOMIC_LOCK_STATUS_REG register - * lock status regsiter - */ -#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc) -/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0; - * read hareware lock status for debug - */ -#define ATOMIC_LOCK_STATUS 0x00000003U -#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S) -#define ATOMIC_LOCK_STATUS_V 0x00000003U -#define ATOMIC_LOCK_STATUS_S 0 - -/** ATOMIC_COUNTER_REG register - * wait counter register - */ -#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10) -/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0; - * delay counter - */ -#define ATOMIC_WAIT_COUNTER 0x0000FFFFU -#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S) -#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU -#define ATOMIC_WAIT_COUNTER_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/hardware_lock_struct.h b/components/soc/esp32p4/include/soc/hardware_lock_struct.h deleted file mode 100644 index 4f5f43663c..0000000000 --- a/components/soc/esp32p4/include/soc/hardware_lock_struct.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configuration registers */ -/** Type of addr_lock register - * hardware lock regsiter - */ -typedef union { - struct { - /** lock : R/W; bitpos: [1:0]; default: 0; - * read to acquire hardware lock, write to release hardware lock - */ - uint32_t lock:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} atomic_addr_lock_reg_t; - -/** Type of lr_addr register - * gloable lr address regsiter - */ -typedef union { - struct { - /** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0; - * backup gloable address - */ - uint32_t gloable_lr_addr:32; - }; - uint32_t val; -} atomic_lr_addr_reg_t; - -/** Type of lr_value register - * gloable lr value regsiter - */ -typedef union { - struct { - /** gloable_lr_value : R/W; bitpos: [31:0]; default: 0; - * backup gloable value - */ - uint32_t gloable_lr_value:32; - }; - uint32_t val; -} atomic_lr_value_reg_t; - -/** Type of lock_status register - * lock status regsiter - */ -typedef union { - struct { - /** lock_status : RO; bitpos: [1:0]; default: 0; - * read hareware lock status for debug - */ - uint32_t lock_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} atomic_lock_status_reg_t; - -/** Type of counter register - * wait counter register - */ -typedef union { - struct { - /** wait_counter : R/W; bitpos: [15:0]; default: 0; - * delay counter - */ - uint32_t wait_counter:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} atomic_counter_reg_t; - - -typedef struct atomic_dev_t { - volatile atomic_addr_lock_reg_t addr_lock; - volatile atomic_lr_addr_reg_t lr_addr; - volatile atomic_lr_value_reg_t lr_value; - volatile atomic_lock_status_reg_t lock_status; - volatile atomic_counter_reg_t counter; -} atomic_dev_t; - -extern atomic_dev_t ATOMIC_LOCKER; - -#ifndef __cplusplus -_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/hinf_reg.h b/components/soc/esp32p4/include/soc/hinf_reg.h deleted file mode 100644 index a5184fc97a..0000000000 --- a/components/soc/esp32p4/include/soc/hinf_reg.h +++ /dev/null @@ -1,647 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** HINF_CFG_DATA0_REG register - * Configure sdio cis content - */ -#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) -/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214; - * configure device id of function1 in cis - */ -#define HINF_DEVICE_ID_FN1 0x0000FFFFU -#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S) -#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU -#define HINF_DEVICE_ID_FN1_S 0 -/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146; - * configure user id of function1 in cis - */ -#define HINF_USER_ID_FN1 0x0000FFFFU -#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S) -#define HINF_USER_ID_FN1_V 0x0000FFFFU -#define HINF_USER_ID_FN1_S 16 - -/** HINF_CFG_DATA1_REG register - * SDIO configuration register - */ -#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) -/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1; - * Sdio clock enable - */ -#define HINF_SDIO_ENABLE (BIT(0)) -#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S) -#define HINF_SDIO_ENABLE_V 0x00000001U -#define HINF_SDIO_ENABLE_S 0 -/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0; - * sdio function1 io ready signal in cis - */ -#define HINF_SDIO_IOREADY1 (BIT(1)) -#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S) -#define HINF_SDIO_IOREADY1_V 0x00000001U -#define HINF_SDIO_IOREADY1_S 1 -/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0; - * Highspeed enable in cccr - */ -#define HINF_HIGHSPEED_ENABLE (BIT(2)) -#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S) -#define HINF_HIGHSPEED_ENABLE_V 0x00000001U -#define HINF_HIGHSPEED_ENABLE_S 2 -/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0; - * highspeed mode status in cccr - */ -#define HINF_HIGHSPEED_MODE (BIT(3)) -#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S) -#define HINF_HIGHSPEED_MODE_V 0x00000001U -#define HINF_HIGHSPEED_MODE_S 3 -/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1; - * sdio card detect enable - */ -#define HINF_SDIO_CD_ENABLE (BIT(4)) -#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S) -#define HINF_SDIO_CD_ENABLE_V 0x00000001U -#define HINF_SDIO_CD_ENABLE_S 4 -/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0; - * sdio function1 io ready signal in cis - */ -#define HINF_SDIO_IOREADY2 (BIT(5)) -#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S) -#define HINF_SDIO_IOREADY2_V 0x00000001U -#define HINF_SDIO_IOREADY2_S 5 -/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0; - * mask sdio interrupt in cccr, high active - */ -#define HINF_SDIO_INT_MASK (BIT(6)) -#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S) -#define HINF_SDIO_INT_MASK_V 0x00000001U -#define HINF_SDIO_INT_MASK_S 6 -/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0; - * ioe2 status in cccr - */ -#define HINF_IOENABLE2 (BIT(7)) -#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S) -#define HINF_IOENABLE2_V 0x00000001U -#define HINF_IOENABLE2_S 7 -/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0; - * card disable status in cccr - */ -#define HINF_CD_DISABLE (BIT(8)) -#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S) -#define HINF_CD_DISABLE_V 0x00000001U -#define HINF_CD_DISABLE_S 8 -/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0; - * function1 eps status in fbr - */ -#define HINF_FUNC1_EPS (BIT(9)) -#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S) -#define HINF_FUNC1_EPS_V 0x00000001U -#define HINF_FUNC1_EPS_S 9 -/** HINF_EMP : RO; bitpos: [10]; default: 0; - * empc status in cccr - */ -#define HINF_EMP (BIT(10)) -#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S) -#define HINF_EMP_V 0x00000001U -#define HINF_EMP_S 10 -/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0; - * ioe1 status in cccr - */ -#define HINF_IOENABLE1 (BIT(11)) -#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S) -#define HINF_IOENABLE1_V 0x00000001U -#define HINF_IOENABLE1_S 11 -/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562; - * sdio version in cccr - */ -#define HINF_SDIO_VER 0x00000FFFU -#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S) -#define HINF_SDIO_VER_V 0x00000FFFU -#define HINF_SDIO_VER_S 12 -/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0; - * function2 eps status in fbr - */ -#define HINF_FUNC2_EPS (BIT(24)) -#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S) -#define HINF_FUNC2_EPS_V 0x00000001U -#define HINF_FUNC2_EPS_S 24 -/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0; - * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat - * in delayed cycles control,0:no delay, 1:delay 1 cycle. - * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed - * mode. - * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when - * [12]=0,posedge when highspeed mode enable. - * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. - * [28]: sdio data pad pull up enable - */ -#define HINF_SDIO20_CONF 0x0000007FU -#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S) -#define HINF_SDIO20_CONF_V 0x0000007FU -#define HINF_SDIO20_CONF_S 25 - -/** HINF_CFG_TIMING_REG register - * Timing configuration registers - */ -#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8) -/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2; - * configure Ncrc parameter in sdr50/104 mode, no more than 6. - */ -#define HINF_NCRC 0x00000007U -#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S) -#define HINF_NCRC_V 0x00000007U -#define HINF_NCRC_S 0 -/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2; - * configure cycles to lower cmd after voltage is changed to 1.8V. - */ -#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU -#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S) -#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU -#define HINF_PST_END_CMD_LOW_VALUE_S 3 -/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2; - * configure cycles to lower data after voltage is changed to 1.8V. - */ -#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU -#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S) -#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU -#define HINF_PST_END_DATA_LOW_VALUE_S 10 -/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400; - * Configure the number of cycles of module clk to judge sdclk has stopped - */ -#define HINF_SDCLK_STOP_THRES 0x000007FFU -#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S) -#define HINF_SDCLK_STOP_THRES_V 0x000007FFU -#define HINF_SDCLK_STOP_THRES_S 16 -/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1; - * module clk divider to sample sdclk - */ -#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU -#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S) -#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU -#define HINF_SAMPLE_CLK_DIVIDER_S 28 - -/** HINF_CFG_UPDATE_REG register - * update sdio configurations - */ -#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc) -/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0; - * update the timing configurations - */ -#define HINF_CONF_UPDATE (BIT(0)) -#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S) -#define HINF_CONF_UPDATE_V 0x00000001U -#define HINF_CONF_UPDATE_S 0 - -/** HINF_CFG_DATA7_REG register - * SDIO configuration register - */ -#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c) -/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0; - * configure cis addr 318 and 574 - */ -#define HINF_PIN_STATE 0x000000FFU -#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S) -#define HINF_PIN_STATE_V 0x000000FFU -#define HINF_PIN_STATE_S 0 -/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0; - * configure cis addr 312, 315, 568 and 571 - */ -#define HINF_CHIP_STATE 0x000000FFU -#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S) -#define HINF_CHIP_STATE_V 0x000000FFU -#define HINF_CHIP_STATE_S 8 -/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0; - * soft reset control for sdio module - */ -#define HINF_SDIO_RST (BIT(16)) -#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S) -#define HINF_SDIO_RST_V 0x00000001U -#define HINF_SDIO_RST_S 16 -/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1; - * sdio io ready, high enable - */ -#define HINF_SDIO_IOREADY0 (BIT(17)) -#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S) -#define HINF_SDIO_IOREADY0_V 0x00000001U -#define HINF_SDIO_IOREADY0_S 17 -/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0; - * sdio memory power down, high active - */ -#define HINF_SDIO_MEM_PD (BIT(18)) -#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S) -#define HINF_SDIO_MEM_PD_V 0x00000001U -#define HINF_SDIO_MEM_PD_S 18 -/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0; - * enable sdio interrupt on data1 line - */ -#define HINF_ESDIO_DATA1_INT_EN (BIT(19)) -#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S) -#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U -#define HINF_ESDIO_DATA1_INT_EN_S 19 -/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0; - * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V - */ -#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20)) -#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S) -#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U -#define HINF_SDIO_SWITCH_VOLT_SW_S 20 -/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0; - * enable block length to be fixed to 512 bytes in ddr50 mode - */ -#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21)) -#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S) -#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U -#define HINF_DDR50_BLK_LEN_FIX_EN_S 21 -/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0; - * sdio apb clock for configuration force on control:0-gating,1-force on. - */ -#define HINF_CLK_EN (BIT(22)) -#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S) -#define HINF_CLK_EN_V 0x00000001U -#define HINF_CLK_EN_S 22 -/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1; - * configure if support sdr50 mode in cccr - */ -#define HINF_SDDR50 (BIT(23)) -#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S) -#define HINF_SDDR50_V 0x00000001U -#define HINF_SDDR50_S 23 -/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1; - * configure if support sdr104 mode in cccr - */ -#define HINF_SSDR104 (BIT(24)) -#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S) -#define HINF_SSDR104_V 0x00000001U -#define HINF_SSDR104_S 24 -/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1; - * configure if support ddr50 mode in cccr - */ -#define HINF_SSDR50 (BIT(25)) -#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S) -#define HINF_SSDR50_V 0x00000001U -#define HINF_SSDR50_S 25 -/** HINF_SDTD : R/W; bitpos: [26]; default: 0; - * configure if support driver type D in cccr - */ -#define HINF_SDTD (BIT(26)) -#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S) -#define HINF_SDTD_V 0x00000001U -#define HINF_SDTD_S 26 -/** HINF_SDTA : R/W; bitpos: [27]; default: 0; - * configure if support driver type A in cccr - */ -#define HINF_SDTA (BIT(27)) -#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S) -#define HINF_SDTA_V 0x00000001U -#define HINF_SDTA_S 27 -/** HINF_SDTC : R/W; bitpos: [28]; default: 0; - * configure if support driver type C in cccr - */ -#define HINF_SDTC (BIT(28)) -#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S) -#define HINF_SDTC_V 0x00000001U -#define HINF_SDTC_S 28 -/** HINF_SAI : R/W; bitpos: [29]; default: 1; - * configure if support asynchronous interrupt in cccr - */ -#define HINF_SAI (BIT(29)) -#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S) -#define HINF_SAI_V 0x00000001U -#define HINF_SAI_S 29 -/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0; - * clear sdio_wake_up signal after the chip wakes up - */ -#define HINF_SDIO_WAKEUP_CLR (BIT(30)) -#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S) -#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U -#define HINF_SDIO_WAKEUP_CLR_S 30 - -/** HINF_CIS_CONF_W0_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20) -/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 39~36 - */ -#define HINF_CIS_CONF_W0 0xFFFFFFFFU -#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S) -#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W0_S 0 - -/** HINF_CIS_CONF_W1_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24) -/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 43~40 - */ -#define HINF_CIS_CONF_W1 0xFFFFFFFFU -#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S) -#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W1_S 0 - -/** HINF_CIS_CONF_W2_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28) -/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 47~44 - */ -#define HINF_CIS_CONF_W2 0xFFFFFFFFU -#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S) -#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W2_S 0 - -/** HINF_CIS_CONF_W3_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c) -/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 51~48 - */ -#define HINF_CIS_CONF_W3 0xFFFFFFFFU -#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S) -#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W3_S 0 - -/** HINF_CIS_CONF_W4_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30) -/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 55~52 - */ -#define HINF_CIS_CONF_W4 0xFFFFFFFFU -#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S) -#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W4_S 0 - -/** HINF_CIS_CONF_W5_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34) -/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 59~56 - */ -#define HINF_CIS_CONF_W5 0xFFFFFFFFU -#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S) -#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W5_S 0 - -/** HINF_CIS_CONF_W6_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38) -/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 63~60 - */ -#define HINF_CIS_CONF_W6 0xFFFFFFFFU -#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S) -#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W6_S 0 - -/** HINF_CIS_CONF_W7_REG register - * SDIO cis configuration register - */ -#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c) -/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 67~64 - */ -#define HINF_CIS_CONF_W7 0xFFFFFFFFU -#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S) -#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU -#define HINF_CIS_CONF_W7_S 0 - -/** HINF_CFG_DATA16_REG register - * SDIO cis configuration register - */ -#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) -/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583; - * configure device id of function2 in cis - */ -#define HINF_DEVICE_ID_FN2 0x0000FFFFU -#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S) -#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU -#define HINF_DEVICE_ID_FN2_S 0 -/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146; - * configure user id of function2 in cis - */ -#define HINF_USER_ID_FN2 0x0000FFFFU -#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S) -#define HINF_USER_ID_FN2_V 0x0000FFFFU -#define HINF_USER_ID_FN2_S 16 - -/** HINF_CFG_UHS1_INT_MODE_REG register - * configure int to start and end ahead of time in uhs1 mode - */ -#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44) -/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0; - * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ -#define HINF_INTOE_END_AHEAD_MODE 0x00000003U -#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S) -#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U -#define HINF_INTOE_END_AHEAD_MODE_S 0 -/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0; - * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ -#define HINF_INT_END_AHEAD_MODE 0x00000003U -#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S) -#define HINF_INT_END_AHEAD_MODE_V 0x00000003U -#define HINF_INT_END_AHEAD_MODE_S 2 -/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0; - * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ -#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U -#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S) -#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U -#define HINF_INTOE_ST_AHEAD_MODE_S 4 -/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0; - * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ -#define HINF_INT_ST_AHEAD_MODE 0x00000003U -#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S) -#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U -#define HINF_INT_ST_AHEAD_MODE_S 6 - -/** HINF_CONF_STATUS_REG register - * func0 config0 status - */ -#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54) -/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0; - * func0 config0 (addr: 0x20f0 ) status - */ -#define HINF_FUNC0_CONFIG0 0x000000FFU -#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S) -#define HINF_FUNC0_CONFIG0_V 0x000000FFU -#define HINF_FUNC0_CONFIG0_S 0 -/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0; - * sdr25 status - */ -#define HINF_SDR25_ST (BIT(8)) -#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S) -#define HINF_SDR25_ST_V 0x00000001U -#define HINF_SDR25_ST_S 8 -/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0; - * sdr50 status - */ -#define HINF_SDR50_ST (BIT(9)) -#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S) -#define HINF_SDR50_ST_V 0x00000001U -#define HINF_SDR50_ST_S 9 -/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0; - * sdr104 status - */ -#define HINF_SDR104_ST (BIT(10)) -#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S) -#define HINF_SDR104_ST_V 0x00000001U -#define HINF_SDR104_ST_S 10 -/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0; - * ddr50 status - */ -#define HINF_DDR50_ST (BIT(11)) -#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S) -#define HINF_DDR50_ST_V 0x00000001U -#define HINF_DDR50_ST_S 11 -/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0; - * tune_st fsm status - */ -#define HINF_TUNE_ST 0x00000007U -#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S) -#define HINF_TUNE_ST_V 0x00000007U -#define HINF_TUNE_ST_S 12 -/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0; - * sdio switch voltage status:0-3.3V, 1-1.8V. - */ -#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15)) -#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S) -#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U -#define HINF_SDIO_SWITCH_VOLT_ST_S 15 -/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0; - * sdio switch voltage ldo ready - */ -#define HINF_SDIO_SWITCH_END (BIT(16)) -#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S) -#define HINF_SDIO_SWITCH_END_V 0x00000001U -#define HINF_SDIO_SWITCH_END_S 16 - -/** HINF_SDIO_SLAVE_ECO_LOW_REG register - * sdio_slave redundant control registers - */ -#define HINF_SDIO_SLAVE_ECO_LOW_REG (DR_REG_HINF_BASE + 0xa4) -/** HINF_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; - * redundant registers for sdio_slave - */ -#define HINF_RDN_ECO_LOW 0xFFFFFFFFU -#define HINF_RDN_ECO_LOW_M (HINF_RDN_ECO_LOW_V << HINF_RDN_ECO_LOW_S) -#define HINF_RDN_ECO_LOW_V 0xFFFFFFFFU -#define HINF_RDN_ECO_LOW_S 0 - -/** HINF_SDIO_SLAVE_ECO_HIGH_REG register - * sdio_slave redundant control registers - */ -#define HINF_SDIO_SLAVE_ECO_HIGH_REG (DR_REG_HINF_BASE + 0xa8) -/** HINF_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; - * redundant registers for sdio_slave - */ -#define HINF_RDN_ECO_HIGH 0xFFFFFFFFU -#define HINF_RDN_ECO_HIGH_M (HINF_RDN_ECO_HIGH_V << HINF_RDN_ECO_HIGH_S) -#define HINF_RDN_ECO_HIGH_V 0xFFFFFFFFU -#define HINF_RDN_ECO_HIGH_S 0 - -/** HINF_SDIO_SLAVE_ECO_CONF_REG register - * sdio_slave redundant control registers - */ -#define HINF_SDIO_SLAVE_ECO_CONF_REG (DR_REG_HINF_BASE + 0xac) -/** HINF_SDIO_SLAVE_RDN_RESULT : RO; bitpos: [0]; default: 0; - * redundant registers for sdio_slave - */ -#define HINF_SDIO_SLAVE_RDN_RESULT (BIT(0)) -#define HINF_SDIO_SLAVE_RDN_RESULT_M (HINF_SDIO_SLAVE_RDN_RESULT_V << HINF_SDIO_SLAVE_RDN_RESULT_S) -#define HINF_SDIO_SLAVE_RDN_RESULT_V 0x00000001U -#define HINF_SDIO_SLAVE_RDN_RESULT_S 0 -/** HINF_SDIO_SLAVE_RDN_ENA : R/W; bitpos: [1]; default: 0; - * redundant registers for sdio_slave - */ -#define HINF_SDIO_SLAVE_RDN_ENA (BIT(1)) -#define HINF_SDIO_SLAVE_RDN_ENA_M (HINF_SDIO_SLAVE_RDN_ENA_V << HINF_SDIO_SLAVE_RDN_ENA_S) -#define HINF_SDIO_SLAVE_RDN_ENA_V 0x00000001U -#define HINF_SDIO_SLAVE_RDN_ENA_S 1 -/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT : RO; bitpos: [2]; default: 0; - * redundant registers for sdio_slave - */ -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT (BIT(2)) -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S) -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V 0x00000001U -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S 2 -/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA : R/W; bitpos: [3]; default: 0; - * redundant registers for sdio_slave - */ -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA (BIT(3)) -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S) -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V 0x00000001U -#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S 3 -/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT : RO; bitpos: [4]; default: 0; - * redundant registers for sdio_slave - */ -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT (BIT(4)) -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S) -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V 0x00000001U -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S 4 -/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA : R/W; bitpos: [5]; default: 0; - * redundant registers for sdio_slave - */ -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA (BIT(5)) -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S) -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V 0x00000001U -#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S 5 - -/** HINF_SDIO_SLAVE_LDO_CONF_REG register - * sdio slave ldo control register - */ -#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0) -/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0; - * control ldo ready signal by sdio slave itself - */ -#define HINF_LDO_READY_CTL_IN_EN (BIT(0)) -#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S) -#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U -#define HINF_LDO_READY_CTL_IN_EN_S 0 -/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10; - * configure ldo ready counting threshold value, the actual counting target is - * 2^(ldo_ready_thres)-1 - */ -#define HINF_LDO_READY_THRES 0x0000001FU -#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S) -#define HINF_LDO_READY_THRES_V 0x0000001FU -#define HINF_LDO_READY_THRES_S 1 -/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0; - * ignore ldo ready signal - */ -#define HINF_LDO_READY_IGNORE_EN (BIT(6)) -#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S) -#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U -#define HINF_LDO_READY_IGNORE_EN_S 6 - -/** HINF_SDIO_DATE_REG register - * ******* Description *********** - */ -#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc) -/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208; - * sdio version date. - */ -#define HINF_SDIO_DATE 0xFFFFFFFFU -#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S) -#define HINF_SDIO_DATE_V 0xFFFFFFFFU -#define HINF_SDIO_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/hinf_struct.h b/components/soc/esp32p4/include/soc/hinf_struct.h deleted file mode 100644 index 858db7b848..0000000000 --- a/components/soc/esp32p4/include/soc/hinf_struct.h +++ /dev/null @@ -1,555 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration registers */ -/** Type of cfg_data0 register - * Configure sdio cis content - */ -typedef union { - struct { - /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214; - * configure device id of function1 in cis - */ - uint32_t device_id_fn1:16; - /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146; - * configure user id of function1 in cis - */ - uint32_t user_id_fn1:16; - }; - uint32_t val; -} hinf_cfg_data0_reg_t; - -/** Type of cfg_data1 register - * SDIO configuration register - */ -typedef union { - struct { - /** sdio_enable : R/W; bitpos: [0]; default: 1; - * Sdio clock enable - */ - uint32_t sdio_enable:1; - /** sdio_ioready1 : R/W; bitpos: [1]; default: 0; - * sdio function1 io ready signal in cis - */ - uint32_t sdio_ioready1:1; - /** highspeed_enable : R/W; bitpos: [2]; default: 0; - * Highspeed enable in cccr - */ - uint32_t highspeed_enable:1; - /** highspeed_mode : RO; bitpos: [3]; default: 0; - * highspeed mode status in cccr - */ - uint32_t highspeed_mode:1; - /** sdio_cd_enable : R/W; bitpos: [4]; default: 1; - * sdio card detect enable - */ - uint32_t sdio_cd_enable:1; - /** sdio_ioready2 : R/W; bitpos: [5]; default: 0; - * sdio function1 io ready signal in cis - */ - uint32_t sdio_ioready2:1; - /** sdio_int_mask : R/W; bitpos: [6]; default: 0; - * mask sdio interrupt in cccr, high active - */ - uint32_t sdio_int_mask:1; - /** ioenable2 : RO; bitpos: [7]; default: 0; - * ioe2 status in cccr - */ - uint32_t ioenable2:1; - /** cd_disable : RO; bitpos: [8]; default: 0; - * card disable status in cccr - */ - uint32_t cd_disable:1; - /** func1_eps : RO; bitpos: [9]; default: 0; - * function1 eps status in fbr - */ - uint32_t func1_eps:1; - /** emp : RO; bitpos: [10]; default: 0; - * empc status in cccr - */ - uint32_t emp:1; - /** ioenable1 : RO; bitpos: [11]; default: 0; - * ioe1 status in cccr - */ - uint32_t ioenable1:1; - /** sdio_ver : R/W; bitpos: [23:12]; default: 562; - * sdio version in cccr - */ - uint32_t sdio_ver:12; - /** func2_eps : RO; bitpos: [24]; default: 0; - * function2 eps status in fbr - */ - uint32_t func2_eps:1; - /** sdio20_conf : R/W; bitpos: [31:25]; default: 0; - * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat - * in delayed cycles control,0:no delay, 1:delay 1 cycle. - * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed - * mode. - * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when - * [12]=0,posedge when highspeed mode enable. - * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. - * [28]: sdio data pad pull up enable - */ - uint32_t sdio20_conf:7; - }; - uint32_t val; -} hinf_cfg_data1_reg_t; - -/** Type of cfg_timing register - * Timing configuration registers - */ -typedef union { - struct { - /** ncrc : R/W; bitpos: [2:0]; default: 2; - * configure Ncrc parameter in sdr50/104 mode, no more than 6. - */ - uint32_t ncrc:3; - /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2; - * configure cycles to lower cmd after voltage is changed to 1.8V. - */ - uint32_t pst_end_cmd_low_value:7; - /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2; - * configure cycles to lower data after voltage is changed to 1.8V. - */ - uint32_t pst_end_data_low_value:6; - /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400; - * Configure the number of cycles of module clk to judge sdclk has stopped - */ - uint32_t sdclk_stop_thres:11; - uint32_t reserved_27:1; - /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1; - * module clk divider to sample sdclk - */ - uint32_t sample_clk_divider:4; - }; - uint32_t val; -} hinf_cfg_timing_reg_t; - -/** Type of cfg_update register - * update sdio configurations - */ -typedef union { - struct { - /** conf_update : WT; bitpos: [0]; default: 0; - * update the timing configurations - */ - uint32_t conf_update:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hinf_cfg_update_reg_t; - -/** Type of cfg_data7 register - * SDIO configuration register - */ -typedef union { - struct { - /** pin_state : R/W; bitpos: [7:0]; default: 0; - * configure cis addr 318 and 574 - */ - uint32_t pin_state:8; - /** chip_state : R/W; bitpos: [15:8]; default: 0; - * configure cis addr 312, 315, 568 and 571 - */ - uint32_t chip_state:8; - /** sdio_rst : R/W; bitpos: [16]; default: 0; - * soft reset control for sdio module - */ - uint32_t sdio_rst:1; - /** sdio_ioready0 : R/W; bitpos: [17]; default: 1; - * sdio io ready, high enable - */ - uint32_t sdio_ioready0:1; - /** sdio_mem_pd : R/W; bitpos: [18]; default: 0; - * sdio memory power down, high active - */ - uint32_t sdio_mem_pd:1; - /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0; - * enable sdio interrupt on data1 line - */ - uint32_t esdio_data1_int_en:1; - /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0; - * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V - */ - uint32_t sdio_switch_volt_sw:1; - /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0; - * enable block length to be fixed to 512 bytes in ddr50 mode - */ - uint32_t ddr50_blk_len_fix_en:1; - /** clk_en : R/W; bitpos: [22]; default: 0; - * sdio apb clock for configuration force on control:0-gating,1-force on. - */ - uint32_t clk_en:1; - /** sddr50 : R/W; bitpos: [23]; default: 1; - * configure if support sdr50 mode in cccr - */ - uint32_t sddr50:1; - /** ssdr104 : R/W; bitpos: [24]; default: 1; - * configure if support sdr104 mode in cccr - */ - uint32_t ssdr104:1; - /** ssdr50 : R/W; bitpos: [25]; default: 1; - * configure if support ddr50 mode in cccr - */ - uint32_t ssdr50:1; - /** sdtd : R/W; bitpos: [26]; default: 0; - * configure if support driver type D in cccr - */ - uint32_t sdtd:1; - /** sdta : R/W; bitpos: [27]; default: 0; - * configure if support driver type A in cccr - */ - uint32_t sdta:1; - /** sdtc : R/W; bitpos: [28]; default: 0; - * configure if support driver type C in cccr - */ - uint32_t sdtc:1; - /** sai : R/W; bitpos: [29]; default: 1; - * configure if support asynchronous interrupt in cccr - */ - uint32_t sai:1; - /** sdio_wakeup_clr : WT; bitpos: [30]; default: 0; - * clear sdio_wake_up signal after the chip wakes up - */ - uint32_t sdio_wakeup_clr:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} hinf_cfg_data7_reg_t; - -/** Type of cis_conf_w0 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 39~36 - */ - uint32_t cis_conf_w0:32; - }; - uint32_t val; -} hinf_cis_conf_w0_reg_t; - -/** Type of cis_conf_w1 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 43~40 - */ - uint32_t cis_conf_w1:32; - }; - uint32_t val; -} hinf_cis_conf_w1_reg_t; - -/** Type of cis_conf_w2 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 47~44 - */ - uint32_t cis_conf_w2:32; - }; - uint32_t val; -} hinf_cis_conf_w2_reg_t; - -/** Type of cis_conf_w3 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 51~48 - */ - uint32_t cis_conf_w3:32; - }; - uint32_t val; -} hinf_cis_conf_w3_reg_t; - -/** Type of cis_conf_w4 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 55~52 - */ - uint32_t cis_conf_w4:32; - }; - uint32_t val; -} hinf_cis_conf_w4_reg_t; - -/** Type of cis_conf_w5 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 59~56 - */ - uint32_t cis_conf_w5:32; - }; - uint32_t val; -} hinf_cis_conf_w5_reg_t; - -/** Type of cis_conf_w6 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 63~60 - */ - uint32_t cis_conf_w6:32; - }; - uint32_t val; -} hinf_cis_conf_w6_reg_t; - -/** Type of cis_conf_w7 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295; - * Configure cis addr 67~64 - */ - uint32_t cis_conf_w7:32; - }; - uint32_t val; -} hinf_cis_conf_w7_reg_t; - -/** Type of cfg_data16 register - * SDIO cis configuration register - */ -typedef union { - struct { - /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583; - * configure device id of function2 in cis - */ - uint32_t device_id_fn2:16; - /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146; - * configure user id of function2 in cis - */ - uint32_t user_id_fn2:16; - }; - uint32_t val; -} hinf_cfg_data16_reg_t; - -/** Type of cfg_uhs1_int_mode register - * configure int to start and end ahead of time in uhs1 mode - */ -typedef union { - struct { - /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0; - * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ - uint32_t intoe_end_ahead_mode:2; - /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0; - * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ - uint32_t int_end_ahead_mode:2; - /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0; - * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ - uint32_t intoe_st_ahead_mode:2; - /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0; - * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk - */ - uint32_t int_st_ahead_mode:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} hinf_cfg_uhs1_int_mode_reg_t; - -/** Type of sdio_slave_eco_low register - * sdio_slave redundant control registers - */ -typedef union { - struct { - /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * redundant registers for sdio_slave - */ - uint32_t rdn_eco_low:32; - }; - uint32_t val; -} hinf_sdio_slave_eco_low_reg_t; - -/** Type of sdio_slave_eco_high register - * sdio_slave redundant control registers - */ -typedef union { - struct { - /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * redundant registers for sdio_slave - */ - uint32_t rdn_eco_high:32; - }; - uint32_t val; -} hinf_sdio_slave_eco_high_reg_t; - -/** Type of sdio_slave_eco_conf register - * sdio_slave redundant control registers - */ -typedef union { - struct { - /** sdio_slave_rdn_result : RO; bitpos: [0]; default: 0; - * redundant registers for sdio_slave - */ - uint32_t sdio_slave_rdn_result:1; - /** sdio_slave_rdn_ena : R/W; bitpos: [1]; default: 0; - * redundant registers for sdio_slave - */ - uint32_t sdio_slave_rdn_ena:1; - /** sdio_slave_sdio_clk_rdn_result : RO; bitpos: [2]; default: 0; - * redundant registers for sdio_slave - */ - uint32_t sdio_slave_sdio_clk_rdn_result:1; - /** sdio_slave_sdio_clk_rdn_ena : R/W; bitpos: [3]; default: 0; - * redundant registers for sdio_slave - */ - uint32_t sdio_slave_sdio_clk_rdn_ena:1; - /** sdio_slave_sdclk_pad_rdn_result : RO; bitpos: [4]; default: 0; - * redundant registers for sdio_slave - */ - uint32_t sdio_slave_sdclk_pad_rdn_result:1; - /** sdio_slave_sdclk_pad_rdn_ena : R/W; bitpos: [5]; default: 0; - * redundant registers for sdio_slave - */ - uint32_t sdio_slave_sdclk_pad_rdn_ena:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} hinf_sdio_slave_eco_conf_reg_t; - -/** Type of sdio_slave_ldo_conf register - * sdio slave ldo control register - */ -typedef union { - struct { - /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0; - * control ldo ready signal by sdio slave itself - */ - uint32_t ldo_ready_ctl_in_en:1; - /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10; - * configure ldo ready counting threshold value, the actual counting target is - * 2^(ldo_ready_thres)-1 - */ - uint32_t ldo_ready_thres:5; - /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0; - * ignore ldo ready signal - */ - uint32_t ldo_ready_ignore_en:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} hinf_sdio_slave_ldo_conf_reg_t; - - -/** Group: Status registers */ -/** Type of conf_status register - * func0 config0 status - */ -typedef union { - struct { - /** func0_config0 : RO; bitpos: [7:0]; default: 0; - * func0 config0 (addr: 0x20f0 ) status - */ - uint32_t func0_config0:8; - /** sdr25_st : RO; bitpos: [8]; default: 0; - * sdr25 status - */ - uint32_t sdr25_st:1; - /** sdr50_st : RO; bitpos: [9]; default: 0; - * sdr50 status - */ - uint32_t sdr50_st:1; - /** sdr104_st : RO; bitpos: [10]; default: 0; - * sdr104 status - */ - uint32_t sdr104_st:1; - /** ddr50_st : RO; bitpos: [11]; default: 0; - * ddr50 status - */ - uint32_t ddr50_st:1; - /** tune_st : RO; bitpos: [14:12]; default: 0; - * tune_st fsm status - */ - uint32_t tune_st:3; - /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0; - * sdio switch voltage status:0-3.3V, 1-1.8V. - */ - uint32_t sdio_switch_volt_st:1; - /** sdio_switch_end : RO; bitpos: [16]; default: 0; - * sdio switch voltage ldo ready - */ - uint32_t sdio_switch_end:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} hinf_conf_status_reg_t; - - -/** Group: Version register */ -/** Type of sdio_date register - * ******* Description *********** - */ -typedef union { - struct { - /** sdio_date : R/W; bitpos: [31:0]; default: 35664208; - * sdio version date. - */ - uint32_t sdio_date:32; - }; - uint32_t val; -} hinf_sdio_date_reg_t; - - -typedef struct hinf_dev_t { - volatile hinf_cfg_data0_reg_t cfg_data0; - volatile hinf_cfg_data1_reg_t cfg_data1; - volatile hinf_cfg_timing_reg_t cfg_timing; - volatile hinf_cfg_update_reg_t cfg_update; - uint32_t reserved_010[3]; - volatile hinf_cfg_data7_reg_t cfg_data7; - volatile hinf_cis_conf_w0_reg_t cis_conf_w0; - volatile hinf_cis_conf_w1_reg_t cis_conf_w1; - volatile hinf_cis_conf_w2_reg_t cis_conf_w2; - volatile hinf_cis_conf_w3_reg_t cis_conf_w3; - volatile hinf_cis_conf_w4_reg_t cis_conf_w4; - volatile hinf_cis_conf_w5_reg_t cis_conf_w5; - volatile hinf_cis_conf_w6_reg_t cis_conf_w6; - volatile hinf_cis_conf_w7_reg_t cis_conf_w7; - volatile hinf_cfg_data16_reg_t cfg_data16; - volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode; - uint32_t reserved_048[3]; - volatile hinf_conf_status_reg_t conf_status; - uint32_t reserved_058[19]; - volatile hinf_sdio_slave_eco_low_reg_t sdio_slave_eco_low; - volatile hinf_sdio_slave_eco_high_reg_t sdio_slave_eco_high; - volatile hinf_sdio_slave_eco_conf_reg_t sdio_slave_eco_conf; - volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf; - uint32_t reserved_0b4[18]; - volatile hinf_sdio_date_reg_t sdio_date; -} hinf_dev_t; - -extern hinf_dev_t HINF; - -#ifndef __cplusplus -_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/host_reg.h b/components/soc/esp32p4/include/soc/host_reg.h deleted file mode 100644 index c508e5ab36..0000000000 --- a/components/soc/esp32p4/include/soc/host_reg.h +++ /dev/null @@ -1,3883 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SLCHOST_FUNC2_0_REG register - * *******Description*********** - */ -#define SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10) -/** SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC_FUNC2_INT (BIT(24)) -#define SLCHOST_SLC_FUNC2_INT_M (SLCHOST_SLC_FUNC2_INT_V << SLCHOST_SLC_FUNC2_INT_S) -#define SLCHOST_SLC_FUNC2_INT_V 0x00000001U -#define SLCHOST_SLC_FUNC2_INT_S 24 - -/** SLCHOST_FUNC2_1_REG register - * *******Description*********** - */ -#define SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14) -/** SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC_FUNC2_INT_EN (BIT(0)) -#define SLCHOST_SLC_FUNC2_INT_EN_M (SLCHOST_SLC_FUNC2_INT_EN_V << SLCHOST_SLC_FUNC2_INT_EN_S) -#define SLCHOST_SLC_FUNC2_INT_EN_V 0x00000001U -#define SLCHOST_SLC_FUNC2_INT_EN_S 0 - -/** SLCHOST_FUNC2_2_REG register - * *******Description*********** - */ -#define SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20) -/** SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1; - * *******Description*********** - */ -#define SLCHOST_SLC_FUNC1_MDSTAT (BIT(0)) -#define SLCHOST_SLC_FUNC1_MDSTAT_M (SLCHOST_SLC_FUNC1_MDSTAT_V << SLCHOST_SLC_FUNC1_MDSTAT_S) -#define SLCHOST_SLC_FUNC1_MDSTAT_V 0x00000001U -#define SLCHOST_SLC_FUNC1_MDSTAT_S 0 - -/** SLCHOST_GPIO_STATUS0_REG register - * *******Description*********** - */ -#define SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34) -/** SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_INT0 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_INT0_M (SLCHOST_GPIO_SDIO_INT0_V << SLCHOST_GPIO_SDIO_INT0_S) -#define SLCHOST_GPIO_SDIO_INT0_V 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_INT0_S 0 - -/** SLCHOST_GPIO_STATUS1_REG register - * *******Description*********** - */ -#define SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38) -/** SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_INT1 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_INT1_M (SLCHOST_GPIO_SDIO_INT1_V << SLCHOST_GPIO_SDIO_INT1_S) -#define SLCHOST_GPIO_SDIO_INT1_V 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_INT1_S 0 - -/** SLCHOST_GPIO_IN0_REG register - * *******Description*********** - */ -#define SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3c) -/** SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_IN0 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_IN0_M (SLCHOST_GPIO_SDIO_IN0_V << SLCHOST_GPIO_SDIO_IN0_S) -#define SLCHOST_GPIO_SDIO_IN0_V 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_IN0_S 0 - -/** SLCHOST_GPIO_IN1_REG register - * *******Description*********** - */ -#define SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40) -/** SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_IN1 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_IN1_M (SLCHOST_GPIO_SDIO_IN1_V << SLCHOST_GPIO_SDIO_IN1_S) -#define SLCHOST_GPIO_SDIO_IN1_V 0xFFFFFFFFU -#define SLCHOST_GPIO_SDIO_IN1_S 0 - -/** SLCHOST_SLC0HOST_TOKEN_RDATA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44) -/** SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0 0x00000FFFU -#define SLCHOST_SLC0_TOKEN0_M (SLCHOST_SLC0_TOKEN0_V << SLCHOST_SLC0_TOKEN0_S) -#define SLCHOST_SLC0_TOKEN0_V 0x00000FFFU -#define SLCHOST_SLC0_TOKEN0_S 0 -/** SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_PF_VALID (BIT(12)) -#define SLCHOST_SLC0_RX_PF_VALID_M (SLCHOST_SLC0_RX_PF_VALID_V << SLCHOST_SLC0_RX_PF_VALID_S) -#define SLCHOST_SLC0_RX_PF_VALID_V 0x00000001U -#define SLCHOST_SLC0_RX_PF_VALID_S 12 -/** SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M (SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S) -#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S 16 -/** SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_PF_EOF 0x0000000FU -#define SLCHOST_SLC0_RX_PF_EOF_M (SLCHOST_SLC0_RX_PF_EOF_V << SLCHOST_SLC0_RX_PF_EOF_S) -#define SLCHOST_SLC0_RX_PF_EOF_V 0x0000000FU -#define SLCHOST_SLC0_RX_PF_EOF_S 28 - -/** SLCHOST_SLC0_HOST_PF_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48) -/** SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_PF_DATA 0xFFFFFFFFU -#define SLCHOST_SLC0_PF_DATA_M (SLCHOST_SLC0_PF_DATA_V << SLCHOST_SLC0_PF_DATA_S) -#define SLCHOST_SLC0_PF_DATA_V 0xFFFFFFFFU -#define SLCHOST_SLC0_PF_DATA_S 0 - -/** SLCHOST_SLC1_HOST_PF_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4c) -/** SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_PF_DATA 0xFFFFFFFFU -#define SLCHOST_SLC1_PF_DATA_M (SLCHOST_SLC1_PF_DATA_V << SLCHOST_SLC1_PF_DATA_S) -#define SLCHOST_SLC1_PF_DATA_V 0xFFFFFFFFU -#define SLCHOST_SLC1_PF_DATA_S 0 - -/** SLCHOST_SLC0HOST_INT_RAW_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50) -/** SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 -/** SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 -/** SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 -/** SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 -/** SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 -/** SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 -/** SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 -/** SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 -/** SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 -/** SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 -/** SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 -/** SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 -/** SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) -#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M (SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S) -#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S 12 -/** SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) -#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M (SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S) -#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S 13 -/** SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) -#define SLCHOST_SLC0HOST_RX_START_INT_RAW_M (SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SLCHOST_SLC0HOST_RX_START_INT_RAW_S) -#define SLCHOST_SLC0HOST_RX_START_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_START_INT_RAW_S 14 -/** SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) -#define SLCHOST_SLC0HOST_TX_START_INT_RAW_M (SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SLCHOST_SLC0HOST_TX_START_INT_RAW_S) -#define SLCHOST_SLC0HOST_TX_START_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0HOST_TX_START_INT_RAW_S 15 -/** SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_UDF_INT_RAW (BIT(16)) -#define SLCHOST_SLC0_RX_UDF_INT_RAW_M (SLCHOST_SLC0_RX_UDF_INT_RAW_V << SLCHOST_SLC0_RX_UDF_INT_RAW_S) -#define SLCHOST_SLC0_RX_UDF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_RX_UDF_INT_RAW_S 16 -/** SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TX_OVF_INT_RAW (BIT(17)) -#define SLCHOST_SLC0_TX_OVF_INT_RAW_M (SLCHOST_SLC0_TX_OVF_INT_RAW_V << SLCHOST_SLC0_TX_OVF_INT_RAW_S) -#define SLCHOST_SLC0_TX_OVF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_TX_OVF_INT_RAW_S 17 -/** SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) -#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M (SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S) -#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S 18 -/** SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) -#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_M (SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SLCHOST_SLC0_EXT_BIT0_INT_RAW_S) -#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_S 19 -/** SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) -#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_M (SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SLCHOST_SLC0_EXT_BIT1_INT_RAW_S) -#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_S 20 -/** SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) -#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_M (SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SLCHOST_SLC0_EXT_BIT2_INT_RAW_S) -#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_S 21 -/** SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) -#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_M (SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SLCHOST_SLC0_EXT_BIT3_INT_RAW_S) -#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_S 22 -/** SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 -/** SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x00000001U -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 -/** SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_INT_RAW (BIT(25)) -#define SLCHOST_GPIO_SDIO_INT_RAW_M (SLCHOST_GPIO_SDIO_INT_RAW_V << SLCHOST_GPIO_SDIO_INT_RAW_S) -#define SLCHOST_GPIO_SDIO_INT_RAW_V 0x00000001U -#define SLCHOST_GPIO_SDIO_INT_RAW_S 25 - -/** SLCHOST_SLC1HOST_INT_RAW_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54) -/** SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0)) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S 0 -/** SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1)) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S 1 -/** SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2)) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S 2 -/** SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3)) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S 3 -/** SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4)) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S 4 -/** SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5)) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S 5 -/** SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6)) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S 6 -/** SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7)) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S 7 -/** SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8)) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8 -/** SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9)) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9 -/** SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10)) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10 -/** SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11)) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11 -/** SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12)) -#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M (SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S) -#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S 12 -/** SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13)) -#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M (SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S) -#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S 13 -/** SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_START_INT_RAW (BIT(14)) -#define SLCHOST_SLC1HOST_RX_START_INT_RAW_M (SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SLCHOST_SLC1HOST_RX_START_INT_RAW_S) -#define SLCHOST_SLC1HOST_RX_START_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_START_INT_RAW_S 14 -/** SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TX_START_INT_RAW (BIT(15)) -#define SLCHOST_SLC1HOST_TX_START_INT_RAW_M (SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SLCHOST_SLC1HOST_TX_START_INT_RAW_S) -#define SLCHOST_SLC1HOST_TX_START_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1HOST_TX_START_INT_RAW_S 15 -/** SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_UDF_INT_RAW (BIT(16)) -#define SLCHOST_SLC1_RX_UDF_INT_RAW_M (SLCHOST_SLC1_RX_UDF_INT_RAW_V << SLCHOST_SLC1_RX_UDF_INT_RAW_S) -#define SLCHOST_SLC1_RX_UDF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_RX_UDF_INT_RAW_S 16 -/** SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TX_OVF_INT_RAW (BIT(17)) -#define SLCHOST_SLC1_TX_OVF_INT_RAW_M (SLCHOST_SLC1_TX_OVF_INT_RAW_V << SLCHOST_SLC1_TX_OVF_INT_RAW_S) -#define SLCHOST_SLC1_TX_OVF_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_TX_OVF_INT_RAW_S 17 -/** SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18)) -#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M (SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S) -#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S 18 -/** SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT0_INT_RAW (BIT(19)) -#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_M (SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SLCHOST_SLC1_EXT_BIT0_INT_RAW_S) -#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_S 19 -/** SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT1_INT_RAW (BIT(20)) -#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_M (SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SLCHOST_SLC1_EXT_BIT1_INT_RAW_S) -#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_S 20 -/** SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT2_INT_RAW (BIT(21)) -#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_M (SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SLCHOST_SLC1_EXT_BIT2_INT_RAW_S) -#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_S 21 -/** SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT3_INT_RAW (BIT(22)) -#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_M (SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SLCHOST_SLC1_EXT_BIT3_INT_RAW_S) -#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_S 22 -/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23)) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23 -/** SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24)) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24 -/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25)) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x00000001U -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25 - -/** SLCHOST_SLC0HOST_INT_ST_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58) -/** SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S 0 -/** SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S 1 -/** SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S 2 -/** SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S 3 -/** SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S 4 -/** SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S 5 -/** SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S 6 -/** SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S 7 -/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 -/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 -/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 -/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 -/** SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) -#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_M (SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SLCHOST_SLC0HOST_RX_SOF_INT_ST_S) -#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_S 12 -/** SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) -#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_M (SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SLCHOST_SLC0HOST_RX_EOF_INT_ST_S) -#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_S 13 -/** SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_START_INT_ST (BIT(14)) -#define SLCHOST_SLC0HOST_RX_START_INT_ST_M (SLCHOST_SLC0HOST_RX_START_INT_ST_V << SLCHOST_SLC0HOST_RX_START_INT_ST_S) -#define SLCHOST_SLC0HOST_RX_START_INT_ST_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_START_INT_ST_S 14 -/** SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TX_START_INT_ST (BIT(15)) -#define SLCHOST_SLC0HOST_TX_START_INT_ST_M (SLCHOST_SLC0HOST_TX_START_INT_ST_V << SLCHOST_SLC0HOST_TX_START_INT_ST_S) -#define SLCHOST_SLC0HOST_TX_START_INT_ST_V 0x00000001U -#define SLCHOST_SLC0HOST_TX_START_INT_ST_S 15 -/** SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_UDF_INT_ST (BIT(16)) -#define SLCHOST_SLC0_RX_UDF_INT_ST_M (SLCHOST_SLC0_RX_UDF_INT_ST_V << SLCHOST_SLC0_RX_UDF_INT_ST_S) -#define SLCHOST_SLC0_RX_UDF_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_RX_UDF_INT_ST_S 16 -/** SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TX_OVF_INT_ST (BIT(17)) -#define SLCHOST_SLC0_TX_OVF_INT_ST_M (SLCHOST_SLC0_TX_OVF_INT_ST_V << SLCHOST_SLC0_TX_OVF_INT_ST_S) -#define SLCHOST_SLC0_TX_OVF_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_TX_OVF_INT_ST_S 17 -/** SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) -#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_M (SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SLCHOST_SLC0_RX_PF_VALID_INT_ST_S) -#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_S 18 -/** SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) -#define SLCHOST_SLC0_EXT_BIT0_INT_ST_M (SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SLCHOST_SLC0_EXT_BIT0_INT_ST_S) -#define SLCHOST_SLC0_EXT_BIT0_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT0_INT_ST_S 19 -/** SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) -#define SLCHOST_SLC0_EXT_BIT1_INT_ST_M (SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SLCHOST_SLC0_EXT_BIT1_INT_ST_S) -#define SLCHOST_SLC0_EXT_BIT1_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT1_INT_ST_S 20 -/** SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) -#define SLCHOST_SLC0_EXT_BIT2_INT_ST_M (SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SLCHOST_SLC0_EXT_BIT2_INT_ST_S) -#define SLCHOST_SLC0_EXT_BIT2_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT2_INT_ST_S 21 -/** SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) -#define SLCHOST_SLC0_EXT_BIT3_INT_ST_M (SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SLCHOST_SLC0_EXT_BIT3_INT_ST_S) -#define SLCHOST_SLC0_EXT_BIT3_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT3_INT_ST_S 22 -/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 -/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x00000001U -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 -/** SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_INT_ST (BIT(25)) -#define SLCHOST_GPIO_SDIO_INT_ST_M (SLCHOST_GPIO_SDIO_INT_ST_V << SLCHOST_GPIO_SDIO_INT_ST_S) -#define SLCHOST_GPIO_SDIO_INT_ST_V 0x00000001U -#define SLCHOST_GPIO_SDIO_INT_ST_S 25 - -/** SLCHOST_SLC1HOST_INT_ST_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5c) -/** SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0)) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S 0 -/** SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1)) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S 1 -/** SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2)) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S 2 -/** SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3)) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S 3 -/** SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4)) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S 4 -/** SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5)) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S 5 -/** SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6)) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S 6 -/** SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7)) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S 7 -/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8)) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S 8 -/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9)) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S 9 -/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10)) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S 10 -/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11)) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S 11 -/** SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_SOF_INT_ST (BIT(12)) -#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_M (SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SLCHOST_SLC1HOST_RX_SOF_INT_ST_S) -#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_S 12 -/** SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_EOF_INT_ST (BIT(13)) -#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_M (SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SLCHOST_SLC1HOST_RX_EOF_INT_ST_S) -#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_S 13 -/** SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_START_INT_ST (BIT(14)) -#define SLCHOST_SLC1HOST_RX_START_INT_ST_M (SLCHOST_SLC1HOST_RX_START_INT_ST_V << SLCHOST_SLC1HOST_RX_START_INT_ST_S) -#define SLCHOST_SLC1HOST_RX_START_INT_ST_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_START_INT_ST_S 14 -/** SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TX_START_INT_ST (BIT(15)) -#define SLCHOST_SLC1HOST_TX_START_INT_ST_M (SLCHOST_SLC1HOST_TX_START_INT_ST_V << SLCHOST_SLC1HOST_TX_START_INT_ST_S) -#define SLCHOST_SLC1HOST_TX_START_INT_ST_V 0x00000001U -#define SLCHOST_SLC1HOST_TX_START_INT_ST_S 15 -/** SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_UDF_INT_ST (BIT(16)) -#define SLCHOST_SLC1_RX_UDF_INT_ST_M (SLCHOST_SLC1_RX_UDF_INT_ST_V << SLCHOST_SLC1_RX_UDF_INT_ST_S) -#define SLCHOST_SLC1_RX_UDF_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_RX_UDF_INT_ST_S 16 -/** SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TX_OVF_INT_ST (BIT(17)) -#define SLCHOST_SLC1_TX_OVF_INT_ST_M (SLCHOST_SLC1_TX_OVF_INT_ST_V << SLCHOST_SLC1_TX_OVF_INT_ST_S) -#define SLCHOST_SLC1_TX_OVF_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_TX_OVF_INT_ST_S 17 -/** SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_PF_VALID_INT_ST (BIT(18)) -#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_M (SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SLCHOST_SLC1_RX_PF_VALID_INT_ST_S) -#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_S 18 -/** SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT0_INT_ST (BIT(19)) -#define SLCHOST_SLC1_EXT_BIT0_INT_ST_M (SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SLCHOST_SLC1_EXT_BIT0_INT_ST_S) -#define SLCHOST_SLC1_EXT_BIT0_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT0_INT_ST_S 19 -/** SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT1_INT_ST (BIT(20)) -#define SLCHOST_SLC1_EXT_BIT1_INT_ST_M (SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SLCHOST_SLC1_EXT_BIT1_INT_ST_S) -#define SLCHOST_SLC1_EXT_BIT1_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT1_INT_ST_S 20 -/** SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT2_INT_ST (BIT(21)) -#define SLCHOST_SLC1_EXT_BIT2_INT_ST_M (SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SLCHOST_SLC1_EXT_BIT2_INT_ST_S) -#define SLCHOST_SLC1_EXT_BIT2_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT2_INT_ST_S 21 -/** SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT3_INT_ST (BIT(22)) -#define SLCHOST_SLC1_EXT_BIT3_INT_ST_M (SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SLCHOST_SLC1_EXT_BIT3_INT_ST_S) -#define SLCHOST_SLC1_EXT_BIT3_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT3_INT_ST_S 22 -/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23)) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23 -/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24)) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S 24 -/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25)) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x00000001U -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25 - -/** SLCHOST_PKT_LEN_REG register - * *******Description*********** - */ -#define SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60) -/** SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN_M (SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN_V 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN_S 0 -/** SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S 20 - -/** SLCHOST_STATE_W0_REG register - * *******Description*********** - */ -#define SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64) -/** SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE0 0x000000FFU -#define SLCHOST_SLCHOST_STATE0_M (SLCHOST_SLCHOST_STATE0_V << SLCHOST_SLCHOST_STATE0_S) -#define SLCHOST_SLCHOST_STATE0_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE0_S 0 -/** SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE1 0x000000FFU -#define SLCHOST_SLCHOST_STATE1_M (SLCHOST_SLCHOST_STATE1_V << SLCHOST_SLCHOST_STATE1_S) -#define SLCHOST_SLCHOST_STATE1_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE1_S 8 -/** SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE2 0x000000FFU -#define SLCHOST_SLCHOST_STATE2_M (SLCHOST_SLCHOST_STATE2_V << SLCHOST_SLCHOST_STATE2_S) -#define SLCHOST_SLCHOST_STATE2_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE2_S 16 -/** SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE3 0x000000FFU -#define SLCHOST_SLCHOST_STATE3_M (SLCHOST_SLCHOST_STATE3_V << SLCHOST_SLCHOST_STATE3_S) -#define SLCHOST_SLCHOST_STATE3_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE3_S 24 - -/** SLCHOST_STATE_W1_REG register - * *******Description*********** - */ -#define SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68) -/** SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE4 0x000000FFU -#define SLCHOST_SLCHOST_STATE4_M (SLCHOST_SLCHOST_STATE4_V << SLCHOST_SLCHOST_STATE4_S) -#define SLCHOST_SLCHOST_STATE4_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE4_S 0 -/** SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE5 0x000000FFU -#define SLCHOST_SLCHOST_STATE5_M (SLCHOST_SLCHOST_STATE5_V << SLCHOST_SLCHOST_STATE5_S) -#define SLCHOST_SLCHOST_STATE5_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE5_S 8 -/** SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE6 0x000000FFU -#define SLCHOST_SLCHOST_STATE6_M (SLCHOST_SLCHOST_STATE6_V << SLCHOST_SLCHOST_STATE6_S) -#define SLCHOST_SLCHOST_STATE6_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE6_S 16 -/** SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_STATE7 0x000000FFU -#define SLCHOST_SLCHOST_STATE7_M (SLCHOST_SLCHOST_STATE7_V << SLCHOST_SLCHOST_STATE7_S) -#define SLCHOST_SLCHOST_STATE7_V 0x000000FFU -#define SLCHOST_SLCHOST_STATE7_S 24 - -/** SLCHOST_CONF_W0_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6c) -/** SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF0 0x000000FFU -#define SLCHOST_SLCHOST_CONF0_M (SLCHOST_SLCHOST_CONF0_V << SLCHOST_SLCHOST_CONF0_S) -#define SLCHOST_SLCHOST_CONF0_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF0_S 0 -/** SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF1 0x000000FFU -#define SLCHOST_SLCHOST_CONF1_M (SLCHOST_SLCHOST_CONF1_V << SLCHOST_SLCHOST_CONF1_S) -#define SLCHOST_SLCHOST_CONF1_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF1_S 8 -/** SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF2 0x000000FFU -#define SLCHOST_SLCHOST_CONF2_M (SLCHOST_SLCHOST_CONF2_V << SLCHOST_SLCHOST_CONF2_S) -#define SLCHOST_SLCHOST_CONF2_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF2_S 16 -/** SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF3 0x000000FFU -#define SLCHOST_SLCHOST_CONF3_M (SLCHOST_SLCHOST_CONF3_V << SLCHOST_SLCHOST_CONF3_S) -#define SLCHOST_SLCHOST_CONF3_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF3_S 24 - -/** SLCHOST_CONF_W1_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70) -/** SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF4 0x000000FFU -#define SLCHOST_SLCHOST_CONF4_M (SLCHOST_SLCHOST_CONF4_V << SLCHOST_SLCHOST_CONF4_S) -#define SLCHOST_SLCHOST_CONF4_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF4_S 0 -/** SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF5 0x000000FFU -#define SLCHOST_SLCHOST_CONF5_M (SLCHOST_SLCHOST_CONF5_V << SLCHOST_SLCHOST_CONF5_S) -#define SLCHOST_SLCHOST_CONF5_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF5_S 8 -/** SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF6 0x000000FFU -#define SLCHOST_SLCHOST_CONF6_M (SLCHOST_SLCHOST_CONF6_V << SLCHOST_SLCHOST_CONF6_S) -#define SLCHOST_SLCHOST_CONF6_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF6_S 16 -/** SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF7 0x000000FFU -#define SLCHOST_SLCHOST_CONF7_M (SLCHOST_SLCHOST_CONF7_V << SLCHOST_SLCHOST_CONF7_S) -#define SLCHOST_SLCHOST_CONF7_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF7_S 24 - -/** SLCHOST_CONF_W2_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74) -/** SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF8 0x000000FFU -#define SLCHOST_SLCHOST_CONF8_M (SLCHOST_SLCHOST_CONF8_V << SLCHOST_SLCHOST_CONF8_S) -#define SLCHOST_SLCHOST_CONF8_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF8_S 0 -/** SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF9 0x000000FFU -#define SLCHOST_SLCHOST_CONF9_M (SLCHOST_SLCHOST_CONF9_V << SLCHOST_SLCHOST_CONF9_S) -#define SLCHOST_SLCHOST_CONF9_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF9_S 8 -/** SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF10 0x000000FFU -#define SLCHOST_SLCHOST_CONF10_M (SLCHOST_SLCHOST_CONF10_V << SLCHOST_SLCHOST_CONF10_S) -#define SLCHOST_SLCHOST_CONF10_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF10_S 16 -/** SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF11 0x000000FFU -#define SLCHOST_SLCHOST_CONF11_M (SLCHOST_SLCHOST_CONF11_V << SLCHOST_SLCHOST_CONF11_S) -#define SLCHOST_SLCHOST_CONF11_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF11_S 24 - -/** SLCHOST_CONF_W3_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78) -/** SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF12 0x000000FFU -#define SLCHOST_SLCHOST_CONF12_M (SLCHOST_SLCHOST_CONF12_V << SLCHOST_SLCHOST_CONF12_S) -#define SLCHOST_SLCHOST_CONF12_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF12_S 0 -/** SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF13 0x000000FFU -#define SLCHOST_SLCHOST_CONF13_M (SLCHOST_SLCHOST_CONF13_V << SLCHOST_SLCHOST_CONF13_S) -#define SLCHOST_SLCHOST_CONF13_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF13_S 8 -/** SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF14 0x000000FFU -#define SLCHOST_SLCHOST_CONF14_M (SLCHOST_SLCHOST_CONF14_V << SLCHOST_SLCHOST_CONF14_S) -#define SLCHOST_SLCHOST_CONF14_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF14_S 16 -/** SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF15 0x000000FFU -#define SLCHOST_SLCHOST_CONF15_M (SLCHOST_SLCHOST_CONF15_V << SLCHOST_SLCHOST_CONF15_S) -#define SLCHOST_SLCHOST_CONF15_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF15_S 24 - -/** SLCHOST_CONF_W4_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7c) -/** SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF16 0x000000FFU -#define SLCHOST_SLCHOST_CONF16_M (SLCHOST_SLCHOST_CONF16_V << SLCHOST_SLCHOST_CONF16_S) -#define SLCHOST_SLCHOST_CONF16_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF16_S 0 -/** SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF17 0x000000FFU -#define SLCHOST_SLCHOST_CONF17_M (SLCHOST_SLCHOST_CONF17_V << SLCHOST_SLCHOST_CONF17_S) -#define SLCHOST_SLCHOST_CONF17_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF17_S 8 -/** SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF18 0x000000FFU -#define SLCHOST_SLCHOST_CONF18_M (SLCHOST_SLCHOST_CONF18_V << SLCHOST_SLCHOST_CONF18_S) -#define SLCHOST_SLCHOST_CONF18_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF18_S 16 -/** SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF19 0x000000FFU -#define SLCHOST_SLCHOST_CONF19_M (SLCHOST_SLCHOST_CONF19_V << SLCHOST_SLCHOST_CONF19_S) -#define SLCHOST_SLCHOST_CONF19_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF19_S 24 - -/** SLCHOST_CONF_W5_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80) -/** SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF20 0x000000FFU -#define SLCHOST_SLCHOST_CONF20_M (SLCHOST_SLCHOST_CONF20_V << SLCHOST_SLCHOST_CONF20_S) -#define SLCHOST_SLCHOST_CONF20_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF20_S 0 -/** SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF21 0x000000FFU -#define SLCHOST_SLCHOST_CONF21_M (SLCHOST_SLCHOST_CONF21_V << SLCHOST_SLCHOST_CONF21_S) -#define SLCHOST_SLCHOST_CONF21_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF21_S 8 -/** SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF22 0x000000FFU -#define SLCHOST_SLCHOST_CONF22_M (SLCHOST_SLCHOST_CONF22_V << SLCHOST_SLCHOST_CONF22_S) -#define SLCHOST_SLCHOST_CONF22_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF22_S 16 -/** SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF23 0x000000FFU -#define SLCHOST_SLCHOST_CONF23_M (SLCHOST_SLCHOST_CONF23_V << SLCHOST_SLCHOST_CONF23_S) -#define SLCHOST_SLCHOST_CONF23_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF23_S 24 - -/** SLCHOST_WIN_CMD_REG register - * *******Description*********** - */ -#define SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84) -/** SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_WIN_CMD 0x0000FFFFU -#define SLCHOST_SLCHOST_WIN_CMD_M (SLCHOST_SLCHOST_WIN_CMD_V << SLCHOST_SLCHOST_WIN_CMD_S) -#define SLCHOST_SLCHOST_WIN_CMD_V 0x0000FFFFU -#define SLCHOST_SLCHOST_WIN_CMD_S 0 - -/** SLCHOST_CONF_W6_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88) -/** SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF24 0x000000FFU -#define SLCHOST_SLCHOST_CONF24_M (SLCHOST_SLCHOST_CONF24_V << SLCHOST_SLCHOST_CONF24_S) -#define SLCHOST_SLCHOST_CONF24_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF24_S 0 -/** SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF25 0x000000FFU -#define SLCHOST_SLCHOST_CONF25_M (SLCHOST_SLCHOST_CONF25_V << SLCHOST_SLCHOST_CONF25_S) -#define SLCHOST_SLCHOST_CONF25_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF25_S 8 -/** SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF26 0x000000FFU -#define SLCHOST_SLCHOST_CONF26_M (SLCHOST_SLCHOST_CONF26_V << SLCHOST_SLCHOST_CONF26_S) -#define SLCHOST_SLCHOST_CONF26_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF26_S 16 -/** SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF27 0x000000FFU -#define SLCHOST_SLCHOST_CONF27_M (SLCHOST_SLCHOST_CONF27_V << SLCHOST_SLCHOST_CONF27_S) -#define SLCHOST_SLCHOST_CONF27_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF27_S 24 - -/** SLCHOST_CONF_W7_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8c) -/** SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF28 0x000000FFU -#define SLCHOST_SLCHOST_CONF28_M (SLCHOST_SLCHOST_CONF28_V << SLCHOST_SLCHOST_CONF28_S) -#define SLCHOST_SLCHOST_CONF28_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF28_S 0 -/** SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF29 0x000000FFU -#define SLCHOST_SLCHOST_CONF29_M (SLCHOST_SLCHOST_CONF29_V << SLCHOST_SLCHOST_CONF29_S) -#define SLCHOST_SLCHOST_CONF29_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF29_S 8 -/** SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF30 0x000000FFU -#define SLCHOST_SLCHOST_CONF30_M (SLCHOST_SLCHOST_CONF30_V << SLCHOST_SLCHOST_CONF30_S) -#define SLCHOST_SLCHOST_CONF30_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF30_S 16 -/** SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF31 0x000000FFU -#define SLCHOST_SLCHOST_CONF31_M (SLCHOST_SLCHOST_CONF31_V << SLCHOST_SLCHOST_CONF31_S) -#define SLCHOST_SLCHOST_CONF31_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF31_S 24 - -/** SLCHOST_PKT_LEN0_REG register - * *******Description*********** - */ -#define SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90) -/** SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_M (SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_V 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_S 0 -/** SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S 20 - -/** SLCHOST_PKT_LEN1_REG register - * *******Description*********** - */ -#define SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94) -/** SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_M (SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_V 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_S 0 -/** SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S 20 - -/** SLCHOST_PKT_LEN2_REG register - * *******Description*********** - */ -#define SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98) -/** SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_M (SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_V 0x000FFFFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_S 0 -/** SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S) -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S 20 - -/** SLCHOST_CONF_W8_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9c) -/** SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF32 0x000000FFU -#define SLCHOST_SLCHOST_CONF32_M (SLCHOST_SLCHOST_CONF32_V << SLCHOST_SLCHOST_CONF32_S) -#define SLCHOST_SLCHOST_CONF32_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF32_S 0 -/** SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF33 0x000000FFU -#define SLCHOST_SLCHOST_CONF33_M (SLCHOST_SLCHOST_CONF33_V << SLCHOST_SLCHOST_CONF33_S) -#define SLCHOST_SLCHOST_CONF33_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF33_S 8 -/** SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF34 0x000000FFU -#define SLCHOST_SLCHOST_CONF34_M (SLCHOST_SLCHOST_CONF34_V << SLCHOST_SLCHOST_CONF34_S) -#define SLCHOST_SLCHOST_CONF34_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF34_S 16 -/** SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF35 0x000000FFU -#define SLCHOST_SLCHOST_CONF35_M (SLCHOST_SLCHOST_CONF35_V << SLCHOST_SLCHOST_CONF35_S) -#define SLCHOST_SLCHOST_CONF35_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF35_S 24 - -/** SLCHOST_CONF_W9_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xa0) -/** SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF36 0x000000FFU -#define SLCHOST_SLCHOST_CONF36_M (SLCHOST_SLCHOST_CONF36_V << SLCHOST_SLCHOST_CONF36_S) -#define SLCHOST_SLCHOST_CONF36_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF36_S 0 -/** SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF37 0x000000FFU -#define SLCHOST_SLCHOST_CONF37_M (SLCHOST_SLCHOST_CONF37_V << SLCHOST_SLCHOST_CONF37_S) -#define SLCHOST_SLCHOST_CONF37_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF37_S 8 -/** SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF38 0x000000FFU -#define SLCHOST_SLCHOST_CONF38_M (SLCHOST_SLCHOST_CONF38_V << SLCHOST_SLCHOST_CONF38_S) -#define SLCHOST_SLCHOST_CONF38_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF38_S 16 -/** SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF39 0x000000FFU -#define SLCHOST_SLCHOST_CONF39_M (SLCHOST_SLCHOST_CONF39_V << SLCHOST_SLCHOST_CONF39_S) -#define SLCHOST_SLCHOST_CONF39_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF39_S 24 - -/** SLCHOST_CONF_W10_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xa4) -/** SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF40 0x000000FFU -#define SLCHOST_SLCHOST_CONF40_M (SLCHOST_SLCHOST_CONF40_V << SLCHOST_SLCHOST_CONF40_S) -#define SLCHOST_SLCHOST_CONF40_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF40_S 0 -/** SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF41 0x000000FFU -#define SLCHOST_SLCHOST_CONF41_M (SLCHOST_SLCHOST_CONF41_V << SLCHOST_SLCHOST_CONF41_S) -#define SLCHOST_SLCHOST_CONF41_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF41_S 8 -/** SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF42 0x000000FFU -#define SLCHOST_SLCHOST_CONF42_M (SLCHOST_SLCHOST_CONF42_V << SLCHOST_SLCHOST_CONF42_S) -#define SLCHOST_SLCHOST_CONF42_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF42_S 16 -/** SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF43 0x000000FFU -#define SLCHOST_SLCHOST_CONF43_M (SLCHOST_SLCHOST_CONF43_V << SLCHOST_SLCHOST_CONF43_S) -#define SLCHOST_SLCHOST_CONF43_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF43_S 24 - -/** SLCHOST_CONF_W11_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xa8) -/** SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF44 0x000000FFU -#define SLCHOST_SLCHOST_CONF44_M (SLCHOST_SLCHOST_CONF44_V << SLCHOST_SLCHOST_CONF44_S) -#define SLCHOST_SLCHOST_CONF44_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF44_S 0 -/** SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF45 0x000000FFU -#define SLCHOST_SLCHOST_CONF45_M (SLCHOST_SLCHOST_CONF45_V << SLCHOST_SLCHOST_CONF45_S) -#define SLCHOST_SLCHOST_CONF45_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF45_S 8 -/** SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF46 0x000000FFU -#define SLCHOST_SLCHOST_CONF46_M (SLCHOST_SLCHOST_CONF46_V << SLCHOST_SLCHOST_CONF46_S) -#define SLCHOST_SLCHOST_CONF46_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF46_S 16 -/** SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF47 0x000000FFU -#define SLCHOST_SLCHOST_CONF47_M (SLCHOST_SLCHOST_CONF47_V << SLCHOST_SLCHOST_CONF47_S) -#define SLCHOST_SLCHOST_CONF47_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF47_S 24 - -/** SLCHOST_CONF_W12_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xac) -/** SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF48 0x000000FFU -#define SLCHOST_SLCHOST_CONF48_M (SLCHOST_SLCHOST_CONF48_V << SLCHOST_SLCHOST_CONF48_S) -#define SLCHOST_SLCHOST_CONF48_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF48_S 0 -/** SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF49 0x000000FFU -#define SLCHOST_SLCHOST_CONF49_M (SLCHOST_SLCHOST_CONF49_V << SLCHOST_SLCHOST_CONF49_S) -#define SLCHOST_SLCHOST_CONF49_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF49_S 8 -/** SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF50 0x000000FFU -#define SLCHOST_SLCHOST_CONF50_M (SLCHOST_SLCHOST_CONF50_V << SLCHOST_SLCHOST_CONF50_S) -#define SLCHOST_SLCHOST_CONF50_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF50_S 16 -/** SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF51 0x000000FFU -#define SLCHOST_SLCHOST_CONF51_M (SLCHOST_SLCHOST_CONF51_V << SLCHOST_SLCHOST_CONF51_S) -#define SLCHOST_SLCHOST_CONF51_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF51_S 24 - -/** SLCHOST_CONF_W13_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xb0) -/** SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF52 0x000000FFU -#define SLCHOST_SLCHOST_CONF52_M (SLCHOST_SLCHOST_CONF52_V << SLCHOST_SLCHOST_CONF52_S) -#define SLCHOST_SLCHOST_CONF52_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF52_S 0 -/** SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF53 0x000000FFU -#define SLCHOST_SLCHOST_CONF53_M (SLCHOST_SLCHOST_CONF53_V << SLCHOST_SLCHOST_CONF53_S) -#define SLCHOST_SLCHOST_CONF53_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF53_S 8 -/** SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF54 0x000000FFU -#define SLCHOST_SLCHOST_CONF54_M (SLCHOST_SLCHOST_CONF54_V << SLCHOST_SLCHOST_CONF54_S) -#define SLCHOST_SLCHOST_CONF54_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF54_S 16 -/** SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF55 0x000000FFU -#define SLCHOST_SLCHOST_CONF55_M (SLCHOST_SLCHOST_CONF55_V << SLCHOST_SLCHOST_CONF55_S) -#define SLCHOST_SLCHOST_CONF55_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF55_S 24 - -/** SLCHOST_CONF_W14_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xb4) -/** SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF56 0x000000FFU -#define SLCHOST_SLCHOST_CONF56_M (SLCHOST_SLCHOST_CONF56_V << SLCHOST_SLCHOST_CONF56_S) -#define SLCHOST_SLCHOST_CONF56_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF56_S 0 -/** SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF57 0x000000FFU -#define SLCHOST_SLCHOST_CONF57_M (SLCHOST_SLCHOST_CONF57_V << SLCHOST_SLCHOST_CONF57_S) -#define SLCHOST_SLCHOST_CONF57_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF57_S 8 -/** SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF58 0x000000FFU -#define SLCHOST_SLCHOST_CONF58_M (SLCHOST_SLCHOST_CONF58_V << SLCHOST_SLCHOST_CONF58_S) -#define SLCHOST_SLCHOST_CONF58_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF58_S 16 -/** SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF59 0x000000FFU -#define SLCHOST_SLCHOST_CONF59_M (SLCHOST_SLCHOST_CONF59_V << SLCHOST_SLCHOST_CONF59_S) -#define SLCHOST_SLCHOST_CONF59_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF59_S 24 - -/** SLCHOST_CONF_W15_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xb8) -/** SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF60 0x000000FFU -#define SLCHOST_SLCHOST_CONF60_M (SLCHOST_SLCHOST_CONF60_V << SLCHOST_SLCHOST_CONF60_S) -#define SLCHOST_SLCHOST_CONF60_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF60_S 0 -/** SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF61 0x000000FFU -#define SLCHOST_SLCHOST_CONF61_M (SLCHOST_SLCHOST_CONF61_V << SLCHOST_SLCHOST_CONF61_S) -#define SLCHOST_SLCHOST_CONF61_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF61_S 8 -/** SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF62 0x000000FFU -#define SLCHOST_SLCHOST_CONF62_M (SLCHOST_SLCHOST_CONF62_V << SLCHOST_SLCHOST_CONF62_S) -#define SLCHOST_SLCHOST_CONF62_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF62_S 16 -/** SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CONF63 0x000000FFU -#define SLCHOST_SLCHOST_CONF63_M (SLCHOST_SLCHOST_CONF63_V << SLCHOST_SLCHOST_CONF63_S) -#define SLCHOST_SLCHOST_CONF63_V 0x000000FFU -#define SLCHOST_SLCHOST_CONF63_S 24 - -/** SLCHOST_CHECK_SUM0_REG register - * *******Description*********** - */ -#define SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xbc) -/** SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CHECK_SUM0 0xFFFFFFFFU -#define SLCHOST_SLCHOST_CHECK_SUM0_M (SLCHOST_SLCHOST_CHECK_SUM0_V << SLCHOST_SLCHOST_CHECK_SUM0_S) -#define SLCHOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFFU -#define SLCHOST_SLCHOST_CHECK_SUM0_S 0 - -/** SLCHOST_CHECK_SUM1_REG register - * *******Description*********** - */ -#define SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xc0) -/** SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_CHECK_SUM1 0xFFFFFFFFU -#define SLCHOST_SLCHOST_CHECK_SUM1_M (SLCHOST_SLCHOST_CHECK_SUM1_V << SLCHOST_SLCHOST_CHECK_SUM1_S) -#define SLCHOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFFU -#define SLCHOST_SLCHOST_CHECK_SUM1_S 0 - -/** SLCHOST_SLC1HOST_TOKEN_RDATA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xc4) -/** SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0 0x00000FFFU -#define SLCHOST_SLC1_TOKEN0_M (SLCHOST_SLC1_TOKEN0_V << SLCHOST_SLC1_TOKEN0_S) -#define SLCHOST_SLC1_TOKEN0_V 0x00000FFFU -#define SLCHOST_SLC1_TOKEN0_S 0 -/** SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_PF_VALID (BIT(12)) -#define SLCHOST_SLC1_RX_PF_VALID_M (SLCHOST_SLC1_RX_PF_VALID_V << SLCHOST_SLC1_RX_PF_VALID_S) -#define SLCHOST_SLC1_RX_PF_VALID_V 0x00000001U -#define SLCHOST_SLC1_RX_PF_VALID_S 12 -/** SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M (SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S) -#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V 0x00000FFFU -#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S 16 -/** SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_PF_EOF 0x0000000FU -#define SLCHOST_SLC1_RX_PF_EOF_M (SLCHOST_SLC1_RX_PF_EOF_V << SLCHOST_SLC1_RX_PF_EOF_S) -#define SLCHOST_SLC1_RX_PF_EOF_V 0x0000000FU -#define SLCHOST_SLC1_RX_PF_EOF_S 28 - -/** SLCHOST_SLC0HOST_TOKEN_WDATA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xc8) -/** SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN0_WD 0x00000FFFU -#define SLCHOST_SLC0HOST_TOKEN0_WD_M (SLCHOST_SLC0HOST_TOKEN0_WD_V << SLCHOST_SLC0HOST_TOKEN0_WD_S) -#define SLCHOST_SLC0HOST_TOKEN0_WD_V 0x00000FFFU -#define SLCHOST_SLC0HOST_TOKEN0_WD_S 0 -/** SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN1_WD 0x00000FFFU -#define SLCHOST_SLC0HOST_TOKEN1_WD_M (SLCHOST_SLC0HOST_TOKEN1_WD_V << SLCHOST_SLC0HOST_TOKEN1_WD_S) -#define SLCHOST_SLC0HOST_TOKEN1_WD_V 0x00000FFFU -#define SLCHOST_SLC0HOST_TOKEN1_WD_S 16 - -/** SLCHOST_SLC1HOST_TOKEN_WDATA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xcc) -/** SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN0_WD 0x00000FFFU -#define SLCHOST_SLC1HOST_TOKEN0_WD_M (SLCHOST_SLC1HOST_TOKEN0_WD_V << SLCHOST_SLC1HOST_TOKEN0_WD_S) -#define SLCHOST_SLC1HOST_TOKEN0_WD_V 0x00000FFFU -#define SLCHOST_SLC1HOST_TOKEN0_WD_S 0 -/** SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN1_WD 0x00000FFFU -#define SLCHOST_SLC1HOST_TOKEN1_WD_M (SLCHOST_SLC1HOST_TOKEN1_WD_V << SLCHOST_SLC1HOST_TOKEN1_WD_S) -#define SLCHOST_SLC1HOST_TOKEN1_WD_V 0x00000FFFU -#define SLCHOST_SLC1HOST_TOKEN1_WD_S 16 - -/** SLCHOST_TOKEN_CON_REG register - * *******Description*********** - */ -#define SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xd0) -/** SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN0_DEC (BIT(0)) -#define SLCHOST_SLC0HOST_TOKEN0_DEC_M (SLCHOST_SLC0HOST_TOKEN0_DEC_V << SLCHOST_SLC0HOST_TOKEN0_DEC_S) -#define SLCHOST_SLC0HOST_TOKEN0_DEC_V 0x00000001U -#define SLCHOST_SLC0HOST_TOKEN0_DEC_S 0 -/** SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN1_DEC (BIT(1)) -#define SLCHOST_SLC0HOST_TOKEN1_DEC_M (SLCHOST_SLC0HOST_TOKEN1_DEC_V << SLCHOST_SLC0HOST_TOKEN1_DEC_S) -#define SLCHOST_SLC0HOST_TOKEN1_DEC_V 0x00000001U -#define SLCHOST_SLC0HOST_TOKEN1_DEC_S 1 -/** SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN0_WR (BIT(2)) -#define SLCHOST_SLC0HOST_TOKEN0_WR_M (SLCHOST_SLC0HOST_TOKEN0_WR_V << SLCHOST_SLC0HOST_TOKEN0_WR_S) -#define SLCHOST_SLC0HOST_TOKEN0_WR_V 0x00000001U -#define SLCHOST_SLC0HOST_TOKEN0_WR_S 2 -/** SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TOKEN1_WR (BIT(3)) -#define SLCHOST_SLC0HOST_TOKEN1_WR_M (SLCHOST_SLC0HOST_TOKEN1_WR_V << SLCHOST_SLC0HOST_TOKEN1_WR_S) -#define SLCHOST_SLC0HOST_TOKEN1_WR_V 0x00000001U -#define SLCHOST_SLC0HOST_TOKEN1_WR_S 3 -/** SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN0_DEC (BIT(4)) -#define SLCHOST_SLC1HOST_TOKEN0_DEC_M (SLCHOST_SLC1HOST_TOKEN0_DEC_V << SLCHOST_SLC1HOST_TOKEN0_DEC_S) -#define SLCHOST_SLC1HOST_TOKEN0_DEC_V 0x00000001U -#define SLCHOST_SLC1HOST_TOKEN0_DEC_S 4 -/** SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN1_DEC (BIT(5)) -#define SLCHOST_SLC1HOST_TOKEN1_DEC_M (SLCHOST_SLC1HOST_TOKEN1_DEC_V << SLCHOST_SLC1HOST_TOKEN1_DEC_S) -#define SLCHOST_SLC1HOST_TOKEN1_DEC_V 0x00000001U -#define SLCHOST_SLC1HOST_TOKEN1_DEC_S 5 -/** SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN0_WR (BIT(6)) -#define SLCHOST_SLC1HOST_TOKEN0_WR_M (SLCHOST_SLC1HOST_TOKEN0_WR_V << SLCHOST_SLC1HOST_TOKEN0_WR_S) -#define SLCHOST_SLC1HOST_TOKEN0_WR_V 0x00000001U -#define SLCHOST_SLC1HOST_TOKEN0_WR_S 6 -/** SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TOKEN1_WR (BIT(7)) -#define SLCHOST_SLC1HOST_TOKEN1_WR_M (SLCHOST_SLC1HOST_TOKEN1_WR_V << SLCHOST_SLC1HOST_TOKEN1_WR_S) -#define SLCHOST_SLC1HOST_TOKEN1_WR_V 0x00000001U -#define SLCHOST_SLC1HOST_TOKEN1_WR_S 7 -/** SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_LEN_WR (BIT(8)) -#define SLCHOST_SLC0HOST_LEN_WR_M (SLCHOST_SLC0HOST_LEN_WR_V << SLCHOST_SLC0HOST_LEN_WR_S) -#define SLCHOST_SLC0HOST_LEN_WR_V 0x00000001U -#define SLCHOST_SLC0HOST_LEN_WR_S 8 - -/** SLCHOST_SLC0HOST_INT_CLR_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd4) -/** SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 -/** SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 -/** SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 -/** SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 -/** SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 -/** SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 -/** SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 -/** SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 -/** SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 -/** SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 -/** SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 -/** SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 -/** SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) -#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M (SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S) -#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S 12 -/** SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) -#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M (SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S) -#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S 13 -/** SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) -#define SLCHOST_SLC0HOST_RX_START_INT_CLR_M (SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SLCHOST_SLC0HOST_RX_START_INT_CLR_S) -#define SLCHOST_SLC0HOST_RX_START_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_START_INT_CLR_S 14 -/** SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) -#define SLCHOST_SLC0HOST_TX_START_INT_CLR_M (SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SLCHOST_SLC0HOST_TX_START_INT_CLR_S) -#define SLCHOST_SLC0HOST_TX_START_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0HOST_TX_START_INT_CLR_S 15 -/** SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_UDF_INT_CLR (BIT(16)) -#define SLCHOST_SLC0_RX_UDF_INT_CLR_M (SLCHOST_SLC0_RX_UDF_INT_CLR_V << SLCHOST_SLC0_RX_UDF_INT_CLR_S) -#define SLCHOST_SLC0_RX_UDF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_RX_UDF_INT_CLR_S 16 -/** SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TX_OVF_INT_CLR (BIT(17)) -#define SLCHOST_SLC0_TX_OVF_INT_CLR_M (SLCHOST_SLC0_TX_OVF_INT_CLR_V << SLCHOST_SLC0_TX_OVF_INT_CLR_S) -#define SLCHOST_SLC0_TX_OVF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_TX_OVF_INT_CLR_S 17 -/** SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) -#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M (SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S) -#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S 18 -/** SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) -#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_M (SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SLCHOST_SLC0_EXT_BIT0_INT_CLR_S) -#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_S 19 -/** SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) -#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_M (SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SLCHOST_SLC0_EXT_BIT1_INT_CLR_S) -#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_S 20 -/** SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) -#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_M (SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SLCHOST_SLC0_EXT_BIT2_INT_CLR_S) -#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_S 21 -/** SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) -#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_M (SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SLCHOST_SLC0_EXT_BIT3_INT_CLR_S) -#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_S 22 -/** SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 -/** SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x00000001U -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 -/** SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_INT_CLR (BIT(25)) -#define SLCHOST_GPIO_SDIO_INT_CLR_M (SLCHOST_GPIO_SDIO_INT_CLR_V << SLCHOST_GPIO_SDIO_INT_CLR_S) -#define SLCHOST_GPIO_SDIO_INT_CLR_V 0x00000001U -#define SLCHOST_GPIO_SDIO_INT_CLR_S 25 - -/** SLCHOST_SLC1HOST_INT_CLR_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd8) -/** SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0)) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S 0 -/** SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1)) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S 1 -/** SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2)) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S 2 -/** SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3)) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S 3 -/** SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4)) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S 4 -/** SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5)) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S 5 -/** SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6)) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S 6 -/** SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7)) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S 7 -/** SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8)) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8 -/** SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9)) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9 -/** SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10)) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10 -/** SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11)) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11 -/** SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12)) -#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M (SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S) -#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S 12 -/** SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13)) -#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M (SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S) -#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S 13 -/** SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_START_INT_CLR (BIT(14)) -#define SLCHOST_SLC1HOST_RX_START_INT_CLR_M (SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SLCHOST_SLC1HOST_RX_START_INT_CLR_S) -#define SLCHOST_SLC1HOST_RX_START_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_START_INT_CLR_S 14 -/** SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TX_START_INT_CLR (BIT(15)) -#define SLCHOST_SLC1HOST_TX_START_INT_CLR_M (SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SLCHOST_SLC1HOST_TX_START_INT_CLR_S) -#define SLCHOST_SLC1HOST_TX_START_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1HOST_TX_START_INT_CLR_S 15 -/** SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_UDF_INT_CLR (BIT(16)) -#define SLCHOST_SLC1_RX_UDF_INT_CLR_M (SLCHOST_SLC1_RX_UDF_INT_CLR_V << SLCHOST_SLC1_RX_UDF_INT_CLR_S) -#define SLCHOST_SLC1_RX_UDF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_RX_UDF_INT_CLR_S 16 -/** SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TX_OVF_INT_CLR (BIT(17)) -#define SLCHOST_SLC1_TX_OVF_INT_CLR_M (SLCHOST_SLC1_TX_OVF_INT_CLR_V << SLCHOST_SLC1_TX_OVF_INT_CLR_S) -#define SLCHOST_SLC1_TX_OVF_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_TX_OVF_INT_CLR_S 17 -/** SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18)) -#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M (SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S) -#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S 18 -/** SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT0_INT_CLR (BIT(19)) -#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_M (SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SLCHOST_SLC1_EXT_BIT0_INT_CLR_S) -#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_S 19 -/** SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT1_INT_CLR (BIT(20)) -#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_M (SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SLCHOST_SLC1_EXT_BIT1_INT_CLR_S) -#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_S 20 -/** SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT2_INT_CLR (BIT(21)) -#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_M (SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SLCHOST_SLC1_EXT_BIT2_INT_CLR_S) -#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_S 21 -/** SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT3_INT_CLR (BIT(22)) -#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_M (SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SLCHOST_SLC1_EXT_BIT3_INT_CLR_S) -#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_S 22 -/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23)) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23 -/** SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24)) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24 -/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25)) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x00000001U -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25 - -/** SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xdc) -/** SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 -/** SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 -/** SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 -/** SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 -/** SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 -/** SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 -/** SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 -/** SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) -#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 -/** SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 -/** SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 -/** SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 -/** SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 -/** SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) -#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S) -#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 -/** SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) -#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S) -#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 -/** SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) -#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S) -#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 -/** SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) -#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S) -#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 -/** SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) -#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M (SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S) -#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 -/** SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) -#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M (SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S) -#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 -/** SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) -#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S) -#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 -/** SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) -#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S) -#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 -/** SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) -#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S) -#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 -/** SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) -#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S) -#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 -/** SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) -#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S) -#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 -/** SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 -/** SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S) -#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 -/** SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) -#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_M (SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SLCHOST_FN1_GPIO_SDIO_INT_ENA_S) -#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_S 25 - -/** SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe0) -/** SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0 -/** SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1 -/** SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2 -/** SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3 -/** SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4 -/** SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5 -/** SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6 -/** SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) -#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7 -/** SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8 -/** SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9 -/** SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10 -/** SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11 -/** SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) -#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S) -#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12 -/** SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) -#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S) -#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13 -/** SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14)) -#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S) -#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14 -/** SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15)) -#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S) -#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15 -/** SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16)) -#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M (SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S) -#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S 16 -/** SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17)) -#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M (SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S) -#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S 17 -/** SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) -#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S) -#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18 -/** SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19)) -#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S) -#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19 -/** SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20)) -#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S) -#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20 -/** SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21)) -#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S) -#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21 -/** SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22)) -#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S) -#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22 -/** SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 -/** SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S) -#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24 -/** SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) -#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 - -/** SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe4) -/** SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0 -/** SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1 -/** SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2 -/** SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3 -/** SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4 -/** SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5 -/** SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6 -/** SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) -#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7 -/** SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8 -/** SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9 -/** SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10 -/** SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11 -/** SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) -#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S) -#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12 -/** SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) -#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S) -#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13 -/** SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14)) -#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S) -#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14 -/** SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15)) -#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S) -#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15 -/** SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16)) -#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M (SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S) -#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S 16 -/** SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17)) -#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M (SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S) -#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S 17 -/** SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) -#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S) -#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18 -/** SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19)) -#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S) -#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19 -/** SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20)) -#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S) -#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20 -/** SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21)) -#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S) -#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21 -/** SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22)) -#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S) -#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22 -/** SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23 -/** SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S) -#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24 -/** SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_GPIO_SDIO_INT_ENA (BIT(25)) -#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_M (SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SLCHOST_FN2_GPIO_SDIO_INT_ENA_S) -#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_S 25 - -/** SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe8) -/** SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0 -/** SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1 -/** SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2 -/** SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3 -/** SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4 -/** SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5 -/** SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6 -/** SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) -#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7 -/** SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8 -/** SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9 -/** SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10 -/** SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11 -/** SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) -#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S) -#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12 -/** SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) -#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S) -#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13 -/** SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14)) -#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S) -#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14 -/** SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15)) -#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S) -#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15 -/** SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16)) -#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M (SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S) -#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S 16 -/** SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17)) -#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M (SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S) -#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S 17 -/** SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) -#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S) -#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18 -/** SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19)) -#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S) -#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19 -/** SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20)) -#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S) -#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20 -/** SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21)) -#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S) -#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21 -/** SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22)) -#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S) -#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22 -/** SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 -/** SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S) -#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24 -/** SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) -#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 - -/** SLCHOST_SLC0HOST_INT_ENA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xec) -/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 -/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 -/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 -/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 -/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 -/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 -/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 -/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 -/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 -/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 -/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 -/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 -/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S) -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S 12 -/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S) -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S 13 -/** SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) -#define SLCHOST_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_SLC0HOST_RX_START_INT_ENA_S) -#define SLCHOST_SLC0HOST_RX_START_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_START_INT_ENA_S 14 -/** SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) -#define SLCHOST_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_SLC0HOST_TX_START_INT_ENA_S) -#define SLCHOST_SLC0HOST_TX_START_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0HOST_TX_START_INT_ENA_S 15 -/** SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_UDF_INT_ENA (BIT(16)) -#define SLCHOST_SLC0_RX_UDF_INT_ENA_M (SLCHOST_SLC0_RX_UDF_INT_ENA_V << SLCHOST_SLC0_RX_UDF_INT_ENA_S) -#define SLCHOST_SLC0_RX_UDF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_RX_UDF_INT_ENA_S 16 -/** SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TX_OVF_INT_ENA (BIT(17)) -#define SLCHOST_SLC0_TX_OVF_INT_ENA_M (SLCHOST_SLC0_TX_OVF_INT_ENA_V << SLCHOST_SLC0_TX_OVF_INT_ENA_S) -#define SLCHOST_SLC0_TX_OVF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_TX_OVF_INT_ENA_S 17 -/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S) -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S 18 -/** SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA_S) -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_S 19 -/** SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA_S) -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_S 20 -/** SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA_S) -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_S 21 -/** SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA_S) -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_S 22 -/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 -/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 -/** SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_INT_ENA (BIT(25)) -#define SLCHOST_GPIO_SDIO_INT_ENA_M (SLCHOST_GPIO_SDIO_INT_ENA_V << SLCHOST_GPIO_SDIO_INT_ENA_S) -#define SLCHOST_GPIO_SDIO_INT_ENA_V 0x00000001U -#define SLCHOST_GPIO_SDIO_INT_ENA_S 25 - -/** SLCHOST_SLC1HOST_INT_ENA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xf0) -/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S 0 -/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S 1 -/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S 2 -/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S 3 -/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S 4 -/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S 5 -/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S 6 -/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S 7 -/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8 -/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9 -/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10 -/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11 -/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S) -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S 12 -/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S) -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S 13 -/** SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_START_INT_ENA (BIT(14)) -#define SLCHOST_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_SLC1HOST_RX_START_INT_ENA_S) -#define SLCHOST_SLC1HOST_RX_START_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_START_INT_ENA_S 14 -/** SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TX_START_INT_ENA (BIT(15)) -#define SLCHOST_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_SLC1HOST_TX_START_INT_ENA_S) -#define SLCHOST_SLC1HOST_TX_START_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1HOST_TX_START_INT_ENA_S 15 -/** SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_UDF_INT_ENA (BIT(16)) -#define SLCHOST_SLC1_RX_UDF_INT_ENA_M (SLCHOST_SLC1_RX_UDF_INT_ENA_V << SLCHOST_SLC1_RX_UDF_INT_ENA_S) -#define SLCHOST_SLC1_RX_UDF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_RX_UDF_INT_ENA_S 16 -/** SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TX_OVF_INT_ENA (BIT(17)) -#define SLCHOST_SLC1_TX_OVF_INT_ENA_M (SLCHOST_SLC1_TX_OVF_INT_ENA_V << SLCHOST_SLC1_TX_OVF_INT_ENA_S) -#define SLCHOST_SLC1_TX_OVF_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_TX_OVF_INT_ENA_S 17 -/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S) -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S 18 -/** SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA (BIT(19)) -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA_S) -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_S 19 -/** SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA (BIT(20)) -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA_S) -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_S 20 -/** SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA (BIT(21)) -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA_S) -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_S 21 -/** SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA (BIT(22)) -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA_S) -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_S 22 -/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 -/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24 -/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 - -/** SLCHOST_SLC0HOST_RX_INFOR_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf4) -/** SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_INFOR 0x000FFFFFU -#define SLCHOST_SLC0HOST_RX_INFOR_M (SLCHOST_SLC0HOST_RX_INFOR_V << SLCHOST_SLC0HOST_RX_INFOR_S) -#define SLCHOST_SLC0HOST_RX_INFOR_V 0x000FFFFFU -#define SLCHOST_SLC0HOST_RX_INFOR_S 0 - -/** SLCHOST_SLC1HOST_RX_INFOR_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf8) -/** SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_INFOR 0x000FFFFFU -#define SLCHOST_SLC1HOST_RX_INFOR_M (SLCHOST_SLC1HOST_RX_INFOR_V << SLCHOST_SLC1HOST_RX_INFOR_S) -#define SLCHOST_SLC1HOST_RX_INFOR_V 0x000FFFFFU -#define SLCHOST_SLC1HOST_RX_INFOR_S 0 - -/** SLCHOST_SLC0HOST_LEN_WD_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xfc) -/** SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_LEN_WD 0xFFFFFFFFU -#define SLCHOST_SLC0HOST_LEN_WD_M (SLCHOST_SLC0HOST_LEN_WD_V << SLCHOST_SLC0HOST_LEN_WD_S) -#define SLCHOST_SLC0HOST_LEN_WD_V 0xFFFFFFFFU -#define SLCHOST_SLC0HOST_LEN_WD_S 0 - -/** SLCHOST_SLC_APBWIN_WDATA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100) -/** SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_WDATA 0xFFFFFFFFU -#define SLCHOST_SLC_APBWIN_WDATA_M (SLCHOST_SLC_APBWIN_WDATA_V << SLCHOST_SLC_APBWIN_WDATA_S) -#define SLCHOST_SLC_APBWIN_WDATA_V 0xFFFFFFFFU -#define SLCHOST_SLC_APBWIN_WDATA_S 0 - -/** SLCHOST_SLC_APBWIN_CONF_REG register - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104) -/** SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_ADDR 0x0FFFFFFFU -#define SLCHOST_SLC_APBWIN_ADDR_M (SLCHOST_SLC_APBWIN_ADDR_V << SLCHOST_SLC_APBWIN_ADDR_S) -#define SLCHOST_SLC_APBWIN_ADDR_V 0x0FFFFFFFU -#define SLCHOST_SLC_APBWIN_ADDR_S 0 -/** SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_WR (BIT(28)) -#define SLCHOST_SLC_APBWIN_WR_M (SLCHOST_SLC_APBWIN_WR_V << SLCHOST_SLC_APBWIN_WR_S) -#define SLCHOST_SLC_APBWIN_WR_V 0x00000001U -#define SLCHOST_SLC_APBWIN_WR_S 28 -/** SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_START (BIT(29)) -#define SLCHOST_SLC_APBWIN_START_M (SLCHOST_SLC_APBWIN_START_V << SLCHOST_SLC_APBWIN_START_S) -#define SLCHOST_SLC_APBWIN_START_V 0x00000001U -#define SLCHOST_SLC_APBWIN_START_S 29 - -/** SLCHOST_SLC_APBWIN_RDATA_REG register - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108) -/** SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC_APBWIN_RDATA 0xFFFFFFFFU -#define SLCHOST_SLC_APBWIN_RDATA_M (SLCHOST_SLC_APBWIN_RDATA_V << SLCHOST_SLC_APBWIN_RDATA_S) -#define SLCHOST_SLC_APBWIN_RDATA_V 0xFFFFFFFFU -#define SLCHOST_SLC_APBWIN_RDATA_S 0 - -/** SLCHOST_RDCLR0_REG register - * *******Description*********** - */ -#define SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10c) -/** SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FFU -#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M (SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S) -#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x000001FFU -#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 -/** SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FFU -#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M (SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S) -#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x000001FFU -#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 - -/** SLCHOST_RDCLR1_REG register - * *******Description*********** - */ -#define SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110) -/** SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FFU -#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M (SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S) -#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x000001FFU -#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0 -/** SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FFU -#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M (SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S) -#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x000001FFU -#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9 - -/** SLCHOST_SLC0HOST_INT_ENA1_REG register - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114) -/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 -/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 -/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 -/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 -/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 -/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 -/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 -/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S) -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 -/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S) -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 -/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S) -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 -/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S) -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 -/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S) -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 -/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M (SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S) -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 -/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M (SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S) -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 -/** SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) -#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_M (SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SLCHOST_SLC0HOST_RX_START_INT_ENA1_S) -#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_S 14 -/** SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) -#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_M (SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SLCHOST_SLC0HOST_TX_START_INT_ENA1_S) -#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_S 15 -/** SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) -#define SLCHOST_SLC0_RX_UDF_INT_ENA1_M (SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SLCHOST_SLC0_RX_UDF_INT_ENA1_S) -#define SLCHOST_SLC0_RX_UDF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_RX_UDF_INT_ENA1_S 16 -/** SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) -#define SLCHOST_SLC0_TX_OVF_INT_ENA1_M (SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SLCHOST_SLC0_TX_OVF_INT_ENA1_S) -#define SLCHOST_SLC0_TX_OVF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_TX_OVF_INT_ENA1_S 17 -/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M (SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S) -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 -/** SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S) -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S 19 -/** SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S) -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S 20 -/** SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S) -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S 21 -/** SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S) -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S 22 -/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S) -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 -/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S) -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 -/** SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_GPIO_SDIO_INT_ENA1 (BIT(25)) -#define SLCHOST_GPIO_SDIO_INT_ENA1_M (SLCHOST_GPIO_SDIO_INT_ENA1_V << SLCHOST_GPIO_SDIO_INT_ENA1_S) -#define SLCHOST_GPIO_SDIO_INT_ENA1_V 0x00000001U -#define SLCHOST_GPIO_SDIO_INT_ENA1_S 25 - -/** SLCHOST_SLC1HOST_INT_ENA1_REG register - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118) -/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0)) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0 -/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1)) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1 -/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2)) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2 -/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3)) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3 -/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4)) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4 -/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5)) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5 -/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6)) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6 -/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7)) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S) -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7 -/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8)) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S) -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8 -/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9)) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S) -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9 -/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10)) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S) -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10 -/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11)) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S) -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11 -/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12)) -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M (SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S) -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S 12 -/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13)) -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M (SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S) -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S 13 -/** SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14)) -#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_M (SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SLCHOST_SLC1HOST_RX_START_INT_ENA1_S) -#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_S 14 -/** SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15)) -#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_M (SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SLCHOST_SLC1HOST_TX_START_INT_ENA1_S) -#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_S 15 -/** SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_UDF_INT_ENA1 (BIT(16)) -#define SLCHOST_SLC1_RX_UDF_INT_ENA1_M (SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SLCHOST_SLC1_RX_UDF_INT_ENA1_S) -#define SLCHOST_SLC1_RX_UDF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_RX_UDF_INT_ENA1_S 16 -/** SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_TX_OVF_INT_ENA1 (BIT(17)) -#define SLCHOST_SLC1_TX_OVF_INT_ENA1_M (SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SLCHOST_SLC1_TX_OVF_INT_ENA1_S) -#define SLCHOST_SLC1_TX_OVF_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_TX_OVF_INT_ENA1_S 17 -/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18)) -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M (SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S) -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S 18 -/** SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19)) -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S) -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S 19 -/** SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20)) -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S) -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S 20 -/** SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21)) -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S) -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S 21 -/** SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22)) -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S) -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S 22 -/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23)) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S) -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23 -/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24)) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S) -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24 -/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25)) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S) -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x00000001U -#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25 - -/** SLCHOST_SLCHOSTDATE_REG register - * *******Description*********** - */ -#define SLCHOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178) -/** SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_DATE 0xFFFFFFFFU -#define SLCHOST_SLCHOST_DATE_M (SLCHOST_SLCHOST_DATE_V << SLCHOST_SLCHOST_DATE_S) -#define SLCHOST_SLCHOST_DATE_V 0xFFFFFFFFU -#define SLCHOST_SLCHOST_DATE_S 0 - -/** SLCHOST_SLCHOSTID_REG register - * *******Description*********** - */ -#define SLCHOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17c) -/** SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536; - * *******Description*********** - */ -#define SLCHOST_SLCHOST_ID 0xFFFFFFFFU -#define SLCHOST_SLCHOST_ID_M (SLCHOST_SLCHOST_ID_V << SLCHOST_SLCHOST_ID_S) -#define SLCHOST_SLCHOST_ID_V 0xFFFFFFFFU -#define SLCHOST_SLCHOST_ID_S 0 - -/** SLCHOST_CONF_REG register - * *******Description*********** - */ -#define SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1f0) -/** SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FRC_SDIO11 0x0000001FU -#define SLCHOST_FRC_SDIO11_M (SLCHOST_FRC_SDIO11_V << SLCHOST_FRC_SDIO11_S) -#define SLCHOST_FRC_SDIO11_V 0x0000001FU -#define SLCHOST_FRC_SDIO11_S 0 -/** SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FRC_SDIO20 0x0000001FU -#define SLCHOST_FRC_SDIO20_M (SLCHOST_FRC_SDIO20_V << SLCHOST_FRC_SDIO20_S) -#define SLCHOST_FRC_SDIO20_V 0x0000001FU -#define SLCHOST_FRC_SDIO20_S 5 -/** SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FRC_NEG_SAMP 0x0000001FU -#define SLCHOST_FRC_NEG_SAMP_M (SLCHOST_FRC_NEG_SAMP_V << SLCHOST_FRC_NEG_SAMP_S) -#define SLCHOST_FRC_NEG_SAMP_V 0x0000001FU -#define SLCHOST_FRC_NEG_SAMP_S 10 -/** SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FRC_POS_SAMP 0x0000001FU -#define SLCHOST_FRC_POS_SAMP_M (SLCHOST_FRC_POS_SAMP_V << SLCHOST_FRC_POS_SAMP_S) -#define SLCHOST_FRC_POS_SAMP_V 0x0000001FU -#define SLCHOST_FRC_POS_SAMP_S 15 -/** SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0; - * *******Description*********** - */ -#define SLCHOST_FRC_QUICK_IN 0x0000001FU -#define SLCHOST_FRC_QUICK_IN_M (SLCHOST_FRC_QUICK_IN_V << SLCHOST_FRC_QUICK_IN_S) -#define SLCHOST_FRC_QUICK_IN_V 0x0000001FU -#define SLCHOST_FRC_QUICK_IN_S 20 -/** SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SDIO20_INT_DELAY (BIT(25)) -#define SLCHOST_SDIO20_INT_DELAY_M (SLCHOST_SDIO20_INT_DELAY_V << SLCHOST_SDIO20_INT_DELAY_S) -#define SLCHOST_SDIO20_INT_DELAY_V 0x00000001U -#define SLCHOST_SDIO20_INT_DELAY_S 25 -/** SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SDIO_PAD_PULLUP (BIT(26)) -#define SLCHOST_SDIO_PAD_PULLUP_M (SLCHOST_SDIO_PAD_PULLUP_V << SLCHOST_SDIO_PAD_PULLUP_S) -#define SLCHOST_SDIO_PAD_PULLUP_V 0x00000001U -#define SLCHOST_SDIO_PAD_PULLUP_S 26 -/** SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0; - * *******Description*********** - */ -#define SLCHOST_HSPEED_CON_EN (BIT(27)) -#define SLCHOST_HSPEED_CON_EN_M (SLCHOST_HSPEED_CON_EN_V << SLCHOST_HSPEED_CON_EN_S) -#define SLCHOST_HSPEED_CON_EN_V 0x00000001U -#define SLCHOST_HSPEED_CON_EN_S 27 - -/** SLCHOST_INF_ST_REG register - * *******Description*********** - */ -#define SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1f4) -/** SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SDIO20_MODE 0x0000001FU -#define SLCHOST_SDIO20_MODE_M (SLCHOST_SDIO20_MODE_V << SLCHOST_SDIO20_MODE_S) -#define SLCHOST_SDIO20_MODE_V 0x0000001FU -#define SLCHOST_SDIO20_MODE_S 0 -/** SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SDIO_NEG_SAMP 0x0000001FU -#define SLCHOST_SDIO_NEG_SAMP_M (SLCHOST_SDIO_NEG_SAMP_V << SLCHOST_SDIO_NEG_SAMP_S) -#define SLCHOST_SDIO_NEG_SAMP_V 0x0000001FU -#define SLCHOST_SDIO_NEG_SAMP_S 5 -/** SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0; - * *******Description*********** - */ -#define SLCHOST_SDIO_QUICK_IN 0x0000001FU -#define SLCHOST_SDIO_QUICK_IN_M (SLCHOST_SDIO_QUICK_IN_V << SLCHOST_SDIO_QUICK_IN_S) -#define SLCHOST_SDIO_QUICK_IN_V 0x0000001FU -#define SLCHOST_SDIO_QUICK_IN_S 10 -/** SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0; - * dll is controlled by software - */ -#define SLCHOST_DLL_ON_SW (BIT(15)) -#define SLCHOST_DLL_ON_SW_M (SLCHOST_DLL_ON_SW_V << SLCHOST_DLL_ON_SW_S) -#define SLCHOST_DLL_ON_SW_V 0x00000001U -#define SLCHOST_DLL_ON_SW_S 15 -/** SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0; - * Software dll on - */ -#define SLCHOST_DLL_ON (BIT(16)) -#define SLCHOST_DLL_ON_M (SLCHOST_DLL_ON_V << SLCHOST_DLL_ON_S) -#define SLCHOST_DLL_ON_V 0x00000001U -#define SLCHOST_DLL_ON_S 16 -/** SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0; - * dll clock mode is controlled by software - */ -#define SLCHOST_CLK_MODE_SW (BIT(17)) -#define SLCHOST_CLK_MODE_SW_M (SLCHOST_CLK_MODE_SW_V << SLCHOST_CLK_MODE_SW_S) -#define SLCHOST_CLK_MODE_SW_V 0x00000001U -#define SLCHOST_CLK_MODE_SW_S 17 -/** SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0; - * Software set clock mode - */ -#define SLCHOST_CLK_MODE 0x00000003U -#define SLCHOST_CLK_MODE_M (SLCHOST_CLK_MODE_V << SLCHOST_CLK_MODE_S) -#define SLCHOST_CLK_MODE_V 0x00000003U -#define SLCHOST_CLK_MODE_S 18 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/host_struct.h b/components/soc/esp32p4/include/soc/host_struct.h deleted file mode 100644 index 275e30e72f..0000000000 --- a/components/soc/esp32p4/include/soc/host_struct.h +++ /dev/null @@ -1,2738 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: ********Registers */ -/** Type of func2_0 register - * *******Description*********** - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** slc_func2_int : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc_func2_int:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} slchost_func2_0_reg_t; - -/** Type of func2_1 register - * *******Description*********** - */ -typedef union { - struct { - /** slc_func2_int_en : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc_func2_int_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} slchost_func2_1_reg_t; - -/** Type of func2_2 register - * *******Description*********** - */ -typedef union { - struct { - /** slc_func1_mdstat : R/W; bitpos: [0]; default: 1; - * *******Description*********** - */ - uint32_t slc_func1_mdstat:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} slchost_func2_2_reg_t; - -/** Type of gpio_status0 register - * *******Description*********** - */ -typedef union { - struct { - /** gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_int0:32; - }; - uint32_t val; -} slchost_gpio_status0_reg_t; - -/** Type of gpio_status1 register - * *******Description*********** - */ -typedef union { - struct { - /** gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_int1:32; - }; - uint32_t val; -} slchost_gpio_status1_reg_t; - -/** Type of gpio_in0 register - * *******Description*********** - */ -typedef union { - struct { - /** gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_in0:32; - }; - uint32_t val; -} slchost_gpio_in0_reg_t; - -/** Type of gpio_in1 register - * *******Description*********** - */ -typedef union { - struct { - /** gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_in1:32; - }; - uint32_t val; -} slchost_gpio_in1_reg_t; - -/** Type of slc0host_token_rdata register - * *******Description*********** - */ -typedef union { - struct { - /** slc0_token0 : RO; bitpos: [11:0]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0:12; - /** slc0_rx_pf_valid : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_pf_valid:1; - uint32_t reserved_13:3; - /** hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_token1:12; - /** slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_pf_eof:4; - }; - uint32_t val; -} slchost_slc0host_token_rdata_reg_t; - -/** Type of slc0_host_pf register - * *******Description*********** - */ -typedef union { - struct { - /** slc0_pf_data : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t slc0_pf_data:32; - }; - uint32_t val; -} slchost_slc0_host_pf_reg_t; - -/** Type of slc1_host_pf register - * *******Description*********** - */ -typedef union { - struct { - /** slc1_pf_data : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t slc1_pf_data:32; - }; - uint32_t val; -} slchost_slc1_host_pf_reg_t; - -/** Type of slc0host_int_raw register - * *******Description*********** - */ -typedef union { - struct { - /** slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit0_int_raw:1; - /** slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit1_int_raw:1; - /** slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit2_int_raw:1; - /** slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit3_int_raw:1; - /** slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit4_int_raw:1; - /** slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit5_int_raw:1; - /** slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit6_int_raw:1; - /** slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit7_int_raw:1; - /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_1to0_int_raw:1; - /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_1to0_int_raw:1; - /** slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_0to1_int_raw:1; - /** slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_0to1_int_raw:1; - /** slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_sof_int_raw:1; - /** slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_eof_int_raw:1; - /** slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_start_int_raw:1; - /** slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_tx_start_int_raw:1; - /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_udf_int_raw:1; - /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tx_ovf_int_raw:1; - /** slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_pf_valid_int_raw:1; - /** slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit0_int_raw:1; - /** slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit1_int_raw:1; - /** slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit2_int_raw:1; - /** slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit3_int_raw:1; - /** slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_new_packet_int_raw:1; - /** slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc0_host_rd_retry_int_raw:1; - /** gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_int_raw:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc0host_int_raw_reg_t; - -/** Type of slc1host_int_raw register - * *******Description*********** - */ -typedef union { - struct { - /** slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit0_int_raw:1; - /** slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit1_int_raw:1; - /** slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit2_int_raw:1; - /** slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit3_int_raw:1; - /** slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit4_int_raw:1; - /** slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit5_int_raw:1; - /** slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit6_int_raw:1; - /** slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit7_int_raw:1; - /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_1to0_int_raw:1; - /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_1to0_int_raw:1; - /** slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_0to1_int_raw:1; - /** slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_0to1_int_raw:1; - /** slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_sof_int_raw:1; - /** slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_eof_int_raw:1; - /** slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_start_int_raw:1; - /** slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_tx_start_int_raw:1; - /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_udf_int_raw:1; - /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tx_ovf_int_raw:1; - /** slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_pf_valid_int_raw:1; - /** slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit0_int_raw:1; - /** slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit1_int_raw:1; - /** slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit2_int_raw:1; - /** slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit3_int_raw:1; - /** slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc1_wifi_rx_new_packet_int_raw:1; - /** slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc1_host_rd_retry_int_raw:1; - /** slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t slc1_bt_rx_new_packet_int_raw:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc1host_int_raw_reg_t; - -/** Type of slc0host_int_st register - * *******Description*********** - */ -typedef union { - struct { - /** slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit0_int_st:1; - /** slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit1_int_st:1; - /** slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit2_int_st:1; - /** slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit3_int_st:1; - /** slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit4_int_st:1; - /** slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit5_int_st:1; - /** slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit6_int_st:1; - /** slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit7_int_st:1; - /** slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_1to0_int_st:1; - /** slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_1to0_int_st:1; - /** slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_0to1_int_st:1; - /** slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_0to1_int_st:1; - /** slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_sof_int_st:1; - /** slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_eof_int_st:1; - /** slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_start_int_st:1; - /** slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_tx_start_int_st:1; - /** slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_udf_int_st:1; - /** slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tx_ovf_int_st:1; - /** slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_pf_valid_int_st:1; - /** slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit0_int_st:1; - /** slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit1_int_st:1; - /** slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit2_int_st:1; - /** slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit3_int_st:1; - /** slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_new_packet_int_st:1; - /** slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc0_host_rd_retry_int_st:1; - /** gpio_sdio_int_st : RO; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_int_st:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc0host_int_st_reg_t; - -/** Type of slc1host_int_st register - * *******Description*********** - */ -typedef union { - struct { - /** slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit0_int_st:1; - /** slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit1_int_st:1; - /** slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit2_int_st:1; - /** slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit3_int_st:1; - /** slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit4_int_st:1; - /** slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit5_int_st:1; - /** slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit6_int_st:1; - /** slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit7_int_st:1; - /** slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_1to0_int_st:1; - /** slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_1to0_int_st:1; - /** slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_0to1_int_st:1; - /** slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_0to1_int_st:1; - /** slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_sof_int_st:1; - /** slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_eof_int_st:1; - /** slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_start_int_st:1; - /** slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_tx_start_int_st:1; - /** slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_udf_int_st:1; - /** slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tx_ovf_int_st:1; - /** slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_pf_valid_int_st:1; - /** slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit0_int_st:1; - /** slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit1_int_st:1; - /** slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit2_int_st:1; - /** slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit3_int_st:1; - /** slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc1_wifi_rx_new_packet_int_st:1; - /** slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc1_host_rd_retry_int_st:1; - /** slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t slc1_bt_rx_new_packet_int_st:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc1host_int_st_reg_t; - -/** Type of pkt_len register - * *******Description*********** - */ -typedef union { - struct { - /** hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len:20; - /** hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len_check:12; - }; - uint32_t val; -} slchost_pkt_len_reg_t; - -/** Type of state_w0 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_state0 : RO; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state0:8; - /** slchost_state1 : RO; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state1:8; - /** slchost_state2 : RO; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state2:8; - /** slchost_state3 : RO; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state3:8; - }; - uint32_t val; -} slchost_state_w0_reg_t; - -/** Type of state_w1 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_state4 : RO; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state4:8; - /** slchost_state5 : RO; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state5:8; - /** slchost_state6 : RO; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state6:8; - /** slchost_state7 : RO; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_state7:8; - }; - uint32_t val; -} slchost_state_w1_reg_t; - -/** Type of conf_w0 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf0 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf0:8; - /** slchost_conf1 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf1:8; - /** slchost_conf2 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf2:8; - /** slchost_conf3 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf3:8; - }; - uint32_t val; -} slchost_conf_w0_reg_t; - -/** Type of conf_w1 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf4 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf4:8; - /** slchost_conf5 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf5:8; - /** slchost_conf6 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf6:8; - /** slchost_conf7 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf7:8; - }; - uint32_t val; -} slchost_conf_w1_reg_t; - -/** Type of conf_w2 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf8 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf8:8; - /** slchost_conf9 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf9:8; - /** slchost_conf10 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf10:8; - /** slchost_conf11 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf11:8; - }; - uint32_t val; -} slchost_conf_w2_reg_t; - -/** Type of conf_w3 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf12 : R/W; bitpos: [7:0]; default: 192; - * *******Description*********** - */ - uint32_t slchost_conf12:8; - /** slchost_conf13 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf13:8; - /** slchost_conf14 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf14:8; - /** slchost_conf15 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf15:8; - }; - uint32_t val; -} slchost_conf_w3_reg_t; - -/** Type of conf_w4 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf16 : R/W; bitpos: [7:0]; default: 255; - * *******Description*********** - */ - uint32_t slchost_conf16:8; - /** slchost_conf17 : R/W; bitpos: [15:8]; default: 1; - * *******Description*********** - */ - uint32_t slchost_conf17:8; - /** slchost_conf18 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf18:8; - /** slchost_conf19 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf19:8; - }; - uint32_t val; -} slchost_conf_w4_reg_t; - -/** Type of conf_w5 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf20 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf20:8; - /** slchost_conf21 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf21:8; - /** slchost_conf22 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf22:8; - /** slchost_conf23 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf23:8; - }; - uint32_t val; -} slchost_conf_w5_reg_t; - -/** Type of win_cmd register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_win_cmd : R/W; bitpos: [15:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_win_cmd:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} slchost_win_cmd_reg_t; - -/** Type of conf_w6 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf24 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf24:8; - /** slchost_conf25 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf25:8; - /** slchost_conf26 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf26:8; - /** slchost_conf27 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf27:8; - }; - uint32_t val; -} slchost_conf_w6_reg_t; - -/** Type of conf_w7 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf28 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf28:8; - /** slchost_conf29 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf29:8; - /** slchost_conf30 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf30:8; - /** slchost_conf31 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf31:8; - }; - uint32_t val; -} slchost_conf_w7_reg_t; - -/** Type of pkt_len0 register - * *******Description*********** - */ -typedef union { - struct { - /** hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len0:20; - /** hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len0_check:12; - }; - uint32_t val; -} slchost_pkt_len0_reg_t; - -/** Type of pkt_len1 register - * *******Description*********** - */ -typedef union { - struct { - /** hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len1:20; - /** hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len1_check:12; - }; - uint32_t val; -} slchost_pkt_len1_reg_t; - -/** Type of pkt_len2 register - * *******Description*********** - */ -typedef union { - struct { - /** hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len2:20; - /** hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc0_len2_check:12; - }; - uint32_t val; -} slchost_pkt_len2_reg_t; - -/** Type of conf_w8 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf32 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf32:8; - /** slchost_conf33 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf33:8; - /** slchost_conf34 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf34:8; - /** slchost_conf35 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf35:8; - }; - uint32_t val; -} slchost_conf_w8_reg_t; - -/** Type of conf_w9 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf36 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf36:8; - /** slchost_conf37 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf37:8; - /** slchost_conf38 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf38:8; - /** slchost_conf39 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf39:8; - }; - uint32_t val; -} slchost_conf_w9_reg_t; - -/** Type of conf_w10 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf40 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf40:8; - /** slchost_conf41 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf41:8; - /** slchost_conf42 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf42:8; - /** slchost_conf43 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf43:8; - }; - uint32_t val; -} slchost_conf_w10_reg_t; - -/** Type of conf_w11 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf44 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf44:8; - /** slchost_conf45 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf45:8; - /** slchost_conf46 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf46:8; - /** slchost_conf47 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf47:8; - }; - uint32_t val; -} slchost_conf_w11_reg_t; - -/** Type of conf_w12 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf48 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf48:8; - /** slchost_conf49 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf49:8; - /** slchost_conf50 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf50:8; - /** slchost_conf51 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf51:8; - }; - uint32_t val; -} slchost_conf_w12_reg_t; - -/** Type of conf_w13 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf52 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf52:8; - /** slchost_conf53 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf53:8; - /** slchost_conf54 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf54:8; - /** slchost_conf55 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf55:8; - }; - uint32_t val; -} slchost_conf_w13_reg_t; - -/** Type of conf_w14 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf56 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf56:8; - /** slchost_conf57 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf57:8; - /** slchost_conf58 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf58:8; - /** slchost_conf59 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf59:8; - }; - uint32_t val; -} slchost_conf_w14_reg_t; - -/** Type of conf_w15 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_conf60 : R/W; bitpos: [7:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf60:8; - /** slchost_conf61 : R/W; bitpos: [15:8]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf61:8; - /** slchost_conf62 : R/W; bitpos: [23:16]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf62:8; - /** slchost_conf63 : R/W; bitpos: [31:24]; default: 0; - * *******Description*********** - */ - uint32_t slchost_conf63:8; - }; - uint32_t val; -} slchost_conf_w15_reg_t; - -/** Type of check_sum0 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_check_sum0 : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t slchost_check_sum0:32; - }; - uint32_t val; -} slchost_check_sum0_reg_t; - -/** Type of check_sum1 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_check_sum1 : RO; bitpos: [31:0]; default: 319; - * *******Description*********** - */ - uint32_t slchost_check_sum1:32; - }; - uint32_t val; -} slchost_check_sum1_reg_t; - -/** Type of slc1host_token_rdata register - * *******Description*********** - */ -typedef union { - struct { - /** slc1_token0 : RO; bitpos: [11:0]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0:12; - /** slc1_rx_pf_valid : RO; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_pf_valid:1; - uint32_t reserved_13:3; - /** hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0; - * *******Description*********** - */ - uint32_t hostslchost_slc1_token1:12; - /** slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_pf_eof:4; - }; - uint32_t val; -} slchost_slc1host_token_rdata_reg_t; - -/** Type of slc0host_token_wdata register - * *******Description*********** - */ -typedef union { - struct { - /** slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_token0_wd:12; - uint32_t reserved_12:4; - /** slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_token1_wd:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} slchost_slc0host_token_wdata_reg_t; - -/** Type of slc1host_token_wdata register - * *******Description*********** - */ -typedef union { - struct { - /** slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_token0_wd:12; - uint32_t reserved_12:4; - /** slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_token1_wd:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} slchost_slc1host_token_wdata_reg_t; - -/** Type of token_con register - * *******Description*********** - */ -typedef union { - struct { - /** slc0host_token0_dec : WT; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_token0_dec:1; - /** slc0host_token1_dec : WT; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_token1_dec:1; - /** slc0host_token0_wr : WT; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_token0_wr:1; - /** slc0host_token1_wr : WT; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_token1_wr:1; - /** slc1host_token0_dec : WT; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_token0_dec:1; - /** slc1host_token1_dec : WT; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_token1_dec:1; - /** slc1host_token0_wr : WT; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_token0_wr:1; - /** slc1host_token1_wr : WT; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_token1_wr:1; - /** slc0host_len_wr : WT; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_len_wr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} slchost_token_con_reg_t; - -/** Type of slc0host_int_clr register - * *******Description*********** - */ -typedef union { - struct { - /** slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit0_int_clr:1; - /** slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit1_int_clr:1; - /** slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit2_int_clr:1; - /** slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit3_int_clr:1; - /** slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit4_int_clr:1; - /** slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit5_int_clr:1; - /** slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit6_int_clr:1; - /** slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit7_int_clr:1; - /** slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_1to0_int_clr:1; - /** slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_1to0_int_clr:1; - /** slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_0to1_int_clr:1; - /** slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_0to1_int_clr:1; - /** slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_sof_int_clr:1; - /** slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_eof_int_clr:1; - /** slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_start_int_clr:1; - /** slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_tx_start_int_clr:1; - /** slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_udf_int_clr:1; - /** slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tx_ovf_int_clr:1; - /** slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_pf_valid_int_clr:1; - /** slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit0_int_clr:1; - /** slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit1_int_clr:1; - /** slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit2_int_clr:1; - /** slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit3_int_clr:1; - /** slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_new_packet_int_clr:1; - /** slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc0_host_rd_retry_int_clr:1; - /** gpio_sdio_int_clr : WT; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_int_clr:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc0host_int_clr_reg_t; - -/** Type of slc1host_int_clr register - * *******Description*********** - */ -typedef union { - struct { - /** slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit0_int_clr:1; - /** slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit1_int_clr:1; - /** slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit2_int_clr:1; - /** slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit3_int_clr:1; - /** slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit4_int_clr:1; - /** slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit5_int_clr:1; - /** slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit6_int_clr:1; - /** slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit7_int_clr:1; - /** slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_1to0_int_clr:1; - /** slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_1to0_int_clr:1; - /** slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_0to1_int_clr:1; - /** slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_0to1_int_clr:1; - /** slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_sof_int_clr:1; - /** slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_eof_int_clr:1; - /** slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_start_int_clr:1; - /** slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_tx_start_int_clr:1; - /** slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_udf_int_clr:1; - /** slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tx_ovf_int_clr:1; - /** slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_pf_valid_int_clr:1; - /** slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit0_int_clr:1; - /** slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit1_int_clr:1; - /** slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit2_int_clr:1; - /** slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit3_int_clr:1; - /** slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc1_wifi_rx_new_packet_int_clr:1; - /** slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc1_host_rd_retry_int_clr:1; - /** slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t slc1_bt_rx_new_packet_int_clr:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc1host_int_clr_reg_t; - -/** Type of slc0host_func1_int_ena register - * *******Description*********** - */ -typedef union { - struct { - /** fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit0_int_ena:1; - /** fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit1_int_ena:1; - /** fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit2_int_ena:1; - /** fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit3_int_ena:1; - /** fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit4_int_ena:1; - /** fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit5_int_ena:1; - /** fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit6_int_ena:1; - /** fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tohost_bit7_int_ena:1; - /** fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_token0_1to0_int_ena:1; - /** fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_token1_1to0_int_ena:1; - /** fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_token0_0to1_int_ena:1; - /** fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_token1_0to1_int_ena:1; - /** fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0host_rx_sof_int_ena:1; - /** fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0host_rx_eof_int_ena:1; - /** fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0host_rx_start_int_ena:1; - /** fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0host_tx_start_int_ena:1; - /** fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_rx_udf_int_ena:1; - /** fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_tx_ovf_int_ena:1; - /** fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_rx_pf_valid_int_ena:1; - /** fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_ext_bit0_int_ena:1; - /** fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_ext_bit1_int_ena:1; - /** fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_ext_bit2_int_ena:1; - /** fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_ext_bit3_int_ena:1; - /** fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_rx_new_packet_int_ena:1; - /** fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc0_host_rd_retry_int_ena:1; - /** fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t fn1_gpio_sdio_int_ena:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc0host_func1_int_ena_reg_t; - -/** Type of slc1host_func1_int_ena register - * *******Description*********** - */ -typedef union { - struct { - /** fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit0_int_ena:1; - /** fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit1_int_ena:1; - /** fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit2_int_ena:1; - /** fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit3_int_ena:1; - /** fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit4_int_ena:1; - /** fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit5_int_ena:1; - /** fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit6_int_ena:1; - /** fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tohost_bit7_int_ena:1; - /** fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_token0_1to0_int_ena:1; - /** fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_token1_1to0_int_ena:1; - /** fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_token0_0to1_int_ena:1; - /** fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_token1_0to1_int_ena:1; - /** fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1host_rx_sof_int_ena:1; - /** fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1host_rx_eof_int_ena:1; - /** fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1host_rx_start_int_ena:1; - /** fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1host_tx_start_int_ena:1; - /** fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_rx_udf_int_ena:1; - /** fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_tx_ovf_int_ena:1; - /** fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_rx_pf_valid_int_ena:1; - /** fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_ext_bit0_int_ena:1; - /** fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_ext_bit1_int_ena:1; - /** fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_ext_bit2_int_ena:1; - /** fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_ext_bit3_int_ena:1; - /** fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_wifi_rx_new_packet_int_ena:1; - /** fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_host_rd_retry_int_ena:1; - /** fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t fn1_slc1_bt_rx_new_packet_int_ena:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc1host_func1_int_ena_reg_t; - -/** Type of slc0host_func2_int_ena register - * *******Description*********** - */ -typedef union { - struct { - /** fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit0_int_ena:1; - /** fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit1_int_ena:1; - /** fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit2_int_ena:1; - /** fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit3_int_ena:1; - /** fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit4_int_ena:1; - /** fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit5_int_ena:1; - /** fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit6_int_ena:1; - /** fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tohost_bit7_int_ena:1; - /** fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_token0_1to0_int_ena:1; - /** fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_token1_1to0_int_ena:1; - /** fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_token0_0to1_int_ena:1; - /** fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_token1_0to1_int_ena:1; - /** fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0host_rx_sof_int_ena:1; - /** fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0host_rx_eof_int_ena:1; - /** fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0host_rx_start_int_ena:1; - /** fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0host_tx_start_int_ena:1; - /** fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_rx_udf_int_ena:1; - /** fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_tx_ovf_int_ena:1; - /** fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_rx_pf_valid_int_ena:1; - /** fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_ext_bit0_int_ena:1; - /** fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_ext_bit1_int_ena:1; - /** fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_ext_bit2_int_ena:1; - /** fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_ext_bit3_int_ena:1; - /** fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_rx_new_packet_int_ena:1; - /** fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc0_host_rd_retry_int_ena:1; - /** fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t fn2_gpio_sdio_int_ena:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc0host_func2_int_ena_reg_t; - -/** Type of slc1host_func2_int_ena register - * *******Description*********** - */ -typedef union { - struct { - /** fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit0_int_ena:1; - /** fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit1_int_ena:1; - /** fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit2_int_ena:1; - /** fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit3_int_ena:1; - /** fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit4_int_ena:1; - /** fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit5_int_ena:1; - /** fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit6_int_ena:1; - /** fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tohost_bit7_int_ena:1; - /** fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_token0_1to0_int_ena:1; - /** fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_token1_1to0_int_ena:1; - /** fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_token0_0to1_int_ena:1; - /** fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_token1_0to1_int_ena:1; - /** fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1host_rx_sof_int_ena:1; - /** fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1host_rx_eof_int_ena:1; - /** fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1host_rx_start_int_ena:1; - /** fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1host_tx_start_int_ena:1; - /** fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_rx_udf_int_ena:1; - /** fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_tx_ovf_int_ena:1; - /** fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_rx_pf_valid_int_ena:1; - /** fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_ext_bit0_int_ena:1; - /** fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_ext_bit1_int_ena:1; - /** fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_ext_bit2_int_ena:1; - /** fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_ext_bit3_int_ena:1; - /** fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_wifi_rx_new_packet_int_ena:1; - /** fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_host_rd_retry_int_ena:1; - /** fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t fn2_slc1_bt_rx_new_packet_int_ena:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc1host_func2_int_ena_reg_t; - -/** Type of slc0host_int_ena register - * *******Description*********** - */ -typedef union { - struct { - /** slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit0_int_ena:1; - /** slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit1_int_ena:1; - /** slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit2_int_ena:1; - /** slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit3_int_ena:1; - /** slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit4_int_ena:1; - /** slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit5_int_ena:1; - /** slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit6_int_ena:1; - /** slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit7_int_ena:1; - /** slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_1to0_int_ena:1; - /** slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_1to0_int_ena:1; - /** slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_0to1_int_ena:1; - /** slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_0to1_int_ena:1; - /** slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_sof_int_ena:1; - /** slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_eof_int_ena:1; - /** slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_start_int_ena:1; - /** slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_tx_start_int_ena:1; - /** slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_udf_int_ena:1; - /** slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tx_ovf_int_ena:1; - /** slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_pf_valid_int_ena:1; - /** slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit0_int_ena:1; - /** slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit1_int_ena:1; - /** slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit2_int_ena:1; - /** slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit3_int_ena:1; - /** slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_new_packet_int_ena:1; - /** slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc0_host_rd_retry_int_ena:1; - /** gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_int_ena:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc0host_int_ena_reg_t; - -/** Type of slc1host_int_ena register - * *******Description*********** - */ -typedef union { - struct { - /** slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit0_int_ena:1; - /** slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit1_int_ena:1; - /** slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit2_int_ena:1; - /** slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit3_int_ena:1; - /** slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit4_int_ena:1; - /** slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit5_int_ena:1; - /** slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit6_int_ena:1; - /** slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit7_int_ena:1; - /** slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_1to0_int_ena:1; - /** slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_1to0_int_ena:1; - /** slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_0to1_int_ena:1; - /** slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_0to1_int_ena:1; - /** slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_sof_int_ena:1; - /** slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_eof_int_ena:1; - /** slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_start_int_ena:1; - /** slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_tx_start_int_ena:1; - /** slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_udf_int_ena:1; - /** slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tx_ovf_int_ena:1; - /** slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_pf_valid_int_ena:1; - /** slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit0_int_ena:1; - /** slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit1_int_ena:1; - /** slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit2_int_ena:1; - /** slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit3_int_ena:1; - /** slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc1_wifi_rx_new_packet_int_ena:1; - /** slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc1_host_rd_retry_int_ena:1; - /** slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t slc1_bt_rx_new_packet_int_ena:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc1host_int_ena_reg_t; - -/** Type of slc0host_rx_infor register - * *******Description*********** - */ -typedef union { - struct { - /** slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_infor:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} slchost_slc0host_rx_infor_reg_t; - -/** Type of slc1host_rx_infor register - * *******Description*********** - */ -typedef union { - struct { - /** slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_infor:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} slchost_slc1host_rx_infor_reg_t; - -/** Type of slc0host_len_wd register - * *******Description*********** - */ -typedef union { - struct { - /** slc0host_len_wd : R/W; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_len_wd:32; - }; - uint32_t val; -} slchost_slc0host_len_wd_reg_t; - -/** Type of slc_apbwin_wdata register - * *******Description*********** - */ -typedef union { - struct { - /** slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t slc_apbwin_wdata:32; - }; - uint32_t val; -} slchost_slc_apbwin_wdata_reg_t; - -/** Type of slc_apbwin_conf register - * *******Description*********** - */ -typedef union { - struct { - /** slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0; - * *******Description*********** - */ - uint32_t slc_apbwin_addr:28; - /** slc_apbwin_wr : R/W; bitpos: [28]; default: 0; - * *******Description*********** - */ - uint32_t slc_apbwin_wr:1; - /** slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0; - * *******Description*********** - */ - uint32_t slc_apbwin_start:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} slchost_slc_apbwin_conf_reg_t; - -/** Type of slc_apbwin_rdata register - * *******Description*********** - */ -typedef union { - struct { - /** slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0; - * *******Description*********** - */ - uint32_t slc_apbwin_rdata:32; - }; - uint32_t val; -} slchost_slc_apbwin_rdata_reg_t; - -/** Type of rdclr0 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68; - * *******Description*********** - */ - uint32_t slchost_slc0_bit7_clraddr:9; - /** slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; - * *******Description*********** - */ - uint32_t slchost_slc0_bit6_clraddr:9; - uint32_t reserved_18:14; - }; - uint32_t val; -} slchost_rdclr0_reg_t; - -/** Type of rdclr1 register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480; - * *******Description*********** - */ - uint32_t slchost_slc1_bit7_clraddr:9; - /** slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; - * *******Description*********** - */ - uint32_t slchost_slc1_bit6_clraddr:9; - uint32_t reserved_18:14; - }; - uint32_t val; -} slchost_rdclr1_reg_t; - -/** Type of slc0host_int_ena1 register - * *******Description*********** - */ -typedef union { - struct { - /** slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit0_int_ena1:1; - /** slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit1_int_ena1:1; - /** slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit2_int_ena1:1; - /** slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit3_int_ena1:1; - /** slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit4_int_ena1:1; - /** slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit5_int_ena1:1; - /** slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit6_int_ena1:1; - /** slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tohost_bit7_int_ena1:1; - /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_1to0_int_ena1:1; - /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_1to0_int_ena1:1; - /** slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token0_0to1_int_ena1:1; - /** slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc0_token1_0to1_int_ena1:1; - /** slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_sof_int_ena1:1; - /** slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_eof_int_ena1:1; - /** slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_rx_start_int_ena1:1; - /** slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc0host_tx_start_int_ena1:1; - /** slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_udf_int_ena1:1; - /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc0_tx_ovf_int_ena1:1; - /** slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_pf_valid_int_ena1:1; - /** slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit0_int_ena1:1; - /** slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit1_int_ena1:1; - /** slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit2_int_ena1:1; - /** slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc0_ext_bit3_int_ena1:1; - /** slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc0_rx_new_packet_int_ena1:1; - /** slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc0_host_rd_retry_int_ena1:1; - /** gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t gpio_sdio_int_ena1:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc0host_int_ena1_reg_t; - -/** Type of slc1host_int_ena1 register - * *******Description*********** - */ -typedef union { - struct { - /** slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit0_int_ena1:1; - /** slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit1_int_ena1:1; - /** slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit2_int_ena1:1; - /** slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit3_int_ena1:1; - /** slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit4_int_ena1:1; - /** slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit5_int_ena1:1; - /** slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit6_int_ena1:1; - /** slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tohost_bit7_int_ena1:1; - /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_1to0_int_ena1:1; - /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_1to0_int_ena1:1; - /** slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token0_0to1_int_ena1:1; - /** slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; - * *******Description*********** - */ - uint32_t slc1_token1_0to1_int_ena1:1; - /** slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_sof_int_ena1:1; - /** slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_eof_int_ena1:1; - /** slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_rx_start_int_ena1:1; - /** slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; - * *******Description*********** - */ - uint32_t slc1host_tx_start_int_ena1:1; - /** slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_udf_int_ena1:1; - /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; - * *******Description*********** - */ - uint32_t slc1_tx_ovf_int_ena1:1; - /** slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; - * *******Description*********** - */ - uint32_t slc1_rx_pf_valid_int_ena1:1; - /** slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit0_int_ena1:1; - /** slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit1_int_ena1:1; - /** slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit2_int_ena1:1; - /** slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; - * *******Description*********** - */ - uint32_t slc1_ext_bit3_int_ena1:1; - /** slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; - * *******Description*********** - */ - uint32_t slc1_wifi_rx_new_packet_int_ena1:1; - /** slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; - * *******Description*********** - */ - uint32_t slc1_host_rd_retry_int_ena1:1; - /** slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t slc1_bt_rx_new_packet_int_ena1:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} slchost_slc1host_int_ena1_reg_t; - -/** Type of slchostdate register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_date : R/W; bitpos: [31:0]; default: 554043136; - * *******Description*********** - */ - uint32_t slchost_date:32; - }; - uint32_t val; -} slchost_slchostdate_reg_t; - -/** Type of slchostid register - * *******Description*********** - */ -typedef union { - struct { - /** slchost_id : R/W; bitpos: [31:0]; default: 1536; - * *******Description*********** - */ - uint32_t slchost_id:32; - }; - uint32_t val; -} slchost_slchostid_reg_t; - -/** Type of conf register - * *******Description*********** - */ -typedef union { - struct { - /** frc_sdio11 : R/W; bitpos: [4:0]; default: 0; - * *******Description*********** - */ - uint32_t frc_sdio11:5; - /** frc_sdio20 : R/W; bitpos: [9:5]; default: 0; - * *******Description*********** - */ - uint32_t frc_sdio20:5; - /** frc_neg_samp : R/W; bitpos: [14:10]; default: 0; - * *******Description*********** - */ - uint32_t frc_neg_samp:5; - /** frc_pos_samp : R/W; bitpos: [19:15]; default: 0; - * *******Description*********** - */ - uint32_t frc_pos_samp:5; - /** frc_quick_in : R/W; bitpos: [24:20]; default: 0; - * *******Description*********** - */ - uint32_t frc_quick_in:5; - /** sdio20_int_delay : R/W; bitpos: [25]; default: 0; - * *******Description*********** - */ - uint32_t sdio20_int_delay:1; - /** sdio_pad_pullup : R/W; bitpos: [26]; default: 0; - * *******Description*********** - */ - uint32_t sdio_pad_pullup:1; - /** hspeed_con_en : R/W; bitpos: [27]; default: 0; - * *******Description*********** - */ - uint32_t hspeed_con_en:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} slchost_conf_reg_t; - -/** Type of inf_st register - * *******Description*********** - */ -typedef union { - struct { - /** sdio20_mode : RO; bitpos: [4:0]; default: 0; - * *******Description*********** - */ - uint32_t sdio20_mode:5; - /** sdio_neg_samp : RO; bitpos: [9:5]; default: 0; - * *******Description*********** - */ - uint32_t sdio_neg_samp:5; - /** sdio_quick_in : RO; bitpos: [14:10]; default: 0; - * *******Description*********** - */ - uint32_t sdio_quick_in:5; - /** dll_on_sw : R/W; bitpos: [15]; default: 0; - * dll is controlled by software - */ - uint32_t dll_on_sw:1; - /** dll_on : R/W; bitpos: [16]; default: 0; - * Software dll on - */ - uint32_t dll_on:1; - /** clk_mode_sw : R/W; bitpos: [17]; default: 0; - * dll clock mode is controlled by software - */ - uint32_t clk_mode_sw:1; - /** clk_mode : R/W; bitpos: [19:18]; default: 0; - * Software set clock mode - */ - uint32_t clk_mode:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} slchost_inf_st_reg_t; - - -typedef struct host_dev_t { - uint32_t reserved_000[4]; - volatile slchost_func2_0_reg_t func2_0; - volatile slchost_func2_1_reg_t func2_1; - uint32_t reserved_018[2]; - volatile slchost_func2_2_reg_t func2_2; - uint32_t reserved_024[4]; - volatile slchost_gpio_status0_reg_t gpio_status0; - volatile slchost_gpio_status1_reg_t gpio_status1; - volatile slchost_gpio_in0_reg_t gpio_in0; - volatile slchost_gpio_in1_reg_t gpio_in1; - volatile slchost_slc0host_token_rdata_reg_t slc0host_token_rdata; - volatile slchost_slc0_host_pf_reg_t slc0_host_pf; - volatile slchost_slc1_host_pf_reg_t slc1_host_pf; - volatile slchost_slc0host_int_raw_reg_t slc0host_int_raw; - volatile slchost_slc1host_int_raw_reg_t slc1host_int_raw; - volatile slchost_slc0host_int_st_reg_t slc0host_int_st; - volatile slchost_slc1host_int_st_reg_t slc1host_int_st; - volatile slchost_pkt_len_reg_t pkt_len; - volatile slchost_state_w0_reg_t state_w0; - volatile slchost_state_w1_reg_t state_w1; - volatile slchost_conf_w0_reg_t conf_w0; - volatile slchost_conf_w1_reg_t conf_w1; - volatile slchost_conf_w2_reg_t conf_w2; - volatile slchost_conf_w3_reg_t conf_w3; - volatile slchost_conf_w4_reg_t conf_w4; - volatile slchost_conf_w5_reg_t conf_w5; - volatile slchost_win_cmd_reg_t win_cmd; - volatile slchost_conf_w6_reg_t conf_w6; - volatile slchost_conf_w7_reg_t conf_w7; - volatile slchost_pkt_len0_reg_t pkt_len0; - volatile slchost_pkt_len1_reg_t pkt_len1; - volatile slchost_pkt_len2_reg_t pkt_len2; - volatile slchost_conf_w8_reg_t conf_w8; - volatile slchost_conf_w9_reg_t conf_w9; - volatile slchost_conf_w10_reg_t conf_w10; - volatile slchost_conf_w11_reg_t conf_w11; - volatile slchost_conf_w12_reg_t conf_w12; - volatile slchost_conf_w13_reg_t conf_w13; - volatile slchost_conf_w14_reg_t conf_w14; - volatile slchost_conf_w15_reg_t conf_w15; - volatile slchost_check_sum0_reg_t check_sum0; - volatile slchost_check_sum1_reg_t check_sum1; - volatile slchost_slc1host_token_rdata_reg_t slc1host_token_rdata; - volatile slchost_slc0host_token_wdata_reg_t slc0host_token_wdata; - volatile slchost_slc1host_token_wdata_reg_t slc1host_token_wdata; - volatile slchost_token_con_reg_t token_con; - volatile slchost_slc0host_int_clr_reg_t slc0host_int_clr; - volatile slchost_slc1host_int_clr_reg_t slc1host_int_clr; - volatile slchost_slc0host_func1_int_ena_reg_t slc0host_func1_int_ena; - volatile slchost_slc1host_func1_int_ena_reg_t slc1host_func1_int_ena; - volatile slchost_slc0host_func2_int_ena_reg_t slc0host_func2_int_ena; - volatile slchost_slc1host_func2_int_ena_reg_t slc1host_func2_int_ena; - volatile slchost_slc0host_int_ena_reg_t slc0host_int_ena; - volatile slchost_slc1host_int_ena_reg_t slc1host_int_ena; - volatile slchost_slc0host_rx_infor_reg_t slc0host_rx_infor; - volatile slchost_slc1host_rx_infor_reg_t slc1host_rx_infor; - volatile slchost_slc0host_len_wd_reg_t slc0host_len_wd; - volatile slchost_slc_apbwin_wdata_reg_t slc_apbwin_wdata; - volatile slchost_slc_apbwin_conf_reg_t slc_apbwin_conf; - volatile slchost_slc_apbwin_rdata_reg_t slc_apbwin_rdata; - volatile slchost_rdclr0_reg_t rdclr0; - volatile slchost_rdclr1_reg_t rdclr1; - volatile slchost_slc0host_int_ena1_reg_t slc0host_int_ena1; - volatile slchost_slc1host_int_ena1_reg_t slc1host_int_ena1; - uint32_t reserved_11c[23]; - volatile slchost_slchostdate_reg_t slchostdate; - volatile slchost_slchostid_reg_t slchostid; - uint32_t reserved_180[28]; - volatile slchost_conf_reg_t conf; - volatile slchost_inf_st_reg_t inf_st; -} host_dev_t; - -extern host_dev_t HOST; - -#ifndef __cplusplus -_Static_assert(sizeof(host_dev_t) == 0x1f8, "Invalid size of host_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/hp_apm_reg.h b/components/soc/esp32p4/include/soc/hp_apm_reg.h deleted file mode 100644 index 4a9151ab69..0000000000 --- a/components/soc/esp32p4/include/soc/hp_apm_reg.h +++ /dev/null @@ -1,1838 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** HP_APM_REGION_FILTER_EN_REG register - * Region filter enable register - */ -#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) -/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; - * Region filter enable - */ -#define HP_APM_REGION_FILTER_EN 0x0000FFFFU -#define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) -#define HP_APM_REGION_FILTER_EN_V 0x0000FFFFU -#define HP_APM_REGION_FILTER_EN_S 0 - -/** HP_APM_REGION0_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) -/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region0 - */ -#define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) -#define HP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION0_ADDR_START_S 0 - -/** HP_APM_REGION0_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) -/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region0 - */ -#define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) -#define HP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION0_ADDR_END_S 0 - -/** HP_APM_REGION0_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) -/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION0_R0_PMS_X (BIT(0)) -#define HP_APM_REGION0_R0_PMS_X_M (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S) -#define HP_APM_REGION0_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION0_R0_PMS_X_S 0 -/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION0_R0_PMS_W (BIT(1)) -#define HP_APM_REGION0_R0_PMS_W_M (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S) -#define HP_APM_REGION0_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION0_R0_PMS_W_S 1 -/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION0_R0_PMS_R (BIT(2)) -#define HP_APM_REGION0_R0_PMS_R_M (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S) -#define HP_APM_REGION0_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION0_R0_PMS_R_S 2 -/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION0_R1_PMS_X (BIT(4)) -#define HP_APM_REGION0_R1_PMS_X_M (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S) -#define HP_APM_REGION0_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION0_R1_PMS_X_S 4 -/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION0_R1_PMS_W (BIT(5)) -#define HP_APM_REGION0_R1_PMS_W_M (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S) -#define HP_APM_REGION0_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION0_R1_PMS_W_S 5 -/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION0_R1_PMS_R (BIT(6)) -#define HP_APM_REGION0_R1_PMS_R_M (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S) -#define HP_APM_REGION0_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION0_R1_PMS_R_S 6 -/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION0_R2_PMS_X (BIT(8)) -#define HP_APM_REGION0_R2_PMS_X_M (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S) -#define HP_APM_REGION0_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION0_R2_PMS_X_S 8 -/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION0_R2_PMS_W (BIT(9)) -#define HP_APM_REGION0_R2_PMS_W_M (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S) -#define HP_APM_REGION0_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION0_R2_PMS_W_S 9 -/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION0_R2_PMS_R (BIT(10)) -#define HP_APM_REGION0_R2_PMS_R_M (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S) -#define HP_APM_REGION0_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION0_R2_PMS_R_S 10 - -/** HP_APM_REGION1_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) -/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region1 - */ -#define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) -#define HP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION1_ADDR_START_S 0 - -/** HP_APM_REGION1_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) -/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region1 - */ -#define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) -#define HP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION1_ADDR_END_S 0 - -/** HP_APM_REGION1_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) -/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION1_R0_PMS_X (BIT(0)) -#define HP_APM_REGION1_R0_PMS_X_M (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S) -#define HP_APM_REGION1_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION1_R0_PMS_X_S 0 -/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION1_R0_PMS_W (BIT(1)) -#define HP_APM_REGION1_R0_PMS_W_M (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S) -#define HP_APM_REGION1_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION1_R0_PMS_W_S 1 -/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION1_R0_PMS_R (BIT(2)) -#define HP_APM_REGION1_R0_PMS_R_M (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S) -#define HP_APM_REGION1_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION1_R0_PMS_R_S 2 -/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION1_R1_PMS_X (BIT(4)) -#define HP_APM_REGION1_R1_PMS_X_M (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S) -#define HP_APM_REGION1_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION1_R1_PMS_X_S 4 -/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION1_R1_PMS_W (BIT(5)) -#define HP_APM_REGION1_R1_PMS_W_M (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S) -#define HP_APM_REGION1_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION1_R1_PMS_W_S 5 -/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION1_R1_PMS_R (BIT(6)) -#define HP_APM_REGION1_R1_PMS_R_M (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S) -#define HP_APM_REGION1_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION1_R1_PMS_R_S 6 -/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION1_R2_PMS_X (BIT(8)) -#define HP_APM_REGION1_R2_PMS_X_M (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S) -#define HP_APM_REGION1_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION1_R2_PMS_X_S 8 -/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION1_R2_PMS_W (BIT(9)) -#define HP_APM_REGION1_R2_PMS_W_M (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S) -#define HP_APM_REGION1_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION1_R2_PMS_W_S 9 -/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION1_R2_PMS_R (BIT(10)) -#define HP_APM_REGION1_R2_PMS_R_M (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S) -#define HP_APM_REGION1_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION1_R2_PMS_R_S 10 - -/** HP_APM_REGION2_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) -/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region2 - */ -#define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) -#define HP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION2_ADDR_START_S 0 - -/** HP_APM_REGION2_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) -/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region2 - */ -#define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) -#define HP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION2_ADDR_END_S 0 - -/** HP_APM_REGION2_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) -/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION2_R0_PMS_X (BIT(0)) -#define HP_APM_REGION2_R0_PMS_X_M (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S) -#define HP_APM_REGION2_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION2_R0_PMS_X_S 0 -/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION2_R0_PMS_W (BIT(1)) -#define HP_APM_REGION2_R0_PMS_W_M (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S) -#define HP_APM_REGION2_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION2_R0_PMS_W_S 1 -/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION2_R0_PMS_R (BIT(2)) -#define HP_APM_REGION2_R0_PMS_R_M (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S) -#define HP_APM_REGION2_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION2_R0_PMS_R_S 2 -/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION2_R1_PMS_X (BIT(4)) -#define HP_APM_REGION2_R1_PMS_X_M (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S) -#define HP_APM_REGION2_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION2_R1_PMS_X_S 4 -/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION2_R1_PMS_W (BIT(5)) -#define HP_APM_REGION2_R1_PMS_W_M (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S) -#define HP_APM_REGION2_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION2_R1_PMS_W_S 5 -/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION2_R1_PMS_R (BIT(6)) -#define HP_APM_REGION2_R1_PMS_R_M (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S) -#define HP_APM_REGION2_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION2_R1_PMS_R_S 6 -/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION2_R2_PMS_X (BIT(8)) -#define HP_APM_REGION2_R2_PMS_X_M (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S) -#define HP_APM_REGION2_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION2_R2_PMS_X_S 8 -/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION2_R2_PMS_W (BIT(9)) -#define HP_APM_REGION2_R2_PMS_W_M (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S) -#define HP_APM_REGION2_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION2_R2_PMS_W_S 9 -/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION2_R2_PMS_R (BIT(10)) -#define HP_APM_REGION2_R2_PMS_R_M (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S) -#define HP_APM_REGION2_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION2_R2_PMS_R_S 10 - -/** HP_APM_REGION3_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) -/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region3 - */ -#define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) -#define HP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION3_ADDR_START_S 0 - -/** HP_APM_REGION3_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) -/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region3 - */ -#define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) -#define HP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION3_ADDR_END_S 0 - -/** HP_APM_REGION3_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) -/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION3_R0_PMS_X (BIT(0)) -#define HP_APM_REGION3_R0_PMS_X_M (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S) -#define HP_APM_REGION3_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION3_R0_PMS_X_S 0 -/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION3_R0_PMS_W (BIT(1)) -#define HP_APM_REGION3_R0_PMS_W_M (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S) -#define HP_APM_REGION3_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION3_R0_PMS_W_S 1 -/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION3_R0_PMS_R (BIT(2)) -#define HP_APM_REGION3_R0_PMS_R_M (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S) -#define HP_APM_REGION3_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION3_R0_PMS_R_S 2 -/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION3_R1_PMS_X (BIT(4)) -#define HP_APM_REGION3_R1_PMS_X_M (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S) -#define HP_APM_REGION3_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION3_R1_PMS_X_S 4 -/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION3_R1_PMS_W (BIT(5)) -#define HP_APM_REGION3_R1_PMS_W_M (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S) -#define HP_APM_REGION3_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION3_R1_PMS_W_S 5 -/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION3_R1_PMS_R (BIT(6)) -#define HP_APM_REGION3_R1_PMS_R_M (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S) -#define HP_APM_REGION3_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION3_R1_PMS_R_S 6 -/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION3_R2_PMS_X (BIT(8)) -#define HP_APM_REGION3_R2_PMS_X_M (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S) -#define HP_APM_REGION3_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION3_R2_PMS_X_S 8 -/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION3_R2_PMS_W (BIT(9)) -#define HP_APM_REGION3_R2_PMS_W_M (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S) -#define HP_APM_REGION3_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION3_R2_PMS_W_S 9 -/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION3_R2_PMS_R (BIT(10)) -#define HP_APM_REGION3_R2_PMS_R_M (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S) -#define HP_APM_REGION3_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION3_R2_PMS_R_S 10 - -/** HP_APM_REGION4_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) -/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region4 - */ -#define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) -#define HP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION4_ADDR_START_S 0 - -/** HP_APM_REGION4_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) -/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region4 - */ -#define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) -#define HP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION4_ADDR_END_S 0 - -/** HP_APM_REGION4_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) -/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION4_R0_PMS_X (BIT(0)) -#define HP_APM_REGION4_R0_PMS_X_M (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S) -#define HP_APM_REGION4_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION4_R0_PMS_X_S 0 -/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION4_R0_PMS_W (BIT(1)) -#define HP_APM_REGION4_R0_PMS_W_M (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S) -#define HP_APM_REGION4_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION4_R0_PMS_W_S 1 -/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION4_R0_PMS_R (BIT(2)) -#define HP_APM_REGION4_R0_PMS_R_M (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S) -#define HP_APM_REGION4_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION4_R0_PMS_R_S 2 -/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION4_R1_PMS_X (BIT(4)) -#define HP_APM_REGION4_R1_PMS_X_M (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S) -#define HP_APM_REGION4_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION4_R1_PMS_X_S 4 -/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION4_R1_PMS_W (BIT(5)) -#define HP_APM_REGION4_R1_PMS_W_M (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S) -#define HP_APM_REGION4_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION4_R1_PMS_W_S 5 -/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION4_R1_PMS_R (BIT(6)) -#define HP_APM_REGION4_R1_PMS_R_M (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S) -#define HP_APM_REGION4_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION4_R1_PMS_R_S 6 -/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION4_R2_PMS_X (BIT(8)) -#define HP_APM_REGION4_R2_PMS_X_M (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S) -#define HP_APM_REGION4_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION4_R2_PMS_X_S 8 -/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION4_R2_PMS_W (BIT(9)) -#define HP_APM_REGION4_R2_PMS_W_M (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S) -#define HP_APM_REGION4_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION4_R2_PMS_W_S 9 -/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION4_R2_PMS_R (BIT(10)) -#define HP_APM_REGION4_R2_PMS_R_M (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S) -#define HP_APM_REGION4_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION4_R2_PMS_R_S 10 - -/** HP_APM_REGION5_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) -/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region5 - */ -#define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) -#define HP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION5_ADDR_START_S 0 - -/** HP_APM_REGION5_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) -/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region5 - */ -#define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) -#define HP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION5_ADDR_END_S 0 - -/** HP_APM_REGION5_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) -/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION5_R0_PMS_X (BIT(0)) -#define HP_APM_REGION5_R0_PMS_X_M (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S) -#define HP_APM_REGION5_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION5_R0_PMS_X_S 0 -/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION5_R0_PMS_W (BIT(1)) -#define HP_APM_REGION5_R0_PMS_W_M (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S) -#define HP_APM_REGION5_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION5_R0_PMS_W_S 1 -/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION5_R0_PMS_R (BIT(2)) -#define HP_APM_REGION5_R0_PMS_R_M (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S) -#define HP_APM_REGION5_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION5_R0_PMS_R_S 2 -/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION5_R1_PMS_X (BIT(4)) -#define HP_APM_REGION5_R1_PMS_X_M (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S) -#define HP_APM_REGION5_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION5_R1_PMS_X_S 4 -/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION5_R1_PMS_W (BIT(5)) -#define HP_APM_REGION5_R1_PMS_W_M (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S) -#define HP_APM_REGION5_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION5_R1_PMS_W_S 5 -/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION5_R1_PMS_R (BIT(6)) -#define HP_APM_REGION5_R1_PMS_R_M (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S) -#define HP_APM_REGION5_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION5_R1_PMS_R_S 6 -/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION5_R2_PMS_X (BIT(8)) -#define HP_APM_REGION5_R2_PMS_X_M (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S) -#define HP_APM_REGION5_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION5_R2_PMS_X_S 8 -/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION5_R2_PMS_W (BIT(9)) -#define HP_APM_REGION5_R2_PMS_W_M (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S) -#define HP_APM_REGION5_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION5_R2_PMS_W_S 9 -/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION5_R2_PMS_R (BIT(10)) -#define HP_APM_REGION5_R2_PMS_R_M (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S) -#define HP_APM_REGION5_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION5_R2_PMS_R_S 10 - -/** HP_APM_REGION6_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) -/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region6 - */ -#define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) -#define HP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION6_ADDR_START_S 0 - -/** HP_APM_REGION6_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) -/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region6 - */ -#define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) -#define HP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION6_ADDR_END_S 0 - -/** HP_APM_REGION6_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) -/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION6_R0_PMS_X (BIT(0)) -#define HP_APM_REGION6_R0_PMS_X_M (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S) -#define HP_APM_REGION6_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION6_R0_PMS_X_S 0 -/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION6_R0_PMS_W (BIT(1)) -#define HP_APM_REGION6_R0_PMS_W_M (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S) -#define HP_APM_REGION6_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION6_R0_PMS_W_S 1 -/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION6_R0_PMS_R (BIT(2)) -#define HP_APM_REGION6_R0_PMS_R_M (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S) -#define HP_APM_REGION6_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION6_R0_PMS_R_S 2 -/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION6_R1_PMS_X (BIT(4)) -#define HP_APM_REGION6_R1_PMS_X_M (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S) -#define HP_APM_REGION6_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION6_R1_PMS_X_S 4 -/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION6_R1_PMS_W (BIT(5)) -#define HP_APM_REGION6_R1_PMS_W_M (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S) -#define HP_APM_REGION6_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION6_R1_PMS_W_S 5 -/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION6_R1_PMS_R (BIT(6)) -#define HP_APM_REGION6_R1_PMS_R_M (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S) -#define HP_APM_REGION6_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION6_R1_PMS_R_S 6 -/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION6_R2_PMS_X (BIT(8)) -#define HP_APM_REGION6_R2_PMS_X_M (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S) -#define HP_APM_REGION6_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION6_R2_PMS_X_S 8 -/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION6_R2_PMS_W (BIT(9)) -#define HP_APM_REGION6_R2_PMS_W_M (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S) -#define HP_APM_REGION6_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION6_R2_PMS_W_S 9 -/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION6_R2_PMS_R (BIT(10)) -#define HP_APM_REGION6_R2_PMS_R_M (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S) -#define HP_APM_REGION6_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION6_R2_PMS_R_S 10 - -/** HP_APM_REGION7_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) -/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region7 - */ -#define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) -#define HP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION7_ADDR_START_S 0 - -/** HP_APM_REGION7_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) -/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region7 - */ -#define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) -#define HP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION7_ADDR_END_S 0 - -/** HP_APM_REGION7_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) -/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION7_R0_PMS_X (BIT(0)) -#define HP_APM_REGION7_R0_PMS_X_M (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S) -#define HP_APM_REGION7_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION7_R0_PMS_X_S 0 -/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION7_R0_PMS_W (BIT(1)) -#define HP_APM_REGION7_R0_PMS_W_M (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S) -#define HP_APM_REGION7_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION7_R0_PMS_W_S 1 -/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION7_R0_PMS_R (BIT(2)) -#define HP_APM_REGION7_R0_PMS_R_M (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S) -#define HP_APM_REGION7_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION7_R0_PMS_R_S 2 -/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION7_R1_PMS_X (BIT(4)) -#define HP_APM_REGION7_R1_PMS_X_M (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S) -#define HP_APM_REGION7_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION7_R1_PMS_X_S 4 -/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION7_R1_PMS_W (BIT(5)) -#define HP_APM_REGION7_R1_PMS_W_M (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S) -#define HP_APM_REGION7_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION7_R1_PMS_W_S 5 -/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION7_R1_PMS_R (BIT(6)) -#define HP_APM_REGION7_R1_PMS_R_M (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S) -#define HP_APM_REGION7_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION7_R1_PMS_R_S 6 -/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION7_R2_PMS_X (BIT(8)) -#define HP_APM_REGION7_R2_PMS_X_M (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S) -#define HP_APM_REGION7_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION7_R2_PMS_X_S 8 -/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION7_R2_PMS_W (BIT(9)) -#define HP_APM_REGION7_R2_PMS_W_M (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S) -#define HP_APM_REGION7_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION7_R2_PMS_W_S 9 -/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION7_R2_PMS_R (BIT(10)) -#define HP_APM_REGION7_R2_PMS_R_M (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S) -#define HP_APM_REGION7_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION7_R2_PMS_R_S 10 - -/** HP_APM_REGION8_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) -/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region8 - */ -#define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) -#define HP_APM_REGION8_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION8_ADDR_START_S 0 - -/** HP_APM_REGION8_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) -/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region8 - */ -#define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) -#define HP_APM_REGION8_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION8_ADDR_END_S 0 - -/** HP_APM_REGION8_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) -/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION8_R0_PMS_X (BIT(0)) -#define HP_APM_REGION8_R0_PMS_X_M (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S) -#define HP_APM_REGION8_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION8_R0_PMS_X_S 0 -/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION8_R0_PMS_W (BIT(1)) -#define HP_APM_REGION8_R0_PMS_W_M (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S) -#define HP_APM_REGION8_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION8_R0_PMS_W_S 1 -/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION8_R0_PMS_R (BIT(2)) -#define HP_APM_REGION8_R0_PMS_R_M (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S) -#define HP_APM_REGION8_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION8_R0_PMS_R_S 2 -/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION8_R1_PMS_X (BIT(4)) -#define HP_APM_REGION8_R1_PMS_X_M (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S) -#define HP_APM_REGION8_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION8_R1_PMS_X_S 4 -/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION8_R1_PMS_W (BIT(5)) -#define HP_APM_REGION8_R1_PMS_W_M (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S) -#define HP_APM_REGION8_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION8_R1_PMS_W_S 5 -/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION8_R1_PMS_R (BIT(6)) -#define HP_APM_REGION8_R1_PMS_R_M (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S) -#define HP_APM_REGION8_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION8_R1_PMS_R_S 6 -/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION8_R2_PMS_X (BIT(8)) -#define HP_APM_REGION8_R2_PMS_X_M (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S) -#define HP_APM_REGION8_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION8_R2_PMS_X_S 8 -/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION8_R2_PMS_W (BIT(9)) -#define HP_APM_REGION8_R2_PMS_W_M (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S) -#define HP_APM_REGION8_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION8_R2_PMS_W_S 9 -/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION8_R2_PMS_R (BIT(10)) -#define HP_APM_REGION8_R2_PMS_R_M (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S) -#define HP_APM_REGION8_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION8_R2_PMS_R_S 10 - -/** HP_APM_REGION9_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) -/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region9 - */ -#define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) -#define HP_APM_REGION9_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION9_ADDR_START_S 0 - -/** HP_APM_REGION9_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) -/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region9 - */ -#define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) -#define HP_APM_REGION9_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION9_ADDR_END_S 0 - -/** HP_APM_REGION9_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) -/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION9_R0_PMS_X (BIT(0)) -#define HP_APM_REGION9_R0_PMS_X_M (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S) -#define HP_APM_REGION9_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION9_R0_PMS_X_S 0 -/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION9_R0_PMS_W (BIT(1)) -#define HP_APM_REGION9_R0_PMS_W_M (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S) -#define HP_APM_REGION9_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION9_R0_PMS_W_S 1 -/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION9_R0_PMS_R (BIT(2)) -#define HP_APM_REGION9_R0_PMS_R_M (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S) -#define HP_APM_REGION9_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION9_R0_PMS_R_S 2 -/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION9_R1_PMS_X (BIT(4)) -#define HP_APM_REGION9_R1_PMS_X_M (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S) -#define HP_APM_REGION9_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION9_R1_PMS_X_S 4 -/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION9_R1_PMS_W (BIT(5)) -#define HP_APM_REGION9_R1_PMS_W_M (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S) -#define HP_APM_REGION9_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION9_R1_PMS_W_S 5 -/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION9_R1_PMS_R (BIT(6)) -#define HP_APM_REGION9_R1_PMS_R_M (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S) -#define HP_APM_REGION9_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION9_R1_PMS_R_S 6 -/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION9_R2_PMS_X (BIT(8)) -#define HP_APM_REGION9_R2_PMS_X_M (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S) -#define HP_APM_REGION9_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION9_R2_PMS_X_S 8 -/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION9_R2_PMS_W (BIT(9)) -#define HP_APM_REGION9_R2_PMS_W_M (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S) -#define HP_APM_REGION9_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION9_R2_PMS_W_S 9 -/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION9_R2_PMS_R (BIT(10)) -#define HP_APM_REGION9_R2_PMS_R_M (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S) -#define HP_APM_REGION9_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION9_R2_PMS_R_S 10 - -/** HP_APM_REGION10_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) -/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region10 - */ -#define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) -#define HP_APM_REGION10_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION10_ADDR_START_S 0 - -/** HP_APM_REGION10_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) -/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region10 - */ -#define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) -#define HP_APM_REGION10_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION10_ADDR_END_S 0 - -/** HP_APM_REGION10_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) -/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION10_R0_PMS_X (BIT(0)) -#define HP_APM_REGION10_R0_PMS_X_M (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S) -#define HP_APM_REGION10_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION10_R0_PMS_X_S 0 -/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION10_R0_PMS_W (BIT(1)) -#define HP_APM_REGION10_R0_PMS_W_M (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S) -#define HP_APM_REGION10_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION10_R0_PMS_W_S 1 -/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION10_R0_PMS_R (BIT(2)) -#define HP_APM_REGION10_R0_PMS_R_M (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S) -#define HP_APM_REGION10_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION10_R0_PMS_R_S 2 -/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION10_R1_PMS_X (BIT(4)) -#define HP_APM_REGION10_R1_PMS_X_M (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S) -#define HP_APM_REGION10_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION10_R1_PMS_X_S 4 -/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION10_R1_PMS_W (BIT(5)) -#define HP_APM_REGION10_R1_PMS_W_M (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S) -#define HP_APM_REGION10_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION10_R1_PMS_W_S 5 -/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION10_R1_PMS_R (BIT(6)) -#define HP_APM_REGION10_R1_PMS_R_M (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S) -#define HP_APM_REGION10_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION10_R1_PMS_R_S 6 -/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION10_R2_PMS_X (BIT(8)) -#define HP_APM_REGION10_R2_PMS_X_M (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S) -#define HP_APM_REGION10_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION10_R2_PMS_X_S 8 -/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION10_R2_PMS_W (BIT(9)) -#define HP_APM_REGION10_R2_PMS_W_M (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S) -#define HP_APM_REGION10_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION10_R2_PMS_W_S 9 -/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION10_R2_PMS_R (BIT(10)) -#define HP_APM_REGION10_R2_PMS_R_M (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S) -#define HP_APM_REGION10_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION10_R2_PMS_R_S 10 - -/** HP_APM_REGION11_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) -/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region11 - */ -#define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) -#define HP_APM_REGION11_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION11_ADDR_START_S 0 - -/** HP_APM_REGION11_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) -/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region11 - */ -#define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) -#define HP_APM_REGION11_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION11_ADDR_END_S 0 - -/** HP_APM_REGION11_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) -/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION11_R0_PMS_X (BIT(0)) -#define HP_APM_REGION11_R0_PMS_X_M (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S) -#define HP_APM_REGION11_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION11_R0_PMS_X_S 0 -/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION11_R0_PMS_W (BIT(1)) -#define HP_APM_REGION11_R0_PMS_W_M (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S) -#define HP_APM_REGION11_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION11_R0_PMS_W_S 1 -/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION11_R0_PMS_R (BIT(2)) -#define HP_APM_REGION11_R0_PMS_R_M (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S) -#define HP_APM_REGION11_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION11_R0_PMS_R_S 2 -/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION11_R1_PMS_X (BIT(4)) -#define HP_APM_REGION11_R1_PMS_X_M (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S) -#define HP_APM_REGION11_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION11_R1_PMS_X_S 4 -/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION11_R1_PMS_W (BIT(5)) -#define HP_APM_REGION11_R1_PMS_W_M (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S) -#define HP_APM_REGION11_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION11_R1_PMS_W_S 5 -/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION11_R1_PMS_R (BIT(6)) -#define HP_APM_REGION11_R1_PMS_R_M (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S) -#define HP_APM_REGION11_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION11_R1_PMS_R_S 6 -/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION11_R2_PMS_X (BIT(8)) -#define HP_APM_REGION11_R2_PMS_X_M (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S) -#define HP_APM_REGION11_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION11_R2_PMS_X_S 8 -/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION11_R2_PMS_W (BIT(9)) -#define HP_APM_REGION11_R2_PMS_W_M (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S) -#define HP_APM_REGION11_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION11_R2_PMS_W_S 9 -/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION11_R2_PMS_R (BIT(10)) -#define HP_APM_REGION11_R2_PMS_R_M (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S) -#define HP_APM_REGION11_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION11_R2_PMS_R_S 10 - -/** HP_APM_REGION12_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) -/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region12 - */ -#define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) -#define HP_APM_REGION12_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION12_ADDR_START_S 0 - -/** HP_APM_REGION12_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) -/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region12 - */ -#define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) -#define HP_APM_REGION12_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION12_ADDR_END_S 0 - -/** HP_APM_REGION12_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) -/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION12_R0_PMS_X (BIT(0)) -#define HP_APM_REGION12_R0_PMS_X_M (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S) -#define HP_APM_REGION12_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION12_R0_PMS_X_S 0 -/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION12_R0_PMS_W (BIT(1)) -#define HP_APM_REGION12_R0_PMS_W_M (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S) -#define HP_APM_REGION12_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION12_R0_PMS_W_S 1 -/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION12_R0_PMS_R (BIT(2)) -#define HP_APM_REGION12_R0_PMS_R_M (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S) -#define HP_APM_REGION12_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION12_R0_PMS_R_S 2 -/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION12_R1_PMS_X (BIT(4)) -#define HP_APM_REGION12_R1_PMS_X_M (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S) -#define HP_APM_REGION12_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION12_R1_PMS_X_S 4 -/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION12_R1_PMS_W (BIT(5)) -#define HP_APM_REGION12_R1_PMS_W_M (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S) -#define HP_APM_REGION12_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION12_R1_PMS_W_S 5 -/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION12_R1_PMS_R (BIT(6)) -#define HP_APM_REGION12_R1_PMS_R_M (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S) -#define HP_APM_REGION12_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION12_R1_PMS_R_S 6 -/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION12_R2_PMS_X (BIT(8)) -#define HP_APM_REGION12_R2_PMS_X_M (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S) -#define HP_APM_REGION12_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION12_R2_PMS_X_S 8 -/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION12_R2_PMS_W (BIT(9)) -#define HP_APM_REGION12_R2_PMS_W_M (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S) -#define HP_APM_REGION12_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION12_R2_PMS_W_S 9 -/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION12_R2_PMS_R (BIT(10)) -#define HP_APM_REGION12_R2_PMS_R_M (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S) -#define HP_APM_REGION12_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION12_R2_PMS_R_S 10 - -/** HP_APM_REGION13_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) -/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region13 - */ -#define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) -#define HP_APM_REGION13_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION13_ADDR_START_S 0 - -/** HP_APM_REGION13_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) -/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region13 - */ -#define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) -#define HP_APM_REGION13_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION13_ADDR_END_S 0 - -/** HP_APM_REGION13_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) -/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION13_R0_PMS_X (BIT(0)) -#define HP_APM_REGION13_R0_PMS_X_M (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S) -#define HP_APM_REGION13_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION13_R0_PMS_X_S 0 -/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION13_R0_PMS_W (BIT(1)) -#define HP_APM_REGION13_R0_PMS_W_M (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S) -#define HP_APM_REGION13_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION13_R0_PMS_W_S 1 -/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION13_R0_PMS_R (BIT(2)) -#define HP_APM_REGION13_R0_PMS_R_M (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S) -#define HP_APM_REGION13_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION13_R0_PMS_R_S 2 -/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION13_R1_PMS_X (BIT(4)) -#define HP_APM_REGION13_R1_PMS_X_M (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S) -#define HP_APM_REGION13_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION13_R1_PMS_X_S 4 -/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION13_R1_PMS_W (BIT(5)) -#define HP_APM_REGION13_R1_PMS_W_M (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S) -#define HP_APM_REGION13_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION13_R1_PMS_W_S 5 -/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION13_R1_PMS_R (BIT(6)) -#define HP_APM_REGION13_R1_PMS_R_M (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S) -#define HP_APM_REGION13_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION13_R1_PMS_R_S 6 -/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION13_R2_PMS_X (BIT(8)) -#define HP_APM_REGION13_R2_PMS_X_M (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S) -#define HP_APM_REGION13_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION13_R2_PMS_X_S 8 -/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION13_R2_PMS_W (BIT(9)) -#define HP_APM_REGION13_R2_PMS_W_M (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S) -#define HP_APM_REGION13_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION13_R2_PMS_W_S 9 -/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION13_R2_PMS_R (BIT(10)) -#define HP_APM_REGION13_R2_PMS_R_M (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S) -#define HP_APM_REGION13_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION13_R2_PMS_R_S 10 - -/** HP_APM_REGION14_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) -/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region14 - */ -#define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) -#define HP_APM_REGION14_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION14_ADDR_START_S 0 - -/** HP_APM_REGION14_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) -/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region14 - */ -#define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) -#define HP_APM_REGION14_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION14_ADDR_END_S 0 - -/** HP_APM_REGION14_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) -/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION14_R0_PMS_X (BIT(0)) -#define HP_APM_REGION14_R0_PMS_X_M (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S) -#define HP_APM_REGION14_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION14_R0_PMS_X_S 0 -/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION14_R0_PMS_W (BIT(1)) -#define HP_APM_REGION14_R0_PMS_W_M (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S) -#define HP_APM_REGION14_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION14_R0_PMS_W_S 1 -/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION14_R0_PMS_R (BIT(2)) -#define HP_APM_REGION14_R0_PMS_R_M (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S) -#define HP_APM_REGION14_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION14_R0_PMS_R_S 2 -/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION14_R1_PMS_X (BIT(4)) -#define HP_APM_REGION14_R1_PMS_X_M (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S) -#define HP_APM_REGION14_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION14_R1_PMS_X_S 4 -/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION14_R1_PMS_W (BIT(5)) -#define HP_APM_REGION14_R1_PMS_W_M (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S) -#define HP_APM_REGION14_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION14_R1_PMS_W_S 5 -/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION14_R1_PMS_R (BIT(6)) -#define HP_APM_REGION14_R1_PMS_R_M (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S) -#define HP_APM_REGION14_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION14_R1_PMS_R_S 6 -/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION14_R2_PMS_X (BIT(8)) -#define HP_APM_REGION14_R2_PMS_X_M (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S) -#define HP_APM_REGION14_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION14_R2_PMS_X_S 8 -/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION14_R2_PMS_W (BIT(9)) -#define HP_APM_REGION14_R2_PMS_W_M (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S) -#define HP_APM_REGION14_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION14_R2_PMS_W_S 9 -/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION14_R2_PMS_R (BIT(10)) -#define HP_APM_REGION14_R2_PMS_R_M (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S) -#define HP_APM_REGION14_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION14_R2_PMS_R_S 10 - -/** HP_APM_REGION15_ADDR_START_REG register - * Region address register - */ -#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) -/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region15 - */ -#define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU -#define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) -#define HP_APM_REGION15_ADDR_START_V 0xFFFFFFFFU -#define HP_APM_REGION15_ADDR_START_S 0 - -/** HP_APM_REGION15_ADDR_END_REG register - * Region address register - */ -#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) -/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region15 - */ -#define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU -#define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) -#define HP_APM_REGION15_ADDR_END_V 0xFFFFFFFFU -#define HP_APM_REGION15_ADDR_END_S 0 - -/** HP_APM_REGION15_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) -/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define HP_APM_REGION15_R0_PMS_X (BIT(0)) -#define HP_APM_REGION15_R0_PMS_X_M (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S) -#define HP_APM_REGION15_R0_PMS_X_V 0x00000001U -#define HP_APM_REGION15_R0_PMS_X_S 0 -/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define HP_APM_REGION15_R0_PMS_W (BIT(1)) -#define HP_APM_REGION15_R0_PMS_W_M (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S) -#define HP_APM_REGION15_R0_PMS_W_V 0x00000001U -#define HP_APM_REGION15_R0_PMS_W_S 1 -/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define HP_APM_REGION15_R0_PMS_R (BIT(2)) -#define HP_APM_REGION15_R0_PMS_R_M (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S) -#define HP_APM_REGION15_R0_PMS_R_V 0x00000001U -#define HP_APM_REGION15_R0_PMS_R_S 2 -/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define HP_APM_REGION15_R1_PMS_X (BIT(4)) -#define HP_APM_REGION15_R1_PMS_X_M (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S) -#define HP_APM_REGION15_R1_PMS_X_V 0x00000001U -#define HP_APM_REGION15_R1_PMS_X_S 4 -/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define HP_APM_REGION15_R1_PMS_W (BIT(5)) -#define HP_APM_REGION15_R1_PMS_W_M (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S) -#define HP_APM_REGION15_R1_PMS_W_V 0x00000001U -#define HP_APM_REGION15_R1_PMS_W_S 5 -/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define HP_APM_REGION15_R1_PMS_R (BIT(6)) -#define HP_APM_REGION15_R1_PMS_R_M (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S) -#define HP_APM_REGION15_R1_PMS_R_V 0x00000001U -#define HP_APM_REGION15_R1_PMS_R_S 6 -/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define HP_APM_REGION15_R2_PMS_X (BIT(8)) -#define HP_APM_REGION15_R2_PMS_X_M (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S) -#define HP_APM_REGION15_R2_PMS_X_V 0x00000001U -#define HP_APM_REGION15_R2_PMS_X_S 8 -/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define HP_APM_REGION15_R2_PMS_W (BIT(9)) -#define HP_APM_REGION15_R2_PMS_W_M (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S) -#define HP_APM_REGION15_R2_PMS_W_V 0x00000001U -#define HP_APM_REGION15_R2_PMS_W_S 9 -/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define HP_APM_REGION15_R2_PMS_R (BIT(10)) -#define HP_APM_REGION15_R2_PMS_R_M (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S) -#define HP_APM_REGION15_R2_PMS_R_V 0x00000001U -#define HP_APM_REGION15_R2_PMS_R_S 10 - -/** HP_APM_FUNC_CTRL_REG register - * PMS function control register - */ -#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) -/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable - */ -#define HP_APM_M0_PMS_FUNC_EN (BIT(0)) -#define HP_APM_M0_PMS_FUNC_EN_M (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S) -#define HP_APM_M0_PMS_FUNC_EN_V 0x00000001U -#define HP_APM_M0_PMS_FUNC_EN_S 0 -/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable - */ -#define HP_APM_M1_PMS_FUNC_EN (BIT(1)) -#define HP_APM_M1_PMS_FUNC_EN_M (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S) -#define HP_APM_M1_PMS_FUNC_EN_V 0x00000001U -#define HP_APM_M1_PMS_FUNC_EN_S 1 -/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable - */ -#define HP_APM_M2_PMS_FUNC_EN (BIT(2)) -#define HP_APM_M2_PMS_FUNC_EN_M (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S) -#define HP_APM_M2_PMS_FUNC_EN_V 0x00000001U -#define HP_APM_M2_PMS_FUNC_EN_S 2 -/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable - */ -#define HP_APM_M3_PMS_FUNC_EN (BIT(3)) -#define HP_APM_M3_PMS_FUNC_EN_M (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S) -#define HP_APM_M3_PMS_FUNC_EN_V 0x00000001U -#define HP_APM_M3_PMS_FUNC_EN_S 3 - -/** HP_APM_M0_STATUS_REG register - * M0 status register - */ -#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) -/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Exception status - */ -#define HP_APM_M0_EXCEPTION_STATUS 0x00000003U -#define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) -#define HP_APM_M0_EXCEPTION_STATUS_V 0x00000003U -#define HP_APM_M0_EXCEPTION_STATUS_S 0 - -/** HP_APM_M0_STATUS_CLR_REG register - * M0 status clear register - */ -#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) -/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Clear exception status - */ -#define HP_APM_M0_REGION_STATUS_CLR (BIT(0)) -#define HP_APM_M0_REGION_STATUS_CLR_M (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S) -#define HP_APM_M0_REGION_STATUS_CLR_V 0x00000001U -#define HP_APM_M0_REGION_STATUS_CLR_S 0 - -/** HP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register - */ -#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) -/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Exception region - */ -#define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU -#define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) -#define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU -#define HP_APM_M0_EXCEPTION_REGION_S 0 -/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ -#define HP_APM_M0_EXCEPTION_MODE 0x00000003U -#define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) -#define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U -#define HP_APM_M0_EXCEPTION_MODE_S 16 -/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ -#define HP_APM_M0_EXCEPTION_ID 0x0000001FU -#define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) -#define HP_APM_M0_EXCEPTION_ID_V 0x0000001FU -#define HP_APM_M0_EXCEPTION_ID_S 18 - -/** HP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register - */ -#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) -/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ -#define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU -#define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) -#define HP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU -#define HP_APM_M0_EXCEPTION_ADDR_S 0 - -/** HP_APM_M1_STATUS_REG register - * M1 status register - */ -#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) -/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Exception status - */ -#define HP_APM_M1_EXCEPTION_STATUS 0x00000003U -#define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) -#define HP_APM_M1_EXCEPTION_STATUS_V 0x00000003U -#define HP_APM_M1_EXCEPTION_STATUS_S 0 - -/** HP_APM_M1_STATUS_CLR_REG register - * M1 status clear register - */ -#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) -/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Clear exception status - */ -#define HP_APM_M1_REGION_STATUS_CLR (BIT(0)) -#define HP_APM_M1_REGION_STATUS_CLR_M (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S) -#define HP_APM_M1_REGION_STATUS_CLR_V 0x00000001U -#define HP_APM_M1_REGION_STATUS_CLR_S 0 - -/** HP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register - */ -#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) -/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Exception region - */ -#define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU -#define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) -#define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU -#define HP_APM_M1_EXCEPTION_REGION_S 0 -/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ -#define HP_APM_M1_EXCEPTION_MODE 0x00000003U -#define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) -#define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U -#define HP_APM_M1_EXCEPTION_MODE_S 16 -/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ -#define HP_APM_M1_EXCEPTION_ID 0x0000001FU -#define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) -#define HP_APM_M1_EXCEPTION_ID_V 0x0000001FU -#define HP_APM_M1_EXCEPTION_ID_S 18 - -/** HP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register - */ -#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) -/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ -#define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU -#define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) -#define HP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU -#define HP_APM_M1_EXCEPTION_ADDR_S 0 - -/** HP_APM_M2_STATUS_REG register - * M2 status register - */ -#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) -/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Exception status - */ -#define HP_APM_M2_EXCEPTION_STATUS 0x00000003U -#define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) -#define HP_APM_M2_EXCEPTION_STATUS_V 0x00000003U -#define HP_APM_M2_EXCEPTION_STATUS_S 0 - -/** HP_APM_M2_STATUS_CLR_REG register - * M2 status clear register - */ -#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) -/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Clear exception status - */ -#define HP_APM_M2_REGION_STATUS_CLR (BIT(0)) -#define HP_APM_M2_REGION_STATUS_CLR_M (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S) -#define HP_APM_M2_REGION_STATUS_CLR_V 0x00000001U -#define HP_APM_M2_REGION_STATUS_CLR_S 0 - -/** HP_APM_M2_EXCEPTION_INFO0_REG register - * M2 exception_info0 register - */ -#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) -/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Exception region - */ -#define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU -#define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) -#define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU -#define HP_APM_M2_EXCEPTION_REGION_S 0 -/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ -#define HP_APM_M2_EXCEPTION_MODE 0x00000003U -#define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) -#define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U -#define HP_APM_M2_EXCEPTION_MODE_S 16 -/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ -#define HP_APM_M2_EXCEPTION_ID 0x0000001FU -#define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) -#define HP_APM_M2_EXCEPTION_ID_V 0x0000001FU -#define HP_APM_M2_EXCEPTION_ID_S 18 - -/** HP_APM_M2_EXCEPTION_INFO1_REG register - * M2 exception_info1 register - */ -#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) -/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ -#define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU -#define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) -#define HP_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU -#define HP_APM_M2_EXCEPTION_ADDR_S 0 - -/** HP_APM_M3_STATUS_REG register - * M3 status register - */ -#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) -/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Exception status - */ -#define HP_APM_M3_EXCEPTION_STATUS 0x00000003U -#define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) -#define HP_APM_M3_EXCEPTION_STATUS_V 0x00000003U -#define HP_APM_M3_EXCEPTION_STATUS_S 0 - -/** HP_APM_M3_STATUS_CLR_REG register - * M3 status clear register - */ -#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) -/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Clear exception status - */ -#define HP_APM_M3_REGION_STATUS_CLR (BIT(0)) -#define HP_APM_M3_REGION_STATUS_CLR_M (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S) -#define HP_APM_M3_REGION_STATUS_CLR_V 0x00000001U -#define HP_APM_M3_REGION_STATUS_CLR_S 0 - -/** HP_APM_M3_EXCEPTION_INFO0_REG register - * M3 exception_info0 register - */ -#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) -/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Exception region - */ -#define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU -#define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) -#define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU -#define HP_APM_M3_EXCEPTION_REGION_S 0 -/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ -#define HP_APM_M3_EXCEPTION_MODE 0x00000003U -#define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) -#define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U -#define HP_APM_M3_EXCEPTION_MODE_S 16 -/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ -#define HP_APM_M3_EXCEPTION_ID 0x0000001FU -#define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) -#define HP_APM_M3_EXCEPTION_ID_V 0x0000001FU -#define HP_APM_M3_EXCEPTION_ID_S 18 - -/** HP_APM_M3_EXCEPTION_INFO1_REG register - * M3 exception_info1 register - */ -#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) -/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ -#define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU -#define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) -#define HP_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU -#define HP_APM_M3_EXCEPTION_ADDR_S 0 - -/** HP_APM_INT_EN_REG register - * APM interrupt enable register - */ -#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108) -/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * APM M0 interrupt enable - */ -#define HP_APM_M0_APM_INT_EN (BIT(0)) -#define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) -#define HP_APM_M0_APM_INT_EN_V 0x00000001U -#define HP_APM_M0_APM_INT_EN_S 0 -/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * APM M1 interrupt enable - */ -#define HP_APM_M1_APM_INT_EN (BIT(1)) -#define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) -#define HP_APM_M1_APM_INT_EN_V 0x00000001U -#define HP_APM_M1_APM_INT_EN_S 1 -/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; - * APM M2 interrupt enable - */ -#define HP_APM_M2_APM_INT_EN (BIT(2)) -#define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) -#define HP_APM_M2_APM_INT_EN_V 0x00000001U -#define HP_APM_M2_APM_INT_EN_S 2 -/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; - * APM M3 interrupt enable - */ -#define HP_APM_M3_APM_INT_EN (BIT(3)) -#define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) -#define HP_APM_M3_APM_INT_EN_V 0x00000001U -#define HP_APM_M3_APM_INT_EN_S 3 - -/** HP_APM_CLOCK_GATE_REG register - * clock gating register - */ -#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c) -/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ -#define HP_APM_CLK_EN (BIT(0)) -#define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) -#define HP_APM_CLK_EN_V 0x00000001U -#define HP_APM_CLK_EN_S 0 - -/** HP_APM_DATE_REG register - * Version register - */ -#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) -/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640; - * reg_date - */ -#define HP_APM_DATE 0x0FFFFFFFU -#define HP_APM_DATE_M (HP_APM_DATE_V << HP_APM_DATE_S) -#define HP_APM_DATE_V 0x0FFFFFFFU -#define HP_APM_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/hp_apm_struct.h b/components/soc/esp32p4/include/soc/hp_apm_struct.h deleted file mode 100644 index faec6b3372..0000000000 --- a/components/soc/esp32p4/include/soc/hp_apm_struct.h +++ /dev/null @@ -1,1670 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Region filter enable register */ -/** Type of region_filter_en register - * Region filter enable register - */ -typedef union { - struct { - /** region_filter_en : R/W; bitpos: [15:0]; default: 1; - * Region filter enable - */ - uint32_t region_filter_en:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} hp_apm_region_filter_en_reg_t; - - -/** Group: Region address register */ -/** Type of region0_addr_start register - * Region address register - */ -typedef union { - struct { - /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region0 - */ - uint32_t region0_addr_start:32; - }; - uint32_t val; -} hp_apm_region0_addr_start_reg_t; - -/** Type of region0_addr_end register - * Region address register - */ -typedef union { - struct { - /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region0 - */ - uint32_t region0_addr_end:32; - }; - uint32_t val; -} hp_apm_region0_addr_end_reg_t; - -/** Type of region1_addr_start register - * Region address register - */ -typedef union { - struct { - /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region1 - */ - uint32_t region1_addr_start:32; - }; - uint32_t val; -} hp_apm_region1_addr_start_reg_t; - -/** Type of region1_addr_end register - * Region address register - */ -typedef union { - struct { - /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region1 - */ - uint32_t region1_addr_end:32; - }; - uint32_t val; -} hp_apm_region1_addr_end_reg_t; - -/** Type of region2_addr_start register - * Region address register - */ -typedef union { - struct { - /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region2 - */ - uint32_t region2_addr_start:32; - }; - uint32_t val; -} hp_apm_region2_addr_start_reg_t; - -/** Type of region2_addr_end register - * Region address register - */ -typedef union { - struct { - /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region2 - */ - uint32_t region2_addr_end:32; - }; - uint32_t val; -} hp_apm_region2_addr_end_reg_t; - -/** Type of region3_addr_start register - * Region address register - */ -typedef union { - struct { - /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region3 - */ - uint32_t region3_addr_start:32; - }; - uint32_t val; -} hp_apm_region3_addr_start_reg_t; - -/** Type of region3_addr_end register - * Region address register - */ -typedef union { - struct { - /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region3 - */ - uint32_t region3_addr_end:32; - }; - uint32_t val; -} hp_apm_region3_addr_end_reg_t; - -/** Type of region4_addr_start register - * Region address register - */ -typedef union { - struct { - /** region4_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region4 - */ - uint32_t region4_addr_start:32; - }; - uint32_t val; -} hp_apm_region4_addr_start_reg_t; - -/** Type of region4_addr_end register - * Region address register - */ -typedef union { - struct { - /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region4 - */ - uint32_t region4_addr_end:32; - }; - uint32_t val; -} hp_apm_region4_addr_end_reg_t; - -/** Type of region5_addr_start register - * Region address register - */ -typedef union { - struct { - /** region5_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region5 - */ - uint32_t region5_addr_start:32; - }; - uint32_t val; -} hp_apm_region5_addr_start_reg_t; - -/** Type of region5_addr_end register - * Region address register - */ -typedef union { - struct { - /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region5 - */ - uint32_t region5_addr_end:32; - }; - uint32_t val; -} hp_apm_region5_addr_end_reg_t; - -/** Type of region6_addr_start register - * Region address register - */ -typedef union { - struct { - /** region6_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region6 - */ - uint32_t region6_addr_start:32; - }; - uint32_t val; -} hp_apm_region6_addr_start_reg_t; - -/** Type of region6_addr_end register - * Region address register - */ -typedef union { - struct { - /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region6 - */ - uint32_t region6_addr_end:32; - }; - uint32_t val; -} hp_apm_region6_addr_end_reg_t; - -/** Type of region7_addr_start register - * Region address register - */ -typedef union { - struct { - /** region7_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region7 - */ - uint32_t region7_addr_start:32; - }; - uint32_t val; -} hp_apm_region7_addr_start_reg_t; - -/** Type of region7_addr_end register - * Region address register - */ -typedef union { - struct { - /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region7 - */ - uint32_t region7_addr_end:32; - }; - uint32_t val; -} hp_apm_region7_addr_end_reg_t; - -/** Type of region8_addr_start register - * Region address register - */ -typedef union { - struct { - /** region8_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region8 - */ - uint32_t region8_addr_start:32; - }; - uint32_t val; -} hp_apm_region8_addr_start_reg_t; - -/** Type of region8_addr_end register - * Region address register - */ -typedef union { - struct { - /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region8 - */ - uint32_t region8_addr_end:32; - }; - uint32_t val; -} hp_apm_region8_addr_end_reg_t; - -/** Type of region9_addr_start register - * Region address register - */ -typedef union { - struct { - /** region9_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region9 - */ - uint32_t region9_addr_start:32; - }; - uint32_t val; -} hp_apm_region9_addr_start_reg_t; - -/** Type of region9_addr_end register - * Region address register - */ -typedef union { - struct { - /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region9 - */ - uint32_t region9_addr_end:32; - }; - uint32_t val; -} hp_apm_region9_addr_end_reg_t; - -/** Type of region10_addr_start register - * Region address register - */ -typedef union { - struct { - /** region10_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region10 - */ - uint32_t region10_addr_start:32; - }; - uint32_t val; -} hp_apm_region10_addr_start_reg_t; - -/** Type of region10_addr_end register - * Region address register - */ -typedef union { - struct { - /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region10 - */ - uint32_t region10_addr_end:32; - }; - uint32_t val; -} hp_apm_region10_addr_end_reg_t; - -/** Type of region11_addr_start register - * Region address register - */ -typedef union { - struct { - /** region11_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region11 - */ - uint32_t region11_addr_start:32; - }; - uint32_t val; -} hp_apm_region11_addr_start_reg_t; - -/** Type of region11_addr_end register - * Region address register - */ -typedef union { - struct { - /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region11 - */ - uint32_t region11_addr_end:32; - }; - uint32_t val; -} hp_apm_region11_addr_end_reg_t; - -/** Type of region12_addr_start register - * Region address register - */ -typedef union { - struct { - /** region12_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region12 - */ - uint32_t region12_addr_start:32; - }; - uint32_t val; -} hp_apm_region12_addr_start_reg_t; - -/** Type of region12_addr_end register - * Region address register - */ -typedef union { - struct { - /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region12 - */ - uint32_t region12_addr_end:32; - }; - uint32_t val; -} hp_apm_region12_addr_end_reg_t; - -/** Type of region13_addr_start register - * Region address register - */ -typedef union { - struct { - /** region13_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region13 - */ - uint32_t region13_addr_start:32; - }; - uint32_t val; -} hp_apm_region13_addr_start_reg_t; - -/** Type of region13_addr_end register - * Region address register - */ -typedef union { - struct { - /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region13 - */ - uint32_t region13_addr_end:32; - }; - uint32_t val; -} hp_apm_region13_addr_end_reg_t; - -/** Type of region14_addr_start register - * Region address register - */ -typedef union { - struct { - /** region14_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region14 - */ - uint32_t region14_addr_start:32; - }; - uint32_t val; -} hp_apm_region14_addr_start_reg_t; - -/** Type of region14_addr_end register - * Region address register - */ -typedef union { - struct { - /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region14 - */ - uint32_t region14_addr_end:32; - }; - uint32_t val; -} hp_apm_region14_addr_end_reg_t; - -/** Type of region15_addr_start register - * Region address register - */ -typedef union { - struct { - /** region15_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region15 - */ - uint32_t region15_addr_start:32; - }; - uint32_t val; -} hp_apm_region15_addr_start_reg_t; - -/** Type of region15_addr_end register - * Region address register - */ -typedef union { - struct { - /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region15 - */ - uint32_t region15_addr_end:32; - }; - uint32_t val; -} hp_apm_region15_addr_end_reg_t; - - -/** Group: Region access authority attribute register */ -/** Type of region0_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region0_r0_pms_x:1; - /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region0_r0_pms_w:1; - /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region0_r0_pms_r:1; - uint32_t reserved_3:1; - /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region0_r1_pms_x:1; - /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region0_r1_pms_w:1; - /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region0_r1_pms_r:1; - uint32_t reserved_7:1; - /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region0_r2_pms_x:1; - /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region0_r2_pms_w:1; - /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region0_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region0_pms_attr_reg_t; - -/** Type of region1_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region1_r0_pms_x:1; - /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region1_r0_pms_w:1; - /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region1_r0_pms_r:1; - uint32_t reserved_3:1; - /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region1_r1_pms_x:1; - /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region1_r1_pms_w:1; - /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region1_r1_pms_r:1; - uint32_t reserved_7:1; - /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region1_r2_pms_x:1; - /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region1_r2_pms_w:1; - /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region1_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region1_pms_attr_reg_t; - -/** Type of region2_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region2_r0_pms_x:1; - /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region2_r0_pms_w:1; - /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region2_r0_pms_r:1; - uint32_t reserved_3:1; - /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region2_r1_pms_x:1; - /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region2_r1_pms_w:1; - /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region2_r1_pms_r:1; - uint32_t reserved_7:1; - /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region2_r2_pms_x:1; - /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region2_r2_pms_w:1; - /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region2_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region2_pms_attr_reg_t; - -/** Type of region3_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region3_r0_pms_x:1; - /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region3_r0_pms_w:1; - /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region3_r0_pms_r:1; - uint32_t reserved_3:1; - /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region3_r1_pms_x:1; - /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region3_r1_pms_w:1; - /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region3_r1_pms_r:1; - uint32_t reserved_7:1; - /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region3_r2_pms_x:1; - /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region3_r2_pms_w:1; - /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region3_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region3_pms_attr_reg_t; - -/** Type of region4_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region4_r0_pms_x:1; - /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region4_r0_pms_w:1; - /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region4_r0_pms_r:1; - uint32_t reserved_3:1; - /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region4_r1_pms_x:1; - /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region4_r1_pms_w:1; - /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region4_r1_pms_r:1; - uint32_t reserved_7:1; - /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region4_r2_pms_x:1; - /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region4_r2_pms_w:1; - /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region4_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region4_pms_attr_reg_t; - -/** Type of region5_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region5_r0_pms_x:1; - /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region5_r0_pms_w:1; - /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region5_r0_pms_r:1; - uint32_t reserved_3:1; - /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region5_r1_pms_x:1; - /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region5_r1_pms_w:1; - /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region5_r1_pms_r:1; - uint32_t reserved_7:1; - /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region5_r2_pms_x:1; - /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region5_r2_pms_w:1; - /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region5_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region5_pms_attr_reg_t; - -/** Type of region6_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region6_r0_pms_x:1; - /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region6_r0_pms_w:1; - /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region6_r0_pms_r:1; - uint32_t reserved_3:1; - /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region6_r1_pms_x:1; - /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region6_r1_pms_w:1; - /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region6_r1_pms_r:1; - uint32_t reserved_7:1; - /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region6_r2_pms_x:1; - /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region6_r2_pms_w:1; - /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region6_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region6_pms_attr_reg_t; - -/** Type of region7_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region7_r0_pms_x:1; - /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region7_r0_pms_w:1; - /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region7_r0_pms_r:1; - uint32_t reserved_3:1; - /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region7_r1_pms_x:1; - /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region7_r1_pms_w:1; - /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region7_r1_pms_r:1; - uint32_t reserved_7:1; - /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region7_r2_pms_x:1; - /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region7_r2_pms_w:1; - /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region7_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region7_pms_attr_reg_t; - -/** Type of region8_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region8_r0_pms_x:1; - /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region8_r0_pms_w:1; - /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region8_r0_pms_r:1; - uint32_t reserved_3:1; - /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region8_r1_pms_x:1; - /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region8_r1_pms_w:1; - /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region8_r1_pms_r:1; - uint32_t reserved_7:1; - /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region8_r2_pms_x:1; - /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region8_r2_pms_w:1; - /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region8_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region8_pms_attr_reg_t; - -/** Type of region9_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region9_r0_pms_x:1; - /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region9_r0_pms_w:1; - /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region9_r0_pms_r:1; - uint32_t reserved_3:1; - /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region9_r1_pms_x:1; - /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region9_r1_pms_w:1; - /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region9_r1_pms_r:1; - uint32_t reserved_7:1; - /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region9_r2_pms_x:1; - /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region9_r2_pms_w:1; - /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region9_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region9_pms_attr_reg_t; - -/** Type of region10_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region10_r0_pms_x:1; - /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region10_r0_pms_w:1; - /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region10_r0_pms_r:1; - uint32_t reserved_3:1; - /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region10_r1_pms_x:1; - /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region10_r1_pms_w:1; - /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region10_r1_pms_r:1; - uint32_t reserved_7:1; - /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region10_r2_pms_x:1; - /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region10_r2_pms_w:1; - /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region10_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region10_pms_attr_reg_t; - -/** Type of region11_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region11_r0_pms_x:1; - /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region11_r0_pms_w:1; - /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region11_r0_pms_r:1; - uint32_t reserved_3:1; - /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region11_r1_pms_x:1; - /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region11_r1_pms_w:1; - /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region11_r1_pms_r:1; - uint32_t reserved_7:1; - /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region11_r2_pms_x:1; - /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region11_r2_pms_w:1; - /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region11_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region11_pms_attr_reg_t; - -/** Type of region12_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region12_r0_pms_x:1; - /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region12_r0_pms_w:1; - /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region12_r0_pms_r:1; - uint32_t reserved_3:1; - /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region12_r1_pms_x:1; - /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region12_r1_pms_w:1; - /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region12_r1_pms_r:1; - uint32_t reserved_7:1; - /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region12_r2_pms_x:1; - /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region12_r2_pms_w:1; - /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region12_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region12_pms_attr_reg_t; - -/** Type of region13_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region13_r0_pms_x:1; - /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region13_r0_pms_w:1; - /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region13_r0_pms_r:1; - uint32_t reserved_3:1; - /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region13_r1_pms_x:1; - /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region13_r1_pms_w:1; - /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region13_r1_pms_r:1; - uint32_t reserved_7:1; - /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region13_r2_pms_x:1; - /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region13_r2_pms_w:1; - /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region13_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region13_pms_attr_reg_t; - -/** Type of region14_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region14_r0_pms_x:1; - /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region14_r0_pms_w:1; - /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region14_r0_pms_r:1; - uint32_t reserved_3:1; - /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region14_r1_pms_x:1; - /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region14_r1_pms_w:1; - /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region14_r1_pms_r:1; - uint32_t reserved_7:1; - /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region14_r2_pms_x:1; - /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region14_r2_pms_w:1; - /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region14_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region14_pms_attr_reg_t; - -/** Type of region15_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region15_r0_pms_x:1; - /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region15_r0_pms_w:1; - /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region15_r0_pms_r:1; - uint32_t reserved_3:1; - /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region15_r1_pms_x:1; - /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region15_r1_pms_w:1; - /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region15_r1_pms_r:1; - uint32_t reserved_7:1; - /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region15_r2_pms_x:1; - /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region15_r2_pms_w:1; - /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region15_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} hp_apm_region15_pms_attr_reg_t; - - -/** Group: PMS function control register */ -/** Type of func_ctrl register - * PMS function control register - */ -typedef union { - struct { - /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable - */ - uint32_t m0_pms_func_en:1; - /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable - */ - uint32_t m1_pms_func_en:1; - /** m2_pms_func_en : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable - */ - uint32_t m2_pms_func_en:1; - /** m3_pms_func_en : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable - */ - uint32_t m3_pms_func_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} hp_apm_func_ctrl_reg_t; - - -/** Group: M0 status register */ -/** Type of m0_status register - * M0 status register - */ -typedef union { - struct { - /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Exception status - */ - uint32_t m0_exception_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} hp_apm_m0_status_reg_t; - - -/** Group: M0 status clear register */ -/** Type of m0_status_clr register - * M0 status clear register - */ -typedef union { - struct { - /** m0_region_status_clr : WT; bitpos: [0]; default: 0; - * Clear exception status - */ - uint32_t m0_region_status_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hp_apm_m0_status_clr_reg_t; - - -/** Group: M0 exception_info0 register */ -/** Type of m0_exception_info0 register - * M0 exception_info0 register - */ -typedef union { - struct { - /** m0_exception_region : RO; bitpos: [15:0]; default: 0; - * Exception region - */ - uint32_t m0_exception_region:16; - /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ - uint32_t m0_exception_mode:2; - /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ - uint32_t m0_exception_id:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} hp_apm_m0_exception_info0_reg_t; - - -/** Group: M0 exception_info1 register */ -/** Type of m0_exception_info1 register - * M0 exception_info1 register - */ -typedef union { - struct { - /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ - uint32_t m0_exception_addr:32; - }; - uint32_t val; -} hp_apm_m0_exception_info1_reg_t; - - -/** Group: M1 status register */ -/** Type of m1_status register - * M1 status register - */ -typedef union { - struct { - /** m1_exception_status : RO; bitpos: [1:0]; default: 0; - * Exception status - */ - uint32_t m1_exception_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} hp_apm_m1_status_reg_t; - - -/** Group: M1 status clear register */ -/** Type of m1_status_clr register - * M1 status clear register - */ -typedef union { - struct { - /** m1_region_status_clr : WT; bitpos: [0]; default: 0; - * Clear exception status - */ - uint32_t m1_region_status_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hp_apm_m1_status_clr_reg_t; - - -/** Group: M1 exception_info0 register */ -/** Type of m1_exception_info0 register - * M1 exception_info0 register - */ -typedef union { - struct { - /** m1_exception_region : RO; bitpos: [15:0]; default: 0; - * Exception region - */ - uint32_t m1_exception_region:16; - /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ - uint32_t m1_exception_mode:2; - /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ - uint32_t m1_exception_id:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} hp_apm_m1_exception_info0_reg_t; - - -/** Group: M1 exception_info1 register */ -/** Type of m1_exception_info1 register - * M1 exception_info1 register - */ -typedef union { - struct { - /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ - uint32_t m1_exception_addr:32; - }; - uint32_t val; -} hp_apm_m1_exception_info1_reg_t; - - -/** Group: M2 status register */ -/** Type of m2_status register - * M2 status register - */ -typedef union { - struct { - /** m2_exception_status : RO; bitpos: [1:0]; default: 0; - * Exception status - */ - uint32_t m2_exception_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} hp_apm_m2_status_reg_t; - - -/** Group: M2 status clear register */ -/** Type of m2_status_clr register - * M2 status clear register - */ -typedef union { - struct { - /** m2_region_status_clr : WT; bitpos: [0]; default: 0; - * Clear exception status - */ - uint32_t m2_region_status_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hp_apm_m2_status_clr_reg_t; - - -/** Group: M2 exception_info0 register */ -/** Type of m2_exception_info0 register - * M2 exception_info0 register - */ -typedef union { - struct { - /** m2_exception_region : RO; bitpos: [15:0]; default: 0; - * Exception region - */ - uint32_t m2_exception_region:16; - /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ - uint32_t m2_exception_mode:2; - /** m2_exception_id : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ - uint32_t m2_exception_id:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} hp_apm_m2_exception_info0_reg_t; - - -/** Group: M2 exception_info1 register */ -/** Type of m2_exception_info1 register - * M2 exception_info1 register - */ -typedef union { - struct { - /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ - uint32_t m2_exception_addr:32; - }; - uint32_t val; -} hp_apm_m2_exception_info1_reg_t; - - -/** Group: M3 status register */ -/** Type of m3_status register - * M3 status register - */ -typedef union { - struct { - /** m3_exception_status : RO; bitpos: [1:0]; default: 0; - * Exception status - */ - uint32_t m3_exception_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} hp_apm_m3_status_reg_t; - - -/** Group: M3 status clear register */ -/** Type of m3_status_clr register - * M3 status clear register - */ -typedef union { - struct { - /** m3_region_status_clr : WT; bitpos: [0]; default: 0; - * Clear exception status - */ - uint32_t m3_region_status_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hp_apm_m3_status_clr_reg_t; - - -/** Group: M3 exception_info0 register */ -/** Type of m3_exception_info0 register - * M3 exception_info0 register - */ -typedef union { - struct { - /** m3_exception_region : RO; bitpos: [15:0]; default: 0; - * Exception region - */ - uint32_t m3_exception_region:16; - /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ - uint32_t m3_exception_mode:2; - /** m3_exception_id : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ - uint32_t m3_exception_id:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} hp_apm_m3_exception_info0_reg_t; - - -/** Group: M3 exception_info1 register */ -/** Type of m3_exception_info1 register - * M3 exception_info1 register - */ -typedef union { - struct { - /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ - uint32_t m3_exception_addr:32; - }; - uint32_t val; -} hp_apm_m3_exception_info1_reg_t; - - -/** Group: APM interrupt enable register */ -/** Type of int_en register - * APM interrupt enable register - */ -typedef union { - struct { - /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * APM M0 interrupt enable - */ - uint32_t m0_apm_int_en:1; - /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * APM M1 interrupt enable - */ - uint32_t m1_apm_int_en:1; - /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; - * APM M2 interrupt enable - */ - uint32_t m2_apm_int_en:1; - /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; - * APM M3 interrupt enable - */ - uint32_t m3_apm_int_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} hp_apm_int_en_reg_t; - - -/** Group: clock gating register */ -/** Type of clock_gate register - * clock gating register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hp_apm_clock_gate_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35672640; - * reg_date - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} hp_apm_date_reg_t; - - -typedef struct hp_apm_dev_t { - volatile hp_apm_region_filter_en_reg_t region_filter_en; - volatile hp_apm_region0_addr_start_reg_t region0_addr_start; - volatile hp_apm_region0_addr_end_reg_t region0_addr_end; - volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr; - volatile hp_apm_region1_addr_start_reg_t region1_addr_start; - volatile hp_apm_region1_addr_end_reg_t region1_addr_end; - volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr; - volatile hp_apm_region2_addr_start_reg_t region2_addr_start; - volatile hp_apm_region2_addr_end_reg_t region2_addr_end; - volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr; - volatile hp_apm_region3_addr_start_reg_t region3_addr_start; - volatile hp_apm_region3_addr_end_reg_t region3_addr_end; - volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr; - volatile hp_apm_region4_addr_start_reg_t region4_addr_start; - volatile hp_apm_region4_addr_end_reg_t region4_addr_end; - volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr; - volatile hp_apm_region5_addr_start_reg_t region5_addr_start; - volatile hp_apm_region5_addr_end_reg_t region5_addr_end; - volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr; - volatile hp_apm_region6_addr_start_reg_t region6_addr_start; - volatile hp_apm_region6_addr_end_reg_t region6_addr_end; - volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr; - volatile hp_apm_region7_addr_start_reg_t region7_addr_start; - volatile hp_apm_region7_addr_end_reg_t region7_addr_end; - volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr; - volatile hp_apm_region8_addr_start_reg_t region8_addr_start; - volatile hp_apm_region8_addr_end_reg_t region8_addr_end; - volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr; - volatile hp_apm_region9_addr_start_reg_t region9_addr_start; - volatile hp_apm_region9_addr_end_reg_t region9_addr_end; - volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr; - volatile hp_apm_region10_addr_start_reg_t region10_addr_start; - volatile hp_apm_region10_addr_end_reg_t region10_addr_end; - volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr; - volatile hp_apm_region11_addr_start_reg_t region11_addr_start; - volatile hp_apm_region11_addr_end_reg_t region11_addr_end; - volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr; - volatile hp_apm_region12_addr_start_reg_t region12_addr_start; - volatile hp_apm_region12_addr_end_reg_t region12_addr_end; - volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr; - volatile hp_apm_region13_addr_start_reg_t region13_addr_start; - volatile hp_apm_region13_addr_end_reg_t region13_addr_end; - volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr; - volatile hp_apm_region14_addr_start_reg_t region14_addr_start; - volatile hp_apm_region14_addr_end_reg_t region14_addr_end; - volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr; - volatile hp_apm_region15_addr_start_reg_t region15_addr_start; - volatile hp_apm_region15_addr_end_reg_t region15_addr_end; - volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr; - volatile hp_apm_func_ctrl_reg_t func_ctrl; - volatile hp_apm_m0_status_reg_t m0_status; - volatile hp_apm_m0_status_clr_reg_t m0_status_clr; - volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0; - volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1; - volatile hp_apm_m1_status_reg_t m1_status; - volatile hp_apm_m1_status_clr_reg_t m1_status_clr; - volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0; - volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1; - volatile hp_apm_m2_status_reg_t m2_status; - volatile hp_apm_m2_status_clr_reg_t m2_status_clr; - volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0; - volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1; - volatile hp_apm_m3_status_reg_t m3_status; - volatile hp_apm_m3_status_clr_reg_t m3_status_clr; - volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0; - volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1; - volatile hp_apm_int_en_reg_t int_en; - volatile hp_apm_clock_gate_reg_t clock_gate; - uint32_t reserved_110[443]; - volatile hp_apm_date_reg_t date; -} hp_apm_dev_t; - -extern hp_apm_dev_t HP_APM; - -#ifndef __cplusplus -_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/hp_clkrst_reg.h b/components/soc/esp32p4/include/soc/hp_clkrst_reg.h deleted file mode 100644 index 661563894f..0000000000 --- a/components/soc/esp32p4/include/soc/hp_clkrst_reg.h +++ /dev/null @@ -1,629 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_HP_CLKRST_REG_H_ -#define _SOC_HP_CLKRST_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" - -#define HP_CLKRST_VER_DATE_REG (DR_REG_HP_CLKRST_BASE + 0x0) -/* HP_CLKRST_VER_DATE : R/W ;bitpos:[31:0] ;default: 32'h20201229 ; */ -/*description: .*/ -#define HP_CLKRST_VER_DATE 0xFFFFFFFF -#define HP_CLKRST_VER_DATE_M ((HP_CLKRST_VER_DATE_V)<<(HP_CLKRST_VER_DATE_S)) -#define HP_CLKRST_VER_DATE_V 0xFFFFFFFF -#define HP_CLKRST_VER_DATE_S 0 - -#define HP_CLKRST_HP_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x4) -/* HP_CLKRST_HP_CPU_ROOT_CLK_SEL : R/W ;bitpos:[3:2] ;default: 2'h1 ; */ -/*description: Hp cpu root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP CPU -PLL clock; 2'h3: HP system PLL clock.*/ -#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL 0x00000003 -#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_M ((HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S)) -#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V 0x3 -#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S 2 -/* HP_CLKRST_HP_SYS_ROOT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */ -/*description: Hp system root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP s -ystem PLL clock; 2'h3: HP CPU PLL clock.*/ -#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL 0x00000003 -#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_M ((HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S)) -#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V 0x3 -#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S 0 - -#define HP_CLKRST_CPU_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x8) -/* HP_CLKRST_CPU_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM 0x000000FF -#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_M ((HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S)) -#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V 0xFF -#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S 24 -/* HP_CLKRST_CPU_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define HP_CLKRST_CPU_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_CPU_CLK_DIV_NUM_M ((HP_CLKRST_CPU_CLK_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_DIV_NUM_S)) -#define HP_CLKRST_CPU_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_CPU_CLK_DIV_NUM_S 8 -/* HP_CLKRST_CPU_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define HP_CLKRST_CPU_CLK_EN (BIT(0)) -#define HP_CLKRST_CPU_CLK_EN_M (BIT(0)) -#define HP_CLKRST_CPU_CLK_EN_V 0x1 -#define HP_CLKRST_CPU_CLK_EN_S 0 - -#define HP_CLKRST_SYS_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0xC) -/* HP_CLKRST_SYS_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM 0x000000FF -#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_M ((HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S)) -#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V 0xFF -#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S 24 -/* HP_CLKRST_SYS_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: phase offset compare to clock sync signal.*/ -#define HP_CLKRST_SYS_CLK_PHASE_OFFSET 0x000000FF -#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_M ((HP_CLKRST_SYS_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_SYS_CLK_PHASE_OFFSET_S)) -#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_V 0xFF -#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_S 16 -/* HP_CLKRST_SYS_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define HP_CLKRST_SYS_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_SYS_CLK_DIV_NUM_M ((HP_CLKRST_SYS_CLK_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_DIV_NUM_S)) -#define HP_CLKRST_SYS_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_SYS_CLK_DIV_NUM_S 8 -/* HP_CLKRST_SYS_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN (BIT(2)) -#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_V 0x1 -#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_S 2 -/* HP_CLKRST_SYS_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define HP_CLKRST_SYS_CLK_SYNC_EN (BIT(1)) -#define HP_CLKRST_SYS_CLK_SYNC_EN_M (BIT(1)) -#define HP_CLKRST_SYS_CLK_SYNC_EN_V 0x1 -#define HP_CLKRST_SYS_CLK_SYNC_EN_S 1 -/* HP_CLKRST_SYS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define HP_CLKRST_SYS_CLK_EN (BIT(0)) -#define HP_CLKRST_SYS_CLK_EN_M (BIT(0)) -#define HP_CLKRST_SYS_CLK_EN_V 0x1 -#define HP_CLKRST_SYS_CLK_EN_S 0 - -#define HP_CLKRST_PERI1_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x10) -/* HP_CLKRST_PERI1_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM 0x000000FF -#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_M ((HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S)) -#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V 0xFF -#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S 24 -/* HP_CLKRST_PERI1_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: phase offset compare to clock sync signal.*/ -#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET 0x000000FF -#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_M ((HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S)) -#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V 0xFF -#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S 16 -/* HP_CLKRST_PERI1_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define HP_CLKRST_PERI1_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_PERI1_CLK_DIV_NUM_M ((HP_CLKRST_PERI1_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_DIV_NUM_S)) -#define HP_CLKRST_PERI1_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_PERI1_CLK_DIV_NUM_S 8 -/* HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN (BIT(2)) -#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_V 0x1 -#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_S 2 -/* HP_CLKRST_PERI1_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define HP_CLKRST_PERI1_CLK_SYNC_EN (BIT(1)) -#define HP_CLKRST_PERI1_CLK_SYNC_EN_M (BIT(1)) -#define HP_CLKRST_PERI1_CLK_SYNC_EN_V 0x1 -#define HP_CLKRST_PERI1_CLK_SYNC_EN_S 1 -/* HP_CLKRST_PERI1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define HP_CLKRST_PERI1_CLK_EN (BIT(0)) -#define HP_CLKRST_PERI1_CLK_EN_M (BIT(0)) -#define HP_CLKRST_PERI1_CLK_EN_V 0x1 -#define HP_CLKRST_PERI1_CLK_EN_S 0 - -#define HP_CLKRST_PERI2_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x14) -/* HP_CLKRST_PERI2_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM 0x000000FF -#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_M ((HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S)) -#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V 0xFF -#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S 24 -/* HP_CLKRST_PERI2_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: phase offset compare to clock sync signal.*/ -#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET 0x000000FF -#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_M ((HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S)) -#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V 0xFF -#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S 16 -/* HP_CLKRST_PERI2_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define HP_CLKRST_PERI2_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_PERI2_CLK_DIV_NUM_M ((HP_CLKRST_PERI2_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_DIV_NUM_S)) -#define HP_CLKRST_PERI2_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_PERI2_CLK_DIV_NUM_S 8 -/* HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN (BIT(2)) -#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_V 0x1 -#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_S 2 -/* HP_CLKRST_PERI2_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define HP_CLKRST_PERI2_CLK_SYNC_EN (BIT(1)) -#define HP_CLKRST_PERI2_CLK_SYNC_EN_M (BIT(1)) -#define HP_CLKRST_PERI2_CLK_SYNC_EN_V 0x1 -#define HP_CLKRST_PERI2_CLK_SYNC_EN_S 1 -/* HP_CLKRST_PERI2_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define HP_CLKRST_PERI2_CLK_EN (BIT(0)) -#define HP_CLKRST_PERI2_CLK_EN_M (BIT(0)) -#define HP_CLKRST_PERI2_CLK_EN_V 0x1 -#define HP_CLKRST_PERI2_CLK_EN_S 0 - -#define HP_CLKRST_PSRAM_PHY_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x18) -/* HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM 0x000000FF -#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_M ((HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S)) -#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V 0xFF -#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S 24 -/* HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: .*/ -#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_M ((HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S)) -#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S 8 -/* HP_CLKRST_PSRAM_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */ -/*description: .*/ -#define HP_CLKRST_PSRAM_PHY_CLK_SEL 0x00000003 -#define HP_CLKRST_PSRAM_PHY_CLK_SEL_M ((HP_CLKRST_PSRAM_PHY_CLK_SEL_V)<<(HP_CLKRST_PSRAM_PHY_CLK_SEL_S)) -#define HP_CLKRST_PSRAM_PHY_CLK_SEL_V 0x3 -#define HP_CLKRST_PSRAM_PHY_CLK_SEL_S 1 -/* HP_CLKRST_PSRAM_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define HP_CLKRST_PSRAM_PHY_CLK_EN (BIT(0)) -#define HP_CLKRST_PSRAM_PHY_CLK_EN_M (BIT(0)) -#define HP_CLKRST_PSRAM_PHY_CLK_EN_V 0x1 -#define HP_CLKRST_PSRAM_PHY_CLK_EN_S 0 - -#define HP_CLKRST_DDR_PHY_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x1C) -/* HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM 0x000000FF -#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_M ((HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S)) -#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V 0xFF -#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S 24 -/* HP_CLKRST_DDR_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: .*/ -#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_M ((HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S)) -#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S 8 -/* HP_CLKRST_DDR_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */ -/*description: .*/ -#define HP_CLKRST_DDR_PHY_CLK_SEL 0x00000003 -#define HP_CLKRST_DDR_PHY_CLK_SEL_M ((HP_CLKRST_DDR_PHY_CLK_SEL_V)<<(HP_CLKRST_DDR_PHY_CLK_SEL_S)) -#define HP_CLKRST_DDR_PHY_CLK_SEL_V 0x3 -#define HP_CLKRST_DDR_PHY_CLK_SEL_S 1 -/* HP_CLKRST_DDR_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define HP_CLKRST_DDR_PHY_CLK_EN (BIT(0)) -#define HP_CLKRST_DDR_PHY_CLK_EN_M (BIT(0)) -#define HP_CLKRST_DDR_PHY_CLK_EN_V 0x1 -#define HP_CLKRST_DDR_PHY_CLK_EN_S 0 - -#define HP_CLKRST_MSPI_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x20) -/* HP_CLKRST_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */ -/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/ -#define HP_CLKRST_MSPI_SRC_CLK_SEL 0x00000003 -#define HP_CLKRST_MSPI_SRC_CLK_SEL_M ((HP_CLKRST_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_MSPI_SRC_CLK_SEL_S)) -#define HP_CLKRST_MSPI_SRC_CLK_SEL_V 0x3 -#define HP_CLKRST_MSPI_SRC_CLK_SEL_S 16 -/* HP_CLKRST_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */ -/*description: clock divider number.*/ -#define HP_CLKRST_MSPI_CLK_DIV_NUM 0x0000000F -#define HP_CLKRST_MSPI_CLK_DIV_NUM_M ((HP_CLKRST_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_MSPI_CLK_DIV_NUM_S)) -#define HP_CLKRST_MSPI_CLK_DIV_NUM_V 0xF -#define HP_CLKRST_MSPI_CLK_DIV_NUM_S 8 -/* HP_CLKRST_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define HP_CLKRST_MSPI_CLK_EN (BIT(0)) -#define HP_CLKRST_MSPI_CLK_EN_M (BIT(0)) -#define HP_CLKRST_MSPI_CLK_EN_V 0x1 -#define HP_CLKRST_MSPI_CLK_EN_S 0 - -#define HP_CLKRST_DUAL_MSPI_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x24) -/* HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */ -/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/ -#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL 0x00000003 -#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_M ((HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S)) -#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V 0x3 -#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S 16 -/* HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */ -/*description: clock divider number.*/ -#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM 0x0000000F -#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_M ((HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S)) -#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V 0xF -#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S 8 -/* HP_CLKRST_DUAL_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define HP_CLKRST_DUAL_MSPI_CLK_EN (BIT(0)) -#define HP_CLKRST_DUAL_MSPI_CLK_EN_M (BIT(0)) -#define HP_CLKRST_DUAL_MSPI_CLK_EN_V 0x1 -#define HP_CLKRST_DUAL_MSPI_CLK_EN_S 0 - -#define HP_CLKRST_REF_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x28) -/* HP_CLKRST_REF_CLK2_DIV_NUM : R/W ;bitpos:[27:24] ;default: 4'h3 ; */ -/*description: 120MHz reference clock divider number, used by i3c master.*/ -#define HP_CLKRST_REF_CLK2_DIV_NUM 0x0000000F -#define HP_CLKRST_REF_CLK2_DIV_NUM_M ((HP_CLKRST_REF_CLK2_DIV_NUM_V)<<(HP_CLKRST_REF_CLK2_DIV_NUM_S)) -#define HP_CLKRST_REF_CLK2_DIV_NUM_V 0xF -#define HP_CLKRST_REF_CLK2_DIV_NUM_S 24 -/* HP_CLKRST_USBPHY_CLK_DIV_NUM : R/W ;bitpos:[23:20] ;default: 4'h9 ; */ -/*description: usbphy clock divider number.*/ -#define HP_CLKRST_USBPHY_CLK_DIV_NUM 0x0000000F -#define HP_CLKRST_USBPHY_CLK_DIV_NUM_M ((HP_CLKRST_USBPHY_CLK_DIV_NUM_V)<<(HP_CLKRST_USBPHY_CLK_DIV_NUM_S)) -#define HP_CLKRST_USBPHY_CLK_DIV_NUM_V 0xF -#define HP_CLKRST_USBPHY_CLK_DIV_NUM_S 20 -/* HP_CLKRST_LEDC_REF_CLK_DIV_NUM : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: ledc reference clock divider number.*/ -#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM 0x0000000F -#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_M ((HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S)) -#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V 0xF -#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S 16 -/* HP_CLKRST_USB2_REF_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h27 ; */ -/*description: usb2 phy reference clock divider number.*/ -#define HP_CLKRST_USB2_REF_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_M ((HP_CLKRST_USB2_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_USB2_REF_CLK_DIV_NUM_S)) -#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_S 8 -/* HP_CLKRST_REF_CLK_DIV_NUM : R/W ;bitpos:[4:1] ;default: 4'h2 ; */ -/*description: reference clock divider number.*/ -#define HP_CLKRST_REF_CLK_DIV_NUM 0x0000000F -#define HP_CLKRST_REF_CLK_DIV_NUM_M ((HP_CLKRST_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_REF_CLK_DIV_NUM_S)) -#define HP_CLKRST_REF_CLK_DIV_NUM_V 0xF -#define HP_CLKRST_REF_CLK_DIV_NUM_S 1 -/* HP_CLKRST_REF_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: reference clock output enable.*/ -#define HP_CLKRST_REF_CLK_EN (BIT(0)) -#define HP_CLKRST_REF_CLK_EN_M (BIT(0)) -#define HP_CLKRST_REF_CLK_EN_V 0x1 -#define HP_CLKRST_REF_CLK_EN_S 0 - -#define HP_CLKRST_TM_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x2C) -/* HP_CLKRST_TM_240M_CLK_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: 240M test mode clock enable.*/ -#define HP_CLKRST_TM_240M_CLK_EN (BIT(7)) -#define HP_CLKRST_TM_240M_CLK_EN_M (BIT(7)) -#define HP_CLKRST_TM_240M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_240M_CLK_EN_S 7 -/* HP_CLKRST_TM_200M_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: 200M test mode clock enable.*/ -#define HP_CLKRST_TM_200M_CLK_EN (BIT(6)) -#define HP_CLKRST_TM_200M_CLK_EN_M (BIT(6)) -#define HP_CLKRST_TM_200M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_200M_CLK_EN_S 6 -/* HP_CLKRST_TM_160M_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: 160M test mode clock enable.*/ -#define HP_CLKRST_TM_160M_CLK_EN (BIT(5)) -#define HP_CLKRST_TM_160M_CLK_EN_M (BIT(5)) -#define HP_CLKRST_TM_160M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_160M_CLK_EN_S 5 -/* HP_CLKRST_TM_120M_CLK_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: 120M test mode clock enable.*/ -#define HP_CLKRST_TM_120M_CLK_EN (BIT(4)) -#define HP_CLKRST_TM_120M_CLK_EN_M (BIT(4)) -#define HP_CLKRST_TM_120M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_120M_CLK_EN_S 4 -/* HP_CLKRST_TM_80M_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: 80M test mode clock enable.*/ -#define HP_CLKRST_TM_80M_CLK_EN (BIT(3)) -#define HP_CLKRST_TM_80M_CLK_EN_M (BIT(3)) -#define HP_CLKRST_TM_80M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_80M_CLK_EN_S 3 -/* HP_CLKRST_TM_48M_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: 48M test mode clock enable.*/ -#define HP_CLKRST_TM_48M_CLK_EN (BIT(2)) -#define HP_CLKRST_TM_48M_CLK_EN_M (BIT(2)) -#define HP_CLKRST_TM_48M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_48M_CLK_EN_S 2 -/* HP_CLKRST_TM_40M_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 40M test mode clock enable.*/ -#define HP_CLKRST_TM_40M_CLK_EN (BIT(1)) -#define HP_CLKRST_TM_40M_CLK_EN_M (BIT(1)) -#define HP_CLKRST_TM_40M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_40M_CLK_EN_S 1 -/* HP_CLKRST_TM_20M_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 20M test mode clock enabl.*/ -#define HP_CLKRST_TM_20M_CLK_EN (BIT(0)) -#define HP_CLKRST_TM_20M_CLK_EN_M (BIT(0)) -#define HP_CLKRST_TM_20M_CLK_EN_V 0x1 -#define HP_CLKRST_TM_20M_CLK_EN_S 0 - -#define HP_CLKRST_CORE_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x30) -/* HP_CLKRST_CORE0_GLOBAL_RSTN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: core0 software global reset.*/ -#define HP_CLKRST_CORE0_GLOBAL_RSTN (BIT(9)) -#define HP_CLKRST_CORE0_GLOBAL_RSTN_M (BIT(9)) -#define HP_CLKRST_CORE0_GLOBAL_RSTN_V 0x1 -#define HP_CLKRST_CORE0_GLOBAL_RSTN_S 9 -/* HP_CLKRST_CORE1_GLOBAL_RSTN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: core1 software global reset.*/ -#define HP_CLKRST_CORE1_GLOBAL_RSTN (BIT(8)) -#define HP_CLKRST_CORE1_GLOBAL_RSTN_M (BIT(8)) -#define HP_CLKRST_CORE1_GLOBAL_RSTN_V 0x1 -#define HP_CLKRST_CORE1_GLOBAL_RSTN_S 8 -/* HP_CLKRST_CORE0_FORCE_NORST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define HP_CLKRST_CORE0_FORCE_NORST (BIT(7)) -#define HP_CLKRST_CORE0_FORCE_NORST_M (BIT(7)) -#define HP_CLKRST_CORE0_FORCE_NORST_V 0x1 -#define HP_CLKRST_CORE0_FORCE_NORST_S 7 -/* HP_CLKRST_CORE1_FORCE_NORST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define HP_CLKRST_CORE1_FORCE_NORST (BIT(6)) -#define HP_CLKRST_CORE1_FORCE_NORST_M (BIT(6)) -#define HP_CLKRST_CORE1_FORCE_NORST_V 0x1 -#define HP_CLKRST_CORE1_FORCE_NORST_S 6 -/* HP_CLKRST_CORE2_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define HP_CLKRST_CORE2_FORCE_NORST (BIT(5)) -#define HP_CLKRST_CORE2_FORCE_NORST_M (BIT(5)) -#define HP_CLKRST_CORE2_FORCE_NORST_V 0x1 -#define HP_CLKRST_CORE2_FORCE_NORST_S 5 -/* HP_CLKRST_CORE3_FORCE_NORST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define HP_CLKRST_CORE3_FORCE_NORST (BIT(4)) -#define HP_CLKRST_CORE3_FORCE_NORST_M (BIT(4)) -#define HP_CLKRST_CORE3_FORCE_NORST_V 0x1 -#define HP_CLKRST_CORE3_FORCE_NORST_S 4 -/* HP_CLKRST_CORE0_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: hp core0 clock enable.*/ -#define HP_CLKRST_CORE0_CLK_EN (BIT(3)) -#define HP_CLKRST_CORE0_CLK_EN_M (BIT(3)) -#define HP_CLKRST_CORE0_CLK_EN_V 0x1 -#define HP_CLKRST_CORE0_CLK_EN_S 3 -/* HP_CLKRST_CORE1_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: hp core1 clock enable.*/ -#define HP_CLKRST_CORE1_CLK_EN (BIT(2)) -#define HP_CLKRST_CORE1_CLK_EN_M (BIT(2)) -#define HP_CLKRST_CORE1_CLK_EN_V 0x1 -#define HP_CLKRST_CORE1_CLK_EN_S 2 -/* HP_CLKRST_CORE2_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: hp core2 clock enable.*/ -#define HP_CLKRST_CORE2_CLK_EN (BIT(1)) -#define HP_CLKRST_CORE2_CLK_EN_M (BIT(1)) -#define HP_CLKRST_CORE2_CLK_EN_V 0x1 -#define HP_CLKRST_CORE2_CLK_EN_S 1 -/* HP_CLKRST_CORE3_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: hp core3 clock enable.*/ -#define HP_CLKRST_CORE3_CLK_EN (BIT(0)) -#define HP_CLKRST_CORE3_CLK_EN_M (BIT(0)) -#define HP_CLKRST_CORE3_CLK_EN_V 0x1 -#define HP_CLKRST_CORE3_CLK_EN_S 0 - -#define HP_CLKRST_CACHE_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x34) -/* HP_CLKRST_CACHE_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: L2 cache clock divider number.*/ -#define HP_CLKRST_CACHE_CLK_DIV_NUM 0x000000FF -#define HP_CLKRST_CACHE_CLK_DIV_NUM_M ((HP_CLKRST_CACHE_CLK_DIV_NUM_V)<<(HP_CLKRST_CACHE_CLK_DIV_NUM_S)) -#define HP_CLKRST_CACHE_CLK_DIV_NUM_V 0xFF -#define HP_CLKRST_CACHE_CLK_DIV_NUM_S 8 -/* HP_CLKRST_HP_CACHE_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: cache software reset: low active.*/ -#define HP_CLKRST_HP_CACHE_RSTN (BIT(2)) -#define HP_CLKRST_HP_CACHE_RSTN_M (BIT(2)) -#define HP_CLKRST_HP_CACHE_RSTN_V 0x1 -#define HP_CLKRST_HP_CACHE_RSTN_S 2 -/* HP_CLKRST_CACHE_APB_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: cache apb clock enable.*/ -#define HP_CLKRST_CACHE_APB_CLK_EN (BIT(1)) -#define HP_CLKRST_CACHE_APB_CLK_EN_M (BIT(1)) -#define HP_CLKRST_CACHE_APB_CLK_EN_V 0x1 -#define HP_CLKRST_CACHE_APB_CLK_EN_S 1 -/* HP_CLKRST_CACHE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: cache clock enable.*/ -#define HP_CLKRST_CACHE_CLK_EN (BIT(0)) -#define HP_CLKRST_CACHE_CLK_EN_M (BIT(0)) -#define HP_CLKRST_CACHE_CLK_EN_V 0x1 -#define HP_CLKRST_CACHE_CLK_EN_S 0 - -#define HP_CLKRST_CPU_PERI_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x38) -/* HP_CLKRST_L2_MEM_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: l2 memory software reset: low active.*/ -#define HP_CLKRST_L2_MEM_RSTN (BIT(4)) -#define HP_CLKRST_L2_MEM_RSTN_M (BIT(4)) -#define HP_CLKRST_L2_MEM_RSTN_V 0x1 -#define HP_CLKRST_L2_MEM_RSTN_S 4 -/* HP_CLKRST_L2_MEM_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: l2 memory clock enable.*/ -#define HP_CLKRST_L2_MEM_CLK_EN (BIT(3)) -#define HP_CLKRST_L2_MEM_CLK_EN_M (BIT(3)) -#define HP_CLKRST_L2_MEM_CLK_EN_V 0x1 -#define HP_CLKRST_L2_MEM_CLK_EN_S 3 -/* HP_CLKRST_TCM_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: tcm software reset: low active.*/ -#define HP_CLKRST_TCM_RSTN (BIT(2)) -#define HP_CLKRST_TCM_RSTN_M (BIT(2)) -#define HP_CLKRST_TCM_RSTN_V 0x1 -#define HP_CLKRST_TCM_RSTN_S 2 -/* HP_CLKRST_TCM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: tcm clock enable.*/ -#define HP_CLKRST_TCM_CLK_EN (BIT(1)) -#define HP_CLKRST_TCM_CLK_EN_M (BIT(1)) -#define HP_CLKRST_TCM_CLK_EN_V 0x1 -#define HP_CLKRST_TCM_CLK_EN_S 1 -/* HP_CLKRST_CPU_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: cpu control logic clock enable.*/ -#define HP_CLKRST_CPU_CTRL_CLK_EN (BIT(0)) -#define HP_CLKRST_CPU_CTRL_CLK_EN_M (BIT(0)) -#define HP_CLKRST_CPU_CTRL_CLK_EN_V 0x1 -#define HP_CLKRST_CPU_CTRL_CLK_EN_S 0 - -#define HP_CLKRST_SYNC_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x3C) -/* HP_CLKRST_CLK_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */ -/*description: .*/ -#define HP_CLKRST_CLK_EN (BIT(17)) -#define HP_CLKRST_CLK_EN_M (BIT(17)) -#define HP_CLKRST_CLK_EN_V 0x1 -#define HP_CLKRST_CLK_EN_S 17 -/* HP_CLKRST_HP_ROOT_CLK_SYNC_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: clock sync signal output enable.*/ -#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN (BIT(16)) -#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_M (BIT(16)) -#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_V 0x1 -#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_S 16 -/* HP_CLKRST_HP_ROOT_CLK_SYNC_PERID : R/W ;bitpos:[15:0] ;default: 16'h347 ; */ -/*description: clock sync signal generation period.*/ -#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID 0x0000FFFF -#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_M ((HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V)<<(HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S)) -#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V 0xFFFF -#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S 0 - -#define HP_CLKRST_WFI_GATE_CLK_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x40) -/* HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: force group3(L2 Memory) clock on after WFI.*/ -#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON (BIT(18)) -#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_M (BIT(18)) -#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_V 0x1 -#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_S 18 -/* HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON : R/W ;bitpos:[17] ;default: 1'b1 ; */ -/*description: force group2(HP TCM) clock on after WFI.*/ -#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON (BIT(17)) -#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_M (BIT(17)) -#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_V 0x1 -#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_S 17 -/* HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: force group1(L1/L2 cache & trace & cpu_icm_ibus) clock on after WFI.*/ -#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON (BIT(16)) -#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_M (BIT(16)) -#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_V 0x1 -#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_S 16 -/* HP_CLKRST_CPU_WFI_DELAY_NUM : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: This register indicates delayed clock cycles before auto gating HP cache/trace c -lock once WFI asserted.*/ -#define HP_CLKRST_CPU_WFI_DELAY_NUM 0x0000000F -#define HP_CLKRST_CPU_WFI_DELAY_NUM_M ((HP_CLKRST_CPU_WFI_DELAY_NUM_V)<<(HP_CLKRST_CPU_WFI_DELAY_NUM_S)) -#define HP_CLKRST_CPU_WFI_DELAY_NUM_V 0xF -#define HP_CLKRST_CPU_WFI_DELAY_NUM_S 0 - -#define HP_CLKRST_PVT_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x44) -/* HP_CLKRST_PVT_APB_RSTN : R/W ;bitpos:[21] ;default: 1'h1 ; */ -/*description: pvt apb resetn.*/ -#define HP_CLKRST_PVT_APB_RSTN (BIT(21)) -#define HP_CLKRST_PVT_APB_RSTN_M (BIT(21)) -#define HP_CLKRST_PVT_APB_RSTN_V 0x1 -#define HP_CLKRST_PVT_APB_RSTN_S 21 -/* HP_CLKRST_PVT_PERI_GROUP2_RSTN : R/W ;bitpos:[20] ;default: 1'h1 ; */ -/*description: pvt peri group2 resetn.*/ -#define HP_CLKRST_PVT_PERI_GROUP2_RSTN (BIT(20)) -#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_M (BIT(20)) -#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_V 0x1 -#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_S 20 -/* HP_CLKRST_PVT_PERI_GROUP1_RSTN : R/W ;bitpos:[19] ;default: 1'h1 ; */ -/*description: pvt peri group1 resetn.*/ -#define HP_CLKRST_PVT_PERI_GROUP1_RSTN (BIT(19)) -#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_M (BIT(19)) -#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_V 0x1 -#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_S 19 -/* HP_CLKRST_PVT_CPU_GROUP2_RSTN : R/W ;bitpos:[18] ;default: 1'h1 ; */ -/*description: pvt cpu group2 resetn.*/ -#define HP_CLKRST_PVT_CPU_GROUP2_RSTN (BIT(18)) -#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_M (BIT(18)) -#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_V 0x1 -#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_S 18 -/* HP_CLKRST_PVT_CPU_GROUP1_RSTN : R/W ;bitpos:[17] ;default: 1'h1 ; */ -/*description: pvt cpu group1 resetn.*/ -#define HP_CLKRST_PVT_CPU_GROUP1_RSTN (BIT(17)) -#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_M (BIT(17)) -#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_V 0x1 -#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_S 17 -/* HP_CLKRST_PVT_TOP_RSTN : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: pvt top resetn.*/ -#define HP_CLKRST_PVT_TOP_RSTN (BIT(16)) -#define HP_CLKRST_PVT_TOP_RSTN_M (BIT(16)) -#define HP_CLKRST_PVT_TOP_RSTN_V 0x1 -#define HP_CLKRST_PVT_TOP_RSTN_S 16 -/* HP_CLKRST_PVT_APB_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: pvt apb clk en.*/ -#define HP_CLKRST_PVT_APB_CLK_EN (BIT(13)) -#define HP_CLKRST_PVT_APB_CLK_EN_M (BIT(13)) -#define HP_CLKRST_PVT_APB_CLK_EN_V 0x1 -#define HP_CLKRST_PVT_APB_CLK_EN_S 13 -/* HP_CLKRST_PVT_PERI_GROUP2_CLK_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: pvt peri group2 clk en.*/ -#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN (BIT(12)) -#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_M (BIT(12)) -#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_V 0x1 -#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_S 12 -/* HP_CLKRST_PVT_PERI_GROUP1_CLK_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: pvt peri group1 clk en.*/ -#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN (BIT(11)) -#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_M (BIT(11)) -#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_V 0x1 -#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_S 11 -/* HP_CLKRST_PVT_CPU_GROUP2_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: pvt cpu group2 clk en.*/ -#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN (BIT(10)) -#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_M (BIT(10)) -#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_V 0x1 -#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_S 10 -/* HP_CLKRST_PVT_CPU_GROUP1_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: pvt cpu group1 clk en.*/ -#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN (BIT(9)) -#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_M (BIT(9)) -#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_V 0x1 -#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_S 9 -/* HP_CLKRST_PVT_TOP_CLK_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: pvt top clock en.*/ -#define HP_CLKRST_PVT_TOP_CLK_EN (BIT(8)) -#define HP_CLKRST_PVT_TOP_CLK_EN_M (BIT(8)) -#define HP_CLKRST_PVT_TOP_CLK_EN_V 0x1 -#define HP_CLKRST_PVT_TOP_CLK_EN_S 8 -/* HP_CLKRST_PVT_CLK_DIV_NUM : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ -/*description: pvt clock div number.*/ -#define HP_CLKRST_PVT_CLK_DIV_NUM 0x0000000F -#define HP_CLKRST_PVT_CLK_DIV_NUM_M ((HP_CLKRST_PVT_CLK_DIV_NUM_V)<<(HP_CLKRST_PVT_CLK_DIV_NUM_S)) -#define HP_CLKRST_PVT_CLK_DIV_NUM_V 0xF -#define HP_CLKRST_PVT_CLK_DIV_NUM_S 4 -/* HP_CLKRST_PVT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */ -/*description: pvt clock sel.*/ -#define HP_CLKRST_PVT_CLK_SEL 0x00000003 -#define HP_CLKRST_PVT_CLK_SEL_M ((HP_CLKRST_PVT_CLK_SEL_V)<<(HP_CLKRST_PVT_CLK_SEL_S)) -#define HP_CLKRST_PVT_CLK_SEL_V 0x3 -#define HP_CLKRST_PVT_CLK_SEL_S 0 - -#define HP_CLKRST_TEST_PLL_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x48) -/* HP_CLKRST_TEST_PLL_DIV_NUM : R/W ;bitpos:[27:16] ;default: 12'h3e7 ; */ -/*description: test pll divider number.*/ -#define HP_CLKRST_TEST_PLL_DIV_NUM 0x00000FFF -#define HP_CLKRST_TEST_PLL_DIV_NUM_M ((HP_CLKRST_TEST_PLL_DIV_NUM_V)<<(HP_CLKRST_TEST_PLL_DIV_NUM_S)) -#define HP_CLKRST_TEST_PLL_DIV_NUM_V 0xFFF -#define HP_CLKRST_TEST_PLL_DIV_NUM_S 16 -/* HP_CLKRST_TEST_PLL_SEL : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: test pll source select; 3'h0: RSVD; 3'h1: system PLL; 3'h2: CPU PLL; 3'h3: MPSI -DLL; 3'h4: SDIO PLL CK0; 3'h5: SDIO PLL CK1; 3'h6: SDIO PLL CK2; 3'h7: AUDIO APL -L.*/ -#define HP_CLKRST_TEST_PLL_SEL 0x00000007 -#define HP_CLKRST_TEST_PLL_SEL_M ((HP_CLKRST_TEST_PLL_SEL_V)<<(HP_CLKRST_TEST_PLL_SEL_S)) -#define HP_CLKRST_TEST_PLL_SEL_V 0x7 -#define HP_CLKRST_TEST_PLL_SEL_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_HP_CLKRST_REG_H_ */ diff --git a/components/soc/esp32p4/include/soc/hwcrypto_reg.h b/components/soc/esp32p4/include/soc/hwcrypto_reg.h deleted file mode 100644 index af608fcd27..0000000000 --- a/components/soc/esp32p4/include/soc/hwcrypto_reg.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef __HWCRYPTO_REG_H__ -#define __HWCRYPTO_REG_H__ - -#include "soc/soc.h" - -/* registers for RSA acceleration via Multiple Precision Integer ops */ -#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) -/* RB & Z use the same memory block, depending on phase of operation */ -#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) -#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) -#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400) -#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600) - -/* Configuration registers */ -#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800) -#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804) -#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) -#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) -#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) - -/* Initialization registers */ -#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) - -/* Calculation start registers */ -#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) -#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810) -#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) - -/* Interrupt registers */ -#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818) -#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C) -#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) -#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x82C) - -#define SHA_MODE_SHA1 0 -#define SHA_MODE_SHA224 1 -#define SHA_MODE_SHA256 2 - -/* SHA acceleration registers */ -#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00) -#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C) -#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10) -#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14) -#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18) -#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C) -#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20) -#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24) -#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28) -#define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C) - -#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40) -#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80) - -/* AES Block operation modes */ -#define AES_BLOCK_MODE_ECB 0 -#define AES_BLOCK_MODE_CBC 1 -#define AES_BLOCK_MODE_OFB 2 -#define AES_BLOCK_MODE_CTR 3 -#define AES_BLOCK_MODE_CFB8 4 -#define AES_BLOCK_MODE_CFB128 5 - -/* AES Block operation modes (used with DMA) */ -#define AES_BLOCK_MODE_ECB 0 -#define AES_BLOCK_MODE_CBC 1 -#define AES_BLOCK_MODE_OFB 2 -#define AES_BLOCK_MODE_CTR 3 -#define AES_BLOCK_MODE_CFB8 4 -#define AES_BLOCK_MODE_CFB128 5 - -/* AES acceleration registers */ -#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40) -#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44) -#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48) -#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c) -#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) -#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) -#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) -#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) -#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) -#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) -#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) -#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC) -#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) -#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) -#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) - -#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) -#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) -#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) -#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) -#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) -#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) -#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) - -#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00) -#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20) -#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30) -#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50) -#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60) -#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) -#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) - -#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) -#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) -#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) -#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) - -/* AES_STATE_REG values */ -#define AES_STATE_IDLE 0 -#define AES_STATE_BUSY 1 -#define AES_STATE_DONE 2 - -/* HMAC Module */ -#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40) -#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44) -#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48) -#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c) -#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50) -#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54) -#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58) -#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c) -#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60) -#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64) -#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68) -#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c) - -#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80) -#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0) -#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0) -#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4) - -#define HMAC_SOFT_JTAG_CTRL_REG ((DR_REG_HMAC_BASE) + 0xF8) -#define HMAC_WR_JTAG_REG ((DR_REG_HMAC_BASE) + 0xFC) - -#define HMAC_DATE_REG ((DR_REG_HMAC_BASE) + 0xF8) - - -/* AES-XTS registers */ -#define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00) -#define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40) -#define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44) -#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48) - -#define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C) -#define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50) -#define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54) -#define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58) -#define AES_XTS_DATE_REG ((DR_REG_AES_XTS_BASE) + 0x5C) - -/* Digital Signature registers and memory blocks */ -#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) -#define DS_C_Y_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) -#define DS_C_M_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 ) -#define DS_C_RB_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 ) -#define DS_C_BOX_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 ) -#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 ) -#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 ) -#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 ) - -#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00) -#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04) -#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08) - -#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C) -#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10) -#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14) - -#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0) -#define DS_QUERY_CHECK_INVALID_PADDING (1<<1) - -#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20) - -#endif diff --git a/components/soc/esp32p4/include/soc/i2c_ext_reg.h b/components/soc/esp32p4/include/soc/i2c_ext_reg.h deleted file mode 100644 index 9cdfdcede6..0000000000 --- a/components/soc/esp32p4/include/soc/i2c_ext_reg.h +++ /dev/null @@ -1,1521 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** I2C_SCL_LOW_PERIOD_REG register - * Configures the low level width of the SCL Clock. - */ -#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) -/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; - * Configures the low level width of the SCL Clock. - * Measurement unit: i2c_sclk. - */ -#define I2C_SCL_LOW_PERIOD 0x000001FFU -#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) -#define I2C_SCL_LOW_PERIOD_V 0x000001FFU -#define I2C_SCL_LOW_PERIOD_S 0 - -/** I2C_CTR_REG register - * Transmission setting - */ -#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) -/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; - * Configures the SDA output mode - * 1: Direct output, - * - * 0: Open drain output. - */ -#define I2C_SDA_FORCE_OUT (BIT(0)) -#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) -#define I2C_SDA_FORCE_OUT_V 0x00000001U -#define I2C_SDA_FORCE_OUT_S 0 -/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; - * Configures the SCL output mode - * 1: Direct output, - * - * 0: Open drain output. - */ -#define I2C_SCL_FORCE_OUT (BIT(1)) -#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) -#define I2C_SCL_FORCE_OUT_V 0x00000001U -#define I2C_SCL_FORCE_OUT_S 1 -/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; - * Configures the sample mode for SDA. - * 1: Sample SDA data on the SCL low level. - * - * 0: Sample SDA data on the SCL high level. - */ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) -#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; - * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has - * reached the threshold. - */ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) -#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U -#define I2C_RX_FULL_ACK_LEVEL_S 3 -/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; - * Configures the module as an I2C Master or Slave. - * 0: Slave - * - * 1: Master - */ -#define I2C_MS_MODE (BIT(4)) -#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) -#define I2C_MS_MODE_V 0x00000001U -#define I2C_MS_MODE_S 4 -/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; - * Configures to start sending the data in txfifo for slave. - * 0: No effect - * - * 1: Start - */ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) -#define I2C_TRANS_START_V 0x00000001U -#define I2C_TRANS_START_S 5 -/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; - * Configures to control the sending order for data needing to be sent. - * 1: send data from the least significant bit, - * - * 0: send data from the most significant bit. - */ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) -#define I2C_TX_LSB_FIRST_V 0x00000001U -#define I2C_TX_LSB_FIRST_S 6 -/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; - * Configures to control the storage order for received data. - * 1: receive data from the least significant bit - * - * 0: receive data from the most significant bit. - */ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) -#define I2C_RX_LSB_FIRST_V 0x00000001U -#define I2C_RX_LSB_FIRST_S 7 -/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; - * Configures whether to gate clock signal for registers. - * - * 0: Force clock on for registers - * - * 1: Support clock only when registers are read or written to by software. - */ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) -#define I2C_CLK_EN_V 0x00000001U -#define I2C_CLK_EN_S 8 -/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; - * Configures to enable I2C bus arbitration detection. - * 0: No effect - * - * 1: Enable - */ -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) -#define I2C_ARBITRATION_EN_V 0x00000001U -#define I2C_ARBITRATION_EN_S 9 -/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; - * Configures to reset the SCL_FSM. - * 0: No effect - * - * 1: Reset - */ -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) -#define I2C_FSM_RST_V 0x00000001U -#define I2C_FSM_RST_S 10 -/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; - * Configures this bit for synchronization - * 0: No effect - * - * 1: Synchronize - */ -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) -#define I2C_CONF_UPGATE_V 0x00000001U -#define I2C_CONF_UPGATE_S 11 -/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; - * Configures to enable slave to send data automatically - * 0: Disable - * - * 1: Enable - */ -#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) -#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) -#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U -#define I2C_SLV_TX_AUTO_START_EN_S 12 -/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; - * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. - * 0: Not check - * - * 1: Check - */ -#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) -#define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) -#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U -#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 -/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; - * Configures to support the 7bit general call function. - * 0: Not support - * - * 1: Support - */ -#define I2C_ADDR_BROADCASTING_EN (BIT(14)) -#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) -#define I2C_ADDR_BROADCASTING_EN_V 0x00000001U -#define I2C_ADDR_BROADCASTING_EN_S 14 - -/** I2C_SR_REG register - * Describe I2C work status. - */ -#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) -/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; - * Represents the received ACK value in master mode or slave mode. - * 0: ACK, - * - * 1: NACK. - */ -#define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) -#define I2C_RESP_REC_V 0x00000001U -#define I2C_RESP_REC_S 0 -/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; - * Represents the transfer direction in slave mode,. - * 1: Master reads from slave, - * - * 0: Master writes to slave. - */ -#define I2C_SLAVE_RW (BIT(1)) -#define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) -#define I2C_SLAVE_RW_V 0x00000001U -#define I2C_SLAVE_RW_S 1 -/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; - * Represents whether the I2C controller loses control of SCL line. - * 0: No arbitration lost - * - * 1: Arbitration lost - */ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) -#define I2C_ARB_LOST_V 0x00000001U -#define I2C_ARB_LOST_S 3 -/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; - * Represents the I2C bus state. - * 1: The I2C bus is busy transferring data, - * - * 0: The I2C bus is in idle state. - */ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) -#define I2C_BUS_BUSY_V 0x00000001U -#define I2C_BUS_BUSY_S 4 -/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; - * Represents whether the address sent by the master is equal to the address of the - * slave. - * Valid only when the module is configured as an I2C Slave. - * 0: Not equal - * - * 1: Equal - */ -#define I2C_SLAVE_ADDRESSED (BIT(5)) -#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) -#define I2C_SLAVE_ADDRESSED_V 0x00000001U -#define I2C_SLAVE_ADDRESSED_S 5 -/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; - * Represents the number of data bytes to be sent. - */ -#define I2C_RXFIFO_CNT 0x0000003FU -#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) -#define I2C_RXFIFO_CNT_V 0x0000003FU -#define I2C_RXFIFO_CNT_S 8 -/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; - * Represents the cause of SCL clocking stretching in slave mode. - * 0: Stretching SCL low when the master starts to read data. - * - * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. - * - * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. - */ -#define I2C_STRETCH_CAUSE 0x00000003U -#define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) -#define I2C_STRETCH_CAUSE_V 0x00000003U -#define I2C_STRETCH_CAUSE_S 14 -/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; - * Represents the number of data bytes received in RAM. - */ -#define I2C_TXFIFO_CNT 0x0000003FU -#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) -#define I2C_TXFIFO_CNT_V 0x0000003FU -#define I2C_TXFIFO_CNT_S 18 -/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; - * Represents the states of the I2C module state machine. - * 0: Idle, - * - * 1: Address shift, - * - * 2: ACK address, - * - * 3: Rx data, - * - * 4: Tx data, - * - * 5: Send ACK, - * - * 6: Wait ACK - */ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) -#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; - * Represents the states of the state machine used to produce SCL. - * 0: Idle, - * - * 1: Start, - * - * 2: Negative edge, - * - * 3: Low, - * - * 4: Positive edge, - * - * 5: High, - * - * 6: Stop - */ -#define I2C_SCL_STATE_LAST 0x00000007U -#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) -#define I2C_SCL_STATE_LAST_V 0x00000007U -#define I2C_SCL_STATE_LAST_S 28 - -/** I2C_TO_REG register - * Setting time out control for receiving data. - */ -#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) -/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; - * Configures the timeout threshold period for SCL stucking at high or low level. The - * actual period is 2^(reg_time_out_value). - * Measurement unit: i2c_sclk. - */ -#define I2C_TIME_OUT_VALUE 0x0000001FU -#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) -#define I2C_TIME_OUT_VALUE_V 0x0000001FU -#define I2C_TIME_OUT_VALUE_S 0 -/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; - * Configures to enable time out control. - * 0: No effect - * - * 1: Enable - */ -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) -#define I2C_TIME_OUT_EN_V 0x00000001U -#define I2C_TIME_OUT_EN_S 5 - -/** I2C_SLAVE_ADDR_REG register - * Local slave address setting - */ -#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) -/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; - * Configure the slave address of I2C Slave. - */ -#define I2C_SLAVE_ADDR 0x00007FFFU -#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) -#define I2C_SLAVE_ADDR_V 0x00007FFFU -#define I2C_SLAVE_ADDR_S 0 -/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; - * Configures to enable the slave 10-bit addressing mode in master mode. - * 0: No effect - * - * 1: Enable - */ -#define I2C_ADDR_10BIT_EN (BIT(31)) -#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) -#define I2C_ADDR_10BIT_EN_V 0x00000001U -#define I2C_ADDR_10BIT_EN_S 31 - -/** I2C_FIFO_ST_REG register - * FIFO status register. - */ -#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) -/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; - * Represents the offset address of the APB reading from RXFIFO - */ -#define I2C_RXFIFO_RADDR 0x0000001FU -#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) -#define I2C_RXFIFO_RADDR_V 0x0000001FU -#define I2C_RXFIFO_RADDR_S 0 -/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; - * Represents the offset address of i2c module receiving data and writing to RXFIFO. - */ -#define I2C_RXFIFO_WADDR 0x0000001FU -#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) -#define I2C_RXFIFO_WADDR_V 0x0000001FU -#define I2C_RXFIFO_WADDR_S 5 -/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; - * Represents the offset address of i2c module reading from TXFIFO. - */ -#define I2C_TXFIFO_RADDR 0x0000001FU -#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) -#define I2C_TXFIFO_RADDR_V 0x0000001FU -#define I2C_TXFIFO_RADDR_S 10 -/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; - * Represents the offset address of APB bus writing to TXFIFO. - */ -#define I2C_TXFIFO_WADDR 0x0000001FU -#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) -#define I2C_TXFIFO_WADDR_V 0x0000001FU -#define I2C_TXFIFO_WADDR_S 15 -/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; - * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in - * I2C slave mode. - */ -#define I2C_SLAVE_RW_POINT 0x000000FFU -#define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) -#define I2C_SLAVE_RW_POINT_V 0x000000FFU -#define I2C_SLAVE_RW_POINT_S 22 - -/** I2C_FIFO_CONF_REG register - * FIFO configuration register. - */ -#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) -/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; - * Configures the water mark threshold of RXFIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than - * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. - */ -#define I2C_RXFIFO_WM_THRHD 0x0000001FU -#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) -#define I2C_RXFIFO_WM_THRHD_V 0x0000001FU -#define I2C_RXFIFO_WM_THRHD_S 0 -/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; - * Configures the water mark threshold of TXFIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than - * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. - */ -#define I2C_TXFIFO_WM_THRHD 0x0000001FU -#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) -#define I2C_TXFIFO_WM_THRHD_V 0x0000001FU -#define I2C_TXFIFO_WM_THRHD_S 5 -/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; - * Configures to enable APB nonfifo access. - */ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) -#define I2C_NONFIFO_EN_V 0x00000001U -#define I2C_NONFIFO_EN_S 10 -/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; - * Configures to enable double addressing mode. When this mode is enabled, the byte - * received after the I2C address byte represents the offset address in the I2C Slave - * RAM. - * 0: Disable - * - * 1: Enable - */ -#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) -#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U -#define I2C_FIFO_ADDR_CFG_EN_S 11 -/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; - * Configures to reset RXFIFO. - * 0: No effect - * - * 1: Reset - */ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) -#define I2C_RX_FIFO_RST_V 0x00000001U -#define I2C_RX_FIFO_RST_S 12 -/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; - * Configures to reset TXFIFO. - * 0: No effect - * - * 1: Reset - */ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) -#define I2C_TX_FIFO_RST_V 0x00000001U -#define I2C_TX_FIFO_RST_S 13 -/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; - * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the - * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. - * 0: No effect - * - * 1: Enable - */ -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) -#define I2C_FIFO_PRT_EN_V 0x00000001U -#define I2C_FIFO_PRT_EN_S 14 - -/** I2C_DATA_REG register - * Rx FIFO read data. - */ -#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) -/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; - * Represents the value of RXFIFO read data. - */ -#define I2C_FIFO_RDATA 0x000000FFU -#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) -#define I2C_FIFO_RDATA_V 0x000000FFU -#define I2C_FIFO_RDATA_S 0 - -/** I2C_INT_RAW_REG register - * Raw interrupt status - */ -#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) -/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) -#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_WM_INT_RAW_S 0 -/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) -#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_WM_INT_RAW_S 1 -/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt status of the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) -#define I2C_END_DETECT_INT_RAW_V 0x00000001U -#define I2C_END_DETECT_INT_RAW_S 3 -/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt status of the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 -/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 -/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) -#define I2C_TIME_OUT_INT_RAW_V 0x00000001U -#define I2C_TIME_OUT_INT_RAW_S 8 -/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt status of the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) -#define I2C_TRANS_START_INT_RAW_V 0x00000001U -#define I2C_TRANS_START_INT_RAW_S 9 -/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) -#define I2C_NACK_INT_RAW_V 0x00000001U -#define I2C_NACK_INT_RAW_S 10 -/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_RAW_S 11 -/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_RAW_S 12 -/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) -#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_ST_TO_INT_RAW_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 -/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt status of I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) -#define I2C_DET_START_INT_RAW_V 0x00000001U -#define I2C_DET_START_INT_RAW_S 15 -/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; - * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) -#define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U -#define I2C_SLAVE_STRETCH_INT_RAW_S 16 -/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; - * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. - */ -#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) -#define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) -#define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U -#define I2C_GENERAL_CALL_INT_RAW_S 17 -/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; - * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - */ -#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW (BIT(18)) -#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S) -#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V 0x00000001U -#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S 18 - -/** I2C_INT_CLR_REG register - * Interrupt clear bits - */ -#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) -/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) -#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_WM_INT_CLR_S 0 -/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) -#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_WM_INT_CLR_S 1 -/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) -#define I2C_END_DETECT_INT_CLR_V 0x00000001U -#define I2C_END_DETECT_INT_CLR_S 3 -/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 -/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 -/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Write 1 to clear the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) -#define I2C_TIME_OUT_INT_CLR_V 0x00000001U -#define I2C_TIME_OUT_INT_CLR_S 8 -/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; - * Write 1 to clear the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) -#define I2C_TRANS_START_INT_CLR_V 0x00000001U -#define I2C_TRANS_START_INT_CLR_S 9 -/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; - * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) -#define I2C_NACK_INT_CLR_V 0x00000001U -#define I2C_NACK_INT_CLR_S 10 -/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_CLR_S 11 -/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; - * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_CLR_S 12 -/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; - * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) -#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_ST_TO_INT_CLR_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; - * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 -/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; - * Write 1 to clear I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) -#define I2C_DET_START_INT_CLR_V 0x00000001U -#define I2C_DET_START_INT_CLR_S 15 -/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; - * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) -#define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U -#define I2C_SLAVE_STRETCH_INT_CLR_S 16 -/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; - * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. - */ -#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) -#define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) -#define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U -#define I2C_GENERAL_CALL_INT_CLR_S 17 -/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0; - * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - */ -#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR (BIT(18)) -#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S) -#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V 0x00000001U -#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S 18 - -/** I2C_INT_ENA_REG register - * Interrupt enable bits - */ -#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) -/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) -#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ENA_S 0 -/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) -#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ENA_S 1 -/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) -#define I2C_END_DETECT_INT_ENA_V 0x00000001U -#define I2C_END_DETECT_INT_ENA_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 -/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 -/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; - * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * Write 1 to enable the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) -#define I2C_TIME_OUT_INT_ENA_V 0x00000001U -#define I2C_TIME_OUT_INT_ENA_S 8 -/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * Write 1 to enable the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) -#define I2C_TRANS_START_INT_ENA_V 0x00000001U -#define I2C_TRANS_START_INT_ENA_S 9 -/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; - * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) -#define I2C_NACK_INT_ENA_V 0x00000001U -#define I2C_NACK_INT_ENA_S 10 -/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ENA_S 11 -/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; - * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ENA_S 12 -/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; - * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) -#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ENA_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; - * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 -/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * Write 1 to enable I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) -#define I2C_DET_START_INT_ENA_V 0x00000001U -#define I2C_DET_START_INT_ENA_S 15 -/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; - * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) -#define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U -#define I2C_SLAVE_STRETCH_INT_ENA_S 16 -/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; - * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. - */ -#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) -#define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) -#define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U -#define I2C_GENERAL_CALL_INT_ENA_S 17 -/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0; - * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - */ -#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA (BIT(18)) -#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S) -#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V 0x00000001U -#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S 18 - -/** I2C_INT_STATUS_REG register - * Status of captured I2C communication events - */ -#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) -/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) -#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ST_S 0 -/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) -#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ST_S 1 -/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) -#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) -#define I2C_END_DETECT_INT_ST_V 0x00000001U -#define I2C_END_DETECT_INT_ST_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 -/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 -/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; - * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) -#define I2C_TIME_OUT_INT_ST_V 0x00000001U -#define I2C_TIME_OUT_INT_ST_S 8 -/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; - * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) -#define I2C_TRANS_START_INT_ST_V 0x00000001U -#define I2C_TRANS_START_INT_ST_S 9 -/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; - * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) -#define I2C_NACK_INT_ST_V 0x00000001U -#define I2C_NACK_INT_ST_S 10 -/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) -#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ST_S 11 -/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) -#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ST_S 12 -/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; - * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) -#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ST_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; - * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 -/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; - * The masked interrupt status status of I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) -#define I2C_DET_START_INT_ST_V 0x00000001U -#define I2C_DET_START_INT_ST_S 15 -/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; - * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) -#define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U -#define I2C_SLAVE_STRETCH_INT_ST_S 16 -/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; - * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. - */ -#define I2C_GENERAL_CALL_INT_ST (BIT(17)) -#define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) -#define I2C_GENERAL_CALL_INT_ST_V 0x00000001U -#define I2C_GENERAL_CALL_INT_ST_S 17 -/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0; - * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - */ -#define I2C_SLAVE_ADDR_UNMATCH_INT_ST (BIT(18)) -#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S) -#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V 0x00000001U -#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S 18 - -/** I2C_SDA_HOLD_REG register - * Configures the hold time after a negative SCL edge. - */ -#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) -/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; - * Configures the time to hold the data after the falling edge of SCL. - * Measurement unit: i2c_sclk - */ -#define I2C_SDA_HOLD_TIME 0x000001FFU -#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) -#define I2C_SDA_HOLD_TIME_V 0x000001FFU -#define I2C_SDA_HOLD_TIME_S 0 - -/** I2C_SDA_SAMPLE_REG register - * Configures the sample time after a positive SCL edge. - */ -#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) -/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; - * Configures the sample time after a positive SCL edge. - * Measurement unit: i2c_sclk - */ -#define I2C_SDA_SAMPLE_TIME 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) -#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_S 0 - -/** I2C_SCL_HIGH_PERIOD_REG register - * Configures the high level width of SCL - */ -#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) -/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; - * Configures for how long SCL remains high in master mode. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_HIGH_PERIOD 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) -#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_S 0 -/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; - * Configures the SCL_FSM's waiting period for SCL high level in master mode. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 - -/** I2C_SCL_START_HOLD_REG register - * Configures the delay between the SDA and SCL negative edge for a start condition - */ -#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) -/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the falling edge of SDA and the falling edge of SCL for - * a START condition. - * Measurement unit: i2c_sclk. - */ -#define I2C_SCL_START_HOLD_TIME 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) -#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_S 0 - -/** I2C_SCL_RSTART_SETUP_REG register - * Configures the delay between the positive edge of SCL and the negative edge of SDA - */ -#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) -/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the positive edge of SCL and the negative edge of SDA - * for a RESTART condition. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_S 0 - -/** I2C_SCL_STOP_HOLD_REG register - * Configures the delay after the SCL clock edge for a stop condition - */ -#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) -/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; - * Configures the delay after the STOP condition. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) -#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_S 0 - -/** I2C_SCL_STOP_SETUP_REG register - * Configures the delay between the SDA and SCL rising edge for a stop condition. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) -/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the rising edge of SCL and the rising edge of SDA. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) -#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_S 0 - -/** I2C_FILTER_CFG_REG register - * SCL and SDA filter configuration register - */ -#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) -/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; - * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL - * input has smaller width than this register value, the I2C controller will ignore - * that pulse. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_FILTER_THRES 0x0000000FU -#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) -#define I2C_SCL_FILTER_THRES_V 0x0000000FU -#define I2C_SCL_FILTER_THRES_S 0 -/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; - * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA - * input has smaller width than this register value, the I2C controller will ignore - * that pulse. - * Measurement unit: i2c_sclk - */ -#define I2C_SDA_FILTER_THRES 0x0000000FU -#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) -#define I2C_SDA_FILTER_THRES_V 0x0000000FU -#define I2C_SDA_FILTER_THRES_S 4 -/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; - * Configures to enable the filter function for SCL. - */ -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) -#define I2C_SCL_FILTER_EN_V 0x00000001U -#define I2C_SCL_FILTER_EN_S 8 -/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; - * Configures to enable the filter function for SDA. - */ -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) -#define I2C_SDA_FILTER_EN_V 0x00000001U -#define I2C_SDA_FILTER_EN_S 9 - -/** I2C_COMD0_REG register - * I2C command register 0 - */ -#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) -/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. It consists of three parts: - * op_code is the command, - * 0: RSTART, - * 1: WRITE, - * 2: READ, - * 3: STOP, - * 4: END. - * - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more information. - */ -#define I2C_COMMAND0 0x00003FFFU -#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) -#define I2C_COMMAND0_V 0x00003FFFU -#define I2C_COMMAND0_S 0 -/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) -#define I2C_COMMAND0_DONE_V 0x00000001U -#define I2C_COMMAND0_DONE_S 31 - -/** I2C_COMD1_REG register - * I2C command register 1 - */ -#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) -/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; - * Configures command 1. See details in I2C_CMD0_REG[13:0]. - */ -#define I2C_COMMAND1 0x00003FFFU -#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) -#define I2C_COMMAND1_V 0x00003FFFU -#define I2C_COMMAND1_S 0 -/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 1 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) -#define I2C_COMMAND1_DONE_V 0x00000001U -#define I2C_COMMAND1_DONE_S 31 - -/** I2C_COMD2_REG register - * I2C command register 2 - */ -#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) -/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; - * Configures command 2. See details in I2C_CMD0_REG[13:0]. - */ -#define I2C_COMMAND2 0x00003FFFU -#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) -#define I2C_COMMAND2_V 0x00003FFFU -#define I2C_COMMAND2_S 0 -/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 2 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) -#define I2C_COMMAND2_DONE_V 0x00000001U -#define I2C_COMMAND2_DONE_S 31 - -/** I2C_COMD3_REG register - * I2C command register 3 - */ -#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) -/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; - * Configures command 3. See details in I2C_CMD0_REG[13:0]. - */ -#define I2C_COMMAND3 0x00003FFFU -#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) -#define I2C_COMMAND3_V 0x00003FFFU -#define I2C_COMMAND3_S 0 -/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 3 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) -#define I2C_COMMAND3_DONE_V 0x00000001U -#define I2C_COMMAND3_DONE_S 31 - -/** I2C_COMD4_REG register - * I2C command register 4 - */ -#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) -/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; - * Configures command 4. See details in I2C_CMD0_REG[13:0]. - */ -#define I2C_COMMAND4 0x00003FFFU -#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) -#define I2C_COMMAND4_V 0x00003FFFU -#define I2C_COMMAND4_S 0 -/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 4 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) -#define I2C_COMMAND4_DONE_V 0x00000001U -#define I2C_COMMAND4_DONE_S 31 - -/** I2C_COMD5_REG register - * I2C command register 5 - */ -#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) -/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; - * Configures command 5. See details in I2C_CMD0_REG[13:0]. - */ -#define I2C_COMMAND5 0x00003FFFU -#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) -#define I2C_COMMAND5_V 0x00003FFFU -#define I2C_COMMAND5_S 0 -/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 5 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) -#define I2C_COMMAND5_DONE_V 0x00000001U -#define I2C_COMMAND5_DONE_S 31 - -/** I2C_COMD6_REG register - * I2C command register 6 - */ -#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) -/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; - * Configures command 6. See details in I2C_CMD0_REG[13:0]. - */ -#define I2C_COMMAND6 0x00003FFFU -#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) -#define I2C_COMMAND6_V 0x00003FFFU -#define I2C_COMMAND6_S 0 -/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 6 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) -#define I2C_COMMAND6_DONE_V 0x00000001U -#define I2C_COMMAND6_DONE_S 31 - -/** I2C_COMD7_REG register - * I2C command register 7 - */ -#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) -/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; - * Configures command 7. See details in I2C_CMD0_REG[13:0]. - */ -#define I2C_COMMAND7 0x00003FFFU -#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) -#define I2C_COMMAND7_V 0x00003FFFU -#define I2C_COMMAND7_S 0 -/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 7 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) -#define I2C_COMMAND7_DONE_V 0x00000001U -#define I2C_COMMAND7_DONE_S 31 - -/** I2C_SCL_ST_TIME_OUT_REG register - * SCL status time out register - */ -#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) -/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; - * Configures the threshold value of SCL_FSM state unchanged period. It should be no - * more than 23. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_ST_TO_I2C 0x0000001FU -#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) -#define I2C_SCL_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_ST_TO_I2C_S 0 - -/** I2C_SCL_MAIN_ST_TIME_OUT_REG register - * SCL main status time out register - */ -#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) -/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; - * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be - * no more than 23. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) -#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_S 0 - -/** I2C_SCL_SP_CONF_REG register - * Power configuration register - */ -#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) -/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; - * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses - * equals to reg_scl_rst_slv_num[4:0]. - */ -#define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) -#define I2C_SCL_RST_SLV_EN_V 0x00000001U -#define I2C_SCL_RST_SLV_EN_S 0 -/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. - * Valid when reg_scl_rst_slv_en is 1. - * Measurement unit: i2c_sclk - */ -#define I2C_SCL_RST_SLV_NUM 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) -#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_S 1 -/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; - * Configures to power down the I2C output SCL line. - * 0: Not power down. - * - * 1: Power down. - * Valid only when reg_scl_force_out is 1. - */ -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) -#define I2C_SCL_PD_EN_V 0x00000001U -#define I2C_SCL_PD_EN_S 6 -/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; - * Configures to power down the I2C output SDA line. - * 0: Not power down. - * - * 1: Power down. - * Valid only when reg_sda_force_out is 1. - */ -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) -#define I2C_SDA_PD_EN_V 0x00000001U -#define I2C_SDA_PD_EN_S 7 - -/** I2C_SCL_STRETCH_CONF_REG register - * Set SCL stretch of I2C slave - */ -#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) -/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; - * Configures the time period to release the SCL line from stretching to avoid timing - * violation. Usually it should be larger than the SDA setup time. - * Measurement unit: i2c_sclk - */ -#define I2C_STRETCH_PROTECT_NUM 0x000003FFU -#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) -#define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU -#define I2C_STRETCH_PROTECT_NUM_S 0 -/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; - * Configures to enable slave SCL stretch function. - * 0: Disable - * - * 1: Enable - * The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and - * stretch event happens. The stretch cause can be seen in reg_stretch_cause. - */ -#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) -#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) -#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U -#define I2C_SLAVE_SCL_STRETCH_EN_S 10 -/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; - * Configures to clear the I2C slave SCL stretch function. - * 0: No effect - * - * 1: Clear - */ -#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) -#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) -#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U -#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 -/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; - * Configures to enable the function for slave to control ACK level. - * 0: Disable - * - * 1: Enable - */ -#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U -#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 -/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables. - * 0: Low level - * - * 1: High level - */ -#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) -#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) -#define I2C_SLAVE_BYTE_ACK_LVL_V 0x00000001U -#define I2C_SLAVE_BYTE_ACK_LVL_S 13 - -/** I2C_DATE_REG register - * Version register - */ -#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) -/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050; - * Version control register. - */ -#define I2C_DATE 0xFFFFFFFFU -#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) -#define I2C_DATE_V 0xFFFFFFFFU -#define I2C_DATE_S 0 - -/** I2C_TXFIFO_START_ADDR_REG register - * I2C TXFIFO base address register - */ -#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) -/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C txfifo first address. - */ -#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) -#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_S 0 - -/** I2C_RXFIFO_START_ADDR_REG register - * I2C RXFIFO base address register - */ -#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) -/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C rxfifo first address. - */ -#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) -#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/i2c_ext_struct.h b/components/soc/esp32p4/include/soc/i2c_ext_struct.h deleted file mode 100644 index eb8069be9c..0000000000 --- a/components/soc/esp32p4/include/soc/i2c_ext_struct.h +++ /dev/null @@ -1,1276 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Timing registers */ -/** Type of scl_low_period register - * Configures the low level width of the SCL Clock. - */ -typedef union { - struct { - /** scl_low_period : R/W; bitpos: [8:0]; default: 0; - * Configures the low level width of the SCL Clock. - * Measurement unit: i2c_sclk. - */ - uint32_t scl_low_period:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_low_period_reg_t; - -/** Type of sda_hold register - * Configures the hold time after a negative SCL edge. - */ -typedef union { - struct { - /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; - * Configures the time to hold the data after the falling edge of SCL. - * Measurement unit: i2c_sclk - */ - uint32_t sda_hold_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_sda_hold_reg_t; - -/** Type of sda_sample register - * Configures the sample time after a positive SCL edge. - */ -typedef union { - struct { - /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; - * Configures the sample time after a positive SCL edge. - * Measurement unit: i2c_sclk - */ - uint32_t sda_sample_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_sda_sample_reg_t; - -/** Type of scl_high_period register - * Configures the high level width of SCL - */ -typedef union { - struct { - /** scl_high_period : R/W; bitpos: [8:0]; default: 0; - * Configures for how long SCL remains high in master mode. - * Measurement unit: i2c_sclk - */ - uint32_t scl_high_period:9; - /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; - * Configures the SCL_FSM's waiting period for SCL high level in master mode. - * Measurement unit: i2c_sclk - */ - uint32_t scl_wait_high_period:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} i2c_scl_high_period_reg_t; - -/** Type of scl_start_hold register - * Configures the delay between the SDA and SCL negative edge for a start condition - */ -typedef union { - struct { - /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the falling edge of SDA and the falling edge of SCL for - * a START condition. - * Measurement unit: i2c_sclk. - */ - uint32_t scl_start_hold_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_start_hold_reg_t; - -/** Type of scl_rstart_setup register - * Configures the delay between the positive edge of SCL and the negative edge of SDA - */ -typedef union { - struct { - /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the positive edge of SCL and the negative edge of SDA - * for a RESTART condition. - * Measurement unit: i2c_sclk - */ - uint32_t scl_rstart_setup_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_rstart_setup_reg_t; - -/** Type of scl_stop_hold register - * Configures the delay after the SCL clock edge for a stop condition - */ -typedef union { - struct { - /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; - * Configures the delay after the STOP condition. - * Measurement unit: i2c_sclk - */ - uint32_t scl_stop_hold_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_stop_hold_reg_t; - -/** Type of scl_stop_setup register - * Configures the delay between the SDA and SCL rising edge for a stop condition. - * Measurement unit: i2c_sclk - */ -typedef union { - struct { - /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the rising edge of SCL and the rising edge of SDA. - * Measurement unit: i2c_sclk - */ - uint32_t scl_stop_setup_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_stop_setup_reg_t; - -/** Type of scl_st_time_out register - * SCL status time out register - */ -typedef union { - struct { - /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; - * Configures the threshold value of SCL_FSM state unchanged period. It should be no - * more than 23. - * Measurement unit: i2c_sclk - */ - uint32_t scl_st_to_i2c:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} i2c_scl_st_time_out_reg_t; - -/** Type of scl_main_st_time_out register - * SCL main status time out register - */ -typedef union { - struct { - /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; - * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be - * no more than 23. - * Measurement unit: i2c_sclk - */ - uint32_t scl_main_st_to_i2c:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} i2c_scl_main_st_time_out_reg_t; - - -/** Group: Configuration registers */ -/** Type of ctr register - * Transmission setting - */ -typedef union { - struct { - /** sda_force_out : R/W; bitpos: [0]; default: 0; - * Configures the SDA output mode - * 1: Direct output, - * - * 0: Open drain output. - */ - uint32_t sda_force_out:1; - /** scl_force_out : R/W; bitpos: [1]; default: 0; - * Configures the SCL output mode - * 1: Direct output, - * - * 0: Open drain output. - */ - uint32_t scl_force_out:1; - /** sample_scl_level : R/W; bitpos: [2]; default: 0; - * Configures the sample mode for SDA. - * 1: Sample SDA data on the SCL low level. - * - * 0: Sample SDA data on the SCL high level. - */ - uint32_t sample_scl_level:1; - /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; - * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has - * reached the threshold. - */ - uint32_t rx_full_ack_level:1; - /** ms_mode : R/W; bitpos: [4]; default: 0; - * Configures the module as an I2C Master or Slave. - * 0: Slave - * - * 1: Master - */ - uint32_t ms_mode:1; - /** trans_start : WT; bitpos: [5]; default: 0; - * Configures to start sending the data in txfifo for slave. - * 0: No effect - * - * 1: Start - */ - uint32_t trans_start:1; - /** tx_lsb_first : R/W; bitpos: [6]; default: 0; - * Configures to control the sending order for data needing to be sent. - * 1: send data from the least significant bit, - * - * 0: send data from the most significant bit. - */ - uint32_t tx_lsb_first:1; - /** rx_lsb_first : R/W; bitpos: [7]; default: 0; - * Configures to control the storage order for received data. - * 1: receive data from the least significant bit - * - * 0: receive data from the most significant bit. - */ - uint32_t rx_lsb_first:1; - /** clk_en : R/W; bitpos: [8]; default: 0; - * Configures whether to gate clock signal for registers. - * - * 0: Force clock on for registers - * - * 1: Support clock only when registers are read or written to by software. - */ - uint32_t clk_en:1; - /** arbitration_en : R/W; bitpos: [9]; default: 1; - * Configures to enable I2C bus arbitration detection. - * 0: No effect - * - * 1: Enable - */ - uint32_t arbitration_en:1; - /** fsm_rst : WT; bitpos: [10]; default: 0; - * Configures to reset the SCL_FSM. - * 0: No effect - * - * 1: Reset - */ - uint32_t fsm_rst:1; - /** conf_upgate : WT; bitpos: [11]; default: 0; - * Configures this bit for synchronization - * 0: No effect - * - * 1: Synchronize - */ - uint32_t conf_upgate:1; - /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; - * Configures to enable slave to send data automatically - * 0: Disable - * - * 1: Enable - */ - uint32_t slv_tx_auto_start_en:1; - /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; - * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. - * 0: Not check - * - * 1: Check - */ - uint32_t addr_10bit_rw_check_en:1; - /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; - * Configures to support the 7bit general call function. - * 0: Not support - * - * 1: Support - */ - uint32_t addr_broadcasting_en:1; - uint32_t reserved_15:17; - }; - uint32_t val; -} i2c_ctr_reg_t; - -/** Type of to register - * Setting time out control for receiving data. - */ -typedef union { - struct { - /** time_out_value : R/W; bitpos: [4:0]; default: 16; - * Configures the timeout threshold period for SCL stucking at high or low level. The - * actual period is 2^(reg_time_out_value). - * Measurement unit: i2c_sclk. - */ - uint32_t time_out_value:5; - /** time_out_en : R/W; bitpos: [5]; default: 0; - * Configures to enable time out control. - * 0: No effect - * - * 1: Enable - */ - uint32_t time_out_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} i2c_to_reg_t; - -/** Type of slave_addr register - * Local slave address setting - */ -typedef union { - struct { - /** slave_addr : R/W; bitpos: [14:0]; default: 0; - * Configure the slave address of I2C Slave. - */ - uint32_t slave_addr:15; - uint32_t reserved_15:16; - /** addr_10bit_en : R/W; bitpos: [31]; default: 0; - * Configures to enable the slave 10-bit addressing mode in master mode. - * 0: No effect - * - * 1: Enable - */ - uint32_t addr_10bit_en:1; - }; - uint32_t val; -} i2c_slave_addr_reg_t; - -/** Type of fifo_conf register - * FIFO configuration register. - */ -typedef union { - struct { - /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; - * Configures the water mark threshold of RXFIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than - * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. - */ - uint32_t rxfifo_wm_thrhd:5; - /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; - * Configures the water mark threshold of TXFIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than - * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. - */ - uint32_t txfifo_wm_thrhd:5; - /** nonfifo_en : R/W; bitpos: [10]; default: 0; - * Configures to enable APB nonfifo access. - */ - uint32_t nonfifo_en:1; - /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; - * Configures to enable double addressing mode. When this mode is enabled, the byte - * received after the I2C address byte represents the offset address in the I2C Slave - * RAM. - * 0: Disable - * - * 1: Enable - */ - uint32_t fifo_addr_cfg_en:1; - /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; - * Configures to reset RXFIFO. - * 0: No effect - * - * 1: Reset - */ - uint32_t rx_fifo_rst:1; - /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; - * Configures to reset TXFIFO. - * 0: No effect - * - * 1: Reset - */ - uint32_t tx_fifo_rst:1; - /** fifo_prt_en : R/W; bitpos: [14]; default: 1; - * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the - * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. - * 0: No effect - * - * 1: Enable - */ - uint32_t fifo_prt_en:1; - uint32_t reserved_15:17; - }; - uint32_t val; -} i2c_fifo_conf_reg_t; - -/** Type of filter_cfg register - * SCL and SDA filter configuration register - */ -typedef union { - struct { - /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; - * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL - * input has smaller width than this register value, the I2C controller will ignore - * that pulse. - * Measurement unit: i2c_sclk - */ - uint32_t scl_filter_thres:4; - /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; - * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA - * input has smaller width than this register value, the I2C controller will ignore - * that pulse. - * Measurement unit: i2c_sclk - */ - uint32_t sda_filter_thres:4; - /** scl_filter_en : R/W; bitpos: [8]; default: 1; - * Configures to enable the filter function for SCL. - */ - uint32_t scl_filter_en:1; - /** sda_filter_en : R/W; bitpos: [9]; default: 1; - * Configures to enable the filter function for SDA. - */ - uint32_t sda_filter_en:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} i2c_filter_cfg_reg_t; - -/** Type of scl_sp_conf register - * Power configuration register - */ -typedef union { - struct { - /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; - * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses - * equals to reg_scl_rst_slv_num[4:0]. - */ - uint32_t scl_rst_slv_en:1; - /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. - * Valid when reg_scl_rst_slv_en is 1. - * Measurement unit: i2c_sclk - */ - uint32_t scl_rst_slv_num:5; - /** scl_pd_en : R/W; bitpos: [6]; default: 0; - * Configures to power down the I2C output SCL line. - * 0: Not power down. - * - * 1: Power down. - * Valid only when reg_scl_force_out is 1. - */ - uint32_t scl_pd_en:1; - /** sda_pd_en : R/W; bitpos: [7]; default: 0; - * Configures to power down the I2C output SDA line. - * 0: Not power down. - * - * 1: Power down. - * Valid only when reg_sda_force_out is 1. - */ - uint32_t sda_pd_en:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} i2c_scl_sp_conf_reg_t; - -/** Type of scl_stretch_conf register - * Set SCL stretch of I2C slave - */ -typedef union { - struct { - /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; - * Configures the time period to release the SCL line from stretching to avoid timing - * violation. Usually it should be larger than the SDA setup time. - * Measurement unit: i2c_sclk - */ - uint32_t stretch_protect_num:10; - /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; - * Configures to enable slave SCL stretch function. - * 0: Disable - * - * 1: Enable - * The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and - * stretch event happens. The stretch cause can be seen in reg_stretch_cause. - */ - uint32_t slave_scl_stretch_en:1; - /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; - * Configures to clear the I2C slave SCL stretch function. - * 0: No effect - * - * 1: Clear - */ - uint32_t slave_scl_stretch_clr:1; - /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; - * Configures to enable the function for slave to control ACK level. - * 0: Disable - * - * 1: Enable - */ - uint32_t slave_byte_ack_ctl_en:1; - /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables. - * 0: Low level - * - * 1: High level - */ - uint32_t slave_byte_ack_lvl:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} i2c_scl_stretch_conf_reg_t; - - -/** Group: Status registers */ -/** Type of sr register - * Describe I2C work status. - */ -typedef union { - struct { - /** resp_rec : RO; bitpos: [0]; default: 0; - * Represents the received ACK value in master mode or slave mode. - * 0: ACK, - * - * 1: NACK. - */ - uint32_t resp_rec:1; - /** slave_rw : RO; bitpos: [1]; default: 0; - * Represents the transfer direction in slave mode,. - * 1: Master reads from slave, - * - * 0: Master writes to slave. - */ - uint32_t slave_rw:1; - uint32_t reserved_2:1; - /** arb_lost : RO; bitpos: [3]; default: 0; - * Represents whether the I2C controller loses control of SCL line. - * 0: No arbitration lost - * - * 1: Arbitration lost - */ - uint32_t arb_lost:1; - /** bus_busy : RO; bitpos: [4]; default: 0; - * Represents the I2C bus state. - * 1: The I2C bus is busy transferring data, - * - * 0: The I2C bus is in idle state. - */ - uint32_t bus_busy:1; - /** slave_addressed : RO; bitpos: [5]; default: 0; - * Represents whether the address sent by the master is equal to the address of the - * slave. - * Valid only when the module is configured as an I2C Slave. - * 0: Not equal - * - * 1: Equal - */ - uint32_t slave_addressed:1; - uint32_t reserved_6:2; - /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; - * Represents the number of data bytes to be sent. - */ - uint32_t rxfifo_cnt:6; - /** stretch_cause : RO; bitpos: [15:14]; default: 3; - * Represents the cause of SCL clocking stretching in slave mode. - * 0: Stretching SCL low when the master starts to read data. - * - * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. - * - * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. - */ - uint32_t stretch_cause:2; - uint32_t reserved_16:2; - /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; - * Represents the number of data bytes received in RAM. - */ - uint32_t txfifo_cnt:6; - /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; - * Represents the states of the I2C module state machine. - * 0: Idle, - * - * 1: Address shift, - * - * 2: ACK address, - * - * 3: Rx data, - * - * 4: Tx data, - * - * 5: Send ACK, - * - * 6: Wait ACK - */ - uint32_t scl_main_state_last:3; - uint32_t reserved_27:1; - /** scl_state_last : RO; bitpos: [30:28]; default: 0; - * Represents the states of the state machine used to produce SCL. - * 0: Idle, - * - * 1: Start, - * - * 2: Negative edge, - * - * 3: Low, - * - * 4: Positive edge, - * - * 5: High, - * - * 6: Stop - */ - uint32_t scl_state_last:3; - uint32_t reserved_31:1; - }; - uint32_t val; -} i2c_sr_reg_t; - -/** Type of fifo_st register - * FIFO status register. - */ -typedef union { - struct { - /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; - * Represents the offset address of the APB reading from RXFIFO - */ - uint32_t rxfifo_raddr:5; - /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; - * Represents the offset address of i2c module receiving data and writing to RXFIFO. - */ - uint32_t rxfifo_waddr:5; - /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; - * Represents the offset address of i2c module reading from TXFIFO. - */ - uint32_t txfifo_raddr:5; - /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; - * Represents the offset address of APB bus writing to TXFIFO. - */ - uint32_t txfifo_waddr:5; - uint32_t reserved_20:2; - /** slave_rw_point : RO; bitpos: [29:22]; default: 0; - * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in - * I2C slave mode. - */ - uint32_t slave_rw_point:8; - uint32_t reserved_30:2; - }; - uint32_t val; -} i2c_fifo_st_reg_t; - -/** Type of data register - * Rx FIFO read data. - */ -typedef union { - struct { - /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; - * Represents the value of RXFIFO read data. - */ - uint32_t fifo_rdata:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} i2c_data_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_raw register - * Raw interrupt status - */ -typedef union { - struct { - /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_raw:1; - /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_raw:1; - /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_raw:1; - /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_raw:1; - /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_raw:1; - /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_raw:1; - /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_raw:1; - /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_raw:1; - /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_raw:1; - /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt status of the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_raw:1; - /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_raw:1; - /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_raw:1; - /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_raw:1; - /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_raw:1; - /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_raw:1; - /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt status of I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_raw:1; - /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; - * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_raw:1; - /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; - * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_raw:1; - /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; - * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - */ - uint32_t slave_addr_unmatch_int_raw:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_raw_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_clr:1; - /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_clr:1; - /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_clr:1; - /** end_detect_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_clr:1; - /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_clr:1; - /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_clr:1; - /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_clr:1; - /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_clr:1; - /** time_out_int_clr : WT; bitpos: [8]; default: 0; - * Write 1 to clear the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_clr:1; - /** trans_start_int_clr : WT; bitpos: [9]; default: 0; - * Write 1 to clear the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_clr:1; - /** nack_int_clr : WT; bitpos: [10]; default: 0; - * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_clr:1; - /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; - * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_clr:1; - /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; - * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_clr:1; - /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; - * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_clr:1; - /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; - * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_clr:1; - /** det_start_int_clr : WT; bitpos: [15]; default: 0; - * Write 1 to clear I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_clr:1; - /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; - * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_clr:1; - /** general_call_int_clr : WT; bitpos: [17]; default: 0; - * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_clr:1; - /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; - * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - */ - uint32_t slave_addr_unmatch_int_clr:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_clr_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_ena:1; - /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_ena:1; - /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_ena:1; - /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_ena:1; - /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_ena:1; - /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_ena:1; - /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_ena:1; - /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_ena:1; - /** time_out_int_ena : R/W; bitpos: [8]; default: 0; - * Write 1 to enable the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_ena:1; - /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; - * Write 1 to enable the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_ena:1; - /** nack_int_ena : R/W; bitpos: [10]; default: 0; - * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_ena:1; - /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; - * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_ena:1; - /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; - * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_ena:1; - /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; - * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_ena:1; - /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; - * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_ena:1; - /** det_start_int_ena : R/W; bitpos: [15]; default: 0; - * Write 1 to enable I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_ena:1; - /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; - * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_ena:1; - /** general_call_int_ena : R/W; bitpos: [17]; default: 0; - * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_ena:1; - /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; - * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - */ - uint32_t slave_addr_unmatch_int_ena:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_ena_reg_t; - -/** Type of int_status register - * Status of captured I2C communication events - */ -typedef union { - struct { - /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_st:1; - /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_st:1; - /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_st:1; - /** end_detect_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_st:1; - /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_st:1; - /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_st:1; - /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_st:1; - /** trans_complete_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_st:1; - /** time_out_int_st : RO; bitpos: [8]; default: 0; - * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_st:1; - /** trans_start_int_st : RO; bitpos: [9]; default: 0; - * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_st:1; - /** nack_int_st : RO; bitpos: [10]; default: 0; - * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_st:1; - /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; - * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_st:1; - /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_st:1; - /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; - * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_st:1; - /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; - * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_st:1; - /** det_start_int_st : RO; bitpos: [15]; default: 0; - * The masked interrupt status status of I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_st:1; - /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; - * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_st:1; - /** general_call_int_st : RO; bitpos: [17]; default: 0; - * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_st:1; - /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; - * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - */ - uint32_t slave_addr_unmatch_int_st:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_status_reg_t; - - -/** Group: Command registers */ -/** Type of comd0 register - * I2C command register 0 - */ -typedef union { - struct { - /** command0 : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. It consists of three parts: - * op_code is the command, - * 0: RSTART, - * 1: WRITE, - * 2: READ, - * 3: STOP, - * 4: END. - * - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more information. - */ - uint32_t command0:14; - uint32_t reserved_14:17; - /** command0_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command0_done:1; - }; - uint32_t val; -} i2c_comd0_reg_t; - -/** Type of comd1 register - * I2C command register 1 - */ -typedef union { - struct { - /** command1 : R/W; bitpos: [13:0]; default: 0; - * Configures command 1. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command1:14; - uint32_t reserved_14:17; - /** command1_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 1 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command1_done:1; - }; - uint32_t val; -} i2c_comd1_reg_t; - -/** Type of comd2 register - * I2C command register 2 - */ -typedef union { - struct { - /** command2 : R/W; bitpos: [13:0]; default: 0; - * Configures command 2. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command2:14; - uint32_t reserved_14:17; - /** command2_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 2 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command2_done:1; - }; - uint32_t val; -} i2c_comd2_reg_t; - -/** Type of comd3 register - * I2C command register 3 - */ -typedef union { - struct { - /** command3 : R/W; bitpos: [13:0]; default: 0; - * Configures command 3. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command3:14; - uint32_t reserved_14:17; - /** command3_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 3 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command3_done:1; - }; - uint32_t val; -} i2c_comd3_reg_t; - -/** Type of comd4 register - * I2C command register 4 - */ -typedef union { - struct { - /** command4 : R/W; bitpos: [13:0]; default: 0; - * Configures command 4. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command4:14; - uint32_t reserved_14:17; - /** command4_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 4 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command4_done:1; - }; - uint32_t val; -} i2c_comd4_reg_t; - -/** Type of comd5 register - * I2C command register 5 - */ -typedef union { - struct { - /** command5 : R/W; bitpos: [13:0]; default: 0; - * Configures command 5. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command5:14; - uint32_t reserved_14:17; - /** command5_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 5 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command5_done:1; - }; - uint32_t val; -} i2c_comd5_reg_t; - -/** Type of comd6 register - * I2C command register 6 - */ -typedef union { - struct { - /** command6 : R/W; bitpos: [13:0]; default: 0; - * Configures command 6. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command6:14; - uint32_t reserved_14:17; - /** command6_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 6 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command6_done:1; - }; - uint32_t val; -} i2c_comd6_reg_t; - -/** Type of comd7 register - * I2C command register 7 - */ -typedef union { - struct { - /** command7 : R/W; bitpos: [13:0]; default: 0; - * Configures command 7. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command7:14; - uint32_t reserved_14:17; - /** command7_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 7 is done in I2C Master mode. - * 0: Not done - * - * 1: Done - */ - uint32_t command7_done:1; - }; - uint32_t val; -} i2c_comd7_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 35656050; - * Version control register. - */ - uint32_t date:32; - }; - uint32_t val; -} i2c_date_reg_t; - - -/** Group: Address register */ -/** Type of txfifo_start_addr register - * I2C TXFIFO base address register - */ -typedef union { - struct { - /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C txfifo first address. - */ - uint32_t txfifo_start_addr:32; - }; - uint32_t val; -} i2c_txfifo_start_addr_reg_t; - -/** Type of rxfifo_start_addr register - * I2C RXFIFO base address register - */ -typedef union { - struct { - /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C rxfifo first address. - */ - uint32_t rxfifo_start_addr:32; - }; - uint32_t val; -} i2c_rxfifo_start_addr_reg_t; - - -typedef struct { - volatile i2c_scl_low_period_reg_t scl_low_period; - volatile i2c_ctr_reg_t ctr; - volatile i2c_sr_reg_t sr; - volatile i2c_to_reg_t to; - volatile i2c_slave_addr_reg_t slave_addr; - volatile i2c_fifo_st_reg_t fifo_st; - volatile i2c_fifo_conf_reg_t fifo_conf; - volatile i2c_data_reg_t data; - volatile i2c_int_raw_reg_t int_raw; - volatile i2c_int_clr_reg_t int_clr; - volatile i2c_int_ena_reg_t int_ena; - volatile i2c_int_status_reg_t int_status; - volatile i2c_sda_hold_reg_t sda_hold; - volatile i2c_sda_sample_reg_t sda_sample; - volatile i2c_scl_high_period_reg_t scl_high_period; - uint32_t reserved_03c; - volatile i2c_scl_start_hold_reg_t scl_start_hold; - volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; - volatile i2c_scl_stop_hold_reg_t scl_stop_hold; - volatile i2c_scl_stop_setup_reg_t scl_stop_setup; - volatile i2c_filter_cfg_reg_t filter_cfg; - uint32_t reserved_054; - volatile i2c_comd0_reg_t comd0; - volatile i2c_comd1_reg_t comd1; - volatile i2c_comd2_reg_t comd2; - volatile i2c_comd3_reg_t comd3; - volatile i2c_comd4_reg_t comd4; - volatile i2c_comd5_reg_t comd5; - volatile i2c_comd6_reg_t comd6; - volatile i2c_comd7_reg_t comd7; - volatile i2c_scl_st_time_out_reg_t scl_st_time_out; - volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; - volatile i2c_scl_sp_conf_reg_t scl_sp_conf; - volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; - uint32_t reserved_088[28]; - volatile i2c_date_reg_t date; - uint32_t reserved_0fc; - volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; - uint32_t reserved_104[31]; - volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; -} i2c_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h index 98a17b234a..ac0b5a9ad3 100644 --- a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp32p4/include/soc/interrupt_core0_reg.h @@ -1,1094 +1,1624 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_INTERRUPT_CORE0_REG_H_ -#define _SOC_INTERRUPT_CORE0_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) -/* INTERRUPT_CORE0_LP_RTC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_RTC_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_RTC_INT_MAP_M ((INTERRUPT_CORE0_LP_RTC_INT_MAP_V)<<(INTERRUPT_CORE0_LP_RTC_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_RTC_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_RTC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +/** INTERRUPT_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_RTC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_INT_MAP_M (CORE0_LP_RTC_INT_MAP_V << CORE0_LP_RTC_INT_MAP_S) +#define INTERRUPT_CORE0_LP_RTC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_RTC_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) -/* INTERRUPT_CORE0_LP_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_WDT_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_WDT_INT_MAP_M ((INTERRUPT_CORE0_LP_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_LP_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_WDT_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +/** INTERRUPT_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INT_MAP_M (CORE0_LP_WDT_INT_MAP_V << CORE0_LP_WDT_INT_MAP_S) +#define INTERRUPT_CORE0_LP_WDT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) -/* INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_M ((INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +/** INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_M (CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_LP_TIMER_REG_0_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC) -/* INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_M ((INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +/** INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_M (CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_LP_TIMER_REG_1_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_S 0 -#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) -/* INTERRUPT_CORE0_MB_HP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_MB_HP_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_MB_HP_INT_MAP_M ((INTERRUPT_CORE0_MB_HP_INT_MAP_V)<<(INTERRUPT_CORE0_MB_HP_INT_MAP_S)) -#define INTERRUPT_CORE0_MB_HP_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_MB_HP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +/** INTERRUPT_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_MB_HP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_MB_HP_INT_MAP_M (CORE0_MB_HP_INT_MAP_V << CORE0_MB_HP_INT_MAP_S) +#define INTERRUPT_CORE0_MB_HP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MB_HP_INT_MAP_S 0 -#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) -/* INTERRUPT_CORE0_MB_LP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_MB_LP_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_MB_LP_INT_MAP_M ((INTERRUPT_CORE0_MB_LP_INT_MAP_V)<<(INTERRUPT_CORE0_MB_LP_INT_MAP_S)) -#define INTERRUPT_CORE0_MB_LP_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_MB_LP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +/** INTERRUPT_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_MB_LP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_MB_LP_INT_MAP_M (CORE0_MB_LP_INT_MAP_V << CORE0_MB_LP_INT_MAP_S) +#define INTERRUPT_CORE0_MB_LP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MB_LP_INT_MAP_S 0 -#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) -/* INTERRUPT_CORE0_PMU_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_M ((INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V)<<(INTERRUPT_CORE0_PMU_REG_0_INT_MAP_S)) -#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +/** INTERRUPT_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_M (CORE0_PMU_REG_0_INT_MAP_V << CORE0_PMU_REG_0_INT_MAP_S) +#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_S 0 -#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C) -/* INTERRUPT_CORE0_PMU_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_M ((INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V)<<(INTERRUPT_CORE0_PMU_REG_1_INT_MAP_S)) -#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +/** INTERRUPT_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_M (CORE0_PMU_REG_1_INT_MAP_V << CORE0_PMU_REG_1_INT_MAP_S) +#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) -/* INTERRUPT_CORE0_LP_ANAPERI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_M ((INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V)<<(INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +/** INTERRUPT_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_M (CORE0_LP_ANAPERI_INT_MAP_V << CORE0_LP_ANAPERI_INT_MAP_S) +#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) -/* INTERRUPT_CORE0_LP_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_ADC_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_ADC_INT_MAP_M ((INTERRUPT_CORE0_LP_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_LP_ADC_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_ADC_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +/** INTERRUPT_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_ADC_INT_MAP_M (CORE0_LP_ADC_INT_MAP_V << CORE0_LP_ADC_INT_MAP_S) +#define INTERRUPT_CORE0_LP_ADC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_ADC_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) -/* INTERRUPT_CORE0_LP_GPIO_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_GPIO_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_M ((INTERRUPT_CORE0_LP_GPIO_INT_MAP_V)<<(INTERRUPT_CORE0_LP_GPIO_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +/** INTERRUPT_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_M (CORE0_LP_GPIO_INT_MAP_V << CORE0_LP_GPIO_INT_MAP_S) +#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_GPIO_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2C) -/* INTERRUPT_CORE0_LP_I2C_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_I2C_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_I2C_INT_MAP_M ((INTERRUPT_CORE0_LP_I2C_INT_MAP_V)<<(INTERRUPT_CORE0_LP_I2C_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_I2C_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_I2C_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +/** INTERRUPT_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_I2C_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_I2C_INT_MAP_M (CORE0_LP_I2C_INT_MAP_V << CORE0_LP_I2C_INT_MAP_S) +#define INTERRUPT_CORE0_LP_I2C_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_I2C_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) -/* INTERRUPT_CORE0_LP_I2S_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_I2S_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_I2S_INT_MAP_M ((INTERRUPT_CORE0_LP_I2S_INT_MAP_V)<<(INTERRUPT_CORE0_LP_I2S_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_I2S_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_I2S_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +/** INTERRUPT_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_I2S_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_I2S_INT_MAP_M (CORE0_LP_I2S_INT_MAP_V << CORE0_LP_I2S_INT_MAP_S) +#define INTERRUPT_CORE0_LP_I2S_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_I2S_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) -/* INTERRUPT_CORE0_LP_SPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_SPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_SPI_INT_MAP_M ((INTERRUPT_CORE0_LP_SPI_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SPI_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_SPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_SPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +/** INTERRUPT_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_SPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_SPI_INT_MAP_M (CORE0_LP_SPI_INT_MAP_V << CORE0_LP_SPI_INT_MAP_S) +#define INTERRUPT_CORE0_LP_SPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_SPI_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) -/* INTERRUPT_CORE0_LP_TOUCH_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_M ((INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TOUCH_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +/** INTERRUPT_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_M (CORE0_LP_TOUCH_INT_MAP_V << CORE0_LP_TOUCH_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3C) -/* INTERRUPT_CORE0_LP_TSENS_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_TSENS_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_M ((INTERRUPT_CORE0_LP_TSENS_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TSENS_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +/** INTERRUPT_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_M (CORE0_LP_TSENS_INT_MAP_V << CORE0_LP_TSENS_INT_MAP_S) +#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_TSENS_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) -/* INTERRUPT_CORE0_LP_UART_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_UART_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_UART_INT_MAP_M ((INTERRUPT_CORE0_LP_UART_INT_MAP_V)<<(INTERRUPT_CORE0_LP_UART_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_UART_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_UART_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +/** INTERRUPT_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_UART_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_UART_INT_MAP_M (CORE0_LP_UART_INT_MAP_V << CORE0_LP_UART_INT_MAP_S) +#define INTERRUPT_CORE0_LP_UART_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_UART_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) -/* INTERRUPT_CORE0_LP_EFUSE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_LP_EFUSE_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +/** INTERRUPT_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_M (CORE0_LP_EFUSE_INT_MAP_V << CORE0_LP_EFUSE_INT_MAP_S) +#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) -/* INTERRUPT_CORE0_LP_SW_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_SW_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_SW_INT_MAP_M ((INTERRUPT_CORE0_LP_SW_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SW_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_SW_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_SW_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +/** INTERRUPT_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_SW_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_SW_INT_MAP_M (CORE0_LP_SW_INT_MAP_V << CORE0_LP_SW_INT_MAP_S) +#define INTERRUPT_CORE0_LP_SW_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_SW_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4C) -/* INTERRUPT_CORE0_LP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_M ((INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE0_LP_SYSREG_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +/** INTERRUPT_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_M (CORE0_LP_SYSREG_INT_MAP_V << CORE0_LP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_S 0 -#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) -/* INTERRUPT_CORE0_LP_HUK_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LP_HUK_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LP_HUK_INT_MAP_M ((INTERRUPT_CORE0_LP_HUK_INT_MAP_V)<<(INTERRUPT_CORE0_LP_HUK_INT_MAP_S)) -#define INTERRUPT_CORE0_LP_HUK_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LP_HUK_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +/** INTERRUPT_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LP_HUK_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_HUK_INT_MAP_M (CORE0_LP_HUK_INT_MAP_V << CORE0_LP_HUK_INT_MAP_S) +#define INTERRUPT_CORE0_LP_HUK_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_HUK_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) -/* INTERRUPT_CORE0_SYS_ICM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SYS_ICM_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_M ((INTERRUPT_CORE0_SYS_ICM_INT_MAP_V)<<(INTERRUPT_CORE0_SYS_ICM_INT_MAP_S)) -#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +/** INTERRUPT_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_M (CORE0_SYS_ICM_INT_MAP_V << CORE0_SYS_ICM_INT_MAP_S) +#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYS_ICM_INT_MAP_S 0 -#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) -/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S)) -#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +/** INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M (CORE0_USB_DEVICE_INT_MAP_V << CORE0_USB_DEVICE_INT_MAP_S) +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S 0 -#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5C) -/* INTERRUPT_CORE0_SDIO_HOST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_M ((INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V)<<(INTERRUPT_CORE0_SDIO_HOST_INT_MAP_S)) -#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +/** INTERRUPT_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_M (CORE0_SDIO_HOST_INT_MAP_V << CORE0_SDIO_HOST_INT_MAP_S) +#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_S 0 -#define INTERRUPT_CORE0_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) -/* INTERRUPT_CORE0_GDMA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_GDMA_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_GDMA_INT_MAP_M ((INTERRUPT_CORE0_GDMA_INT_MAP_V)<<(INTERRUPT_CORE0_GDMA_INT_MAP_S)) -#define INTERRUPT_CORE0_GDMA_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_GDMA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +/** INTERRUPT_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GDMA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_GDMA_INT_MAP_M (CORE0_GDMA_INT_MAP_V << CORE0_GDMA_INT_MAP_S) +#define INTERRUPT_CORE0_GDMA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GDMA_INT_MAP_S 0 -#define INTERRUPT_CORE0_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) -/* INTERRUPT_CORE0_SPI2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SPI2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SPI2_INT_MAP_M ((INTERRUPT_CORE0_SPI2_INT_MAP_V)<<(INTERRUPT_CORE0_SPI2_INT_MAP_S)) -#define INTERRUPT_CORE0_SPI2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SPI2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +/** INTERRUPT_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SPI2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SPI2_INT_MAP_M (CORE0_SPI2_INT_MAP_V << CORE0_SPI2_INT_MAP_S) +#define INTERRUPT_CORE0_SPI2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SPI2_INT_MAP_S 0 -#define INTERRUPT_CORE0_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) -/* INTERRUPT_CORE0_SPI3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SPI3_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SPI3_INT_MAP_M ((INTERRUPT_CORE0_SPI3_INT_MAP_V)<<(INTERRUPT_CORE0_SPI3_INT_MAP_S)) -#define INTERRUPT_CORE0_SPI3_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SPI3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +/** INTERRUPT_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SPI3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SPI3_INT_MAP_M (CORE0_SPI3_INT_MAP_V << CORE0_SPI3_INT_MAP_S) +#define INTERRUPT_CORE0_SPI3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SPI3_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6C) -/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_I2S0_INT_MAP_M ((INTERRUPT_CORE0_I2S0_INT_MAP_V)<<(INTERRUPT_CORE0_I2S0_INT_MAP_S)) -#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_I2S0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +/** INTERRUPT_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S0_INT_MAP_M (CORE0_I2S0_INT_MAP_V << CORE0_I2S0_INT_MAP_S) +#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2S0_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) -/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S)) -#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_I2S1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +/** INTERRUPT_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INT_MAP_M (CORE0_I2S1_INT_MAP_V << CORE0_I2S1_INT_MAP_S) +#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) -/* INTERRUPT_CORE0_I2S2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_I2S2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_I2S2_INT_MAP_M ((INTERRUPT_CORE0_I2S2_INT_MAP_V)<<(INTERRUPT_CORE0_I2S2_INT_MAP_S)) -#define INTERRUPT_CORE0_I2S2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_I2S2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +/** INTERRUPT_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2S2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S2_INT_MAP_M (CORE0_I2S2_INT_MAP_V << CORE0_I2S2_INT_MAP_S) +#define INTERRUPT_CORE0_I2S2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2S2_INT_MAP_S 0 -#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) -/* INTERRUPT_CORE0_UHCI0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_UHCI0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_UHCI0_INT_MAP_M ((INTERRUPT_CORE0_UHCI0_INT_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INT_MAP_S)) -#define INTERRUPT_CORE0_UHCI0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_UHCI0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +/** INTERRUPT_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UHCI0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INT_MAP_M (CORE0_UHCI0_INT_MAP_V << CORE0_UHCI0_INT_MAP_S) +#define INTERRUPT_CORE0_UHCI0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UHCI0_INT_MAP_S 0 -#define INTERRUPT_CORE0_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7C) -/* INTERRUPT_CORE0_UART0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_UART0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_UART0_INT_MAP_M ((INTERRUPT_CORE0_UART0_INT_MAP_V)<<(INTERRUPT_CORE0_UART0_INT_MAP_S)) -#define INTERRUPT_CORE0_UART0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_UART0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +/** INTERRUPT_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART0_INT_MAP_M (CORE0_UART0_INT_MAP_V << CORE0_UART0_INT_MAP_S) +#define INTERRUPT_CORE0_UART0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART0_INT_MAP_S 0 -#define INTERRUPT_CORE0_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) -/* INTERRUPT_CORE0_UART1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_UART1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_UART1_INT_MAP_M ((INTERRUPT_CORE0_UART1_INT_MAP_V)<<(INTERRUPT_CORE0_UART1_INT_MAP_S)) -#define INTERRUPT_CORE0_UART1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_UART1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +/** INTERRUPT_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART1_INT_MAP_M (CORE0_UART1_INT_MAP_V << CORE0_UART1_INT_MAP_S) +#define INTERRUPT_CORE0_UART1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART1_INT_MAP_S 0 -#define INTERRUPT_CORE0_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) -/* INTERRUPT_CORE0_UART2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_UART2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_UART2_INT_MAP_M ((INTERRUPT_CORE0_UART2_INT_MAP_V)<<(INTERRUPT_CORE0_UART2_INT_MAP_S)) -#define INTERRUPT_CORE0_UART2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_UART2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +/** INTERRUPT_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART2_INT_MAP_M (CORE0_UART2_INT_MAP_V << CORE0_UART2_INT_MAP_S) +#define INTERRUPT_CORE0_UART2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART2_INT_MAP_S 0 -#define INTERRUPT_CORE0_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) -/* INTERRUPT_CORE0_UART3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_UART3_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_UART3_INT_MAP_M ((INTERRUPT_CORE0_UART3_INT_MAP_V)<<(INTERRUPT_CORE0_UART3_INT_MAP_S)) -#define INTERRUPT_CORE0_UART3_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_UART3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +/** INTERRUPT_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART3_INT_MAP_M (CORE0_UART3_INT_MAP_V << CORE0_UART3_INT_MAP_S) +#define INTERRUPT_CORE0_UART3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART3_INT_MAP_S 0 -#define INTERRUPT_CORE0_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8C) -/* INTERRUPT_CORE0_UART4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_UART4_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_UART4_INT_MAP_M ((INTERRUPT_CORE0_UART4_INT_MAP_V)<<(INTERRUPT_CORE0_UART4_INT_MAP_S)) -#define INTERRUPT_CORE0_UART4_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_UART4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +/** INTERRUPT_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_UART4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART4_INT_MAP_M (CORE0_UART4_INT_MAP_V << CORE0_UART4_INT_MAP_S) +#define INTERRUPT_CORE0_UART4_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART4_INT_MAP_S 0 -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) -/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE0_LCD_CAM_INT_MAP_S)) -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +/** INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M (CORE0_LCD_CAM_INT_MAP_V << CORE0_LCD_CAM_INT_MAP_S) +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S 0 -#define INTERRUPT_CORE0_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) -/* INTERRUPT_CORE0_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_ADC_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_ADC_INT_MAP_M ((INTERRUPT_CORE0_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_ADC_INT_MAP_S)) -#define INTERRUPT_CORE0_ADC_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +/** INTERRUPT_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ADC_INT_MAP_M (CORE0_ADC_INT_MAP_V << CORE0_ADC_INT_MAP_S) +#define INTERRUPT_CORE0_ADC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ADC_INT_MAP_S 0 -#define INTERRUPT_CORE0_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) -/* INTERRUPT_CORE0_PWM0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PWM0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PWM0_INT_MAP_M ((INTERRUPT_CORE0_PWM0_INT_MAP_V)<<(INTERRUPT_CORE0_PWM0_INT_MAP_S)) -#define INTERRUPT_CORE0_PWM0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PWM0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +/** INTERRUPT_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PWM0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM0_INT_MAP_M (CORE0_PWM0_INT_MAP_V << CORE0_PWM0_INT_MAP_S) +#define INTERRUPT_CORE0_PWM0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PWM0_INT_MAP_S 0 -#define INTERRUPT_CORE0_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9C) -/* INTERRUPT_CORE0_PWM1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PWM1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PWM1_INT_MAP_M ((INTERRUPT_CORE0_PWM1_INT_MAP_V)<<(INTERRUPT_CORE0_PWM1_INT_MAP_S)) -#define INTERRUPT_CORE0_PWM1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PWM1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +/** INTERRUPT_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PWM1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM1_INT_MAP_M (CORE0_PWM1_INT_MAP_V << CORE0_PWM1_INT_MAP_S) +#define INTERRUPT_CORE0_PWM1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PWM1_INT_MAP_S 0 -#define INTERRUPT_CORE0_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA0) -/* INTERRUPT_CORE0_CAN0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CAN0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_CAN0_INT_MAP_M ((INTERRUPT_CORE0_CAN0_INT_MAP_V)<<(INTERRUPT_CORE0_CAN0_INT_MAP_S)) -#define INTERRUPT_CORE0_CAN0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_CAN0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +/** INTERRUPT_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CAN0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INT_MAP_M (CORE0_CAN0_INT_MAP_V << CORE0_CAN0_INT_MAP_S) +#define INTERRUPT_CORE0_CAN0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CAN0_INT_MAP_S 0 -#define INTERRUPT_CORE0_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA4) -/* INTERRUPT_CORE0_CAN1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CAN1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_CAN1_INT_MAP_M ((INTERRUPT_CORE0_CAN1_INT_MAP_V)<<(INTERRUPT_CORE0_CAN1_INT_MAP_S)) -#define INTERRUPT_CORE0_CAN1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_CAN1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +/** INTERRUPT_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CAN1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN1_INT_MAP_M (CORE0_CAN1_INT_MAP_V << CORE0_CAN1_INT_MAP_S) +#define INTERRUPT_CORE0_CAN1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CAN1_INT_MAP_S 0 -#define INTERRUPT_CORE0_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA8) -/* INTERRUPT_CORE0_CAN2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CAN2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_CAN2_INT_MAP_M ((INTERRUPT_CORE0_CAN2_INT_MAP_V)<<(INTERRUPT_CORE0_CAN2_INT_MAP_S)) -#define INTERRUPT_CORE0_CAN2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_CAN2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +/** INTERRUPT_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CAN2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN2_INT_MAP_M (CORE0_CAN2_INT_MAP_V << CORE0_CAN2_INT_MAP_S) +#define INTERRUPT_CORE0_CAN2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CAN2_INT_MAP_S 0 -#define INTERRUPT_CORE0_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xAC) -/* INTERRUPT_CORE0_RMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_RMT_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_RMT_INT_MAP_M ((INTERRUPT_CORE0_RMT_INT_MAP_V)<<(INTERRUPT_CORE0_RMT_INT_MAP_S)) -#define INTERRUPT_CORE0_RMT_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_RMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +/** INTERRUPT_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_RMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_RMT_INT_MAP_M (CORE0_RMT_INT_MAP_V << CORE0_RMT_INT_MAP_S) +#define INTERRUPT_CORE0_RMT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_RMT_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB0) -/* INTERRUPT_CORE0_I2C0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_I2C0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_I2C0_INT_MAP_M ((INTERRUPT_CORE0_I2C0_INT_MAP_V)<<(INTERRUPT_CORE0_I2C0_INT_MAP_S)) -#define INTERRUPT_CORE0_I2C0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_I2C0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +/** INTERRUPT_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2C0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C0_INT_MAP_M (CORE0_I2C0_INT_MAP_V << CORE0_I2C0_INT_MAP_S) +#define INTERRUPT_CORE0_I2C0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C0_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB4) -/* INTERRUPT_CORE0_I2C1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_I2C1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_I2C1_INT_MAP_M ((INTERRUPT_CORE0_I2C1_INT_MAP_V)<<(INTERRUPT_CORE0_I2C1_INT_MAP_S)) -#define INTERRUPT_CORE0_I2C1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_I2C1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +/** INTERRUPT_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I2C1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C1_INT_MAP_M (CORE0_I2C1_INT_MAP_V << CORE0_I2C1_INT_MAP_S) +#define INTERRUPT_CORE0_I2C1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C1_INT_MAP_S 0 -#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB8) -/* INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_M ((INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +/** INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_M (CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_TIMERGRP0_T0_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_S 0 -#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xBC) -/* INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_M ((INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_S)) -#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +/** INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_M (CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_TIMERGRP0_T1_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_S 0 -#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC0) -/* INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_M ((INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +/** INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_M (CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_TIMERGRP0_WDT_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC4) -/* INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_M ((INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +/** INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_M (CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_TIMERGRP1_T0_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_S 0 -#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC8) -/* INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_M ((INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_S)) -#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +/** INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_M (CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_TIMERGRP1_T1_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_S 0 -#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xCC) -/* INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +/** INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_M (CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_TIMERGRP1_WDT_INT_MAP_S) +#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD0) -/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S)) -#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LEDC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +/** INTERRUPT_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INT_MAP_M (CORE0_LEDC_INT_MAP_V << CORE0_LEDC_INT_MAP_S) +#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD4) -/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M (CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD8) -/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M (CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xDC) -/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M (CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE0) -/* INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M (CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_AHB_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE4) -/* INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M (CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_AHB_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE8) -/* INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M (CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_AHB_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xEC) -/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M (CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF0) -/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M (CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF4) -/* INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M (CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF8) -/* INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M (CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_AXI_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xFC) -/* INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M (CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_AXI_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) -/* INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M (CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_AXI_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) -/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M (CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) -/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M (CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) -/* INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) +/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M (CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) -/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S)) -#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_RSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/** INTERRUPT_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_RSA_INT_MAP_M (CORE0_RSA_INT_MAP_V << CORE0_RSA_INT_MAP_S) +#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_RSA_INT_MAP_S 0 -#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) -/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_AES_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S)) -#define INTERRUPT_CORE0_AES_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_AES_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/** INTERRUPT_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_AES_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_AES_INT_MAP_M (CORE0_AES_INT_MAP_V << CORE0_AES_INT_MAP_S) +#define INTERRUPT_CORE0_AES_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_AES_INT_MAP_S 0 -#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) -/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S)) -#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SHA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/** INTERRUPT_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SHA_INT_MAP_M (CORE0_SHA_INT_MAP_V << CORE0_SHA_INT_MAP_S) +#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SHA_INT_MAP_S 0 -#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) -/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_ECC_INT_MAP_M ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S)) -#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_ECC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) +/** INTERRUPT_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECC_INT_MAP_M (CORE0_ECC_INT_MAP_V << CORE0_ECC_INT_MAP_S) +#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECC_INT_MAP_S 0 -#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) -/* INTERRUPT_CORE0_ECDSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_ECDSA_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_ECDSA_INT_MAP_M ((INTERRUPT_CORE0_ECDSA_INT_MAP_V)<<(INTERRUPT_CORE0_ECDSA_INT_MAP_S)) -#define INTERRUPT_CORE0_ECDSA_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_ECDSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/** INTERRUPT_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ECDSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INT_MAP_M (CORE0_ECDSA_INT_MAP_V << CORE0_ECDSA_INT_MAP_S) +#define INTERRUPT_CORE0_ECDSA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECDSA_INT_MAP_S 0 -#define INTERRUPT_CORE0_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) -/* INTERRUPT_CORE0_KM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_KM_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_KM_INT_MAP_M ((INTERRUPT_CORE0_KM_INT_MAP_V)<<(INTERRUPT_CORE0_KM_INT_MAP_S)) -#define INTERRUPT_CORE0_KM_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_KM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/** INTERRUPT_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_KM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_KM_INT_MAP_M (CORE0_KM_INT_MAP_V << CORE0_KM_INT_MAP_S) +#define INTERRUPT_CORE0_KM_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_KM_INT_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) -/* INTERRUPT_CORE0_GPIO_INT0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_GPIO_INT0_MAP 0x0000003F -#define INTERRUPT_CORE0_GPIO_INT0_MAP_M ((INTERRUPT_CORE0_GPIO_INT0_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT0_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INT0_MAP_V 0x3F +/** INTERRUPT_CORE0_GPIO_INT0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/** INTERRUPT_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT0_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT0_MAP_M (CORE0_GPIO_INT0_MAP_V << CORE0_GPIO_INT0_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT0_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INT0_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) -/* INTERRUPT_CORE0_GPIO_INT1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_GPIO_INT1_MAP 0x0000003F -#define INTERRUPT_CORE0_GPIO_INT1_MAP_M ((INTERRUPT_CORE0_GPIO_INT1_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT1_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INT1_MAP_V 0x3F +/** INTERRUPT_CORE0_GPIO_INT1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) +/** INTERRUPT_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT1_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT1_MAP_M (CORE0_GPIO_INT1_MAP_V << CORE0_GPIO_INT1_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT1_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INT1_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) -/* INTERRUPT_CORE0_GPIO_INT2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_GPIO_INT2_MAP 0x0000003F -#define INTERRUPT_CORE0_GPIO_INT2_MAP_M ((INTERRUPT_CORE0_GPIO_INT2_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT2_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INT2_MAP_V 0x3F +/** INTERRUPT_CORE0_GPIO_INT2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/** INTERRUPT_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT2_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT2_MAP_M (CORE0_GPIO_INT2_MAP_V << CORE0_GPIO_INT2_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT2_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INT2_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) -/* INTERRUPT_CORE0_GPIO_INT3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_GPIO_INT3_MAP 0x0000003F -#define INTERRUPT_CORE0_GPIO_INT3_MAP_M ((INTERRUPT_CORE0_GPIO_INT3_MAP_V)<<(INTERRUPT_CORE0_GPIO_INT3_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INT3_MAP_V 0x3F +/** INTERRUPT_CORE0_GPIO_INT3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/** INTERRUPT_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_INT3_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INT3_MAP_M (CORE0_GPIO_INT3_MAP_V << CORE0_GPIO_INT3_MAP_S) +#define INTERRUPT_CORE0_GPIO_INT3_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INT3_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) -/* INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_M ((INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V)<<(INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_S)) -#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/** INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_M (CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_GPIO_PAD_COMP_INT_MAP_S) +#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) -/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP 0x0000003F -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_S)) -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V 0x3F +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_M (CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CPU_INT_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) -/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP 0x0000003F -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_S)) -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V 0x3F +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_M (CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CPU_INT_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) -/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP 0x0000003F -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_S)) -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V 0x3F +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_M (CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CPU_INT_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) -/* INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP 0x0000003F -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_S)) -#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V 0x3F +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/** INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_M (CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CPU_INT_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_S 0 -#define INTERRUPT_CORE0_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) -/* INTERRUPT_CORE0_CACHE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CACHE_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_CACHE_INT_MAP_M ((INTERRUPT_CORE0_CACHE_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_CACHE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) +/** INTERRUPT_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CACHE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INT_MAP_M (CORE0_CACHE_INT_MAP_V << CORE0_CACHE_INT_MAP_S) +#define INTERRUPT_CORE0_CACHE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CACHE_INT_MAP_S 0 -#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) -/* INTERRUPT_CORE0_FLASH_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_M ((INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V)<<(INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_S)) -#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/** INTERRUPT_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_M (CORE0_FLASH_MSPI_INT_MAP_V << CORE0_FLASH_MSPI_INT_MAP_S) +#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_S 0 -#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) -/* INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_M ((INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_S)) -#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/** INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_M (CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_S 0 -#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) -/* INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_M ((INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_S)) -#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/** INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_M (CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_DSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_S 0 -#define INTERRUPT_CORE0_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) -/* INTERRUPT_CORE0_CSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CSI_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_CSI_INT_MAP_M ((INTERRUPT_CORE0_CSI_INT_MAP_V)<<(INTERRUPT_CORE0_CSI_INT_MAP_S)) -#define INTERRUPT_CORE0_CSI_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_CSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) +/** INTERRUPT_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CSI_INT_MAP_M (CORE0_CSI_INT_MAP_V << CORE0_CSI_INT_MAP_S) +#define INTERRUPT_CORE0_CSI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CSI_INT_MAP_S 0 -#define INTERRUPT_CORE0_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) -/* INTERRUPT_CORE0_DSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_DSI_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_DSI_INT_MAP_M ((INTERRUPT_CORE0_DSI_INT_MAP_V)<<(INTERRUPT_CORE0_DSI_INT_MAP_S)) -#define INTERRUPT_CORE0_DSI_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_DSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/** INTERRUPT_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DSI_INT_MAP_M (CORE0_DSI_INT_MAP_V << CORE0_DSI_INT_MAP_S) +#define INTERRUPT_CORE0_DSI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DSI_INT_MAP_S 0 -#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) -/* INTERRUPT_CORE0_GMII_PHY_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_GMII_PHY_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_M ((INTERRUPT_CORE0_GMII_PHY_INT_MAP_V)<<(INTERRUPT_CORE0_GMII_PHY_INT_MAP_S)) -#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +/** INTERRUPT_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_M (CORE0_GMII_PHY_INT_MAP_V << CORE0_GMII_PHY_INT_MAP_S) +#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GMII_PHY_INT_MAP_S 0 -#define INTERRUPT_CORE0_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) -/* INTERRUPT_CORE0_LPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_LPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_LPI_INT_MAP_M ((INTERRUPT_CORE0_LPI_INT_MAP_V)<<(INTERRUPT_CORE0_LPI_INT_MAP_S)) -#define INTERRUPT_CORE0_LPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_LPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +/** INTERRUPT_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_LPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_LPI_INT_MAP_M (CORE0_LPI_INT_MAP_V << CORE0_LPI_INT_MAP_S) +#define INTERRUPT_CORE0_LPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LPI_INT_MAP_S 0 -#define INTERRUPT_CORE0_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) -/* INTERRUPT_CORE0_PMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PMT_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PMT_INT_MAP_M ((INTERRUPT_CORE0_PMT_INT_MAP_V)<<(INTERRUPT_CORE0_PMT_INT_MAP_S)) -#define INTERRUPT_CORE0_PMT_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c) +/** INTERRUPT_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMT_INT_MAP_M (CORE0_PMT_INT_MAP_V << CORE0_PMT_INT_MAP_S) +#define INTERRUPT_CORE0_PMT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PMT_INT_MAP_S 0 -#define INTERRUPT_CORE0_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) -/* INTERRUPT_CORE0_SBD_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_SBD_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_SBD_INT_MAP_M ((INTERRUPT_CORE0_SBD_INT_MAP_V)<<(INTERRUPT_CORE0_SBD_INT_MAP_S)) -#define INTERRUPT_CORE0_SBD_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_SBD_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +/** INTERRUPT_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_SBD_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_SBD_INT_MAP_M (CORE0_SBD_INT_MAP_V << CORE0_SBD_INT_MAP_S) +#define INTERRUPT_CORE0_SBD_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SBD_INT_MAP_S 0 -#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) -/* INTERRUPT_CORE0_USB_OTG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_USB_OTG_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_USB_OTG_INT_MAP_M ((INTERRUPT_CORE0_USB_OTG_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG_INT_MAP_S)) -#define INTERRUPT_CORE0_USB_OTG_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_USB_OTG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +/** INTERRUPT_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG_INT_MAP_M (CORE0_USB_OTG_INT_MAP_V << CORE0_USB_OTG_INT_MAP_S) +#define INTERRUPT_CORE0_USB_OTG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_USB_OTG_INT_MAP_S 0 -#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) -/* INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M ((INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)) -#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) +/** INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) +#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 -#define INTERRUPT_CORE0_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C) -/* INTERRUPT_CORE0_JPEG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_JPEG_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_JPEG_INT_MAP_M ((INTERRUPT_CORE0_JPEG_INT_MAP_V)<<(INTERRUPT_CORE0_JPEG_INT_MAP_S)) -#define INTERRUPT_CORE0_JPEG_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_JPEG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c) +/** INTERRUPT_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_JPEG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_JPEG_INT_MAP_M (CORE0_JPEG_INT_MAP_V << CORE0_JPEG_INT_MAP_S) +#define INTERRUPT_CORE0_JPEG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_JPEG_INT_MAP_S 0 -#define INTERRUPT_CORE0_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) -/* INTERRUPT_CORE0_PPA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PPA_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PPA_INT_MAP_M ((INTERRUPT_CORE0_PPA_INT_MAP_V)<<(INTERRUPT_CORE0_PPA_INT_MAP_S)) -#define INTERRUPT_CORE0_PPA_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PPA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +/** INTERRUPT_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PPA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PPA_INT_MAP_M (CORE0_PPA_INT_MAP_V << CORE0_PPA_INT_MAP_S) +#define INTERRUPT_CORE0_PPA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PPA_INT_MAP_S 0 -#define INTERRUPT_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) -/* INTERRUPT_CORE0_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_TRACE_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_TRACE_INT_MAP_M ((INTERRUPT_CORE0_TRACE_INT_MAP_V)<<(INTERRUPT_CORE0_TRACE_INT_MAP_S)) -#define INTERRUPT_CORE0_TRACE_INT_MAP_V 0x3F -#define INTERRUPT_CORE0_TRACE_INT_MAP_S 0 +/** INTERRUPT_CORE0_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +/** INTERRUPT_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_M (CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_TRACE_INT_MAP_S) +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_S 0 -#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) -/* INTERRUPT_CORE0_CORE1_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_M ((INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V)<<(INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_S)) -#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +/** INTERRUPT_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_M (CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE1_TRACE_INT_MAP_S) +#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_S 0 -#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C) -/* INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_M ((INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V)<<(INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_S)) -#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c) +/** INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_M (CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_HP_CORE_CTRL_INT_MAP_S) +#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_S 0 -#define INTERRUPT_CORE0_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) -/* INTERRUPT_CORE0_ISP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_ISP_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_ISP_INT_MAP_M ((INTERRUPT_CORE0_ISP_INT_MAP_V)<<(INTERRUPT_CORE0_ISP_INT_MAP_S)) -#define INTERRUPT_CORE0_ISP_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_ISP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) +/** INTERRUPT_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ISP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ISP_INT_MAP_M (CORE0_ISP_INT_MAP_V << CORE0_ISP_INT_MAP_S) +#define INTERRUPT_CORE0_ISP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ISP_INT_MAP_S 0 -#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) -/* INTERRUPT_CORE0_I3C_MST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_I3C_MST_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_I3C_MST_INT_MAP_M ((INTERRUPT_CORE0_I3C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I3C_MST_INT_MAP_S)) -#define INTERRUPT_CORE0_I3C_MST_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_I3C_MST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) +/** INTERRUPT_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I3C_MST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I3C_MST_INT_MAP_M (CORE0_I3C_MST_INT_MAP_V << CORE0_I3C_MST_INT_MAP_S) +#define INTERRUPT_CORE0_I3C_MST_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I3C_MST_INT_MAP_S 0 -#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) -/* INTERRUPT_CORE0_I3C_SLV_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_I3C_SLV_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_M ((INTERRUPT_CORE0_I3C_SLV_INT_MAP_V)<<(INTERRUPT_CORE0_I3C_SLV_INT_MAP_S)) -#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) +/** INTERRUPT_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_M (CORE0_I3C_SLV_INT_MAP_V << CORE0_I3C_SLV_INT_MAP_S) +#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I3C_SLV_INT_MAP_S 0 -#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19C) -/* INTERRUPT_CORE0_USB_OTG11_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_USB_OTG11_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_M ((INTERRUPT_CORE0_USB_OTG11_INT_MAP_V)<<(INTERRUPT_CORE0_USB_OTG11_INT_MAP_S)) -#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c) +/** INTERRUPT_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_M (CORE0_USB_OTG11_INT_MAP_V << CORE0_USB_OTG11_INT_MAP_S) +#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_USB_OTG11_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0) -/* INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0) +/** INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_M (CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4) -/* INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4) +/** INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_M (CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8) -/* INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8) +/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_M (CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC) -/* INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac) +/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_M (CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0) -/* INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0) +/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_M (CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4) -/* INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_M ((INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V)<<(INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_S)) -#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b4) +/** INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_M (CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_PSRAM_MSPI_INT_MAP_S) +#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_S 0 -#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B8) -/* INTERRUPT_CORE0_HP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_M ((INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE0_HP_SYSREG_INT_MAP_S)) -#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b8) +/** INTERRUPT_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_M (CORE0_HP_SYSREG_INT_MAP_V << CORE0_HP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_S 0 -#define INTERRUPT_CORE0_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1BC) -/* INTERRUPT_CORE0_PCNT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_PCNT_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_PCNT_INT_MAP_M ((INTERRUPT_CORE0_PCNT_INT_MAP_V)<<(INTERRUPT_CORE0_PCNT_INT_MAP_S)) -#define INTERRUPT_CORE0_PCNT_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_PCNT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1bc) +/** INTERRUPT_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_PCNT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INT_MAP_M (CORE0_PCNT_INT_MAP_V << CORE0_PCNT_INT_MAP_S) +#define INTERRUPT_CORE0_PCNT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PCNT_INT_MAP_S 0 -#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C0) -/* INTERRUPT_CORE0_HP_PAU_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_HP_PAU_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_HP_PAU_INT_MAP_M ((INTERRUPT_CORE0_HP_PAU_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PAU_INT_MAP_S)) -#define INTERRUPT_CORE0_HP_PAU_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_HP_PAU_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c0) +/** INTERRUPT_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_PAU_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PAU_INT_MAP_M (CORE0_HP_PAU_INT_MAP_V << CORE0_HP_PAU_INT_MAP_S) +#define INTERRUPT_CORE0_HP_PAU_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_PAU_INT_MAP_S 0 -#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C4) -/* INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_M ((INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_S)) -#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c4) +/** INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_M (CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_HP_PARLIO_RX_INT_MAP_S) +#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_S 0 -#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C8) -/* INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_M ((INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V)<<(INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_S)) -#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c8) +/** INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_M (CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_HP_PARLIO_TX_INT_MAP_S) +#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1CC) -/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1cc) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1D0) -/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d0) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1D4) -/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d4) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1D8) -/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d8) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1DC) -/* INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1dc) +/** INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M (CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1E0) -/* INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e0) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M (CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_H264_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1E4) -/* INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e4) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M (CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_H264_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1E8) -/* INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e8) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M (CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_H264_DMA2D_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1EC) -/* INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ec) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M (CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_H264_DMA2D_IN_CH3_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1F0) -/* INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f0) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M (CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_H264_DMA2D_IN_CH4_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1F4) -/* INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M ((INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V)<<(INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f4) +/** INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M (CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_H264_DMA2D_IN_CH5_INT_MAP_S) +#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S 0 -#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1F8) -/* INTERRUPT_CORE0_H264_REG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_H264_REG_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_H264_REG_INT_MAP_M ((INTERRUPT_CORE0_H264_REG_INT_MAP_V)<<(INTERRUPT_CORE0_H264_REG_INT_MAP_S)) -#define INTERRUPT_CORE0_H264_REG_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_H264_REG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f8) +/** INTERRUPT_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_H264_REG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_H264_REG_INT_MAP_M (CORE0_H264_REG_INT_MAP_V << CORE0_H264_REG_INT_MAP_S) +#define INTERRUPT_CORE0_H264_REG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_H264_REG_INT_MAP_S 0 -#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1FC) -/* INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP 0x0000003F -#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_S)) -#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V 0x3F +/** INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1fc) +/** INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_M (CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_ASSIST_DEBUG_INT_MAP_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200) -/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S)) -#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF +/** INTERRUPT_CORE0_INTR_STATUS_REG_0_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200) +/** INTERRUPT_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_0_M (CORE0_INTR_STATUS_0_V << CORE0_INTR_STATUS_0_S) +#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INTR_STATUS_0_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204) -/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S)) -#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF +/** INTERRUPT_CORE0_INTR_STATUS_REG_1_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204) +/** INTERRUPT_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_1_M (CORE0_INTR_STATUS_1_V << CORE0_INTR_STATUS_1_S) +#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INTR_STATUS_1_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208) -/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S)) -#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF +/** INTERRUPT_CORE0_INTR_STATUS_REG_2_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208) +/** INTERRUPT_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_2_M (CORE0_INTR_STATUS_2_V << CORE0_INTR_STATUS_2_S) +#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INTR_STATUS_2_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20C) -/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_INTR_STATUS_3 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_3_M ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S)) -#define INTERRUPT_CORE0_INTR_STATUS_3_V 0xFFFFFFFF +/** INTERRUPT_CORE0_INTR_STATUS_REG_3_REG register + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20c) +/** INTERRUPT_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE0_INTR_STATUS_3 0xFFFFFFFFU +#define INTERRUPT_CORE0_INTR_STATUS_3_M (CORE0_INTR_STATUS_3_V << CORE0_INTR_STATUS_3_S) +#define INTERRUPT_CORE0_INTR_STATUS_3_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INTR_STATUS_3_S 0 -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210) -/* INTERRUPT_CORE0_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ +/** INTERRUPT_CORE0_CLOCK_GATE_REG register + * NA + */ +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210) +/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * NA + */ #define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) -#define INTERRUPT_CORE0_REG_CLK_EN_M (BIT(0)) -#define INTERRUPT_CORE0_REG_CLK_EN_V 0x1 +#define INTERRUPT_CORE0_REG_CLK_EN_M (CORE0_REG_CLK_EN_V << CORE0_REG_CLK_EN_S) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U #define INTERRUPT_CORE0_REG_CLK_EN_S 0 -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3FC) -/* INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ -/*description: .*/ -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFF -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M ((INTERRUPT_CORE0_INTERRUPT_REG_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_REG_DATE_S)) -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V 0xFFFFFFF +/** INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG register + * NA + */ +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3fc) +/** INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M (CORE0_INTERRUPT_REG_DATE_V << CORE0_INTERRUPT_REG_DATE_S) +#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU #define INTERRUPT_CORE0_INTERRUPT_REG_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */ diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_struct.h b/components/soc/esp32p4/include/soc/interrupt_core0_struct.h new file mode 100644 index 0000000000..2b5ba97fb8 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupt_core0_struct.h @@ -0,0 +1,2298 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: INTERRUPT_CORE0_LP RTC INT MAP REG */ +/** Type of lp_rtc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_rtc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_rtc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP WDT INT MAP REG */ +/** Type of lp_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_wdt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TIMER REG 0 INT MAP REG */ +/** Type of lp_timer_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_timer_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_timer_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TIMER REG 1 INT MAP REG */ +/** Type of lp_timer_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_timer_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_timer_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_MB HP INT MAP REG */ +/** Type of mb_hp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_mb_hp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_mb_hp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_MB LP INT MAP REG */ +/** Type of mb_lp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_mb_lp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_mb_lp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PMU REG 0 INT MAP REG */ +/** Type of pmu_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pmu_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmu_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PMU REG 1 INT MAP REG */ +/** Type of pmu_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pmu_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmu_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP ANAPERI INT MAP REG */ +/** Type of lp_anaperi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_anaperi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_anaperi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP ADC INT MAP REG */ +/** Type of lp_adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_adc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP GPIO INT MAP REG */ +/** Type of lp_gpio_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_gpio_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_gpio_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP I2C INT MAP REG */ +/** Type of lp_i2c_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_i2c_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_i2c_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP I2S INT MAP REG */ +/** Type of lp_i2s_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_i2s_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_i2s_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP SPI INT MAP REG */ +/** Type of lp_spi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_spi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_spi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TOUCH INT MAP REG */ +/** Type of lp_touch_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_touch_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_touch_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP TSENS INT MAP REG */ +/** Type of lp_tsens_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_tsens_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_tsens_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP UART INT MAP REG */ +/** Type of lp_uart_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_uart_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_uart_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP EFUSE INT MAP REG */ +/** Type of lp_efuse_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_efuse_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_efuse_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP SW INT MAP REG */ +/** Type of lp_sw_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_sw_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_sw_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP SYSREG INT MAP REG */ +/** Type of lp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LP HUK INT MAP REG */ +/** Type of lp_huk_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lp_huk_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_huk_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYS ICM INT MAP REG */ +/** Type of sys_icm_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sys_icm_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sys_icm_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB DEVICE INT MAP REG */ +/** Type of usb_device_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_device_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_device_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SDIO HOST INT MAP REG */ +/** Type of sdio_host_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sdio_host_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sdio_host_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GDMA INT MAP REG */ +/** Type of gdma_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gdma_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gdma_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SPI2 INT MAP REG */ +/** Type of spi2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_spi2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_spi2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SPI3 INT MAP REG */ +/** Type of spi3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_spi3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_spi3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2S0 INT MAP REG */ +/** Type of i2s0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2s0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2S1 INT MAP REG */ +/** Type of i2s1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2s1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2S2 INT MAP REG */ +/** Type of i2s2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2s2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UHCI0 INT MAP REG */ +/** Type of uhci0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uhci0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uhci0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART0 INT MAP REG */ +/** Type of uart0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART1 INT MAP REG */ +/** Type of uart1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART2 INT MAP REG */ +/** Type of uart2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART3 INT MAP REG */ +/** Type of uart3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_UART4 INT MAP REG */ +/** Type of uart4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_uart4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart4_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LCD CAM INT MAP REG */ +/** Type of lcd_cam_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lcd_cam_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lcd_cam_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ADC INT MAP REG */ +/** Type of adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_adc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PWM0 INT MAP REG */ +/** Type of pwm0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pwm0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pwm0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PWM1 INT MAP REG */ +/** Type of pwm1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pwm1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pwm1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CAN0 INT MAP REG */ +/** Type of can0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_can0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_can0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CAN1 INT MAP REG */ +/** Type of can1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_can1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_can1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CAN2 INT MAP REG */ +/** Type of can2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_can2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_can2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_RMT INT MAP REG */ +/** Type of rmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_rmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rmt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2C0 INT MAP REG */ +/** Type of i2c0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2c0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I2C1 INT MAP REG */ +/** Type of i2c1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i2c1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP0 T0 INT MAP REG */ +/** Type of timergrp0_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp0_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp0_t0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP0 T1 INT MAP REG */ +/** Type of timergrp0_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp0_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp0_t1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP0 WDT INT MAP REG */ +/** Type of timergrp0_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp0_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp0_wdt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP1 T0 INT MAP REG */ +/** Type of timergrp1_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp1_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp1_t0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP1 T1 INT MAP REG */ +/** Type of timergrp1_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp1_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp1_t1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_TIMERGRP1 WDT INT MAP REG */ +/** Type of timergrp1_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_timergrp1_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_timergrp1_wdt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LEDC INT MAP REG */ +/** Type of ledc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ledc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ledc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYSTIMER TARGET0 INT MAP REG */ +/** Type of systimer_target0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_systimer_target0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYSTIMER TARGET1 INT MAP REG */ +/** Type of systimer_target1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_systimer_target1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SYSTIMER TARGET2 INT MAP REG */ +/** Type of systimer_target2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_systimer_target2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA IN CH0 INT MAP REG */ +/** Type of ahb_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA IN CH1 INT MAP REG */ +/** Type of ahb_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA IN CH2 INT MAP REG */ +/** Type of ahb_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH0 INT MAP REG */ +/** Type of ahb_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH1 INT MAP REG */ +/** Type of ahb_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AHB PDMA OUT CH2 INT MAP REG */ +/** Type of ahb_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ahb_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ahb_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA IN CH0 INT MAP REG */ +/** Type of axi_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA IN CH1 INT MAP REG */ +/** Type of axi_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA IN CH2 INT MAP REG */ +/** Type of axi_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH0 INT MAP REG */ +/** Type of axi_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH1 INT MAP REG */ +/** Type of axi_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AXI PDMA OUT CH2 INT MAP REG */ +/** Type of axi_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_axi_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_axi_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_RSA INT MAP REG */ +/** Type of rsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_rsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rsa_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_AES INT MAP REG */ +/** Type of aes_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_aes_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_aes_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_aes_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SHA INT MAP REG */ +/** Type of sha_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sha_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sha_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sha_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ECC INT MAP REG */ +/** Type of ecc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ecc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ECDSA INT MAP REG */ +/** Type of ecdsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ecdsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecdsa_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_KM INT MAP REG */ +/** Type of km_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_km_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_km_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_km_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT0 MAP REG */ +/** Type of gpio_int0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int0_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT1 MAP REG */ +/** Type of gpio_int1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int1_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT2 MAP REG */ +/** Type of gpio_int2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int2_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO INT3 MAP REG */ +/** Type of gpio_int3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_int3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_int3_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GPIO PAD COMP INT MAP REG */ +/** Type of gpio_pad_comp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gpio_pad_comp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_pad_comp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 0 MAP REG */ +/** Type of cpu_int_from_cpu_0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_0_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 1 MAP REG */ +/** Type of cpu_int_from_cpu_1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_1_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 2 MAP REG */ +/** Type of cpu_int_from_cpu_2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_2_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CPU INT FROM CPU 3 MAP REG */ +/** Type of cpu_int_from_cpu_3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cpu_int_from_cpu_3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_int_from_cpu_3_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CACHE INT MAP REG */ +/** Type of cache_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_cache_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_cache_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cache_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_FLASH MSPI INT MAP REG */ +/** Type of flash_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_flash_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_flash_mspi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CSI BRIDGE INT MAP REG */ +/** Type of csi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_csi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_csi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DSI BRIDGE INT MAP REG */ +/** Type of dsi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dsi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dsi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CSI INT MAP REG */ +/** Type of csi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_csi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_csi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_csi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DSI INT MAP REG */ +/** Type of dsi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dsi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dsi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_GMII PHY INT MAP REG */ +/** Type of gmii_phy_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_gmii_phy_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gmii_phy_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_LPI INT MAP REG */ +/** Type of lpi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_lpi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lpi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PMT INT MAP REG */ +/** Type of pmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_SBD INT MAP REG */ +/** Type of sbd_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_sbd_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sbd_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB OTG INT MAP REG */ +/** Type of usb_otg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_otg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB OTG ENDP MULTI PROC INT MAP REG */ +/** Type of usb_otg_endp_multi_proc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_otg_endp_multi_proc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg_endp_multi_proc_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_JPEG INT MAP REG */ +/** Type of jpeg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_jpeg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_jpeg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PPA INT MAP REG */ +/** Type of ppa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_ppa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ppa_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_INTERRUPT_CORE0_TRACE INT MAP REG */ +/** Type of interrupt_core0_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_trace_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_CORE1 TRACE INT MAP REG */ +/** Type of core1_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_core1_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_core1_trace_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP CORE CTRL INT MAP REG */ +/** Type of hp_core_ctrl_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_core_ctrl_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_core_ctrl_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ISP INT MAP REG */ +/** Type of isp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_isp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_isp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_isp_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I3C MST INT MAP REG */ +/** Type of i3c_mst_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i3c_mst_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i3c_mst_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_I3C SLV INT MAP REG */ +/** Type of i3c_slv_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_i3c_slv_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i3c_slv_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_USB OTG11 INT MAP REG */ +/** Type of usb_otg11_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_usb_otg11_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg11_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D IN CH0 INT MAP REG */ +/** Type of dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D IN CH1 INT MAP REG */ +/** Type of dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D OUT CH0 INT MAP REG */ +/** Type of dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D OUT CH1 INT MAP REG */ +/** Type of dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_DMA2D OUT CH2 INT MAP REG */ +/** Type of dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PSRAM MSPI INT MAP REG */ +/** Type of psram_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_psram_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_psram_mspi_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP SYSREG INT MAP REG */ +/** Type of hp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_PCNT INT MAP REG */ +/** Type of pcnt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_pcnt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pcnt_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP PAU INT MAP REG */ +/** Type of hp_pau_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_pau_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_pau_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP PARLIO RX INT MAP REG */ +/** Type of hp_parlio_rx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_parlio_rx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_parlio_rx_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_HP PARLIO TX INT MAP REG */ +/** Type of hp_parlio_tx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_hp_parlio_tx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_parlio_tx_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH0 INT MAP REG */ +/** Type of h264_dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH1 INT MAP REG */ +/** Type of h264_dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH2 INT MAP REG */ +/** Type of h264_dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH3 INT MAP REG */ +/** Type of h264_dma2d_out_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D OUT CH4 INT MAP REG */ +/** Type of h264_dma2d_out_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_out_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_out_ch4_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH0 INT MAP REG */ +/** Type of h264_dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH1 INT MAP REG */ +/** Type of h264_dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH2 INT MAP REG */ +/** Type of h264_dma2d_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH3 INT MAP REG */ +/** Type of h264_dma2d_in_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch3_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH4 INT MAP REG */ +/** Type of h264_dma2d_in_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch4_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 DMA2D IN CH5 INT MAP REG */ +/** Type of h264_dma2d_in_ch5_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_dma2d_in_ch5_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_dma2d_in_ch5_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_H264 REG INT MAP REG */ +/** Type of h264_reg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_h264_reg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_h264_reg_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_ASSIST DEBUG INT MAP REG */ +/** Type of assist_debug_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_assist_debug_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_assist_debug_int_map_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 0 REG */ +/** Type of intr_status_reg_0 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_0:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_0_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 1 REG */ +/** Type of intr_status_reg_1 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_1:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_1_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 2 REG */ +/** Type of intr_status_reg_2 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_2:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_2_reg_t; + + +/** Group: INTERRUPT_CORE0_INTR STATUS REG 3 REG */ +/** Type of intr_status_reg_3 register + * NA + */ +typedef union { + struct { + /** interrupt_core0_intr_status_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core0_intr_status_3:32; + }; + uint32_t val; +} interrupt_core0_intr_status_reg_3_reg_t; + + +/** Group: INTERRUPT_CORE0_CLOCK GATE REG */ +/** Type of clock_gate register + * NA + */ +typedef union { + struct { + /** interrupt_core0_reg_clk_en : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t interrupt_core0_reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_core0_clock_gate_reg_t; + + +/** Group: INTERRUPT_CORE0_INTERRUPT REG DATE REG */ +/** Type of interrupt_reg_date register + * NA + */ +typedef union { + struct { + /** interrupt_core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ + uint32_t interrupt_core0_interrupt_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_core0_interrupt_reg_date_reg_t; + + +typedef struct { + volatile interrupt_core0_lp_rtc_int_map_reg_t lp_rtc_int_map; + volatile interrupt_core0_lp_wdt_int_map_reg_t lp_wdt_int_map; + volatile interrupt_core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; + volatile interrupt_core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; + volatile interrupt_core0_mb_hp_int_map_reg_t mb_hp_int_map; + volatile interrupt_core0_mb_lp_int_map_reg_t mb_lp_int_map; + volatile interrupt_core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; + volatile interrupt_core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; + volatile interrupt_core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map; + volatile interrupt_core0_lp_adc_int_map_reg_t lp_adc_int_map; + volatile interrupt_core0_lp_gpio_int_map_reg_t lp_gpio_int_map; + volatile interrupt_core0_lp_i2c_int_map_reg_t lp_i2c_int_map; + volatile interrupt_core0_lp_i2s_int_map_reg_t lp_i2s_int_map; + volatile interrupt_core0_lp_spi_int_map_reg_t lp_spi_int_map; + volatile interrupt_core0_lp_touch_int_map_reg_t lp_touch_int_map; + volatile interrupt_core0_lp_tsens_int_map_reg_t lp_tsens_int_map; + volatile interrupt_core0_lp_uart_int_map_reg_t lp_uart_int_map; + volatile interrupt_core0_lp_efuse_int_map_reg_t lp_efuse_int_map; + volatile interrupt_core0_lp_sw_int_map_reg_t lp_sw_int_map; + volatile interrupt_core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map; + volatile interrupt_core0_lp_huk_int_map_reg_t lp_huk_int_map; + volatile interrupt_core0_sys_icm_int_map_reg_t sys_icm_int_map; + volatile interrupt_core0_usb_device_int_map_reg_t usb_device_int_map; + volatile interrupt_core0_sdio_host_int_map_reg_t sdio_host_int_map; + volatile interrupt_core0_gdma_int_map_reg_t gdma_int_map; + volatile interrupt_core0_spi2_int_map_reg_t spi2_int_map; + volatile interrupt_core0_spi3_int_map_reg_t spi3_int_map; + volatile interrupt_core0_i2s0_int_map_reg_t i2s0_int_map; + volatile interrupt_core0_i2s1_int_map_reg_t i2s1_int_map; + volatile interrupt_core0_i2s2_int_map_reg_t i2s2_int_map; + volatile interrupt_core0_uhci0_int_map_reg_t uhci0_int_map; + volatile interrupt_core0_uart0_int_map_reg_t uart0_int_map; + volatile interrupt_core0_uart1_int_map_reg_t uart1_int_map; + volatile interrupt_core0_uart2_int_map_reg_t uart2_int_map; + volatile interrupt_core0_uart3_int_map_reg_t uart3_int_map; + volatile interrupt_core0_uart4_int_map_reg_t uart4_int_map; + volatile interrupt_core0_lcd_cam_int_map_reg_t lcd_cam_int_map; + volatile interrupt_core0_adc_int_map_reg_t adc_int_map; + volatile interrupt_core0_pwm0_int_map_reg_t pwm0_int_map; + volatile interrupt_core0_pwm1_int_map_reg_t pwm1_int_map; + volatile interrupt_core0_can0_int_map_reg_t can0_int_map; + volatile interrupt_core0_can1_int_map_reg_t can1_int_map; + volatile interrupt_core0_can2_int_map_reg_t can2_int_map; + volatile interrupt_core0_rmt_int_map_reg_t rmt_int_map; + volatile interrupt_core0_i2c0_int_map_reg_t i2c0_int_map; + volatile interrupt_core0_i2c1_int_map_reg_t i2c1_int_map; + volatile interrupt_core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; + volatile interrupt_core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; + volatile interrupt_core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; + volatile interrupt_core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; + volatile interrupt_core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; + volatile interrupt_core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; + volatile interrupt_core0_ledc_int_map_reg_t ledc_int_map; + volatile interrupt_core0_systimer_target0_int_map_reg_t systimer_target0_int_map; + volatile interrupt_core0_systimer_target1_int_map_reg_t systimer_target1_int_map; + volatile interrupt_core0_systimer_target2_int_map_reg_t systimer_target2_int_map; + volatile interrupt_core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; + volatile interrupt_core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; + volatile interrupt_core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; + volatile interrupt_core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; + volatile interrupt_core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; + volatile interrupt_core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; + volatile interrupt_core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; + volatile interrupt_core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; + volatile interrupt_core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; + volatile interrupt_core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; + volatile interrupt_core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; + volatile interrupt_core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; + volatile interrupt_core0_rsa_int_map_reg_t rsa_int_map; + volatile interrupt_core0_aes_int_map_reg_t aes_int_map; + volatile interrupt_core0_sha_int_map_reg_t sha_int_map; + volatile interrupt_core0_ecc_int_map_reg_t ecc_int_map; + volatile interrupt_core0_ecdsa_int_map_reg_t ecdsa_int_map; + volatile interrupt_core0_km_int_map_reg_t km_int_map; + volatile interrupt_core0_gpio_int0_map_reg_t gpio_int0_map; + volatile interrupt_core0_gpio_int1_map_reg_t gpio_int1_map; + volatile interrupt_core0_gpio_int2_map_reg_t gpio_int2_map; + volatile interrupt_core0_gpio_int3_map_reg_t gpio_int3_map; + volatile interrupt_core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; + volatile interrupt_core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; + volatile interrupt_core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; + volatile interrupt_core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; + volatile interrupt_core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; + volatile interrupt_core0_cache_int_map_reg_t cache_int_map; + volatile interrupt_core0_flash_mspi_int_map_reg_t flash_mspi_int_map; + volatile interrupt_core0_csi_bridge_int_map_reg_t csi_bridge_int_map; + volatile interrupt_core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map; + volatile interrupt_core0_csi_int_map_reg_t csi_int_map; + volatile interrupt_core0_dsi_int_map_reg_t dsi_int_map; + volatile interrupt_core0_gmii_phy_int_map_reg_t gmii_phy_int_map; + volatile interrupt_core0_lpi_int_map_reg_t lpi_int_map; + volatile interrupt_core0_pmt_int_map_reg_t pmt_int_map; + volatile interrupt_core0_sbd_int_map_reg_t sbd_int_map; + volatile interrupt_core0_usb_otg_int_map_reg_t usb_otg_int_map; + volatile interrupt_core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; + volatile interrupt_core0_jpeg_int_map_reg_t jpeg_int_map; + volatile interrupt_core0_ppa_int_map_reg_t ppa_int_map; + volatile interrupt_core0_trace_int_map_reg_t interrupt_core0_trace_int_map; + volatile interrupt_core0_core1_trace_int_map_reg_t core1_trace_int_map; + volatile interrupt_core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; + volatile interrupt_core0_isp_int_map_reg_t isp_int_map; + volatile interrupt_core0_i3c_mst_int_map_reg_t i3c_mst_int_map; + volatile interrupt_core0_i3c_slv_int_map_reg_t i3c_slv_int_map; + volatile interrupt_core0_usb_otg11_int_map_reg_t usb_otg11_int_map; + volatile interrupt_core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; + volatile interrupt_core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; + volatile interrupt_core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; + volatile interrupt_core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; + volatile interrupt_core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; + volatile interrupt_core0_psram_mspi_int_map_reg_t psram_mspi_int_map; + volatile interrupt_core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map; + volatile interrupt_core0_pcnt_int_map_reg_t pcnt_int_map; + volatile interrupt_core0_hp_pau_int_map_reg_t hp_pau_int_map; + volatile interrupt_core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; + volatile interrupt_core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; + volatile interrupt_core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; + volatile interrupt_core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; + volatile interrupt_core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; + volatile interrupt_core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; + volatile interrupt_core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; + volatile interrupt_core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; + volatile interrupt_core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; + volatile interrupt_core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; + volatile interrupt_core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; + volatile interrupt_core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; + volatile interrupt_core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; + volatile interrupt_core0_h264_reg_int_map_reg_t h264_reg_int_map; + volatile interrupt_core0_assist_debug_int_map_reg_t assist_debug_int_map; + volatile interrupt_core0_intr_status_reg_0_reg_t intr_status_reg_0; + volatile interrupt_core0_intr_status_reg_1_reg_t intr_status_reg_1; + volatile interrupt_core0_intr_status_reg_2_reg_t intr_status_reg_2; + volatile interrupt_core0_intr_status_reg_3_reg_t intr_status_reg_3; + volatile interrupt_core0_clock_gate_reg_t clock_gate; + uint32_t reserved_214[122]; + volatile interrupt_core0_interrupt_reg_date_reg_t interrupt_reg_date; +} interrupt_core0_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_core0_dev_t) == 0x400, "Invalid size of interrupt_core0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h index 7ba04340b6..d4afbcfbe1 100644 --- a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h +++ b/components/soc/esp32p4/include/soc/interrupt_core1_reg.h @@ -1,1094 +1,1624 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_INTERRUPT_CORE1_REG_H_ -#define _SOC_INTERRUPT_CORE1_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x0) -/* INTERRUPT_CORE1_LP_RTC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_RTC_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_RTC_INT_MAP_M ((INTERRUPT_CORE1_LP_RTC_INT_MAP_V)<<(INTERRUPT_CORE1_LP_RTC_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_RTC_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_RTC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x0) +/** INTERRUPT_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_RTC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_M (INTERRUPT_CORE1_LP_RTC_INT_MAP_V << INTERRUPT_CORE1_LP_RTC_INT_MAP_S) +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_RTC_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4) -/* INTERRUPT_CORE1_LP_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_WDT_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_WDT_INT_MAP_M ((INTERRUPT_CORE1_LP_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_LP_WDT_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_WDT_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4) +/** INTERRUPT_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_M (INTERRUPT_CORE1_LP_WDT_INT_MAP_V << INTERRUPT_CORE1_LP_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8) -/* INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_M ((INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8) +/** INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_M (INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xC) -/* INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_M ((INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc) +/** INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_M (INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_S 0 -#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10) -/* INTERRUPT_CORE1_MB_HP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_MB_HP_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_MB_HP_INT_MAP_M ((INTERRUPT_CORE1_MB_HP_INT_MAP_V)<<(INTERRUPT_CORE1_MB_HP_INT_MAP_S)) -#define INTERRUPT_CORE1_MB_HP_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_MB_HP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10) +/** INTERRUPT_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_MB_HP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_MB_HP_INT_MAP_M (INTERRUPT_CORE1_MB_HP_INT_MAP_V << INTERRUPT_CORE1_MB_HP_INT_MAP_S) +#define INTERRUPT_CORE1_MB_HP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_MB_HP_INT_MAP_S 0 -#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14) -/* INTERRUPT_CORE1_MB_LP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_MB_LP_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_MB_LP_INT_MAP_M ((INTERRUPT_CORE1_MB_LP_INT_MAP_V)<<(INTERRUPT_CORE1_MB_LP_INT_MAP_S)) -#define INTERRUPT_CORE1_MB_LP_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_MB_LP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14) +/** INTERRUPT_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_MB_LP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_MB_LP_INT_MAP_M (INTERRUPT_CORE1_MB_LP_INT_MAP_V << INTERRUPT_CORE1_MB_LP_INT_MAP_S) +#define INTERRUPT_CORE1_MB_LP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_MB_LP_INT_MAP_S 0 -#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18) -/* INTERRUPT_CORE1_PMU_REG_0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_M ((INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V)<<(INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S)) -#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18) +/** INTERRUPT_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_M (INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V << INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S) +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_S 0 -#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1C) -/* INTERRUPT_CORE1_PMU_REG_1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_M ((INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V)<<(INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S)) -#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c) +/** INTERRUPT_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_M (INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V << INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S) +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20) -/* INTERRUPT_CORE1_LP_ANAPERI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_M ((INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V)<<(INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20) +/** INTERRUPT_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_M (INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V << INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S) +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24) -/* INTERRUPT_CORE1_LP_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_ADC_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_ADC_INT_MAP_M ((INTERRUPT_CORE1_LP_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_LP_ADC_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_ADC_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24) +/** INTERRUPT_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_M (INTERRUPT_CORE1_LP_ADC_INT_MAP_V << INTERRUPT_CORE1_LP_ADC_INT_MAP_S) +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_ADC_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28) -/* INTERRUPT_CORE1_LP_GPIO_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_GPIO_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_M ((INTERRUPT_CORE1_LP_GPIO_INT_MAP_V)<<(INTERRUPT_CORE1_LP_GPIO_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28) +/** INTERRUPT_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_M (INTERRUPT_CORE1_LP_GPIO_INT_MAP_V << INTERRUPT_CORE1_LP_GPIO_INT_MAP_S) +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_GPIO_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2C) -/* INTERRUPT_CORE1_LP_I2C_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_I2C_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_I2C_INT_MAP_M ((INTERRUPT_CORE1_LP_I2C_INT_MAP_V)<<(INTERRUPT_CORE1_LP_I2C_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_I2C_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_I2C_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c) +/** INTERRUPT_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_I2C_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_M (INTERRUPT_CORE1_LP_I2C_INT_MAP_V << INTERRUPT_CORE1_LP_I2C_INT_MAP_S) +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_I2C_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x30) -/* INTERRUPT_CORE1_LP_I2S_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_I2S_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_I2S_INT_MAP_M ((INTERRUPT_CORE1_LP_I2S_INT_MAP_V)<<(INTERRUPT_CORE1_LP_I2S_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_I2S_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_I2S_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x30) +/** INTERRUPT_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_I2S_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_M (INTERRUPT_CORE1_LP_I2S_INT_MAP_V << INTERRUPT_CORE1_LP_I2S_INT_MAP_S) +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_I2S_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x34) -/* INTERRUPT_CORE1_LP_SPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_SPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_SPI_INT_MAP_M ((INTERRUPT_CORE1_LP_SPI_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SPI_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_SPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_SPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x34) +/** INTERRUPT_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_SPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_M (INTERRUPT_CORE1_LP_SPI_INT_MAP_V << INTERRUPT_CORE1_LP_SPI_INT_MAP_S) +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_SPI_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x38) -/* INTERRUPT_CORE1_LP_TOUCH_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_M ((INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x38) +/** INTERRUPT_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_M (INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V << INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3C) -/* INTERRUPT_CORE1_LP_TSENS_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_TSENS_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_M ((INTERRUPT_CORE1_LP_TSENS_INT_MAP_V)<<(INTERRUPT_CORE1_LP_TSENS_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3c) +/** INTERRUPT_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_M (INTERRUPT_CORE1_LP_TSENS_INT_MAP_V << INTERRUPT_CORE1_LP_TSENS_INT_MAP_S) +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_TSENS_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x40) -/* INTERRUPT_CORE1_LP_UART_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_UART_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_UART_INT_MAP_M ((INTERRUPT_CORE1_LP_UART_INT_MAP_V)<<(INTERRUPT_CORE1_LP_UART_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_UART_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_UART_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x40) +/** INTERRUPT_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_UART_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_UART_INT_MAP_M (INTERRUPT_CORE1_LP_UART_INT_MAP_V << INTERRUPT_CORE1_LP_UART_INT_MAP_S) +#define INTERRUPT_CORE1_LP_UART_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_UART_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x44) -/* INTERRUPT_CORE1_LP_EFUSE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_M ((INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x44) +/** INTERRUPT_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_M (INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V << INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S) +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x48) -/* INTERRUPT_CORE1_LP_SW_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_SW_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_SW_INT_MAP_M ((INTERRUPT_CORE1_LP_SW_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SW_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_SW_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_SW_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x48) +/** INTERRUPT_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_SW_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_SW_INT_MAP_M (INTERRUPT_CORE1_LP_SW_INT_MAP_V << INTERRUPT_CORE1_LP_SW_INT_MAP_S) +#define INTERRUPT_CORE1_LP_SW_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_SW_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4C) -/* INTERRUPT_CORE1_LP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_M ((INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4c) +/** INTERRUPT_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_M (INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V << INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_S 0 -#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x50) -/* INTERRUPT_CORE1_LP_HUK_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LP_HUK_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LP_HUK_INT_MAP_M ((INTERRUPT_CORE1_LP_HUK_INT_MAP_V)<<(INTERRUPT_CORE1_LP_HUK_INT_MAP_S)) -#define INTERRUPT_CORE1_LP_HUK_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LP_HUK_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x50) +/** INTERRUPT_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LP_HUK_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_M (INTERRUPT_CORE1_LP_HUK_INT_MAP_V << INTERRUPT_CORE1_LP_HUK_INT_MAP_S) +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LP_HUK_INT_MAP_S 0 -#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x54) -/* INTERRUPT_CORE1_SYS_ICM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SYS_ICM_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_M ((INTERRUPT_CORE1_SYS_ICM_INT_MAP_V)<<(INTERRUPT_CORE1_SYS_ICM_INT_MAP_S)) -#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x54) +/** INTERRUPT_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_M (INTERRUPT_CORE1_SYS_ICM_INT_MAP_V << INTERRUPT_CORE1_SYS_ICM_INT_MAP_S) +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SYS_ICM_INT_MAP_S 0 -#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x58) -/* INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S)) -#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x58) +/** INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M (INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V << INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S) +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S 0 -#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x5C) -/* INTERRUPT_CORE1_SDIO_HOST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_M ((INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V)<<(INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S)) -#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x5c) +/** INTERRUPT_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_M (INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V << INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S) +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_S 0 -#define INTERRUPT_CORE1_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x60) -/* INTERRUPT_CORE1_GDMA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_GDMA_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_GDMA_INT_MAP_M ((INTERRUPT_CORE1_GDMA_INT_MAP_V)<<(INTERRUPT_CORE1_GDMA_INT_MAP_S)) -#define INTERRUPT_CORE1_GDMA_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_GDMA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x60) +/** INTERRUPT_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GDMA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_GDMA_INT_MAP_M (INTERRUPT_CORE1_GDMA_INT_MAP_V << INTERRUPT_CORE1_GDMA_INT_MAP_S) +#define INTERRUPT_CORE1_GDMA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_GDMA_INT_MAP_S 0 -#define INTERRUPT_CORE1_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x64) -/* INTERRUPT_CORE1_SPI2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SPI2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SPI2_INT_MAP_M ((INTERRUPT_CORE1_SPI2_INT_MAP_V)<<(INTERRUPT_CORE1_SPI2_INT_MAP_S)) -#define INTERRUPT_CORE1_SPI2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SPI2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x64) +/** INTERRUPT_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SPI2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SPI2_INT_MAP_M (INTERRUPT_CORE1_SPI2_INT_MAP_V << INTERRUPT_CORE1_SPI2_INT_MAP_S) +#define INTERRUPT_CORE1_SPI2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SPI2_INT_MAP_S 0 -#define INTERRUPT_CORE1_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x68) -/* INTERRUPT_CORE1_SPI3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SPI3_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SPI3_INT_MAP_M ((INTERRUPT_CORE1_SPI3_INT_MAP_V)<<(INTERRUPT_CORE1_SPI3_INT_MAP_S)) -#define INTERRUPT_CORE1_SPI3_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SPI3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x68) +/** INTERRUPT_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SPI3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SPI3_INT_MAP_M (INTERRUPT_CORE1_SPI3_INT_MAP_V << INTERRUPT_CORE1_SPI3_INT_MAP_S) +#define INTERRUPT_CORE1_SPI3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SPI3_INT_MAP_S 0 -#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x6C) -/* INTERRUPT_CORE1_I2S0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_I2S0_INT_MAP_M ((INTERRUPT_CORE1_I2S0_INT_MAP_V)<<(INTERRUPT_CORE1_I2S0_INT_MAP_S)) -#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_I2S0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x6c) +/** INTERRUPT_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2S0_INT_MAP_M (INTERRUPT_CORE1_I2S0_INT_MAP_V << INTERRUPT_CORE1_I2S0_INT_MAP_S) +#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_I2S0_INT_MAP_S 0 -#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x70) -/* INTERRUPT_CORE1_I2S1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_I2S1_INT_MAP_M ((INTERRUPT_CORE1_I2S1_INT_MAP_V)<<(INTERRUPT_CORE1_I2S1_INT_MAP_S)) -#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_I2S1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x70) +/** INTERRUPT_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2S1_INT_MAP_M (INTERRUPT_CORE1_I2S1_INT_MAP_V << INTERRUPT_CORE1_I2S1_INT_MAP_S) +#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_I2S1_INT_MAP_S 0 -#define INTERRUPT_CORE1_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x74) -/* INTERRUPT_CORE1_I2S2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_I2S2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_I2S2_INT_MAP_M ((INTERRUPT_CORE1_I2S2_INT_MAP_V)<<(INTERRUPT_CORE1_I2S2_INT_MAP_S)) -#define INTERRUPT_CORE1_I2S2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_I2S2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x74) +/** INTERRUPT_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2S2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2S2_INT_MAP_M (INTERRUPT_CORE1_I2S2_INT_MAP_V << INTERRUPT_CORE1_I2S2_INT_MAP_S) +#define INTERRUPT_CORE1_I2S2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_I2S2_INT_MAP_S 0 -#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x78) -/* INTERRUPT_CORE1_UHCI0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_UHCI0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_UHCI0_INT_MAP_M ((INTERRUPT_CORE1_UHCI0_INT_MAP_V)<<(INTERRUPT_CORE1_UHCI0_INT_MAP_S)) -#define INTERRUPT_CORE1_UHCI0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_UHCI0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x78) +/** INTERRUPT_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UHCI0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UHCI0_INT_MAP_M (INTERRUPT_CORE1_UHCI0_INT_MAP_V << INTERRUPT_CORE1_UHCI0_INT_MAP_S) +#define INTERRUPT_CORE1_UHCI0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_UHCI0_INT_MAP_S 0 -#define INTERRUPT_CORE1_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7C) -/* INTERRUPT_CORE1_UART0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_UART0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_UART0_INT_MAP_M ((INTERRUPT_CORE1_UART0_INT_MAP_V)<<(INTERRUPT_CORE1_UART0_INT_MAP_S)) -#define INTERRUPT_CORE1_UART0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_UART0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7c) +/** INTERRUPT_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART0_INT_MAP_M (INTERRUPT_CORE1_UART0_INT_MAP_V << INTERRUPT_CORE1_UART0_INT_MAP_S) +#define INTERRUPT_CORE1_UART0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_UART0_INT_MAP_S 0 -#define INTERRUPT_CORE1_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80) -/* INTERRUPT_CORE1_UART1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_UART1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_UART1_INT_MAP_M ((INTERRUPT_CORE1_UART1_INT_MAP_V)<<(INTERRUPT_CORE1_UART1_INT_MAP_S)) -#define INTERRUPT_CORE1_UART1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_UART1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80) +/** INTERRUPT_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART1_INT_MAP_M (INTERRUPT_CORE1_UART1_INT_MAP_V << INTERRUPT_CORE1_UART1_INT_MAP_S) +#define INTERRUPT_CORE1_UART1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_UART1_INT_MAP_S 0 -#define INTERRUPT_CORE1_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84) -/* INTERRUPT_CORE1_UART2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_UART2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_UART2_INT_MAP_M ((INTERRUPT_CORE1_UART2_INT_MAP_V)<<(INTERRUPT_CORE1_UART2_INT_MAP_S)) -#define INTERRUPT_CORE1_UART2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_UART2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84) +/** INTERRUPT_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART2_INT_MAP_M (INTERRUPT_CORE1_UART2_INT_MAP_V << INTERRUPT_CORE1_UART2_INT_MAP_S) +#define INTERRUPT_CORE1_UART2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_UART2_INT_MAP_S 0 -#define INTERRUPT_CORE1_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88) -/* INTERRUPT_CORE1_UART3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_UART3_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_UART3_INT_MAP_M ((INTERRUPT_CORE1_UART3_INT_MAP_V)<<(INTERRUPT_CORE1_UART3_INT_MAP_S)) -#define INTERRUPT_CORE1_UART3_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_UART3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88) +/** INTERRUPT_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART3_INT_MAP_M (INTERRUPT_CORE1_UART3_INT_MAP_V << INTERRUPT_CORE1_UART3_INT_MAP_S) +#define INTERRUPT_CORE1_UART3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_UART3_INT_MAP_S 0 -#define INTERRUPT_CORE1_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C) -/* INTERRUPT_CORE1_UART4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_UART4_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_UART4_INT_MAP_M ((INTERRUPT_CORE1_UART4_INT_MAP_V)<<(INTERRUPT_CORE1_UART4_INT_MAP_S)) -#define INTERRUPT_CORE1_UART4_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_UART4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8c) +/** INTERRUPT_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_UART4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_UART4_INT_MAP_M (INTERRUPT_CORE1_UART4_INT_MAP_V << INTERRUPT_CORE1_UART4_INT_MAP_S) +#define INTERRUPT_CORE1_UART4_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_UART4_INT_MAP_S 0 -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90) -/* INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE1_LCD_CAM_INT_MAP_S)) -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90) +/** INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M (INTERRUPT_CORE1_LCD_CAM_INT_MAP_V << INTERRUPT_CORE1_LCD_CAM_INT_MAP_S) +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S 0 -#define INTERRUPT_CORE1_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94) -/* INTERRUPT_CORE1_ADC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_ADC_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_ADC_INT_MAP_M ((INTERRUPT_CORE1_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_ADC_INT_MAP_S)) -#define INTERRUPT_CORE1_ADC_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94) +/** INTERRUPT_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ADC_INT_MAP_M (INTERRUPT_CORE1_ADC_INT_MAP_V << INTERRUPT_CORE1_ADC_INT_MAP_S) +#define INTERRUPT_CORE1_ADC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_ADC_INT_MAP_S 0 -#define INTERRUPT_CORE1_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98) -/* INTERRUPT_CORE1_PWM0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PWM0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PWM0_INT_MAP_M ((INTERRUPT_CORE1_PWM0_INT_MAP_V)<<(INTERRUPT_CORE1_PWM0_INT_MAP_S)) -#define INTERRUPT_CORE1_PWM0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PWM0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98) +/** INTERRUPT_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PWM0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PWM0_INT_MAP_M (INTERRUPT_CORE1_PWM0_INT_MAP_V << INTERRUPT_CORE1_PWM0_INT_MAP_S) +#define INTERRUPT_CORE1_PWM0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PWM0_INT_MAP_S 0 -#define INTERRUPT_CORE1_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x9C) -/* INTERRUPT_CORE1_PWM1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PWM1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PWM1_INT_MAP_M ((INTERRUPT_CORE1_PWM1_INT_MAP_V)<<(INTERRUPT_CORE1_PWM1_INT_MAP_S)) -#define INTERRUPT_CORE1_PWM1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PWM1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x9c) +/** INTERRUPT_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PWM1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PWM1_INT_MAP_M (INTERRUPT_CORE1_PWM1_INT_MAP_V << INTERRUPT_CORE1_PWM1_INT_MAP_S) +#define INTERRUPT_CORE1_PWM1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PWM1_INT_MAP_S 0 -#define INTERRUPT_CORE1_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xA0) -/* INTERRUPT_CORE1_CAN0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CAN0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_CAN0_INT_MAP_M ((INTERRUPT_CORE1_CAN0_INT_MAP_V)<<(INTERRUPT_CORE1_CAN0_INT_MAP_S)) -#define INTERRUPT_CORE1_CAN0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_CAN0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa0) +/** INTERRUPT_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CAN0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CAN0_INT_MAP_M (INTERRUPT_CORE1_CAN0_INT_MAP_V << INTERRUPT_CORE1_CAN0_INT_MAP_S) +#define INTERRUPT_CORE1_CAN0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CAN0_INT_MAP_S 0 -#define INTERRUPT_CORE1_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xA4) -/* INTERRUPT_CORE1_CAN1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CAN1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_CAN1_INT_MAP_M ((INTERRUPT_CORE1_CAN1_INT_MAP_V)<<(INTERRUPT_CORE1_CAN1_INT_MAP_S)) -#define INTERRUPT_CORE1_CAN1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_CAN1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa4) +/** INTERRUPT_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CAN1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CAN1_INT_MAP_M (INTERRUPT_CORE1_CAN1_INT_MAP_V << INTERRUPT_CORE1_CAN1_INT_MAP_S) +#define INTERRUPT_CORE1_CAN1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CAN1_INT_MAP_S 0 -#define INTERRUPT_CORE1_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xA8) -/* INTERRUPT_CORE1_CAN2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CAN2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_CAN2_INT_MAP_M ((INTERRUPT_CORE1_CAN2_INT_MAP_V)<<(INTERRUPT_CORE1_CAN2_INT_MAP_S)) -#define INTERRUPT_CORE1_CAN2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_CAN2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa8) +/** INTERRUPT_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CAN2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CAN2_INT_MAP_M (INTERRUPT_CORE1_CAN2_INT_MAP_V << INTERRUPT_CORE1_CAN2_INT_MAP_S) +#define INTERRUPT_CORE1_CAN2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CAN2_INT_MAP_S 0 -#define INTERRUPT_CORE1_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xAC) -/* INTERRUPT_CORE1_RMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_RMT_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_RMT_INT_MAP_M ((INTERRUPT_CORE1_RMT_INT_MAP_V)<<(INTERRUPT_CORE1_RMT_INT_MAP_S)) -#define INTERRUPT_CORE1_RMT_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_RMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xac) +/** INTERRUPT_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_RMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_RMT_INT_MAP_M (INTERRUPT_CORE1_RMT_INT_MAP_V << INTERRUPT_CORE1_RMT_INT_MAP_S) +#define INTERRUPT_CORE1_RMT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_RMT_INT_MAP_S 0 -#define INTERRUPT_CORE1_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xB0) -/* INTERRUPT_CORE1_I2C0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_I2C0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_I2C0_INT_MAP_M ((INTERRUPT_CORE1_I2C0_INT_MAP_V)<<(INTERRUPT_CORE1_I2C0_INT_MAP_S)) -#define INTERRUPT_CORE1_I2C0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_I2C0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb0) +/** INTERRUPT_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2C0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2C0_INT_MAP_M (INTERRUPT_CORE1_I2C0_INT_MAP_V << INTERRUPT_CORE1_I2C0_INT_MAP_S) +#define INTERRUPT_CORE1_I2C0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_I2C0_INT_MAP_S 0 -#define INTERRUPT_CORE1_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xB4) -/* INTERRUPT_CORE1_I2C1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_I2C1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_I2C1_INT_MAP_M ((INTERRUPT_CORE1_I2C1_INT_MAP_V)<<(INTERRUPT_CORE1_I2C1_INT_MAP_S)) -#define INTERRUPT_CORE1_I2C1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_I2C1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb4) +/** INTERRUPT_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I2C1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I2C1_INT_MAP_M (INTERRUPT_CORE1_I2C1_INT_MAP_V << INTERRUPT_CORE1_I2C1_INT_MAP_S) +#define INTERRUPT_CORE1_I2C1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_I2C1_INT_MAP_S 0 -#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xB8) -/* INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_M ((INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S)) -#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb8) +/** INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_S 0 -#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xBC) -/* INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_M ((INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S)) -#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xbc) +/** INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_S 0 -#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xC0) -/* INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_M ((INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S)) -#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc0) +/** INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xC4) -/* INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_M ((INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S)) -#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc4) +/** INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_S 0 -#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xC8) -/* INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_M ((INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S)) -#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc8) +/** INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_S 0 -#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xCC) -/* INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_M ((INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S)) -#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xcc) +/** INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_M (INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V << INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xD0) -/* INTERRUPT_CORE1_LEDC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LEDC_INT_MAP_M ((INTERRUPT_CORE1_LEDC_INT_MAP_V)<<(INTERRUPT_CORE1_LEDC_INT_MAP_S)) -#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LEDC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd0) +/** INTERRUPT_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LEDC_INT_MAP_M (INTERRUPT_CORE1_LEDC_INT_MAP_V << INTERRUPT_CORE1_LEDC_INT_MAP_S) +#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LEDC_INT_MAP_S 0 -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xD4) -/* INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S)) -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd4) +/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M (INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xD8) -/* INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S)) -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd8) +/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M (INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xDC) -/* INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S)) -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xdc) +/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M (INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xE0) -/* INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe0) +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xE4) -/* INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe4) +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xE8) -/* INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe8) +/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xEC) -/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xec) +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xF0) -/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf0) +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xF4) -/* INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf4) +/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xF8) -/* INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf8) +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xFC) -/* INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xfc) +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x100) -/* INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x100) +/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x104) -/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x104) +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x108) -/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x108) +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10C) -/* INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10c) +/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x110) -/* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_RSA_INT_MAP_M ((INTERRUPT_CORE1_RSA_INT_MAP_V)<<(INTERRUPT_CORE1_RSA_INT_MAP_S)) -#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_RSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x110) +/** INTERRUPT_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_RSA_INT_MAP_M (INTERRUPT_CORE1_RSA_INT_MAP_V << INTERRUPT_CORE1_RSA_INT_MAP_S) +#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_RSA_INT_MAP_S 0 -#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x114) -/* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_AES_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_AES_INT_MAP_M ((INTERRUPT_CORE1_AES_INT_MAP_V)<<(INTERRUPT_CORE1_AES_INT_MAP_S)) -#define INTERRUPT_CORE1_AES_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_AES_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x114) +/** INTERRUPT_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_AES_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_AES_INT_MAP_M (INTERRUPT_CORE1_AES_INT_MAP_V << INTERRUPT_CORE1_AES_INT_MAP_S) +#define INTERRUPT_CORE1_AES_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_AES_INT_MAP_S 0 -#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x118) -/* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SHA_INT_MAP_M ((INTERRUPT_CORE1_SHA_INT_MAP_V)<<(INTERRUPT_CORE1_SHA_INT_MAP_S)) -#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SHA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x118) +/** INTERRUPT_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SHA_INT_MAP_M (INTERRUPT_CORE1_SHA_INT_MAP_V << INTERRUPT_CORE1_SHA_INT_MAP_S) +#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SHA_INT_MAP_S 0 -#define INTERRUPT_CORE1_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x11C) -/* INTERRUPT_CORE1_ECC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_ECC_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_ECC_INT_MAP_M ((INTERRUPT_CORE1_ECC_INT_MAP_V)<<(INTERRUPT_CORE1_ECC_INT_MAP_S)) -#define INTERRUPT_CORE1_ECC_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_ECC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x11c) +/** INTERRUPT_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ECC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ECC_INT_MAP_M (INTERRUPT_CORE1_ECC_INT_MAP_V << INTERRUPT_CORE1_ECC_INT_MAP_S) +#define INTERRUPT_CORE1_ECC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_ECC_INT_MAP_S 0 -#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x120) -/* INTERRUPT_CORE1_ECDSA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_ECDSA_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_ECDSA_INT_MAP_M ((INTERRUPT_CORE1_ECDSA_INT_MAP_V)<<(INTERRUPT_CORE1_ECDSA_INT_MAP_S)) -#define INTERRUPT_CORE1_ECDSA_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_ECDSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x120) +/** INTERRUPT_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ECDSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ECDSA_INT_MAP_M (INTERRUPT_CORE1_ECDSA_INT_MAP_V << INTERRUPT_CORE1_ECDSA_INT_MAP_S) +#define INTERRUPT_CORE1_ECDSA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_ECDSA_INT_MAP_S 0 -#define INTERRUPT_CORE1_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x124) -/* INTERRUPT_CORE1_KM_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_KM_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_KM_INT_MAP_M ((INTERRUPT_CORE1_KM_INT_MAP_V)<<(INTERRUPT_CORE1_KM_INT_MAP_S)) -#define INTERRUPT_CORE1_KM_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_KM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x124) +/** INTERRUPT_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_KM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_KM_INT_MAP_M (INTERRUPT_CORE1_KM_INT_MAP_V << INTERRUPT_CORE1_KM_INT_MAP_S) +#define INTERRUPT_CORE1_KM_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_KM_INT_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x128) -/* INTERRUPT_CORE1_GPIO_INT0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_GPIO_INT0_MAP 0x0000003F -#define INTERRUPT_CORE1_GPIO_INT0_MAP_M ((INTERRUPT_CORE1_GPIO_INT0_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT0_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INT0_MAP_V 0x3F +/** INTERRUPT_CORE1_GPIO_INT0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x128) +/** INTERRUPT_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT0_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT0_MAP_M (INTERRUPT_CORE1_GPIO_INT0_MAP_V << INTERRUPT_CORE1_GPIO_INT0_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT0_MAP_V 0x0000003FU #define INTERRUPT_CORE1_GPIO_INT0_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x12C) -/* INTERRUPT_CORE1_GPIO_INT1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_GPIO_INT1_MAP 0x0000003F -#define INTERRUPT_CORE1_GPIO_INT1_MAP_M ((INTERRUPT_CORE1_GPIO_INT1_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT1_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INT1_MAP_V 0x3F +/** INTERRUPT_CORE1_GPIO_INT1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x12c) +/** INTERRUPT_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT1_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT1_MAP_M (INTERRUPT_CORE1_GPIO_INT1_MAP_V << INTERRUPT_CORE1_GPIO_INT1_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT1_MAP_V 0x0000003FU #define INTERRUPT_CORE1_GPIO_INT1_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x130) -/* INTERRUPT_CORE1_GPIO_INT2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_GPIO_INT2_MAP 0x0000003F -#define INTERRUPT_CORE1_GPIO_INT2_MAP_M ((INTERRUPT_CORE1_GPIO_INT2_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT2_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INT2_MAP_V 0x3F +/** INTERRUPT_CORE1_GPIO_INT2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x130) +/** INTERRUPT_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT2_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT2_MAP_M (INTERRUPT_CORE1_GPIO_INT2_MAP_V << INTERRUPT_CORE1_GPIO_INT2_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT2_MAP_V 0x0000003FU #define INTERRUPT_CORE1_GPIO_INT2_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x134) -/* INTERRUPT_CORE1_GPIO_INT3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_GPIO_INT3_MAP 0x0000003F -#define INTERRUPT_CORE1_GPIO_INT3_MAP_M ((INTERRUPT_CORE1_GPIO_INT3_MAP_V)<<(INTERRUPT_CORE1_GPIO_INT3_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INT3_MAP_V 0x3F +/** INTERRUPT_CORE1_GPIO_INT3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x134) +/** INTERRUPT_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT3_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_INT3_MAP_M (INTERRUPT_CORE1_GPIO_INT3_MAP_V << INTERRUPT_CORE1_GPIO_INT3_MAP_S) +#define INTERRUPT_CORE1_GPIO_INT3_MAP_V 0x0000003FU #define INTERRUPT_CORE1_GPIO_INT3_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x138) -/* INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_M ((INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V)<<(INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S)) -#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x138) +/** INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_M (INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V << INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S) +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x13C) -/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP 0x0000003F -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_M ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S)) -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V 0x3F +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x13c) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x140) -/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP 0x0000003F -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_M ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S)) -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V 0x3F +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x140) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x144) -/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP 0x0000003F -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_M ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S)) -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V 0x3F +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x144) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x148) -/* INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP 0x0000003F -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_M ((INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S)) -#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V 0x3F +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x148) +/** INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_M (INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V << INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_S 0 -#define INTERRUPT_CORE1_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14C) -/* INTERRUPT_CORE1_CACHE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CACHE_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_CACHE_INT_MAP_M ((INTERRUPT_CORE1_CACHE_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_INT_MAP_S)) -#define INTERRUPT_CORE1_CACHE_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_CACHE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14c) +/** INTERRUPT_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CACHE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CACHE_INT_MAP_M (INTERRUPT_CORE1_CACHE_INT_MAP_V << INTERRUPT_CORE1_CACHE_INT_MAP_S) +#define INTERRUPT_CORE1_CACHE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CACHE_INT_MAP_S 0 -#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x150) -/* INTERRUPT_CORE1_FLASH_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_M ((INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V)<<(INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S)) -#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x150) +/** INTERRUPT_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_M (INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V << INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S) +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_S 0 -#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x154) -/* INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_M ((INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S)) -#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x154) +/** INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_M (INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V << INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_S 0 -#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x158) -/* INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_M ((INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V)<<(INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S)) -#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x158) +/** INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_M (INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V << INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_S 0 -#define INTERRUPT_CORE1_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x15C) -/* INTERRUPT_CORE1_CSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CSI_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_CSI_INT_MAP_M ((INTERRUPT_CORE1_CSI_INT_MAP_V)<<(INTERRUPT_CORE1_CSI_INT_MAP_S)) -#define INTERRUPT_CORE1_CSI_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_CSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x15c) +/** INTERRUPT_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CSI_INT_MAP_M (INTERRUPT_CORE1_CSI_INT_MAP_V << INTERRUPT_CORE1_CSI_INT_MAP_S) +#define INTERRUPT_CORE1_CSI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CSI_INT_MAP_S 0 -#define INTERRUPT_CORE1_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x160) -/* INTERRUPT_CORE1_DSI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_DSI_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_DSI_INT_MAP_M ((INTERRUPT_CORE1_DSI_INT_MAP_V)<<(INTERRUPT_CORE1_DSI_INT_MAP_S)) -#define INTERRUPT_CORE1_DSI_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_DSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x160) +/** INTERRUPT_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DSI_INT_MAP_M (INTERRUPT_CORE1_DSI_INT_MAP_V << INTERRUPT_CORE1_DSI_INT_MAP_S) +#define INTERRUPT_CORE1_DSI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_DSI_INT_MAP_S 0 -#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x164) -/* INTERRUPT_CORE1_GMII_PHY_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_GMII_PHY_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_M ((INTERRUPT_CORE1_GMII_PHY_INT_MAP_V)<<(INTERRUPT_CORE1_GMII_PHY_INT_MAP_S)) -#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x164) +/** INTERRUPT_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_M (INTERRUPT_CORE1_GMII_PHY_INT_MAP_V << INTERRUPT_CORE1_GMII_PHY_INT_MAP_S) +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_GMII_PHY_INT_MAP_S 0 -#define INTERRUPT_CORE1_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x168) -/* INTERRUPT_CORE1_LPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_LPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_LPI_INT_MAP_M ((INTERRUPT_CORE1_LPI_INT_MAP_V)<<(INTERRUPT_CORE1_LPI_INT_MAP_S)) -#define INTERRUPT_CORE1_LPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_LPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x168) +/** INTERRUPT_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_LPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_LPI_INT_MAP_M (INTERRUPT_CORE1_LPI_INT_MAP_V << INTERRUPT_CORE1_LPI_INT_MAP_S) +#define INTERRUPT_CORE1_LPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_LPI_INT_MAP_S 0 -#define INTERRUPT_CORE1_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x16C) -/* INTERRUPT_CORE1_PMT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PMT_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PMT_INT_MAP_M ((INTERRUPT_CORE1_PMT_INT_MAP_V)<<(INTERRUPT_CORE1_PMT_INT_MAP_S)) -#define INTERRUPT_CORE1_PMT_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x16c) +/** INTERRUPT_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PMT_INT_MAP_M (INTERRUPT_CORE1_PMT_INT_MAP_V << INTERRUPT_CORE1_PMT_INT_MAP_S) +#define INTERRUPT_CORE1_PMT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PMT_INT_MAP_S 0 -#define INTERRUPT_CORE1_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x170) -/* INTERRUPT_CORE1_SBD_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_SBD_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_SBD_INT_MAP_M ((INTERRUPT_CORE1_SBD_INT_MAP_V)<<(INTERRUPT_CORE1_SBD_INT_MAP_S)) -#define INTERRUPT_CORE1_SBD_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_SBD_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x170) +/** INTERRUPT_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_SBD_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_SBD_INT_MAP_M (INTERRUPT_CORE1_SBD_INT_MAP_V << INTERRUPT_CORE1_SBD_INT_MAP_S) +#define INTERRUPT_CORE1_SBD_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_SBD_INT_MAP_S 0 -#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x174) -/* INTERRUPT_CORE1_USB_OTG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_USB_OTG_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_USB_OTG_INT_MAP_M ((INTERRUPT_CORE1_USB_OTG_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG_INT_MAP_S)) -#define INTERRUPT_CORE1_USB_OTG_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_USB_OTG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x174) +/** INTERRUPT_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_M (INTERRUPT_CORE1_USB_OTG_INT_MAP_V << INTERRUPT_CORE1_USB_OTG_INT_MAP_S) +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_USB_OTG_INT_MAP_S 0 -#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x178) -/* INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M ((INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)) -#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x178) +/** INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 -#define INTERRUPT_CORE1_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x17C) -/* INTERRUPT_CORE1_JPEG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_JPEG_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_JPEG_INT_MAP_M ((INTERRUPT_CORE1_JPEG_INT_MAP_V)<<(INTERRUPT_CORE1_JPEG_INT_MAP_S)) -#define INTERRUPT_CORE1_JPEG_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_JPEG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x17c) +/** INTERRUPT_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_JPEG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_JPEG_INT_MAP_M (INTERRUPT_CORE1_JPEG_INT_MAP_V << INTERRUPT_CORE1_JPEG_INT_MAP_S) +#define INTERRUPT_CORE1_JPEG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_JPEG_INT_MAP_S 0 -#define INTERRUPT_CORE1_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x180) -/* INTERRUPT_CORE1_PPA_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PPA_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PPA_INT_MAP_M ((INTERRUPT_CORE1_PPA_INT_MAP_V)<<(INTERRUPT_CORE1_PPA_INT_MAP_S)) -#define INTERRUPT_CORE1_PPA_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PPA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x180) +/** INTERRUPT_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PPA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PPA_INT_MAP_M (INTERRUPT_CORE1_PPA_INT_MAP_V << INTERRUPT_CORE1_PPA_INT_MAP_S) +#define INTERRUPT_CORE1_PPA_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PPA_INT_MAP_S 0 -#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x184) -/* INTERRUPT_CORE1_CORE0_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_M ((INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V)<<(INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S)) -#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x184) +/** INTERRUPT_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_M (INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V << INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_S 0 -#define INTERRUPT_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x188) -/* INTERRUPT_CORE1_TRACE_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_TRACE_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_TRACE_INT_MAP_M ((INTERRUPT_CORE1_TRACE_INT_MAP_V)<<(INTERRUPT_CORE1_TRACE_INT_MAP_S)) -#define INTERRUPT_CORE1_TRACE_INT_MAP_V 0x3F -#define INTERRUPT_CORE1_TRACE_INT_MAP_S 0 +/** INTERRUPT_CORE1_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x188) +/** INTERRUPT_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_M (INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_V << INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_S 0 -#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18C) -/* INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_M ((INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V)<<(INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S)) -#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18c) +/** INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_M (INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V << INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S) +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_S 0 -#define INTERRUPT_CORE1_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x190) -/* INTERRUPT_CORE1_ISP_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_ISP_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_ISP_INT_MAP_M ((INTERRUPT_CORE1_ISP_INT_MAP_V)<<(INTERRUPT_CORE1_ISP_INT_MAP_S)) -#define INTERRUPT_CORE1_ISP_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_ISP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x190) +/** INTERRUPT_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ISP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ISP_INT_MAP_M (INTERRUPT_CORE1_ISP_INT_MAP_V << INTERRUPT_CORE1_ISP_INT_MAP_S) +#define INTERRUPT_CORE1_ISP_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_ISP_INT_MAP_S 0 -#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x194) -/* INTERRUPT_CORE1_I3C_MST_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_I3C_MST_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_I3C_MST_INT_MAP_M ((INTERRUPT_CORE1_I3C_MST_INT_MAP_V)<<(INTERRUPT_CORE1_I3C_MST_INT_MAP_S)) -#define INTERRUPT_CORE1_I3C_MST_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_I3C_MST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x194) +/** INTERRUPT_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I3C_MST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_M (INTERRUPT_CORE1_I3C_MST_INT_MAP_V << INTERRUPT_CORE1_I3C_MST_INT_MAP_S) +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_I3C_MST_INT_MAP_S 0 -#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x198) -/* INTERRUPT_CORE1_I3C_SLV_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_I3C_SLV_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_M ((INTERRUPT_CORE1_I3C_SLV_INT_MAP_V)<<(INTERRUPT_CORE1_I3C_SLV_INT_MAP_S)) -#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x198) +/** INTERRUPT_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_M (INTERRUPT_CORE1_I3C_SLV_INT_MAP_V << INTERRUPT_CORE1_I3C_SLV_INT_MAP_S) +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_I3C_SLV_INT_MAP_S 0 -#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19C) -/* INTERRUPT_CORE1_USB_OTG11_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_USB_OTG11_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_M ((INTERRUPT_CORE1_USB_OTG11_INT_MAP_V)<<(INTERRUPT_CORE1_USB_OTG11_INT_MAP_S)) -#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19c) +/** INTERRUPT_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_M (INTERRUPT_CORE1_USB_OTG11_INT_MAP_V << INTERRUPT_CORE1_USB_OTG11_INT_MAP_S) +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_USB_OTG11_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1A0) -/* INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a0) +/** INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1A4) -/* INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a4) +/** INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1A8) -/* INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a8) +/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1AC) -/* INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ac) +/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1B0) -/* INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b0) +/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1B4) -/* INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_M ((INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V)<<(INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S)) -#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b4) +/** INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_M (INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V << INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S) +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_S 0 -#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1B8) -/* INTERRUPT_CORE1_HP_SYSREG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_M ((INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V)<<(INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S)) -#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b8) +/** INTERRUPT_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_M (INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V << INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_S 0 -#define INTERRUPT_CORE1_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1BC) -/* INTERRUPT_CORE1_PCNT_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_PCNT_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_PCNT_INT_MAP_M ((INTERRUPT_CORE1_PCNT_INT_MAP_V)<<(INTERRUPT_CORE1_PCNT_INT_MAP_S)) -#define INTERRUPT_CORE1_PCNT_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_PCNT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1bc) +/** INTERRUPT_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_PCNT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_PCNT_INT_MAP_M (INTERRUPT_CORE1_PCNT_INT_MAP_V << INTERRUPT_CORE1_PCNT_INT_MAP_S) +#define INTERRUPT_CORE1_PCNT_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_PCNT_INT_MAP_S 0 -#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1C0) -/* INTERRUPT_CORE1_HP_PAU_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_HP_PAU_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_HP_PAU_INT_MAP_M ((INTERRUPT_CORE1_HP_PAU_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PAU_INT_MAP_S)) -#define INTERRUPT_CORE1_HP_PAU_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_HP_PAU_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c0) +/** INTERRUPT_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_PAU_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_M (INTERRUPT_CORE1_HP_PAU_INT_MAP_V << INTERRUPT_CORE1_HP_PAU_INT_MAP_S) +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_HP_PAU_INT_MAP_S 0 -#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1C4) -/* INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_M ((INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S)) -#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c4) +/** INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_M (INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V << INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S) +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_S 0 -#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1C8) -/* INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_M ((INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V)<<(INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S)) -#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c8) +/** INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_M (INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V << INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S) +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1CC) -/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1cc) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1D0) -/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d0) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1D4) -/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d4) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1D8) -/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d8) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1DC) -/* INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1dc) +/** INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1E0) -/* INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e0) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1E4) -/* INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e4) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1E8) -/* INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e8) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1EC) -/* INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ec) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1F0) -/* INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f0) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1F4) -/* INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M ((INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V)<<(INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f4) +/** INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M (INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S) +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S 0 -#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1F8) -/* INTERRUPT_CORE1_H264_REG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_H264_REG_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_H264_REG_INT_MAP_M ((INTERRUPT_CORE1_H264_REG_INT_MAP_V)<<(INTERRUPT_CORE1_H264_REG_INT_MAP_S)) -#define INTERRUPT_CORE1_H264_REG_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_H264_REG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f8) +/** INTERRUPT_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_H264_REG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_H264_REG_INT_MAP_M (INTERRUPT_CORE1_H264_REG_INT_MAP_V << INTERRUPT_CORE1_H264_REG_INT_MAP_S) +#define INTERRUPT_CORE1_H264_REG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_H264_REG_INT_MAP_S 0 -#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1FC) -/* INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP 0x0000003F -#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_M ((INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V)<<(INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S)) -#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V 0x3F +/** INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1fc) +/** INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_M (INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V << INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S) +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_V 0x0000003FU #define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_S 0 -#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x200) -/* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_0_M ((INTERRUPT_CORE1_INTR_STATUS_0_V)<<(INTERRUPT_CORE1_INTR_STATUS_0_S)) -#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFF +/** INTERRUPT_CORE1_INTR_STATUS_REG_0_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x200) +/** INTERRUPT_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_0_M (INTERRUPT_CORE1_INTR_STATUS_0_V << INTERRUPT_CORE1_INTR_STATUS_0_S) +#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFFU #define INTERRUPT_CORE1_INTR_STATUS_0_S 0 -#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x204) -/* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_1_M ((INTERRUPT_CORE1_INTR_STATUS_1_V)<<(INTERRUPT_CORE1_INTR_STATUS_1_S)) -#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFF +/** INTERRUPT_CORE1_INTR_STATUS_REG_1_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x204) +/** INTERRUPT_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_1_M (INTERRUPT_CORE1_INTR_STATUS_1_V << INTERRUPT_CORE1_INTR_STATUS_1_S) +#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFFU #define INTERRUPT_CORE1_INTR_STATUS_1_S 0 -#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x208) -/* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_2_M ((INTERRUPT_CORE1_INTR_STATUS_2_V)<<(INTERRUPT_CORE1_INTR_STATUS_2_S)) -#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFF +/** INTERRUPT_CORE1_INTR_STATUS_REG_2_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x208) +/** INTERRUPT_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_2_M (INTERRUPT_CORE1_INTR_STATUS_2_V << INTERRUPT_CORE1_INTR_STATUS_2_S) +#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFFU #define INTERRUPT_CORE1_INTR_STATUS_2_S 0 -#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20C) -/* INTERRUPT_CORE1_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_INTR_STATUS_3 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_3_M ((INTERRUPT_CORE1_INTR_STATUS_3_V)<<(INTERRUPT_CORE1_INTR_STATUS_3_S)) -#define INTERRUPT_CORE1_INTR_STATUS_3_V 0xFFFFFFFF +/** INTERRUPT_CORE1_INTR_STATUS_REG_3_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20c) +/** INTERRUPT_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_3 0xFFFFFFFFU +#define INTERRUPT_CORE1_INTR_STATUS_3_M (INTERRUPT_CORE1_INTR_STATUS_3_V << INTERRUPT_CORE1_INTR_STATUS_3_S) +#define INTERRUPT_CORE1_INTR_STATUS_3_V 0xFFFFFFFFU #define INTERRUPT_CORE1_INTR_STATUS_3_S 0 -#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x210) -/* INTERRUPT_CORE1_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ +/** INTERRUPT_CORE1_CLOCK_GATE_REG register + * NA + */ +#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x210) +/** INTERRUPT_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * NA + */ #define INTERRUPT_CORE1_REG_CLK_EN (BIT(0)) -#define INTERRUPT_CORE1_REG_CLK_EN_M (BIT(0)) -#define INTERRUPT_CORE1_REG_CLK_EN_V 0x1 +#define INTERRUPT_CORE1_REG_CLK_EN_M (INTERRUPT_CORE1_REG_CLK_EN_V << INTERRUPT_CORE1_REG_CLK_EN_S) +#define INTERRUPT_CORE1_REG_CLK_EN_V 0x00000001U #define INTERRUPT_CORE1_REG_CLK_EN_S 0 -#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3FC) -/* INTERRUPT_CORE1_INTERRUPT_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ -/*description: .*/ -#define INTERRUPT_CORE1_INTERRUPT_REG_DATE 0x0FFFFFFF -#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_M ((INTERRUPT_CORE1_INTERRUPT_REG_DATE_V)<<(INTERRUPT_CORE1_INTERRUPT_REG_DATE_S)) -#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_V 0xFFFFFFF +/** INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG register + * NA + */ +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3fc) +/** INTERRUPT_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_M (INTERRUPT_CORE1_INTERRUPT_REG_DATE_V << INTERRUPT_CORE1_INTERRUPT_REG_DATE_S) +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_V 0x0FFFFFFFU #define INTERRUPT_CORE1_INTERRUPT_REG_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_INTERRUPT_CORE1_REG_H_ */ diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_struct.h b/components/soc/esp32p4/include/soc/interrupt_core1_struct.h new file mode 100644 index 0000000000..8ded5f7582 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupt_core1_struct.h @@ -0,0 +1,2298 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: INTERRUPT CORE1LP RTC INT MAP REG */ +/** Type of lp_rtc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_rtc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_rtc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP WDT INT MAP REG */ +/** Type of lp_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_wdt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TIMER REG 0 INT MAP REG */ +/** Type of lp_timer_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_timer_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_timer_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TIMER REG 1 INT MAP REG */ +/** Type of lp_timer_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_timer_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_timer_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1MB HP INT MAP REG */ +/** Type of mb_hp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_mb_hp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_mb_hp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1MB LP INT MAP REG */ +/** Type of mb_lp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_mb_lp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_mb_lp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PMU REG 0 INT MAP REG */ +/** Type of pmu_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pmu_reg_0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pmu_reg_0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PMU REG 1 INT MAP REG */ +/** Type of pmu_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pmu_reg_1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pmu_reg_1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP ANAPERI INT MAP REG */ +/** Type of lp_anaperi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_anaperi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_anaperi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP ADC INT MAP REG */ +/** Type of lp_adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_adc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP GPIO INT MAP REG */ +/** Type of lp_gpio_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_gpio_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_gpio_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP I2C INT MAP REG */ +/** Type of lp_i2c_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_i2c_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_i2c_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP I2S INT MAP REG */ +/** Type of lp_i2s_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_i2s_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_i2s_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP SPI INT MAP REG */ +/** Type of lp_spi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_spi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_spi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TOUCH INT MAP REG */ +/** Type of lp_touch_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_touch_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_touch_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP TSENS INT MAP REG */ +/** Type of lp_tsens_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_tsens_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_tsens_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP UART INT MAP REG */ +/** Type of lp_uart_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_uart_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_uart_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP EFUSE INT MAP REG */ +/** Type of lp_efuse_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_efuse_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_efuse_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP SW INT MAP REG */ +/** Type of lp_sw_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_sw_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_sw_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP SYSREG INT MAP REG */ +/** Type of lp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LP HUK INT MAP REG */ +/** Type of lp_huk_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lp_huk_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lp_huk_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYS ICM INT MAP REG */ +/** Type of sys_icm_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sys_icm_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sys_icm_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB DEVICE INT MAP REG */ +/** Type of usb_device_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_device_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_device_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SDIO HOST INT MAP REG */ +/** Type of sdio_host_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sdio_host_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sdio_host_int_map_reg_t; + + +/** Group: INTERRUPT CORE1GDMA INT MAP REG */ +/** Type of gdma_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gdma_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gdma_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SPI2 INT MAP REG */ +/** Type of spi2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_spi2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_spi2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SPI3 INT MAP REG */ +/** Type of spi3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_spi3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_spi3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2S0 INT MAP REG */ +/** Type of i2s0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2s0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2s0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2S1 INT MAP REG */ +/** Type of i2s1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2s1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2s1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2S2 INT MAP REG */ +/** Type of i2s2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2s2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2s2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UHCI0 INT MAP REG */ +/** Type of uhci0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uhci0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uhci0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART0 INT MAP REG */ +/** Type of uart0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART1 INT MAP REG */ +/** Type of uart1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART2 INT MAP REG */ +/** Type of uart2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART3 INT MAP REG */ +/** Type of uart3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1UART4 INT MAP REG */ +/** Type of uart4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_uart4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_uart4_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LCD CAM INT MAP REG */ +/** Type of lcd_cam_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lcd_cam_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lcd_cam_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ADC INT MAP REG */ +/** Type of adc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_adc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_adc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PWM0 INT MAP REG */ +/** Type of pwm0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pwm0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pwm0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PWM1 INT MAP REG */ +/** Type of pwm1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pwm1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pwm1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CAN0 INT MAP REG */ +/** Type of can0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_can0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_can0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_can0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CAN1 INT MAP REG */ +/** Type of can1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_can1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_can1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_can1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CAN2 INT MAP REG */ +/** Type of can2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_can2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_can2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_can2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1RMT INT MAP REG */ +/** Type of rmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_rmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_rmt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2C0 INT MAP REG */ +/** Type of i2c0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2c0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2c0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I2C1 INT MAP REG */ +/** Type of i2c1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i2c1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i2c1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP0 T0 INT MAP REG */ +/** Type of timergrp0_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp0_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp0_t0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP0 T1 INT MAP REG */ +/** Type of timergrp0_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp0_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp0_t1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP0 WDT INT MAP REG */ +/** Type of timergrp0_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp0_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp0_wdt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP1 T0 INT MAP REG */ +/** Type of timergrp1_t0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp1_t0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp1_t0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP1 T1 INT MAP REG */ +/** Type of timergrp1_t1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp1_t1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp1_t1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TIMERGRP1 WDT INT MAP REG */ +/** Type of timergrp1_wdt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_timergrp1_wdt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_timergrp1_wdt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LEDC INT MAP REG */ +/** Type of ledc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ledc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ledc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYSTIMER TARGET0 INT MAP REG */ +/** Type of systimer_target0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_systimer_target0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_systimer_target0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYSTIMER TARGET1 INT MAP REG */ +/** Type of systimer_target1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_systimer_target1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_systimer_target1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SYSTIMER TARGET2 INT MAP REG */ +/** Type of systimer_target2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_systimer_target2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_systimer_target2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA IN CH0 INT MAP REG */ +/** Type of ahb_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA IN CH1 INT MAP REG */ +/** Type of ahb_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA IN CH2 INT MAP REG */ +/** Type of ahb_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA OUT CH0 INT MAP REG */ +/** Type of ahb_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA OUT CH1 INT MAP REG */ +/** Type of ahb_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AHB PDMA OUT CH2 INT MAP REG */ +/** Type of ahb_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ahb_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ahb_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA IN CH0 INT MAP REG */ +/** Type of axi_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA IN CH1 INT MAP REG */ +/** Type of axi_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA IN CH2 INT MAP REG */ +/** Type of axi_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA OUT CH0 INT MAP REG */ +/** Type of axi_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA OUT CH1 INT MAP REG */ +/** Type of axi_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AXI PDMA OUT CH2 INT MAP REG */ +/** Type of axi_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_axi_pdma_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_axi_pdma_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1RSA INT MAP REG */ +/** Type of rsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_rsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_rsa_int_map_reg_t; + + +/** Group: INTERRUPT CORE1AES INT MAP REG */ +/** Type of aes_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_aes_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_aes_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_aes_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SHA INT MAP REG */ +/** Type of sha_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sha_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sha_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sha_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ECC INT MAP REG */ +/** Type of ecc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ecc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ecc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ECDSA INT MAP REG */ +/** Type of ecdsa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ecdsa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ecdsa_int_map_reg_t; + + +/** Group: INTERRUPT CORE1KM INT MAP REG */ +/** Type of km_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_km_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_km_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_km_int_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT0 MAP REG */ +/** Type of gpio_int0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int0_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT1 MAP REG */ +/** Type of gpio_int1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int1_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT2 MAP REG */ +/** Type of gpio_int2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int2_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO INT3 MAP REG */ +/** Type of gpio_int3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_int3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_int3_map_reg_t; + + +/** Group: INTERRUPT CORE1GPIO PAD COMP INT MAP REG */ +/** Type of gpio_pad_comp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gpio_pad_comp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gpio_pad_comp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 0 MAP REG */ +/** Type of cpu_int_from_cpu_0_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_0_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 1 MAP REG */ +/** Type of cpu_int_from_cpu_1_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_1_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 2 MAP REG */ +/** Type of cpu_int_from_cpu_2_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_2_map_reg_t; + + +/** Group: INTERRUPT CORE1CPU INT FROM CPU 3 MAP REG */ +/** Type of cpu_int_from_cpu_3_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cpu_int_from_cpu_3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cpu_int_from_cpu_3_map_reg_t; + + +/** Group: INTERRUPT CORE1CACHE INT MAP REG */ +/** Type of cache_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_cache_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_cache_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_cache_int_map_reg_t; + + +/** Group: INTERRUPT CORE1FLASH MSPI INT MAP REG */ +/** Type of flash_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_flash_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_flash_mspi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CSI BRIDGE INT MAP REG */ +/** Type of csi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_csi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_csi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DSI BRIDGE INT MAP REG */ +/** Type of dsi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dsi_bridge_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dsi_bridge_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CSI INT MAP REG */ +/** Type of csi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_csi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_csi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_csi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DSI INT MAP REG */ +/** Type of dsi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dsi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dsi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1GMII PHY INT MAP REG */ +/** Type of gmii_phy_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_gmii_phy_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_gmii_phy_int_map_reg_t; + + +/** Group: INTERRUPT CORE1LPI INT MAP REG */ +/** Type of lpi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_lpi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_lpi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PMT INT MAP REG */ +/** Type of pmt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pmt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pmt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1SBD INT MAP REG */ +/** Type of sbd_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_sbd_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_sbd_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB OTG INT MAP REG */ +/** Type of usb_otg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_otg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_otg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB OTG ENDP MULTI PROC INT MAP REG */ +/** Type of usb_otg_endp_multi_proc_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_otg_endp_multi_proc_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_otg_endp_multi_proc_int_map_reg_t; + + +/** Group: INTERRUPT CORE1JPEG INT MAP REG */ +/** Type of jpeg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_jpeg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_jpeg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PPA INT MAP REG */ +/** Type of ppa_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_ppa_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_ppa_int_map_reg_t; + + +/** Group: INTERRUPT CORE1CORE0 TRACE INT MAP REG */ +/** Type of core0_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_core0_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_core0_trace_int_map_reg_t; + + +/** Group: INTERRUPT CORE1TRACE INT MAP REG */ +/** Type of interrupt_core1_trace_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_trace_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_trace_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP CORE CTRL INT MAP REG */ +/** Type of hp_core_ctrl_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_core_ctrl_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_core_ctrl_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ISP INT MAP REG */ +/** Type of isp_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_isp_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_isp_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_isp_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I3C MST INT MAP REG */ +/** Type of i3c_mst_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i3c_mst_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i3c_mst_int_map_reg_t; + + +/** Group: INTERRUPT CORE1I3C SLV INT MAP REG */ +/** Type of i3c_slv_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_i3c_slv_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_i3c_slv_int_map_reg_t; + + +/** Group: INTERRUPT CORE1USB OTG11 INT MAP REG */ +/** Type of usb_otg11_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_usb_otg11_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_usb_otg11_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D IN CH0 INT MAP REG */ +/** Type of dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D IN CH1 INT MAP REG */ +/** Type of dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D OUT CH0 INT MAP REG */ +/** Type of dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D OUT CH1 INT MAP REG */ +/** Type of dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1DMA2D OUT CH2 INT MAP REG */ +/** Type of dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PSRAM MSPI INT MAP REG */ +/** Type of psram_mspi_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_psram_mspi_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_psram_mspi_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP SYSREG INT MAP REG */ +/** Type of hp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_sysreg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_sysreg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1PCNT INT MAP REG */ +/** Type of pcnt_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_pcnt_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_pcnt_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP PAU INT MAP REG */ +/** Type of hp_pau_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_pau_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_pau_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP PARLIO RX INT MAP REG */ +/** Type of hp_parlio_rx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_parlio_rx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_parlio_rx_int_map_reg_t; + + +/** Group: INTERRUPT CORE1HP PARLIO TX INT MAP REG */ +/** Type of hp_parlio_tx_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_hp_parlio_tx_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_hp_parlio_tx_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH0 INT MAP REG */ +/** Type of h264_dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH1 INT MAP REG */ +/** Type of h264_dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH2 INT MAP REG */ +/** Type of h264_dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH3 INT MAP REG */ +/** Type of h264_dma2d_out_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D OUT CH4 INT MAP REG */ +/** Type of h264_dma2d_out_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_out_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_out_ch4_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH0 INT MAP REG */ +/** Type of h264_dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch0_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch0_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH1 INT MAP REG */ +/** Type of h264_dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch1_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch1_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH2 INT MAP REG */ +/** Type of h264_dma2d_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch2_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch2_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH3 INT MAP REG */ +/** Type of h264_dma2d_in_ch3_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch3_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch3_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH4 INT MAP REG */ +/** Type of h264_dma2d_in_ch4_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch4_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch4_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 DMA2D IN CH5 INT MAP REG */ +/** Type of h264_dma2d_in_ch5_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_dma2d_in_ch5_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_dma2d_in_ch5_int_map_reg_t; + + +/** Group: INTERRUPT CORE1H264 REG INT MAP REG */ +/** Type of h264_reg_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_h264_reg_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_h264_reg_int_map_reg_t; + + +/** Group: INTERRUPT CORE1ASSIST DEBUG INT MAP REG */ +/** Type of assist_debug_int_map register + * NA + */ +typedef union { + struct { + /** interrupt_core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_assist_debug_int_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core1_assist_debug_int_map_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 0 REG */ +/** Type of intr_status_reg_0 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_0:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_0_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 1 REG */ +/** Type of intr_status_reg_1 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_1:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_1_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 2 REG */ +/** Type of intr_status_reg_2 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_2:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_2_reg_t; + + +/** Group: INTERRUPT CORE1INTR STATUS REG 3 REG */ +/** Type of intr_status_reg_3 register + * NA + */ +typedef union { + struct { + /** interrupt_core1_intr_status_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t interrupt_core1_intr_status_3:32; + }; + uint32_t val; +} interrupt_core1_intr_status_reg_3_reg_t; + + +/** Group: INTERRUPT CORE1CLOCK GATE REG */ +/** Type of clock_gate register + * NA + */ +typedef union { + struct { + /** interrupt_core1_reg_clk_en : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t interrupt_core1_reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_core1_clock_gate_reg_t; + + +/** Group: INTERRUPT CORE1INTERRUPT REG DATE REG */ +/** Type of interrupt_reg_date register + * NA + */ +typedef union { + struct { + /** interrupt_core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 33566752; + * NA + */ + uint32_t interrupt_core1_interrupt_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_core1_interrupt_reg_date_reg_t; + + +typedef struct { + volatile interrupt_core1_lp_rtc_int_map_reg_t lp_rtc_int_map; + volatile interrupt_core1_lp_wdt_int_map_reg_t lp_wdt_int_map; + volatile interrupt_core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; + volatile interrupt_core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; + volatile interrupt_core1_mb_hp_int_map_reg_t mb_hp_int_map; + volatile interrupt_core1_mb_lp_int_map_reg_t mb_lp_int_map; + volatile interrupt_core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; + volatile interrupt_core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; + volatile interrupt_core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map; + volatile interrupt_core1_lp_adc_int_map_reg_t lp_adc_int_map; + volatile interrupt_core1_lp_gpio_int_map_reg_t lp_gpio_int_map; + volatile interrupt_core1_lp_i2c_int_map_reg_t lp_i2c_int_map; + volatile interrupt_core1_lp_i2s_int_map_reg_t lp_i2s_int_map; + volatile interrupt_core1_lp_spi_int_map_reg_t lp_spi_int_map; + volatile interrupt_core1_lp_touch_int_map_reg_t lp_touch_int_map; + volatile interrupt_core1_lp_tsens_int_map_reg_t lp_tsens_int_map; + volatile interrupt_core1_lp_uart_int_map_reg_t lp_uart_int_map; + volatile interrupt_core1_lp_efuse_int_map_reg_t lp_efuse_int_map; + volatile interrupt_core1_lp_sw_int_map_reg_t lp_sw_int_map; + volatile interrupt_core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map; + volatile interrupt_core1_lp_huk_int_map_reg_t lp_huk_int_map; + volatile interrupt_core1_sys_icm_int_map_reg_t sys_icm_int_map; + volatile interrupt_core1_usb_device_int_map_reg_t usb_device_int_map; + volatile interrupt_core1_sdio_host_int_map_reg_t sdio_host_int_map; + volatile interrupt_core1_gdma_int_map_reg_t gdma_int_map; + volatile interrupt_core1_spi2_int_map_reg_t spi2_int_map; + volatile interrupt_core1_spi3_int_map_reg_t spi3_int_map; + volatile interrupt_core1_i2s0_int_map_reg_t i2s0_int_map; + volatile interrupt_core1_i2s1_int_map_reg_t i2s1_int_map; + volatile interrupt_core1_i2s2_int_map_reg_t i2s2_int_map; + volatile interrupt_core1_uhci0_int_map_reg_t uhci0_int_map; + volatile interrupt_core1_uart0_int_map_reg_t uart0_int_map; + volatile interrupt_core1_uart1_int_map_reg_t uart1_int_map; + volatile interrupt_core1_uart2_int_map_reg_t uart2_int_map; + volatile interrupt_core1_uart3_int_map_reg_t uart3_int_map; + volatile interrupt_core1_uart4_int_map_reg_t uart4_int_map; + volatile interrupt_core1_lcd_cam_int_map_reg_t lcd_cam_int_map; + volatile interrupt_core1_adc_int_map_reg_t adc_int_map; + volatile interrupt_core1_pwm0_int_map_reg_t pwm0_int_map; + volatile interrupt_core1_pwm1_int_map_reg_t pwm1_int_map; + volatile interrupt_core1_can0_int_map_reg_t can0_int_map; + volatile interrupt_core1_can1_int_map_reg_t can1_int_map; + volatile interrupt_core1_can2_int_map_reg_t can2_int_map; + volatile interrupt_core1_rmt_int_map_reg_t rmt_int_map; + volatile interrupt_core1_i2c0_int_map_reg_t i2c0_int_map; + volatile interrupt_core1_i2c1_int_map_reg_t i2c1_int_map; + volatile interrupt_core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; + volatile interrupt_core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; + volatile interrupt_core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; + volatile interrupt_core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; + volatile interrupt_core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; + volatile interrupt_core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; + volatile interrupt_core1_ledc_int_map_reg_t ledc_int_map; + volatile interrupt_core1_systimer_target0_int_map_reg_t systimer_target0_int_map; + volatile interrupt_core1_systimer_target1_int_map_reg_t systimer_target1_int_map; + volatile interrupt_core1_systimer_target2_int_map_reg_t systimer_target2_int_map; + volatile interrupt_core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; + volatile interrupt_core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; + volatile interrupt_core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; + volatile interrupt_core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; + volatile interrupt_core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; + volatile interrupt_core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; + volatile interrupt_core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; + volatile interrupt_core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; + volatile interrupt_core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; + volatile interrupt_core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; + volatile interrupt_core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; + volatile interrupt_core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; + volatile interrupt_core1_rsa_int_map_reg_t rsa_int_map; + volatile interrupt_core1_aes_int_map_reg_t aes_int_map; + volatile interrupt_core1_sha_int_map_reg_t sha_int_map; + volatile interrupt_core1_ecc_int_map_reg_t ecc_int_map; + volatile interrupt_core1_ecdsa_int_map_reg_t ecdsa_int_map; + volatile interrupt_core1_km_int_map_reg_t km_int_map; + volatile interrupt_core1_gpio_int0_map_reg_t gpio_int0_map; + volatile interrupt_core1_gpio_int1_map_reg_t gpio_int1_map; + volatile interrupt_core1_gpio_int2_map_reg_t gpio_int2_map; + volatile interrupt_core1_gpio_int3_map_reg_t gpio_int3_map; + volatile interrupt_core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; + volatile interrupt_core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; + volatile interrupt_core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; + volatile interrupt_core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; + volatile interrupt_core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; + volatile interrupt_core1_cache_int_map_reg_t cache_int_map; + volatile interrupt_core1_flash_mspi_int_map_reg_t flash_mspi_int_map; + volatile interrupt_core1_csi_bridge_int_map_reg_t csi_bridge_int_map; + volatile interrupt_core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map; + volatile interrupt_core1_csi_int_map_reg_t csi_int_map; + volatile interrupt_core1_dsi_int_map_reg_t dsi_int_map; + volatile interrupt_core1_gmii_phy_int_map_reg_t gmii_phy_int_map; + volatile interrupt_core1_lpi_int_map_reg_t lpi_int_map; + volatile interrupt_core1_pmt_int_map_reg_t pmt_int_map; + volatile interrupt_core1_sbd_int_map_reg_t sbd_int_map; + volatile interrupt_core1_usb_otg_int_map_reg_t usb_otg_int_map; + volatile interrupt_core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; + volatile interrupt_core1_jpeg_int_map_reg_t jpeg_int_map; + volatile interrupt_core1_ppa_int_map_reg_t ppa_int_map; + volatile interrupt_core1_core0_trace_int_map_reg_t core0_trace_int_map; + volatile interrupt_core1_trace_int_map_reg_t interrupt_core1_trace_int_map; + volatile interrupt_core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; + volatile interrupt_core1_isp_int_map_reg_t isp_int_map; + volatile interrupt_core1_i3c_mst_int_map_reg_t i3c_mst_int_map; + volatile interrupt_core1_i3c_slv_int_map_reg_t i3c_slv_int_map; + volatile interrupt_core1_usb_otg11_int_map_reg_t usb_otg11_int_map; + volatile interrupt_core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; + volatile interrupt_core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; + volatile interrupt_core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; + volatile interrupt_core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; + volatile interrupt_core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; + volatile interrupt_core1_psram_mspi_int_map_reg_t psram_mspi_int_map; + volatile interrupt_core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map; + volatile interrupt_core1_pcnt_int_map_reg_t pcnt_int_map; + volatile interrupt_core1_hp_pau_int_map_reg_t hp_pau_int_map; + volatile interrupt_core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; + volatile interrupt_core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; + volatile interrupt_core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; + volatile interrupt_core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; + volatile interrupt_core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; + volatile interrupt_core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; + volatile interrupt_core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; + volatile interrupt_core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; + volatile interrupt_core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; + volatile interrupt_core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; + volatile interrupt_core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; + volatile interrupt_core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; + volatile interrupt_core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; + volatile interrupt_core1_h264_reg_int_map_reg_t h264_reg_int_map; + volatile interrupt_core1_assist_debug_int_map_reg_t assist_debug_int_map; + volatile interrupt_core1_intr_status_reg_0_reg_t intr_status_reg_0; + volatile interrupt_core1_intr_status_reg_1_reg_t intr_status_reg_1; + volatile interrupt_core1_intr_status_reg_2_reg_t intr_status_reg_2; + volatile interrupt_core1_intr_status_reg_3_reg_t intr_status_reg_3; + volatile interrupt_core1_clock_gate_reg_t clock_gate; + uint32_t reserved_214[122]; + volatile interrupt_core1_interrupt_reg_date_reg_t interrupt_reg_date; +} interrupt_core1_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_core1_dev_t) == 0x400, "Invalid size of interrupt_core1_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h b/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h deleted file mode 100644 index 1c41e19b79..0000000000 --- a/components/soc/esp32p4/include/soc/interrupt_matrix_reg.h +++ /dev/null @@ -1,999 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0) -/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_WIFI_MAC_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S) -#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S 0 - -/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register - * register description - */ -#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4) -/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_WIFI_MAC_NMI_MAP 0x0000001FU -#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S) -#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V 0x0000001FU -#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S 0 - -/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8) -/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_WIFI_PWR_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S) -#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S 0 - -/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc) -/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_WIFI_BB_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S) -#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S 0 - -/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10) -/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_BT_MAC_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_BT_MAC_INTR_MAP_M (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S) -#define INTMTX_CORE0_BT_MAC_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_BT_MAC_INTR_MAP_S 0 - -/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14) -/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_BT_BB_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_BT_BB_INTR_MAP_M (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S) -#define INTMTX_CORE0_BT_BB_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_BT_BB_INTR_MAP_S 0 - -/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register - * register description - */ -#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18) -/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_BT_BB_NMI_MAP 0x0000001FU -#define INTMTX_CORE0_BT_BB_NMI_MAP_M (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S) -#define INTMTX_CORE0_BT_BB_NMI_MAP_V 0x0000001FU -#define INTMTX_CORE0_BT_BB_NMI_MAP_S 0 - -/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c) -/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_TIMER_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S) -#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S 0 - -/** INTMTX_CORE0_COEX_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20) -/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_COEX_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_COEX_INTR_MAP_M (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S) -#define INTMTX_CORE0_COEX_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_COEX_INTR_MAP_S 0 - -/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24) -/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S) -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S 0 - -/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28) -/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_BLE_SEC_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S) -#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S 0 - -/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c) -/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_I2C_MST_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_I2C_MST_INTR_MAP_M (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S) -#define INTMTX_CORE0_I2C_MST_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_I2C_MST_INTR_MAP_S 0 - -/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30) -/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_ZB_MAC_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S) -#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S 0 - -/** INTMTX_CORE0_PMU_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34) -/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_PMU_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_PMU_INTR_MAP_M (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S) -#define INTMTX_CORE0_PMU_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_PMU_INTR_MAP_S 0 - -/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38) -/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_EFUSE_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_EFUSE_INTR_MAP_M (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S) -#define INTMTX_CORE0_EFUSE_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_EFUSE_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c) -/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S) -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40) -/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_UART_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_UART_INTR_MAP_M (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S) -#define INTMTX_CORE0_LP_UART_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_UART_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44) -/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_I2C_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_I2C_INTR_MAP_M (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S) -#define INTMTX_CORE0_LP_I2C_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_I2C_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48) -/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_WDT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_WDT_INTR_MAP_M (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S) -#define INTMTX_CORE0_LP_WDT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_WDT_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c) -/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50) -/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S) -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54) -/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_APM_M1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S) -#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S 0 - -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 - -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c) -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 - -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60) -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 - -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64) -/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU -#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 - -/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68) -/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S) -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 - -/** INTMTX_CORE0_TRACE_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c) -/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_TRACE_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_TRACE_INTR_MAP_M (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S) -#define INTMTX_CORE0_TRACE_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_TRACE_INTR_MAP_S 0 - -/** INTMTX_CORE0_CACHE_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70) -/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CACHE_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_CACHE_INTR_MAP_M (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S) -#define INTMTX_CORE0_CACHE_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_CACHE_INTR_MAP_S 0 - -/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74) -/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 - -/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register - * register description - */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78) -/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S) -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 - -/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register - * register description - */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c) -/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S) -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU -#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 - -/** INTMTX_CORE0_PAU_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80) -/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_PAU_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_PAU_INTR_MAP_M (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S) -#define INTMTX_CORE0_PAU_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_PAU_INTR_MAP_S 0 - -/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84) -/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 - -/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88) -/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) -#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 - -/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c) -/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S) -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S 0 - -/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90) -/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S) -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S 0 - -/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) -/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S) -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S 0 - -/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98) -/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S) -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S 0 - -/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c) -/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LP_APM0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LP_APM0_INTR_MAP_M (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S) -#define INTMTX_CORE0_LP_APM0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LP_APM0_INTR_MAP_S 0 - -/** INTMTX_CORE0_MSPI_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0) -/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_MSPI_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_MSPI_INTR_MAP_M (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S) -#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_MSPI_INTR_MAP_S 0 - -/** INTMTX_CORE0_I2S1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4) -/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S) -#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_I2S1_INTR_MAP_S 0 - -/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8) -/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_UHCI0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_UHCI0_INTR_MAP_M (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S) -#define INTMTX_CORE0_UHCI0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_UHCI0_INTR_MAP_S 0 - -/** INTMTX_CORE0_UART0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac) -/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_UART0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_UART0_INTR_MAP_M (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S) -#define INTMTX_CORE0_UART0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_UART0_INTR_MAP_S 0 - -/** INTMTX_CORE0_UART1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0) -/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_UART1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_UART1_INTR_MAP_M (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S) -#define INTMTX_CORE0_UART1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_UART1_INTR_MAP_S 0 - -/** INTMTX_CORE0_LEDC_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4) -/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_LEDC_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_LEDC_INTR_MAP_M (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S) -#define INTMTX_CORE0_LEDC_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_LEDC_INTR_MAP_S 0 - -/** INTMTX_CORE0_CAN0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8) -/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CAN0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_CAN0_INTR_MAP_M (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S) -#define INTMTX_CORE0_CAN0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_CAN0_INTR_MAP_S 0 - -/** INTMTX_CORE0_CAN1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc) -/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_CAN1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_CAN1_INTR_MAP_M (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S) -#define INTMTX_CORE0_CAN1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_CAN1_INTR_MAP_S 0 - -/** INTMTX_CORE0_USB_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0) -/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_USB_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_USB_INTR_MAP_M (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S) -#define INTMTX_CORE0_USB_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_USB_INTR_MAP_S 0 - -/** INTMTX_CORE0_RMT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4) -/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_RMT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_RMT_INTR_MAP_M (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S) -#define INTMTX_CORE0_RMT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_RMT_INTR_MAP_S 0 - -/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8) -/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S) -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S 0 - -/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc) -/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_TG0_T0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_TG0_T0_INTR_MAP_M (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S) -#define INTMTX_CORE0_TG0_T0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_TG0_T0_INTR_MAP_S 0 - -/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0) -/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_TG0_T1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_TG0_T1_INTR_MAP_M (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S) -#define INTMTX_CORE0_TG0_T1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_TG0_T1_INTR_MAP_S 0 - -/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4) -/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_TG0_WDT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S) -#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S 0 - -/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8) -/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_TG1_T0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_TG1_T0_INTR_MAP_M (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S) -#define INTMTX_CORE0_TG1_T0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_TG1_T0_INTR_MAP_S 0 - -/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc) -/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_TG1_T1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_TG1_T1_INTR_MAP_M (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S) -#define INTMTX_CORE0_TG1_T1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_TG1_T1_INTR_MAP_S 0 - -/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0) -/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_TG1_WDT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S) -#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S 0 - -/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4) -/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 - -/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8) -/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 - -/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec) -/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 - -/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0) -/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_APB_ADC_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_APB_ADC_INTR_MAP_M (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S) -#define INTMTX_CORE0_APB_ADC_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_APB_ADC_INTR_MAP_S 0 - -/** INTMTX_CORE0_PWM_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4) -/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_PWM_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_PWM_INTR_MAP_M (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S) -#define INTMTX_CORE0_PWM_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_PWM_INTR_MAP_S 0 - -/** INTMTX_CORE0_PCNT_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8) -/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_PCNT_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_PCNT_INTR_MAP_M (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S) -#define INTMTX_CORE0_PCNT_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_PCNT_INTR_MAP_S 0 - -/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc) -/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_PARL_IO_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_PARL_IO_INTR_MAP_M (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S) -#define INTMTX_CORE0_PARL_IO_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_PARL_IO_INTR_MAP_S 0 - -/** INTMTX_CORE0_SLC0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100) -/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_SLC0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_SLC0_INTR_MAP_M (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S) -#define INTMTX_CORE0_SLC0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_SLC0_INTR_MAP_S 0 - -/** INTMTX_CORE0_SLC1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104) -/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_SLC1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_SLC1_INTR_MAP_M (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S) -#define INTMTX_CORE0_SLC1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_SLC1_INTR_MAP_S 0 - -/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108) -/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S) -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S 0 - -/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c) -/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S) -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S 0 - -/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110) -/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S) -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S 0 - -/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114) -/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S) -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 - -/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118) -/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S) -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 - -/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c) -/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S) -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S 0 - -/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120) -/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_GPSPI2_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_GPSPI2_INTR_MAP_M (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S) -#define INTMTX_CORE0_GPSPI2_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_GPSPI2_INTR_MAP_S 0 - -/** INTMTX_CORE0_AES_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124) -/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_AES_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_AES_INTR_MAP_M (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S) -#define INTMTX_CORE0_AES_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_AES_INTR_MAP_S 0 - -/** INTMTX_CORE0_SHA_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128) -/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_SHA_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_SHA_INTR_MAP_M (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S) -#define INTMTX_CORE0_SHA_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_SHA_INTR_MAP_S 0 - -/** INTMTX_CORE0_RSA_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c) -/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_RSA_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_RSA_INTR_MAP_M (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S) -#define INTMTX_CORE0_RSA_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_RSA_INTR_MAP_S 0 - -/** INTMTX_CORE0_ECC_INTR_MAP_REG register - * register description - */ -#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130) -/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_ECC_INTR_MAP 0x0000001FU -#define INTMTX_CORE0_ECC_INTR_MAP_M (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S) -#define INTMTX_CORE0_ECC_INTR_MAP_V 0x0000001FU -#define INTMTX_CORE0_ECC_INTR_MAP_S 0 - -/** INTMTX_CORE0_INT_STATUS_REG_0_REG register - * register description - */ -#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134) -/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_INT_STATUS_0 0xFFFFFFFFU -#define INTMTX_CORE0_INT_STATUS_0_M (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S) -#define INTMTX_CORE0_INT_STATUS_0_V 0xFFFFFFFFU -#define INTMTX_CORE0_INT_STATUS_0_S 0 - -/** INTMTX_CORE0_INT_STATUS_REG_1_REG register - * register description - */ -#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138) -/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_INT_STATUS_1 0xFFFFFFFFU -#define INTMTX_CORE0_INT_STATUS_1_M (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S) -#define INTMTX_CORE0_INT_STATUS_1_V 0xFFFFFFFFU -#define INTMTX_CORE0_INT_STATUS_1_S 0 - -/** INTMTX_CORE0_INT_STATUS_REG_2_REG register - * register description - */ -#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c) -/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTMTX_CORE0_INT_STATUS_2 0xFFFFFFFFU -#define INTMTX_CORE0_INT_STATUS_2_M (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S) -#define INTMTX_CORE0_INT_STATUS_2_V 0xFFFFFFFFU -#define INTMTX_CORE0_INT_STATUS_2_S 0 - -/** INTMTX_CORE0_CLOCK_GATE_REG register - * register description - */ -#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140) -/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define INTMTX_CORE0_REG_CLK_EN (BIT(0)) -#define INTMTX_CORE0_REG_CLK_EN_M (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S) -#define INTMTX_CORE0_REG_CLK_EN_V 0x00000001U -#define INTMTX_CORE0_REG_CLK_EN_S 0 - -/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register - * register description - */ -#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc) -/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144; - * Need add description - */ -#define INTMTX_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU -#define INTMTX_CORE0_INTERRUPT_REG_DATE_M (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S) -#define INTMTX_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU -#define INTMTX_CORE0_INTERRUPT_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h b/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h deleted file mode 100644 index 95dff43fc6..0000000000 --- a/components/soc/esp32p4/include/soc/interrupt_matrix_struct.h +++ /dev/null @@ -1,1254 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of wifi_mac_intr_map register - * register description - */ -typedef union { - struct { - /** wifi_mac_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t wifi_mac_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_wifi_mac_intr_map_reg_t; - -/** Type of wifi_mac_nmi_map register - * register description - */ -typedef union { - struct { - /** wifi_mac_nmi_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t wifi_mac_nmi_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_wifi_mac_nmi_map_reg_t; - -/** Type of wifi_pwr_intr_map register - * register description - */ -typedef union { - struct { - /** wifi_pwr_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t wifi_pwr_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_wifi_pwr_intr_map_reg_t; - -/** Type of wifi_bb_intr_map register - * register description - */ -typedef union { - struct { - /** wifi_bb_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t wifi_bb_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_wifi_bb_intr_map_reg_t; - -/** Type of bt_mac_intr_map register - * register description - */ -typedef union { - struct { - /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t bt_mac_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_bt_mac_intr_map_reg_t; - -/** Type of bt_bb_intr_map register - * register description - */ -typedef union { - struct { - /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t bt_bb_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_bt_bb_intr_map_reg_t; - -/** Type of bt_bb_nmi_map register - * register description - */ -typedef union { - struct { - /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t bt_bb_nmi_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_bt_bb_nmi_map_reg_t; - -/** Type of lp_timer_intr_map register - * register description - */ -typedef union { - struct { - /** lp_timer_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_timer_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_timer_intr_map_reg_t; - -/** Type of coex_intr_map register - * register description - */ -typedef union { - struct { - /** coex_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t coex_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_coex_intr_map_reg_t; - -/** Type of ble_timer_intr_map register - * register description - */ -typedef union { - struct { - /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t ble_timer_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_ble_timer_intr_map_reg_t; - -/** Type of ble_sec_intr_map register - * register description - */ -typedef union { - struct { - /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t ble_sec_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_ble_sec_intr_map_reg_t; - -/** Type of i2c_mst_intr_map register - * register description - */ -typedef union { - struct { - /** i2c_mst_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t i2c_mst_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_i2c_mst_intr_map_reg_t; - -/** Type of zb_mac_intr_map register - * register description - */ -typedef union { - struct { - /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t zb_mac_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_zb_mac_intr_map_reg_t; - -/** Type of pmu_intr_map register - * register description - */ -typedef union { - struct { - /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t pmu_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_pmu_intr_map_reg_t; - -/** Type of efuse_intr_map register - * register description - */ -typedef union { - struct { - /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t efuse_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_efuse_intr_map_reg_t; - -/** Type of lp_rtc_timer_intr_map register - * register description - */ -typedef union { - struct { - /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_rtc_timer_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_rtc_timer_intr_map_reg_t; - -/** Type of lp_uart_intr_map register - * register description - */ -typedef union { - struct { - /** lp_uart_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_uart_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_uart_intr_map_reg_t; - -/** Type of lp_i2c_intr_map register - * register description - */ -typedef union { - struct { - /** lp_i2c_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_i2c_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_i2c_intr_map_reg_t; - -/** Type of lp_wdt_intr_map register - * register description - */ -typedef union { - struct { - /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_wdt_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_wdt_intr_map_reg_t; - -/** Type of lp_peri_timeout_intr_map register - * register description - */ -typedef union { - struct { - /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_peri_timeout_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_peri_timeout_intr_map_reg_t; - -/** Type of lp_apm_m0_intr_map register - * register description - */ -typedef union { - struct { - /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_apm_m0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_apm_m0_intr_map_reg_t; - -/** Type of lp_apm_m1_intr_map register - * register description - */ -typedef union { - struct { - /** lp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_apm_m1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_apm_m1_intr_map_reg_t; - -/** Type of cpu_intr_from_cpu_0_map register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_0_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t; - -/** Type of cpu_intr_from_cpu_1_map register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_1_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t; - -/** Type of cpu_intr_from_cpu_2_map register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_2_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t; - -/** Type of cpu_intr_from_cpu_3_map register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_3_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t; - -/** Type of assist_debug_intr_map register - * register description - */ -typedef union { - struct { - /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t assist_debug_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_assist_debug_intr_map_reg_t; - -/** Type of trace_intr_map register - * register description - */ -typedef union { - struct { - /** trace_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t trace_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_trace_intr_map_reg_t; - -/** Type of cache_intr_map register - * register description - */ -typedef union { - struct { - /** cache_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t cache_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_cache_intr_map_reg_t; - -/** Type of cpu_peri_timeout_intr_map register - * register description - */ -typedef union { - struct { - /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t cpu_peri_timeout_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t; - -/** Type of gpio_interrupt_pro_map register - * register description - */ -typedef union { - struct { - /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t gpio_interrupt_pro_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_gpio_interrupt_pro_map_reg_t; - -/** Type of gpio_interrupt_pro_nmi_map register - * register description - */ -typedef union { - struct { - /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t gpio_interrupt_pro_nmi_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t; - -/** Type of pau_intr_map register - * register description - */ -typedef union { - struct { - /** pau_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t pau_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_pau_intr_map_reg_t; - -/** Type of hp_peri_timeout_intr_map register - * register description - */ -typedef union { - struct { - /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t hp_peri_timeout_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_hp_peri_timeout_intr_map_reg_t; - -/** Type of modem_peri_timeout_intr_map register - * register description - */ -typedef union { - struct { - /** modem_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t modem_peri_timeout_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_modem_peri_timeout_intr_map_reg_t; - -/** Type of hp_apm_m0_intr_map register - * register description - */ -typedef union { - struct { - /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t hp_apm_m0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_hp_apm_m0_intr_map_reg_t; - -/** Type of hp_apm_m1_intr_map register - * register description - */ -typedef union { - struct { - /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t hp_apm_m1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_hp_apm_m1_intr_map_reg_t; - -/** Type of hp_apm_m2_intr_map register - * register description - */ -typedef union { - struct { - /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t hp_apm_m2_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_hp_apm_m2_intr_map_reg_t; - -/** Type of hp_apm_m3_intr_map register - * register description - */ -typedef union { - struct { - /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t hp_apm_m3_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_hp_apm_m3_intr_map_reg_t; - -/** Type of lp_apm0_intr_map register - * register description - */ -typedef union { - struct { - /** lp_apm0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t lp_apm0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_lp_apm0_intr_map_reg_t; - -/** Type of mspi_intr_map register - * register description - */ -typedef union { - struct { - /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t mspi_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_mspi_intr_map_reg_t; - -/** Type of i2s1_intr_map register - * register description - */ -typedef union { - struct { - /** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t i2s1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_i2s1_intr_map_reg_t; - -/** Type of uhci0_intr_map register - * register description - */ -typedef union { - struct { - /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t uhci0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_uhci0_intr_map_reg_t; - -/** Type of uart0_intr_map register - * register description - */ -typedef union { - struct { - /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t uart0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_uart0_intr_map_reg_t; - -/** Type of uart1_intr_map register - * register description - */ -typedef union { - struct { - /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t uart1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_uart1_intr_map_reg_t; - -/** Type of ledc_intr_map register - * register description - */ -typedef union { - struct { - /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t ledc_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_ledc_intr_map_reg_t; - -/** Type of can0_intr_map register - * register description - */ -typedef union { - struct { - /** can0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t can0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_can0_intr_map_reg_t; - -/** Type of can1_intr_map register - * register description - */ -typedef union { - struct { - /** can1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t can1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_can1_intr_map_reg_t; - -/** Type of usb_intr_map register - * register description - */ -typedef union { - struct { - /** usb_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t usb_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_usb_intr_map_reg_t; - -/** Type of rmt_intr_map register - * register description - */ -typedef union { - struct { - /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t rmt_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_rmt_intr_map_reg_t; - -/** Type of i2c_ext0_intr_map register - * register description - */ -typedef union { - struct { - /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t i2c_ext0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_i2c_ext0_intr_map_reg_t; - -/** Type of tg0_t0_intr_map register - * register description - */ -typedef union { - struct { - /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t tg0_t0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_tg0_t0_intr_map_reg_t; - -/** Type of tg0_t1_intr_map register - * register description - */ -typedef union { - struct { - /** tg0_t1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t tg0_t1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_tg0_t1_intr_map_reg_t; - -/** Type of tg0_wdt_intr_map register - * register description - */ -typedef union { - struct { - /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t tg0_wdt_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_tg0_wdt_intr_map_reg_t; - -/** Type of tg1_t0_intr_map register - * register description - */ -typedef union { - struct { - /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t tg1_t0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_tg1_t0_intr_map_reg_t; - -/** Type of tg1_t1_intr_map register - * register description - */ -typedef union { - struct { - /** tg1_t1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t tg1_t1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_tg1_t1_intr_map_reg_t; - -/** Type of tg1_wdt_intr_map register - * register description - */ -typedef union { - struct { - /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t tg1_wdt_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_tg1_wdt_intr_map_reg_t; - -/** Type of systimer_target0_intr_map register - * register description - */ -typedef union { - struct { - /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t systimer_target0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_systimer_target0_intr_map_reg_t; - -/** Type of systimer_target1_intr_map register - * register description - */ -typedef union { - struct { - /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t systimer_target1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_systimer_target1_intr_map_reg_t; - -/** Type of systimer_target2_intr_map register - * register description - */ -typedef union { - struct { - /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t systimer_target2_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_systimer_target2_intr_map_reg_t; - -/** Type of apb_adc_intr_map register - * register description - */ -typedef union { - struct { - /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t apb_adc_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_apb_adc_intr_map_reg_t; - -/** Type of pwm_intr_map register - * register description - */ -typedef union { - struct { - /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t pwm_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_pwm_intr_map_reg_t; - -/** Type of pcnt_intr_map register - * register description - */ -typedef union { - struct { - /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t pcnt_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_pcnt_intr_map_reg_t; - -/** Type of parl_io_intr_map register - * register description - */ -typedef union { - struct { - /** parl_io_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t parl_io_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_parl_io_intr_map_reg_t; - -/** Type of slc0_intr_map register - * register description - */ -typedef union { - struct { - /** slc0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t slc0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_slc0_intr_map_reg_t; - -/** Type of slc1_intr_map register - * register description - */ -typedef union { - struct { - /** slc1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t slc1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_slc1_intr_map_reg_t; - -/** Type of dma_in_ch0_intr_map register - * register description - */ -typedef union { - struct { - /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t dma_in_ch0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_dma_in_ch0_intr_map_reg_t; - -/** Type of dma_in_ch1_intr_map register - * register description - */ -typedef union { - struct { - /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t dma_in_ch1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_dma_in_ch1_intr_map_reg_t; - -/** Type of dma_in_ch2_intr_map register - * register description - */ -typedef union { - struct { - /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t dma_in_ch2_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_dma_in_ch2_intr_map_reg_t; - -/** Type of dma_out_ch0_intr_map register - * register description - */ -typedef union { - struct { - /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t dma_out_ch0_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_dma_out_ch0_intr_map_reg_t; - -/** Type of dma_out_ch1_intr_map register - * register description - */ -typedef union { - struct { - /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t dma_out_ch1_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_dma_out_ch1_intr_map_reg_t; - -/** Type of dma_out_ch2_intr_map register - * register description - */ -typedef union { - struct { - /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t dma_out_ch2_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_dma_out_ch2_intr_map_reg_t; - -/** Type of gpspi2_intr_map register - * register description - */ -typedef union { - struct { - /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t gpspi2_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_gpspi2_intr_map_reg_t; - -/** Type of aes_intr_map register - * register description - */ -typedef union { - struct { - /** aes_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t aes_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_aes_intr_map_reg_t; - -/** Type of sha_intr_map register - * register description - */ -typedef union { - struct { - /** sha_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t sha_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_sha_intr_map_reg_t; - -/** Type of rsa_intr_map register - * register description - */ -typedef union { - struct { - /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t rsa_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_rsa_intr_map_reg_t; - -/** Type of ecc_intr_map register - * register description - */ -typedef union { - struct { - /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t ecc_intr_map:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} interrupt_matrix_ecc_intr_map_reg_t; - -/** Type of int_status_reg_0 register - * register description - */ -typedef union { - struct { - /** int_status_0 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t int_status_0:32; - }; - uint32_t val; -} interrupt_matrix_int_status_reg_0_reg_t; - -/** Type of int_status_reg_1 register - * register description - */ -typedef union { - struct { - /** int_status_1 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t int_status_1:32; - }; - uint32_t val; -} interrupt_matrix_int_status_reg_1_reg_t; - -/** Type of int_status_reg_2 register - * register description - */ -typedef union { - struct { - /** int_status_2 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t int_status_2:32; - }; - uint32_t val; -} interrupt_matrix_int_status_reg_2_reg_t; - -/** Type of clock_gate register - * register description - */ -typedef union { - struct { - /** reg_clk_en : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t reg_clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} interrupt_matrix_clock_gate_reg_t; - -/** Type of interrupt_reg_date register - * register description - */ -typedef union { - struct { - /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35664144; - * Need add description - */ - uint32_t interrupt_reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} interrupt_matrix_interrupt_reg_date_reg_t; - - -typedef struct interrupt_matrix_dev_t { - volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map; - volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; - volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; - volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map; - volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map; - volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map; - volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map; - volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map; - volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map; - volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map; - volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map; - volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map; - volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map; - volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map; - volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map; - volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; - volatile interrupt_matrix_lp_uart_intr_map_reg_t lp_uart_intr_map; - volatile interrupt_matrix_lp_i2c_intr_map_reg_t lp_i2c_intr_map; - volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map; - volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; - volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; - volatile interrupt_matrix_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map; - volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; - volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; - volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; - volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; - volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map; - volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map; - volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map; - volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; - volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; - volatile interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map; - volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map; - volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; - volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map; - volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; - volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; - volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; - volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; - volatile interrupt_matrix_lp_apm0_intr_map_reg_t lp_apm0_intr_map; - volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map; - volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map; - volatile interrupt_matrix_uhci0_intr_map_reg_t uhci0_intr_map; - volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map; - volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map; - volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map; - volatile interrupt_matrix_can0_intr_map_reg_t can0_intr_map; - volatile interrupt_matrix_can1_intr_map_reg_t can1_intr_map; - volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map; - volatile interrupt_matrix_rmt_intr_map_reg_t rmt_intr_map; - volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; - volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map; - volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map; - volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; - volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map; - volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map; - volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; - volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map; - volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map; - volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map; - volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map; - volatile interrupt_matrix_pwm_intr_map_reg_t pwm_intr_map; - volatile interrupt_matrix_pcnt_intr_map_reg_t pcnt_intr_map; - volatile interrupt_matrix_parl_io_intr_map_reg_t parl_io_intr_map; - volatile interrupt_matrix_slc0_intr_map_reg_t slc0_intr_map; - volatile interrupt_matrix_slc1_intr_map_reg_t slc1_intr_map; - volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; - volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; - volatile interrupt_matrix_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map; - volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; - volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; - volatile interrupt_matrix_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map; - volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map; - volatile interrupt_matrix_aes_intr_map_reg_t aes_intr_map; - volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map; - volatile interrupt_matrix_rsa_intr_map_reg_t rsa_intr_map; - volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map; - volatile interrupt_matrix_int_status_reg_0_reg_t int_status_reg_0; - volatile interrupt_matrix_int_status_reg_1_reg_t int_status_reg_1; - volatile interrupt_matrix_int_status_reg_2_reg_t int_status_reg_2; - volatile interrupt_matrix_clock_gate_reg_t clock_gate; - uint32_t reserved_144[430]; - volatile interrupt_matrix_interrupt_reg_date_reg_t interrupt_reg_date; -} interrupt_matrix_dev_t; - -extern interrupt_matrix_dev_t INTMTX; - -#ifndef __cplusplus -_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/interrupt_reg.h b/components/soc/esp32p4/include/soc/interrupt_reg.h index 4290233051..b799b19144 100644 --- a/components/soc/esp32p4/include/soc/interrupt_reg.h +++ b/components/soc/esp32p4/include/soc/interrupt_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,6 @@ #include "soc/clic_reg.h" #include "soc/soc_caps.h" -// ESP32P4 should use the CLIC controller as the interrupt controller instead of INTC (SOC_INT_CLIC_SUPPORTED = y) +// ESP32P4 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y) #define INTERRUPT_CORE0_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG #define INTERRUPT_CORE1_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG diff --git a/components/soc/esp32p4/include/soc/intpri_reg.h b/components/soc/esp32p4/include/soc/intpri_reg.h deleted file mode 100644 index 25c3acccaa..0000000000 --- a/components/soc/esp32p4/include/soc/intpri_reg.h +++ /dev/null @@ -1,574 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** INTPRI_CORE0_CPU_INT_ENABLE_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0) -/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_ENABLE_M (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S) -#define INTPRI_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_ENABLE_S 0 - -/** INTPRI_CORE0_CPU_INT_TYPE_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4) -/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_INT_TYPE 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_TYPE_M (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S) -#define INTPRI_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_TYPE_S 0 - -/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8) -/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S) -#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_0_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc) -/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_0_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_0_MAP_M (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S) -#define INTPRI_CORE0_CPU_PRI_0_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_0_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_1_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10) -/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_1_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_1_MAP_M (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S) -#define INTPRI_CORE0_CPU_PRI_1_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_1_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_2_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14) -/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_2_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_2_MAP_M (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S) -#define INTPRI_CORE0_CPU_PRI_2_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_2_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_3_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18) -/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_3_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_3_MAP_M (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S) -#define INTPRI_CORE0_CPU_PRI_3_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_3_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_4_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c) -/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_4_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_4_MAP_M (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S) -#define INTPRI_CORE0_CPU_PRI_4_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_4_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_5_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20) -/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_5_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_5_MAP_M (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S) -#define INTPRI_CORE0_CPU_PRI_5_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_5_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_6_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24) -/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_6_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_6_MAP_M (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S) -#define INTPRI_CORE0_CPU_PRI_6_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_6_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_7_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28) -/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_7_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_7_MAP_M (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S) -#define INTPRI_CORE0_CPU_PRI_7_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_7_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_8_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c) -/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_8_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_8_MAP_M (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S) -#define INTPRI_CORE0_CPU_PRI_8_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_8_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_9_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30) -/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_9_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_9_MAP_M (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S) -#define INTPRI_CORE0_CPU_PRI_9_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_9_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_10_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34) -/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_10_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_10_MAP_M (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S) -#define INTPRI_CORE0_CPU_PRI_10_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_10_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_11_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38) -/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_11_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_11_MAP_M (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S) -#define INTPRI_CORE0_CPU_PRI_11_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_11_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_12_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c) -/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_12_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_12_MAP_M (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S) -#define INTPRI_CORE0_CPU_PRI_12_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_12_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_13_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40) -/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_13_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_13_MAP_M (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S) -#define INTPRI_CORE0_CPU_PRI_13_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_13_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_14_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44) -/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_14_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_14_MAP_M (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S) -#define INTPRI_CORE0_CPU_PRI_14_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_14_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_15_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48) -/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_15_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_15_MAP_M (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S) -#define INTPRI_CORE0_CPU_PRI_15_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_15_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_16_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c) -/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_16_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_16_MAP_M (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S) -#define INTPRI_CORE0_CPU_PRI_16_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_16_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_17_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50) -/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_17_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_17_MAP_M (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S) -#define INTPRI_CORE0_CPU_PRI_17_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_17_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_18_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54) -/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_18_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_18_MAP_M (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S) -#define INTPRI_CORE0_CPU_PRI_18_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_18_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_19_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58) -/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_19_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_19_MAP_M (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S) -#define INTPRI_CORE0_CPU_PRI_19_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_19_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_20_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c) -/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_20_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_20_MAP_M (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S) -#define INTPRI_CORE0_CPU_PRI_20_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_20_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_21_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60) -/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_21_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_21_MAP_M (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S) -#define INTPRI_CORE0_CPU_PRI_21_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_21_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_22_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64) -/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_22_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_22_MAP_M (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S) -#define INTPRI_CORE0_CPU_PRI_22_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_22_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_23_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68) -/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_23_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_23_MAP_M (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S) -#define INTPRI_CORE0_CPU_PRI_23_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_23_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_24_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c) -/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_24_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_24_MAP_M (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S) -#define INTPRI_CORE0_CPU_PRI_24_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_24_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_25_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70) -/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_25_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_25_MAP_M (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S) -#define INTPRI_CORE0_CPU_PRI_25_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_25_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_26_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74) -/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_26_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_26_MAP_M (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S) -#define INTPRI_CORE0_CPU_PRI_26_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_26_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_27_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78) -/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_27_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_27_MAP_M (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S) -#define INTPRI_CORE0_CPU_PRI_27_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_27_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_28_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c) -/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_28_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_28_MAP_M (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S) -#define INTPRI_CORE0_CPU_PRI_28_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_28_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_29_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80) -/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_29_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_29_MAP_M (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S) -#define INTPRI_CORE0_CPU_PRI_29_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_29_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_30_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84) -/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_30_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_30_MAP_M (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S) -#define INTPRI_CORE0_CPU_PRI_30_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_30_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_PRI_31_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88) -/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_PRI_31_MAP 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_31_MAP_M (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S) -#define INTPRI_CORE0_CPU_PRI_31_MAP_V 0x0000000FU -#define INTPRI_CORE0_CPU_PRI_31_MAP_S 0 - -/** INTPRI_CORE0_CPU_INT_THRESH_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c) -/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_INT_THRESH 0x000000FFU -#define INTPRI_CORE0_CPU_INT_THRESH_M (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S) -#define INTPRI_CORE0_CPU_INT_THRESH_V 0x000000FFU -#define INTPRI_CORE0_CPU_INT_THRESH_S 0 - -/** INTPRI_CPU_INTR_FROM_CPU_0_REG register - * register description - */ -#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90) -/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)) -#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S) -#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U -#define INTPRI_CPU_INTR_FROM_CPU_0_S 0 - -/** INTPRI_CPU_INTR_FROM_CPU_1_REG register - * register description - */ -#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94) -/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0)) -#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S) -#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U -#define INTPRI_CPU_INTR_FROM_CPU_1_S 0 - -/** INTPRI_CPU_INTR_FROM_CPU_2_REG register - * register description - */ -#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98) -/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0)) -#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S) -#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U -#define INTPRI_CPU_INTR_FROM_CPU_2_S 0 - -/** INTPRI_CPU_INTR_FROM_CPU_3_REG register - * register description - */ -#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c) -/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0)) -#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S) -#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U -#define INTPRI_CPU_INTR_FROM_CPU_3_S 0 - -/** INTPRI_DATE_REG register - * register description - */ -#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0) -/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35655824; - * Need add description - */ -#define INTPRI_DATE 0x0FFFFFFFU -#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S) -#define INTPRI_DATE_V 0x0FFFFFFFU -#define INTPRI_DATE_S 0 - -/** INTPRI_CLOCK_GATE_REG register - * register description - */ -#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4) -/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define INTPRI_CLK_EN (BIT(0)) -#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S) -#define INTPRI_CLK_EN_V 0x00000001U -#define INTPRI_CLK_EN_S 0 - -/** INTPRI_CORE0_CPU_INT_CLEAR_REG register - * register description - */ -#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8) -/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTPRI_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_CLEAR_M (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S) -#define INTPRI_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU -#define INTPRI_CORE0_CPU_INT_CLEAR_S 0 - -/** INTPRI_RND_ECO_REG register - * redcy eco register. - */ -#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac) -/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0; - * Only reserved for ECO. - */ -#define INTPRI_REDCY_ENA (BIT(0)) -#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S) -#define INTPRI_REDCY_ENA_V 0x00000001U -#define INTPRI_REDCY_ENA_S 0 -/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0; - * Only reserved for ECO. - */ -#define INTPRI_REDCY_RESULT (BIT(1)) -#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S) -#define INTPRI_REDCY_RESULT_V 0x00000001U -#define INTPRI_REDCY_RESULT_S 1 - -/** INTPRI_RND_ECO_LOW_REG register - * redcy eco low register. - */ -#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0) -/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; - * Only reserved for ECO. - */ -#define INTPRI_REDCY_LOW 0xFFFFFFFFU -#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S) -#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU -#define INTPRI_REDCY_LOW_S 0 - -/** INTPRI_RND_ECO_HIGH_REG register - * redcy eco high register. - */ -#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc) -/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; - * Only reserved for ECO. - */ -#define INTPRI_REDCY_HIGH 0xFFFFFFFFU -#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S) -#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU -#define INTPRI_REDCY_HIGH_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/intpri_struct.h b/components/soc/esp32p4/include/soc/intpri_struct.h deleted file mode 100644 index 622f00818b..0000000000 --- a/components/soc/esp32p4/include/soc/intpri_struct.h +++ /dev/null @@ -1,256 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of core0_cpu_int_enable register - * register description - */ -typedef union { - struct { - /** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t core0_cpu_int_enable:32; - }; - uint32_t val; -} intpri_core0_cpu_int_enable_reg_t; - -/** Type of core0_cpu_int_type register - * register description - */ -typedef union { - struct { - /** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t core0_cpu_int_type:32; - }; - uint32_t val; -} intpri_core0_cpu_int_type_reg_t; - -/** Type of core0_cpu_int_eip_status register - * register description - */ -typedef union { - struct { - /** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t core0_cpu_int_eip_status:32; - }; - uint32_t val; -} intpri_core0_cpu_int_eip_status_reg_t; - -/** Type of core0_cpu_int_pri_n register - * register description - */ -typedef union { - struct { - /** map : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ - uint32_t map:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} intpri_core0_cpu_int_pri_n_reg_t; - -/** Type of core0_cpu_int_thresh register - * register description - */ -typedef union { - struct { - /** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0; - * Need add description - */ - uint32_t core0_cpu_int_thresh:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} intpri_core0_cpu_int_thresh_reg_t; - -/** Type of clock_gate register - * register description - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} intpri_clock_gate_reg_t; - -/** Type of core0_cpu_int_clear register - * register description - */ -typedef union { - struct { - /** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t core0_cpu_int_clear:32; - }; - uint32_t val; -} intpri_core0_cpu_int_clear_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of cpu_intr_from_cpu_0 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} intpri_cpu_intr_from_cpu_0_reg_t; - -/** Type of cpu_intr_from_cpu_1 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} intpri_cpu_intr_from_cpu_1_reg_t; - -/** Type of cpu_intr_from_cpu_2 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_2:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} intpri_cpu_intr_from_cpu_2_reg_t; - -/** Type of cpu_intr_from_cpu_3 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} intpri_cpu_intr_from_cpu_3_reg_t; - - -/** Group: Version Registers */ -/** Type of date register - * register description - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35655824; - * Need add description - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} intpri_date_reg_t; - - -/** Group: Redcy ECO Registers */ -/** Type of rnd_eco register - * redcy eco register. - */ -typedef union { - struct { - /** redcy_ena : W/R; bitpos: [0]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_ena:1; - /** redcy_result : RO; bitpos: [1]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} intpri_rnd_eco_reg_t; - -/** Type of rnd_eco_low register - * redcy eco low register. - */ -typedef union { - struct { - /** redcy_low : W/R; bitpos: [31:0]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_low:32; - }; - uint32_t val; -} intpri_rnd_eco_low_reg_t; - -/** Type of rnd_eco_high register - * redcy eco high register. - */ -typedef union { - struct { - /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; - * Only reserved for ECO. - */ - uint32_t redcy_high:32; - }; - uint32_t val; -} intpri_rnd_eco_high_reg_t; - - -typedef struct intpri_dev_t { - volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable; - volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type; - volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status; - volatile intpri_core0_cpu_int_pri_n_reg_t core0_cpu_int_pri[32]; - volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh; - volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0; - volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1; - volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2; - volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3; - volatile intpri_date_reg_t date; - volatile intpri_clock_gate_reg_t clock_gate; - volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear; - volatile intpri_rnd_eco_reg_t rnd_eco; - volatile intpri_rnd_eco_low_reg_t rnd_eco_low; - uint32_t reserved_0b4[210]; - volatile intpri_rnd_eco_high_reg_t rnd_eco_high; -} intpri_dev_t; - -extern intpri_dev_t INTPRI; - -#ifndef __cplusplus -_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/iomux_reg.h b/components/soc/esp32p4/include/soc/iomux_reg.h deleted file mode 100644 index 7e2b0b221e..0000000000 --- a/components/soc/esp32p4/include/soc/iomux_reg.h +++ /dev/null @@ -1,5143 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** IO_MUX_gpio0_REG register - * iomux control register for gpio0 - */ -#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4) -/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_OE (BIT(0)) -#define IO_MUX_GPIO0_MCU_OE_M (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S) -#define IO_MUX_GPIO0_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO0_MCU_OE_S 0 -/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO0_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO0_SLP_SEL_M (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S) -#define IO_MUX_GPIO0_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO0_SLP_SEL_S 1 -/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO0_MCU_WPD_M (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S) -#define IO_MUX_GPIO0_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO0_MCU_WPD_S 2 -/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO0_MCU_WPU_M (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S) -#define IO_MUX_GPIO0_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO0_MCU_WPU_S 3 -/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_IE (BIT(4)) -#define IO_MUX_GPIO0_MCU_IE_M (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S) -#define IO_MUX_GPIO0_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO0_MCU_IE_S 4 -/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO0_MCU_DRV 0x00000003U -#define IO_MUX_GPIO0_MCU_DRV_M (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S) -#define IO_MUX_GPIO0_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO0_MCU_DRV_S 5 -/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO0_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO0_FUN_WPD_M (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S) -#define IO_MUX_GPIO0_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO0_FUN_WPD_S 7 -/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO0_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO0_FUN_WPU_M (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S) -#define IO_MUX_GPIO0_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO0_FUN_WPU_S 8 -/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO0_FUN_IE (BIT(9)) -#define IO_MUX_GPIO0_FUN_IE_M (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S) -#define IO_MUX_GPIO0_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO0_FUN_IE_S 9 -/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO0_FUN_DRV 0x00000003U -#define IO_MUX_GPIO0_FUN_DRV_M (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S) -#define IO_MUX_GPIO0_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO0_FUN_DRV_S 10 -/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO0_MCU_SEL 0x00000007U -#define IO_MUX_GPIO0_MCU_SEL_M (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S) -#define IO_MUX_GPIO0_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO0_MCU_SEL_S 12 -/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO0_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO0_FILTER_EN_M (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S) -#define IO_MUX_GPIO0_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO0_FILTER_EN_S 15 - -/** IO_MUX_gpio1_REG register - * iomux control register for gpio1 - */ -#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8) -/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_OE (BIT(0)) -#define IO_MUX_GPIO1_MCU_OE_M (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S) -#define IO_MUX_GPIO1_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO1_MCU_OE_S 0 -/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO1_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO1_SLP_SEL_M (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S) -#define IO_MUX_GPIO1_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO1_SLP_SEL_S 1 -/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO1_MCU_WPD_M (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S) -#define IO_MUX_GPIO1_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO1_MCU_WPD_S 2 -/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO1_MCU_WPU_M (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S) -#define IO_MUX_GPIO1_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO1_MCU_WPU_S 3 -/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_IE (BIT(4)) -#define IO_MUX_GPIO1_MCU_IE_M (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S) -#define IO_MUX_GPIO1_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO1_MCU_IE_S 4 -/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO1_MCU_DRV 0x00000003U -#define IO_MUX_GPIO1_MCU_DRV_M (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S) -#define IO_MUX_GPIO1_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO1_MCU_DRV_S 5 -/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO1_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO1_FUN_WPD_M (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S) -#define IO_MUX_GPIO1_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO1_FUN_WPD_S 7 -/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO1_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO1_FUN_WPU_M (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S) -#define IO_MUX_GPIO1_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO1_FUN_WPU_S 8 -/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO1_FUN_IE (BIT(9)) -#define IO_MUX_GPIO1_FUN_IE_M (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S) -#define IO_MUX_GPIO1_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO1_FUN_IE_S 9 -/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO1_FUN_DRV 0x00000003U -#define IO_MUX_GPIO1_FUN_DRV_M (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S) -#define IO_MUX_GPIO1_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO1_FUN_DRV_S 10 -/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO1_MCU_SEL 0x00000007U -#define IO_MUX_GPIO1_MCU_SEL_M (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S) -#define IO_MUX_GPIO1_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO1_MCU_SEL_S 12 -/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO1_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO1_FILTER_EN_M (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S) -#define IO_MUX_GPIO1_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO1_FILTER_EN_S 15 - -/** IO_MUX_gpio2_REG register - * iomux control register for gpio2 - */ -#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc) -/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_OE (BIT(0)) -#define IO_MUX_GPIO2_MCU_OE_M (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S) -#define IO_MUX_GPIO2_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO2_MCU_OE_S 0 -/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO2_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO2_SLP_SEL_M (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S) -#define IO_MUX_GPIO2_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO2_SLP_SEL_S 1 -/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO2_MCU_WPD_M (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S) -#define IO_MUX_GPIO2_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO2_MCU_WPD_S 2 -/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO2_MCU_WPU_M (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S) -#define IO_MUX_GPIO2_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO2_MCU_WPU_S 3 -/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_IE (BIT(4)) -#define IO_MUX_GPIO2_MCU_IE_M (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S) -#define IO_MUX_GPIO2_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO2_MCU_IE_S 4 -/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO2_MCU_DRV 0x00000003U -#define IO_MUX_GPIO2_MCU_DRV_M (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S) -#define IO_MUX_GPIO2_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO2_MCU_DRV_S 5 -/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO2_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO2_FUN_WPD_M (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S) -#define IO_MUX_GPIO2_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO2_FUN_WPD_S 7 -/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO2_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO2_FUN_WPU_M (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S) -#define IO_MUX_GPIO2_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO2_FUN_WPU_S 8 -/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO2_FUN_IE (BIT(9)) -#define IO_MUX_GPIO2_FUN_IE_M (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S) -#define IO_MUX_GPIO2_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO2_FUN_IE_S 9 -/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO2_FUN_DRV 0x00000003U -#define IO_MUX_GPIO2_FUN_DRV_M (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S) -#define IO_MUX_GPIO2_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO2_FUN_DRV_S 10 -/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO2_MCU_SEL 0x00000007U -#define IO_MUX_GPIO2_MCU_SEL_M (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S) -#define IO_MUX_GPIO2_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO2_MCU_SEL_S 12 -/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO2_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO2_FILTER_EN_M (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S) -#define IO_MUX_GPIO2_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO2_FILTER_EN_S 15 - -/** IO_MUX_gpio3_REG register - * iomux control register for gpio3 - */ -#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10) -/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_OE (BIT(0)) -#define IO_MUX_GPIO3_MCU_OE_M (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S) -#define IO_MUX_GPIO3_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO3_MCU_OE_S 0 -/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO3_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO3_SLP_SEL_M (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S) -#define IO_MUX_GPIO3_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO3_SLP_SEL_S 1 -/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO3_MCU_WPD_M (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S) -#define IO_MUX_GPIO3_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO3_MCU_WPD_S 2 -/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO3_MCU_WPU_M (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S) -#define IO_MUX_GPIO3_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO3_MCU_WPU_S 3 -/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_IE (BIT(4)) -#define IO_MUX_GPIO3_MCU_IE_M (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S) -#define IO_MUX_GPIO3_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO3_MCU_IE_S 4 -/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO3_MCU_DRV 0x00000003U -#define IO_MUX_GPIO3_MCU_DRV_M (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S) -#define IO_MUX_GPIO3_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO3_MCU_DRV_S 5 -/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO3_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO3_FUN_WPD_M (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S) -#define IO_MUX_GPIO3_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO3_FUN_WPD_S 7 -/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO3_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO3_FUN_WPU_M (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S) -#define IO_MUX_GPIO3_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO3_FUN_WPU_S 8 -/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO3_FUN_IE (BIT(9)) -#define IO_MUX_GPIO3_FUN_IE_M (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S) -#define IO_MUX_GPIO3_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO3_FUN_IE_S 9 -/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO3_FUN_DRV 0x00000003U -#define IO_MUX_GPIO3_FUN_DRV_M (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S) -#define IO_MUX_GPIO3_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO3_FUN_DRV_S 10 -/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO3_MCU_SEL 0x00000007U -#define IO_MUX_GPIO3_MCU_SEL_M (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S) -#define IO_MUX_GPIO3_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO3_MCU_SEL_S 12 -/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO3_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO3_FILTER_EN_M (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S) -#define IO_MUX_GPIO3_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO3_FILTER_EN_S 15 - -/** IO_MUX_gpio4_REG register - * iomux control register for gpio4 - */ -#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14) -/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_OE (BIT(0)) -#define IO_MUX_GPIO4_MCU_OE_M (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S) -#define IO_MUX_GPIO4_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO4_MCU_OE_S 0 -/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO4_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO4_SLP_SEL_M (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S) -#define IO_MUX_GPIO4_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO4_SLP_SEL_S 1 -/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO4_MCU_WPD_M (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S) -#define IO_MUX_GPIO4_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO4_MCU_WPD_S 2 -/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO4_MCU_WPU_M (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S) -#define IO_MUX_GPIO4_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO4_MCU_WPU_S 3 -/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_IE (BIT(4)) -#define IO_MUX_GPIO4_MCU_IE_M (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S) -#define IO_MUX_GPIO4_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO4_MCU_IE_S 4 -/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO4_MCU_DRV 0x00000003U -#define IO_MUX_GPIO4_MCU_DRV_M (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S) -#define IO_MUX_GPIO4_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO4_MCU_DRV_S 5 -/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO4_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO4_FUN_WPD_M (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S) -#define IO_MUX_GPIO4_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO4_FUN_WPD_S 7 -/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO4_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO4_FUN_WPU_M (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S) -#define IO_MUX_GPIO4_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO4_FUN_WPU_S 8 -/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO4_FUN_IE (BIT(9)) -#define IO_MUX_GPIO4_FUN_IE_M (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S) -#define IO_MUX_GPIO4_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO4_FUN_IE_S 9 -/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO4_FUN_DRV 0x00000003U -#define IO_MUX_GPIO4_FUN_DRV_M (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S) -#define IO_MUX_GPIO4_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO4_FUN_DRV_S 10 -/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO4_MCU_SEL 0x00000007U -#define IO_MUX_GPIO4_MCU_SEL_M (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S) -#define IO_MUX_GPIO4_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO4_MCU_SEL_S 12 -/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO4_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO4_FILTER_EN_M (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S) -#define IO_MUX_GPIO4_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO4_FILTER_EN_S 15 - -/** IO_MUX_gpio5_REG register - * iomux control register for gpio5 - */ -#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18) -/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_OE (BIT(0)) -#define IO_MUX_GPIO5_MCU_OE_M (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S) -#define IO_MUX_GPIO5_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO5_MCU_OE_S 0 -/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO5_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO5_SLP_SEL_M (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S) -#define IO_MUX_GPIO5_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO5_SLP_SEL_S 1 -/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO5_MCU_WPD_M (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S) -#define IO_MUX_GPIO5_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO5_MCU_WPD_S 2 -/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO5_MCU_WPU_M (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S) -#define IO_MUX_GPIO5_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO5_MCU_WPU_S 3 -/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_IE (BIT(4)) -#define IO_MUX_GPIO5_MCU_IE_M (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S) -#define IO_MUX_GPIO5_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO5_MCU_IE_S 4 -/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO5_MCU_DRV 0x00000003U -#define IO_MUX_GPIO5_MCU_DRV_M (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S) -#define IO_MUX_GPIO5_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO5_MCU_DRV_S 5 -/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO5_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO5_FUN_WPD_M (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S) -#define IO_MUX_GPIO5_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO5_FUN_WPD_S 7 -/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO5_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO5_FUN_WPU_M (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S) -#define IO_MUX_GPIO5_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO5_FUN_WPU_S 8 -/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO5_FUN_IE (BIT(9)) -#define IO_MUX_GPIO5_FUN_IE_M (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S) -#define IO_MUX_GPIO5_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO5_FUN_IE_S 9 -/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO5_FUN_DRV 0x00000003U -#define IO_MUX_GPIO5_FUN_DRV_M (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S) -#define IO_MUX_GPIO5_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO5_FUN_DRV_S 10 -/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO5_MCU_SEL 0x00000007U -#define IO_MUX_GPIO5_MCU_SEL_M (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S) -#define IO_MUX_GPIO5_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO5_MCU_SEL_S 12 -/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO5_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO5_FILTER_EN_M (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S) -#define IO_MUX_GPIO5_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO5_FILTER_EN_S 15 - -/** IO_MUX_gpio6_REG register - * iomux control register for gpio6 - */ -#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c) -/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_OE (BIT(0)) -#define IO_MUX_GPIO6_MCU_OE_M (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S) -#define IO_MUX_GPIO6_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO6_MCU_OE_S 0 -/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO6_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO6_SLP_SEL_M (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S) -#define IO_MUX_GPIO6_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO6_SLP_SEL_S 1 -/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO6_MCU_WPD_M (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S) -#define IO_MUX_GPIO6_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO6_MCU_WPD_S 2 -/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO6_MCU_WPU_M (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S) -#define IO_MUX_GPIO6_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO6_MCU_WPU_S 3 -/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_IE (BIT(4)) -#define IO_MUX_GPIO6_MCU_IE_M (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S) -#define IO_MUX_GPIO6_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO6_MCU_IE_S 4 -/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO6_MCU_DRV 0x00000003U -#define IO_MUX_GPIO6_MCU_DRV_M (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S) -#define IO_MUX_GPIO6_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO6_MCU_DRV_S 5 -/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO6_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO6_FUN_WPD_M (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S) -#define IO_MUX_GPIO6_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO6_FUN_WPD_S 7 -/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO6_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO6_FUN_WPU_M (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S) -#define IO_MUX_GPIO6_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO6_FUN_WPU_S 8 -/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO6_FUN_IE (BIT(9)) -#define IO_MUX_GPIO6_FUN_IE_M (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S) -#define IO_MUX_GPIO6_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO6_FUN_IE_S 9 -/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO6_FUN_DRV 0x00000003U -#define IO_MUX_GPIO6_FUN_DRV_M (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S) -#define IO_MUX_GPIO6_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO6_FUN_DRV_S 10 -/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO6_MCU_SEL 0x00000007U -#define IO_MUX_GPIO6_MCU_SEL_M (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S) -#define IO_MUX_GPIO6_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO6_MCU_SEL_S 12 -/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO6_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO6_FILTER_EN_M (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S) -#define IO_MUX_GPIO6_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO6_FILTER_EN_S 15 - -/** IO_MUX_gpio7_REG register - * iomux control register for gpio7 - */ -#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20) -/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_OE (BIT(0)) -#define IO_MUX_GPIO7_MCU_OE_M (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S) -#define IO_MUX_GPIO7_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO7_MCU_OE_S 0 -/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO7_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO7_SLP_SEL_M (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S) -#define IO_MUX_GPIO7_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO7_SLP_SEL_S 1 -/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO7_MCU_WPD_M (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S) -#define IO_MUX_GPIO7_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO7_MCU_WPD_S 2 -/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO7_MCU_WPU_M (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S) -#define IO_MUX_GPIO7_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO7_MCU_WPU_S 3 -/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_IE (BIT(4)) -#define IO_MUX_GPIO7_MCU_IE_M (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S) -#define IO_MUX_GPIO7_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO7_MCU_IE_S 4 -/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO7_MCU_DRV 0x00000003U -#define IO_MUX_GPIO7_MCU_DRV_M (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S) -#define IO_MUX_GPIO7_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO7_MCU_DRV_S 5 -/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO7_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO7_FUN_WPD_M (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S) -#define IO_MUX_GPIO7_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO7_FUN_WPD_S 7 -/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO7_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO7_FUN_WPU_M (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S) -#define IO_MUX_GPIO7_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO7_FUN_WPU_S 8 -/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO7_FUN_IE (BIT(9)) -#define IO_MUX_GPIO7_FUN_IE_M (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S) -#define IO_MUX_GPIO7_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO7_FUN_IE_S 9 -/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO7_FUN_DRV 0x00000003U -#define IO_MUX_GPIO7_FUN_DRV_M (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S) -#define IO_MUX_GPIO7_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO7_FUN_DRV_S 10 -/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO7_MCU_SEL 0x00000007U -#define IO_MUX_GPIO7_MCU_SEL_M (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S) -#define IO_MUX_GPIO7_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO7_MCU_SEL_S 12 -/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO7_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO7_FILTER_EN_M (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S) -#define IO_MUX_GPIO7_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO7_FILTER_EN_S 15 - -/** IO_MUX_gpio8_REG register - * iomux control register for gpio8 - */ -#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24) -/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_OE (BIT(0)) -#define IO_MUX_GPIO8_MCU_OE_M (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S) -#define IO_MUX_GPIO8_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO8_MCU_OE_S 0 -/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO8_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO8_SLP_SEL_M (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S) -#define IO_MUX_GPIO8_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO8_SLP_SEL_S 1 -/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO8_MCU_WPD_M (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S) -#define IO_MUX_GPIO8_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO8_MCU_WPD_S 2 -/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO8_MCU_WPU_M (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S) -#define IO_MUX_GPIO8_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO8_MCU_WPU_S 3 -/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_IE (BIT(4)) -#define IO_MUX_GPIO8_MCU_IE_M (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S) -#define IO_MUX_GPIO8_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO8_MCU_IE_S 4 -/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO8_MCU_DRV 0x00000003U -#define IO_MUX_GPIO8_MCU_DRV_M (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S) -#define IO_MUX_GPIO8_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO8_MCU_DRV_S 5 -/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO8_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO8_FUN_WPD_M (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S) -#define IO_MUX_GPIO8_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO8_FUN_WPD_S 7 -/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO8_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO8_FUN_WPU_M (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S) -#define IO_MUX_GPIO8_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO8_FUN_WPU_S 8 -/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO8_FUN_IE (BIT(9)) -#define IO_MUX_GPIO8_FUN_IE_M (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S) -#define IO_MUX_GPIO8_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO8_FUN_IE_S 9 -/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO8_FUN_DRV 0x00000003U -#define IO_MUX_GPIO8_FUN_DRV_M (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S) -#define IO_MUX_GPIO8_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO8_FUN_DRV_S 10 -/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO8_MCU_SEL 0x00000007U -#define IO_MUX_GPIO8_MCU_SEL_M (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S) -#define IO_MUX_GPIO8_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO8_MCU_SEL_S 12 -/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO8_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO8_FILTER_EN_M (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S) -#define IO_MUX_GPIO8_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO8_FILTER_EN_S 15 - -/** IO_MUX_gpio9_REG register - * iomux control register for gpio9 - */ -#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28) -/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_OE (BIT(0)) -#define IO_MUX_GPIO9_MCU_OE_M (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S) -#define IO_MUX_GPIO9_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO9_MCU_OE_S 0 -/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO9_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO9_SLP_SEL_M (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S) -#define IO_MUX_GPIO9_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO9_SLP_SEL_S 1 -/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO9_MCU_WPD_M (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S) -#define IO_MUX_GPIO9_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO9_MCU_WPD_S 2 -/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO9_MCU_WPU_M (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S) -#define IO_MUX_GPIO9_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO9_MCU_WPU_S 3 -/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_IE (BIT(4)) -#define IO_MUX_GPIO9_MCU_IE_M (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S) -#define IO_MUX_GPIO9_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO9_MCU_IE_S 4 -/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO9_MCU_DRV 0x00000003U -#define IO_MUX_GPIO9_MCU_DRV_M (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S) -#define IO_MUX_GPIO9_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO9_MCU_DRV_S 5 -/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO9_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO9_FUN_WPD_M (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S) -#define IO_MUX_GPIO9_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO9_FUN_WPD_S 7 -/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO9_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO9_FUN_WPU_M (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S) -#define IO_MUX_GPIO9_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO9_FUN_WPU_S 8 -/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO9_FUN_IE (BIT(9)) -#define IO_MUX_GPIO9_FUN_IE_M (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S) -#define IO_MUX_GPIO9_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO9_FUN_IE_S 9 -/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO9_FUN_DRV 0x00000003U -#define IO_MUX_GPIO9_FUN_DRV_M (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S) -#define IO_MUX_GPIO9_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO9_FUN_DRV_S 10 -/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO9_MCU_SEL 0x00000007U -#define IO_MUX_GPIO9_MCU_SEL_M (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S) -#define IO_MUX_GPIO9_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO9_MCU_SEL_S 12 -/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO9_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO9_FILTER_EN_M (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S) -#define IO_MUX_GPIO9_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO9_FILTER_EN_S 15 - -/** IO_MUX_gpio10_REG register - * iomux control register for gpio10 - */ -#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c) -/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_OE (BIT(0)) -#define IO_MUX_GPIO10_MCU_OE_M (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S) -#define IO_MUX_GPIO10_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO10_MCU_OE_S 0 -/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO10_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO10_SLP_SEL_M (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S) -#define IO_MUX_GPIO10_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO10_SLP_SEL_S 1 -/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO10_MCU_WPD_M (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S) -#define IO_MUX_GPIO10_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO10_MCU_WPD_S 2 -/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO10_MCU_WPU_M (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S) -#define IO_MUX_GPIO10_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO10_MCU_WPU_S 3 -/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_IE (BIT(4)) -#define IO_MUX_GPIO10_MCU_IE_M (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S) -#define IO_MUX_GPIO10_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO10_MCU_IE_S 4 -/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO10_MCU_DRV 0x00000003U -#define IO_MUX_GPIO10_MCU_DRV_M (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S) -#define IO_MUX_GPIO10_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO10_MCU_DRV_S 5 -/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO10_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO10_FUN_WPD_M (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S) -#define IO_MUX_GPIO10_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO10_FUN_WPD_S 7 -/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO10_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO10_FUN_WPU_M (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S) -#define IO_MUX_GPIO10_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO10_FUN_WPU_S 8 -/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO10_FUN_IE (BIT(9)) -#define IO_MUX_GPIO10_FUN_IE_M (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S) -#define IO_MUX_GPIO10_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO10_FUN_IE_S 9 -/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO10_FUN_DRV 0x00000003U -#define IO_MUX_GPIO10_FUN_DRV_M (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S) -#define IO_MUX_GPIO10_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO10_FUN_DRV_S 10 -/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO10_MCU_SEL 0x00000007U -#define IO_MUX_GPIO10_MCU_SEL_M (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S) -#define IO_MUX_GPIO10_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO10_MCU_SEL_S 12 -/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO10_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO10_FILTER_EN_M (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S) -#define IO_MUX_GPIO10_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO10_FILTER_EN_S 15 - -/** IO_MUX_gpio11_REG register - * iomux control register for gpio11 - */ -#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30) -/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_OE (BIT(0)) -#define IO_MUX_GPIO11_MCU_OE_M (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S) -#define IO_MUX_GPIO11_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO11_MCU_OE_S 0 -/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO11_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO11_SLP_SEL_M (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S) -#define IO_MUX_GPIO11_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO11_SLP_SEL_S 1 -/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO11_MCU_WPD_M (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S) -#define IO_MUX_GPIO11_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO11_MCU_WPD_S 2 -/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO11_MCU_WPU_M (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S) -#define IO_MUX_GPIO11_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO11_MCU_WPU_S 3 -/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_IE (BIT(4)) -#define IO_MUX_GPIO11_MCU_IE_M (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S) -#define IO_MUX_GPIO11_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO11_MCU_IE_S 4 -/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO11_MCU_DRV 0x00000003U -#define IO_MUX_GPIO11_MCU_DRV_M (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S) -#define IO_MUX_GPIO11_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO11_MCU_DRV_S 5 -/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO11_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO11_FUN_WPD_M (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S) -#define IO_MUX_GPIO11_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO11_FUN_WPD_S 7 -/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO11_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO11_FUN_WPU_M (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S) -#define IO_MUX_GPIO11_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO11_FUN_WPU_S 8 -/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO11_FUN_IE (BIT(9)) -#define IO_MUX_GPIO11_FUN_IE_M (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S) -#define IO_MUX_GPIO11_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO11_FUN_IE_S 9 -/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO11_FUN_DRV 0x00000003U -#define IO_MUX_GPIO11_FUN_DRV_M (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S) -#define IO_MUX_GPIO11_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO11_FUN_DRV_S 10 -/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO11_MCU_SEL 0x00000007U -#define IO_MUX_GPIO11_MCU_SEL_M (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S) -#define IO_MUX_GPIO11_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO11_MCU_SEL_S 12 -/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO11_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO11_FILTER_EN_M (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S) -#define IO_MUX_GPIO11_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO11_FILTER_EN_S 15 - -/** IO_MUX_gpio12_REG register - * iomux control register for gpio12 - */ -#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34) -/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_OE (BIT(0)) -#define IO_MUX_GPIO12_MCU_OE_M (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S) -#define IO_MUX_GPIO12_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO12_MCU_OE_S 0 -/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO12_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO12_SLP_SEL_M (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S) -#define IO_MUX_GPIO12_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO12_SLP_SEL_S 1 -/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO12_MCU_WPD_M (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S) -#define IO_MUX_GPIO12_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO12_MCU_WPD_S 2 -/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO12_MCU_WPU_M (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S) -#define IO_MUX_GPIO12_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO12_MCU_WPU_S 3 -/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_IE (BIT(4)) -#define IO_MUX_GPIO12_MCU_IE_M (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S) -#define IO_MUX_GPIO12_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO12_MCU_IE_S 4 -/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO12_MCU_DRV 0x00000003U -#define IO_MUX_GPIO12_MCU_DRV_M (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S) -#define IO_MUX_GPIO12_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO12_MCU_DRV_S 5 -/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO12_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO12_FUN_WPD_M (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S) -#define IO_MUX_GPIO12_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO12_FUN_WPD_S 7 -/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO12_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO12_FUN_WPU_M (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S) -#define IO_MUX_GPIO12_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO12_FUN_WPU_S 8 -/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO12_FUN_IE (BIT(9)) -#define IO_MUX_GPIO12_FUN_IE_M (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S) -#define IO_MUX_GPIO12_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO12_FUN_IE_S 9 -/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO12_FUN_DRV 0x00000003U -#define IO_MUX_GPIO12_FUN_DRV_M (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S) -#define IO_MUX_GPIO12_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO12_FUN_DRV_S 10 -/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO12_MCU_SEL 0x00000007U -#define IO_MUX_GPIO12_MCU_SEL_M (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S) -#define IO_MUX_GPIO12_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO12_MCU_SEL_S 12 -/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO12_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO12_FILTER_EN_M (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S) -#define IO_MUX_GPIO12_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO12_FILTER_EN_S 15 - -/** IO_MUX_gpio13_REG register - * iomux control register for gpio13 - */ -#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38) -/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_OE (BIT(0)) -#define IO_MUX_GPIO13_MCU_OE_M (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S) -#define IO_MUX_GPIO13_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO13_MCU_OE_S 0 -/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO13_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO13_SLP_SEL_M (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S) -#define IO_MUX_GPIO13_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO13_SLP_SEL_S 1 -/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO13_MCU_WPD_M (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S) -#define IO_MUX_GPIO13_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO13_MCU_WPD_S 2 -/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO13_MCU_WPU_M (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S) -#define IO_MUX_GPIO13_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO13_MCU_WPU_S 3 -/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_IE (BIT(4)) -#define IO_MUX_GPIO13_MCU_IE_M (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S) -#define IO_MUX_GPIO13_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO13_MCU_IE_S 4 -/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO13_MCU_DRV 0x00000003U -#define IO_MUX_GPIO13_MCU_DRV_M (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S) -#define IO_MUX_GPIO13_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO13_MCU_DRV_S 5 -/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO13_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO13_FUN_WPD_M (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S) -#define IO_MUX_GPIO13_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO13_FUN_WPD_S 7 -/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO13_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO13_FUN_WPU_M (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S) -#define IO_MUX_GPIO13_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO13_FUN_WPU_S 8 -/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO13_FUN_IE (BIT(9)) -#define IO_MUX_GPIO13_FUN_IE_M (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S) -#define IO_MUX_GPIO13_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO13_FUN_IE_S 9 -/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO13_FUN_DRV 0x00000003U -#define IO_MUX_GPIO13_FUN_DRV_M (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S) -#define IO_MUX_GPIO13_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO13_FUN_DRV_S 10 -/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO13_MCU_SEL 0x00000007U -#define IO_MUX_GPIO13_MCU_SEL_M (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S) -#define IO_MUX_GPIO13_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO13_MCU_SEL_S 12 -/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO13_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO13_FILTER_EN_M (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S) -#define IO_MUX_GPIO13_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO13_FILTER_EN_S 15 - -/** IO_MUX_gpio14_REG register - * iomux control register for gpio14 - */ -#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c) -/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_OE (BIT(0)) -#define IO_MUX_GPIO14_MCU_OE_M (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S) -#define IO_MUX_GPIO14_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO14_MCU_OE_S 0 -/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO14_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO14_SLP_SEL_M (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S) -#define IO_MUX_GPIO14_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO14_SLP_SEL_S 1 -/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO14_MCU_WPD_M (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S) -#define IO_MUX_GPIO14_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO14_MCU_WPD_S 2 -/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO14_MCU_WPU_M (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S) -#define IO_MUX_GPIO14_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO14_MCU_WPU_S 3 -/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_IE (BIT(4)) -#define IO_MUX_GPIO14_MCU_IE_M (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S) -#define IO_MUX_GPIO14_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO14_MCU_IE_S 4 -/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO14_MCU_DRV 0x00000003U -#define IO_MUX_GPIO14_MCU_DRV_M (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S) -#define IO_MUX_GPIO14_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO14_MCU_DRV_S 5 -/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO14_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO14_FUN_WPD_M (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S) -#define IO_MUX_GPIO14_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO14_FUN_WPD_S 7 -/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO14_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO14_FUN_WPU_M (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S) -#define IO_MUX_GPIO14_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO14_FUN_WPU_S 8 -/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO14_FUN_IE (BIT(9)) -#define IO_MUX_GPIO14_FUN_IE_M (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S) -#define IO_MUX_GPIO14_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO14_FUN_IE_S 9 -/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO14_FUN_DRV 0x00000003U -#define IO_MUX_GPIO14_FUN_DRV_M (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S) -#define IO_MUX_GPIO14_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO14_FUN_DRV_S 10 -/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO14_MCU_SEL 0x00000007U -#define IO_MUX_GPIO14_MCU_SEL_M (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S) -#define IO_MUX_GPIO14_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO14_MCU_SEL_S 12 -/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO14_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO14_FILTER_EN_M (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S) -#define IO_MUX_GPIO14_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO14_FILTER_EN_S 15 - -/** IO_MUX_gpio15_REG register - * iomux control register for gpio15 - */ -#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40) -/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_OE (BIT(0)) -#define IO_MUX_GPIO15_MCU_OE_M (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S) -#define IO_MUX_GPIO15_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO15_MCU_OE_S 0 -/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO15_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO15_SLP_SEL_M (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S) -#define IO_MUX_GPIO15_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO15_SLP_SEL_S 1 -/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO15_MCU_WPD_M (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S) -#define IO_MUX_GPIO15_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO15_MCU_WPD_S 2 -/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO15_MCU_WPU_M (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S) -#define IO_MUX_GPIO15_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO15_MCU_WPU_S 3 -/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_IE (BIT(4)) -#define IO_MUX_GPIO15_MCU_IE_M (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S) -#define IO_MUX_GPIO15_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO15_MCU_IE_S 4 -/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO15_MCU_DRV 0x00000003U -#define IO_MUX_GPIO15_MCU_DRV_M (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S) -#define IO_MUX_GPIO15_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO15_MCU_DRV_S 5 -/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO15_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO15_FUN_WPD_M (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S) -#define IO_MUX_GPIO15_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO15_FUN_WPD_S 7 -/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO15_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO15_FUN_WPU_M (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S) -#define IO_MUX_GPIO15_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO15_FUN_WPU_S 8 -/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO15_FUN_IE (BIT(9)) -#define IO_MUX_GPIO15_FUN_IE_M (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S) -#define IO_MUX_GPIO15_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO15_FUN_IE_S 9 -/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO15_FUN_DRV 0x00000003U -#define IO_MUX_GPIO15_FUN_DRV_M (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S) -#define IO_MUX_GPIO15_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO15_FUN_DRV_S 10 -/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO15_MCU_SEL 0x00000007U -#define IO_MUX_GPIO15_MCU_SEL_M (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S) -#define IO_MUX_GPIO15_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO15_MCU_SEL_S 12 -/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO15_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO15_FILTER_EN_M (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S) -#define IO_MUX_GPIO15_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO15_FILTER_EN_S 15 - -/** IO_MUX_gpio16_REG register - * iomux control register for gpio16 - */ -#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44) -/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_OE (BIT(0)) -#define IO_MUX_GPIO16_MCU_OE_M (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S) -#define IO_MUX_GPIO16_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO16_MCU_OE_S 0 -/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO16_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO16_SLP_SEL_M (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S) -#define IO_MUX_GPIO16_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO16_SLP_SEL_S 1 -/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO16_MCU_WPD_M (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S) -#define IO_MUX_GPIO16_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO16_MCU_WPD_S 2 -/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO16_MCU_WPU_M (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S) -#define IO_MUX_GPIO16_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO16_MCU_WPU_S 3 -/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_IE (BIT(4)) -#define IO_MUX_GPIO16_MCU_IE_M (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S) -#define IO_MUX_GPIO16_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO16_MCU_IE_S 4 -/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO16_MCU_DRV 0x00000003U -#define IO_MUX_GPIO16_MCU_DRV_M (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S) -#define IO_MUX_GPIO16_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO16_MCU_DRV_S 5 -/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO16_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO16_FUN_WPD_M (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S) -#define IO_MUX_GPIO16_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO16_FUN_WPD_S 7 -/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO16_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO16_FUN_WPU_M (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S) -#define IO_MUX_GPIO16_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO16_FUN_WPU_S 8 -/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO16_FUN_IE (BIT(9)) -#define IO_MUX_GPIO16_FUN_IE_M (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S) -#define IO_MUX_GPIO16_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO16_FUN_IE_S 9 -/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO16_FUN_DRV 0x00000003U -#define IO_MUX_GPIO16_FUN_DRV_M (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S) -#define IO_MUX_GPIO16_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO16_FUN_DRV_S 10 -/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO16_MCU_SEL 0x00000007U -#define IO_MUX_GPIO16_MCU_SEL_M (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S) -#define IO_MUX_GPIO16_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO16_MCU_SEL_S 12 -/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO16_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO16_FILTER_EN_M (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S) -#define IO_MUX_GPIO16_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO16_FILTER_EN_S 15 - -/** IO_MUX_gpio17_REG register - * iomux control register for gpio17 - */ -#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48) -/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_OE (BIT(0)) -#define IO_MUX_GPIO17_MCU_OE_M (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S) -#define IO_MUX_GPIO17_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO17_MCU_OE_S 0 -/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO17_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO17_SLP_SEL_M (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S) -#define IO_MUX_GPIO17_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO17_SLP_SEL_S 1 -/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO17_MCU_WPD_M (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S) -#define IO_MUX_GPIO17_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO17_MCU_WPD_S 2 -/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO17_MCU_WPU_M (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S) -#define IO_MUX_GPIO17_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO17_MCU_WPU_S 3 -/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_IE (BIT(4)) -#define IO_MUX_GPIO17_MCU_IE_M (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S) -#define IO_MUX_GPIO17_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO17_MCU_IE_S 4 -/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO17_MCU_DRV 0x00000003U -#define IO_MUX_GPIO17_MCU_DRV_M (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S) -#define IO_MUX_GPIO17_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO17_MCU_DRV_S 5 -/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO17_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO17_FUN_WPD_M (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S) -#define IO_MUX_GPIO17_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO17_FUN_WPD_S 7 -/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO17_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO17_FUN_WPU_M (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S) -#define IO_MUX_GPIO17_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO17_FUN_WPU_S 8 -/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO17_FUN_IE (BIT(9)) -#define IO_MUX_GPIO17_FUN_IE_M (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S) -#define IO_MUX_GPIO17_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO17_FUN_IE_S 9 -/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO17_FUN_DRV 0x00000003U -#define IO_MUX_GPIO17_FUN_DRV_M (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S) -#define IO_MUX_GPIO17_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO17_FUN_DRV_S 10 -/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO17_MCU_SEL 0x00000007U -#define IO_MUX_GPIO17_MCU_SEL_M (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S) -#define IO_MUX_GPIO17_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO17_MCU_SEL_S 12 -/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO17_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO17_FILTER_EN_M (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S) -#define IO_MUX_GPIO17_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO17_FILTER_EN_S 15 - -/** IO_MUX_gpio18_REG register - * iomux control register for gpio18 - */ -#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c) -/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_OE (BIT(0)) -#define IO_MUX_GPIO18_MCU_OE_M (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S) -#define IO_MUX_GPIO18_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO18_MCU_OE_S 0 -/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO18_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO18_SLP_SEL_M (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S) -#define IO_MUX_GPIO18_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO18_SLP_SEL_S 1 -/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO18_MCU_WPD_M (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S) -#define IO_MUX_GPIO18_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO18_MCU_WPD_S 2 -/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO18_MCU_WPU_M (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S) -#define IO_MUX_GPIO18_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO18_MCU_WPU_S 3 -/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_IE (BIT(4)) -#define IO_MUX_GPIO18_MCU_IE_M (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S) -#define IO_MUX_GPIO18_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO18_MCU_IE_S 4 -/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO18_MCU_DRV 0x00000003U -#define IO_MUX_GPIO18_MCU_DRV_M (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S) -#define IO_MUX_GPIO18_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO18_MCU_DRV_S 5 -/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO18_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO18_FUN_WPD_M (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S) -#define IO_MUX_GPIO18_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO18_FUN_WPD_S 7 -/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO18_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO18_FUN_WPU_M (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S) -#define IO_MUX_GPIO18_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO18_FUN_WPU_S 8 -/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO18_FUN_IE (BIT(9)) -#define IO_MUX_GPIO18_FUN_IE_M (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S) -#define IO_MUX_GPIO18_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO18_FUN_IE_S 9 -/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO18_FUN_DRV 0x00000003U -#define IO_MUX_GPIO18_FUN_DRV_M (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S) -#define IO_MUX_GPIO18_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO18_FUN_DRV_S 10 -/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO18_MCU_SEL 0x00000007U -#define IO_MUX_GPIO18_MCU_SEL_M (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S) -#define IO_MUX_GPIO18_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO18_MCU_SEL_S 12 -/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO18_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO18_FILTER_EN_M (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S) -#define IO_MUX_GPIO18_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO18_FILTER_EN_S 15 - -/** IO_MUX_gpio19_REG register - * iomux control register for gpio19 - */ -#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50) -/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_OE (BIT(0)) -#define IO_MUX_GPIO19_MCU_OE_M (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S) -#define IO_MUX_GPIO19_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO19_MCU_OE_S 0 -/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO19_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO19_SLP_SEL_M (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S) -#define IO_MUX_GPIO19_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO19_SLP_SEL_S 1 -/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO19_MCU_WPD_M (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S) -#define IO_MUX_GPIO19_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO19_MCU_WPD_S 2 -/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO19_MCU_WPU_M (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S) -#define IO_MUX_GPIO19_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO19_MCU_WPU_S 3 -/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_IE (BIT(4)) -#define IO_MUX_GPIO19_MCU_IE_M (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S) -#define IO_MUX_GPIO19_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO19_MCU_IE_S 4 -/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO19_MCU_DRV 0x00000003U -#define IO_MUX_GPIO19_MCU_DRV_M (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S) -#define IO_MUX_GPIO19_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO19_MCU_DRV_S 5 -/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO19_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO19_FUN_WPD_M (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S) -#define IO_MUX_GPIO19_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO19_FUN_WPD_S 7 -/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO19_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO19_FUN_WPU_M (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S) -#define IO_MUX_GPIO19_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO19_FUN_WPU_S 8 -/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO19_FUN_IE (BIT(9)) -#define IO_MUX_GPIO19_FUN_IE_M (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S) -#define IO_MUX_GPIO19_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO19_FUN_IE_S 9 -/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO19_FUN_DRV 0x00000003U -#define IO_MUX_GPIO19_FUN_DRV_M (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S) -#define IO_MUX_GPIO19_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO19_FUN_DRV_S 10 -/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO19_MCU_SEL 0x00000007U -#define IO_MUX_GPIO19_MCU_SEL_M (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S) -#define IO_MUX_GPIO19_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO19_MCU_SEL_S 12 -/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO19_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO19_FILTER_EN_M (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S) -#define IO_MUX_GPIO19_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO19_FILTER_EN_S 15 - -/** IO_MUX_gpio20_REG register - * iomux control register for gpio20 - */ -#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54) -/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_OE (BIT(0)) -#define IO_MUX_GPIO20_MCU_OE_M (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S) -#define IO_MUX_GPIO20_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO20_MCU_OE_S 0 -/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO20_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO20_SLP_SEL_M (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S) -#define IO_MUX_GPIO20_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO20_SLP_SEL_S 1 -/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO20_MCU_WPD_M (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S) -#define IO_MUX_GPIO20_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO20_MCU_WPD_S 2 -/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO20_MCU_WPU_M (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S) -#define IO_MUX_GPIO20_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO20_MCU_WPU_S 3 -/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_IE (BIT(4)) -#define IO_MUX_GPIO20_MCU_IE_M (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S) -#define IO_MUX_GPIO20_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO20_MCU_IE_S 4 -/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO20_MCU_DRV 0x00000003U -#define IO_MUX_GPIO20_MCU_DRV_M (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S) -#define IO_MUX_GPIO20_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO20_MCU_DRV_S 5 -/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO20_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO20_FUN_WPD_M (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S) -#define IO_MUX_GPIO20_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO20_FUN_WPD_S 7 -/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO20_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO20_FUN_WPU_M (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S) -#define IO_MUX_GPIO20_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO20_FUN_WPU_S 8 -/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO20_FUN_IE (BIT(9)) -#define IO_MUX_GPIO20_FUN_IE_M (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S) -#define IO_MUX_GPIO20_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO20_FUN_IE_S 9 -/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO20_FUN_DRV 0x00000003U -#define IO_MUX_GPIO20_FUN_DRV_M (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S) -#define IO_MUX_GPIO20_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO20_FUN_DRV_S 10 -/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO20_MCU_SEL 0x00000007U -#define IO_MUX_GPIO20_MCU_SEL_M (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S) -#define IO_MUX_GPIO20_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO20_MCU_SEL_S 12 -/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO20_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO20_FILTER_EN_M (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S) -#define IO_MUX_GPIO20_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO20_FILTER_EN_S 15 - -/** IO_MUX_gpio21_REG register - * iomux control register for gpio21 - */ -#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58) -/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_OE (BIT(0)) -#define IO_MUX_GPIO21_MCU_OE_M (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S) -#define IO_MUX_GPIO21_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO21_MCU_OE_S 0 -/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO21_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO21_SLP_SEL_M (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S) -#define IO_MUX_GPIO21_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO21_SLP_SEL_S 1 -/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO21_MCU_WPD_M (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S) -#define IO_MUX_GPIO21_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO21_MCU_WPD_S 2 -/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO21_MCU_WPU_M (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S) -#define IO_MUX_GPIO21_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO21_MCU_WPU_S 3 -/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_IE (BIT(4)) -#define IO_MUX_GPIO21_MCU_IE_M (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S) -#define IO_MUX_GPIO21_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO21_MCU_IE_S 4 -/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO21_MCU_DRV 0x00000003U -#define IO_MUX_GPIO21_MCU_DRV_M (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S) -#define IO_MUX_GPIO21_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO21_MCU_DRV_S 5 -/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO21_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO21_FUN_WPD_M (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S) -#define IO_MUX_GPIO21_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO21_FUN_WPD_S 7 -/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO21_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO21_FUN_WPU_M (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S) -#define IO_MUX_GPIO21_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO21_FUN_WPU_S 8 -/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO21_FUN_IE (BIT(9)) -#define IO_MUX_GPIO21_FUN_IE_M (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S) -#define IO_MUX_GPIO21_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO21_FUN_IE_S 9 -/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO21_FUN_DRV 0x00000003U -#define IO_MUX_GPIO21_FUN_DRV_M (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S) -#define IO_MUX_GPIO21_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO21_FUN_DRV_S 10 -/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO21_MCU_SEL 0x00000007U -#define IO_MUX_GPIO21_MCU_SEL_M (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S) -#define IO_MUX_GPIO21_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO21_MCU_SEL_S 12 -/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO21_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO21_FILTER_EN_M (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S) -#define IO_MUX_GPIO21_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO21_FILTER_EN_S 15 - -/** IO_MUX_gpio22_REG register - * iomux control register for gpio22 - */ -#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c) -/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_OE (BIT(0)) -#define IO_MUX_GPIO22_MCU_OE_M (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S) -#define IO_MUX_GPIO22_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO22_MCU_OE_S 0 -/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO22_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO22_SLP_SEL_M (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S) -#define IO_MUX_GPIO22_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO22_SLP_SEL_S 1 -/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO22_MCU_WPD_M (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S) -#define IO_MUX_GPIO22_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO22_MCU_WPD_S 2 -/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO22_MCU_WPU_M (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S) -#define IO_MUX_GPIO22_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO22_MCU_WPU_S 3 -/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_IE (BIT(4)) -#define IO_MUX_GPIO22_MCU_IE_M (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S) -#define IO_MUX_GPIO22_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO22_MCU_IE_S 4 -/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO22_MCU_DRV 0x00000003U -#define IO_MUX_GPIO22_MCU_DRV_M (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S) -#define IO_MUX_GPIO22_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO22_MCU_DRV_S 5 -/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO22_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO22_FUN_WPD_M (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S) -#define IO_MUX_GPIO22_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO22_FUN_WPD_S 7 -/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO22_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO22_FUN_WPU_M (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S) -#define IO_MUX_GPIO22_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO22_FUN_WPU_S 8 -/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO22_FUN_IE (BIT(9)) -#define IO_MUX_GPIO22_FUN_IE_M (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S) -#define IO_MUX_GPIO22_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO22_FUN_IE_S 9 -/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO22_FUN_DRV 0x00000003U -#define IO_MUX_GPIO22_FUN_DRV_M (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S) -#define IO_MUX_GPIO22_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO22_FUN_DRV_S 10 -/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO22_MCU_SEL 0x00000007U -#define IO_MUX_GPIO22_MCU_SEL_M (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S) -#define IO_MUX_GPIO22_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO22_MCU_SEL_S 12 -/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO22_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO22_FILTER_EN_M (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S) -#define IO_MUX_GPIO22_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO22_FILTER_EN_S 15 - -/** IO_MUX_gpio23_REG register - * iomux control register for gpio23 - */ -#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60) -/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_OE (BIT(0)) -#define IO_MUX_GPIO23_MCU_OE_M (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S) -#define IO_MUX_GPIO23_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO23_MCU_OE_S 0 -/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO23_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO23_SLP_SEL_M (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S) -#define IO_MUX_GPIO23_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO23_SLP_SEL_S 1 -/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO23_MCU_WPD_M (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S) -#define IO_MUX_GPIO23_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO23_MCU_WPD_S 2 -/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO23_MCU_WPU_M (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S) -#define IO_MUX_GPIO23_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO23_MCU_WPU_S 3 -/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_IE (BIT(4)) -#define IO_MUX_GPIO23_MCU_IE_M (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S) -#define IO_MUX_GPIO23_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO23_MCU_IE_S 4 -/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO23_MCU_DRV 0x00000003U -#define IO_MUX_GPIO23_MCU_DRV_M (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S) -#define IO_MUX_GPIO23_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO23_MCU_DRV_S 5 -/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO23_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO23_FUN_WPD_M (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S) -#define IO_MUX_GPIO23_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO23_FUN_WPD_S 7 -/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO23_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO23_FUN_WPU_M (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S) -#define IO_MUX_GPIO23_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO23_FUN_WPU_S 8 -/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO23_FUN_IE (BIT(9)) -#define IO_MUX_GPIO23_FUN_IE_M (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S) -#define IO_MUX_GPIO23_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO23_FUN_IE_S 9 -/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO23_FUN_DRV 0x00000003U -#define IO_MUX_GPIO23_FUN_DRV_M (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S) -#define IO_MUX_GPIO23_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO23_FUN_DRV_S 10 -/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO23_MCU_SEL 0x00000007U -#define IO_MUX_GPIO23_MCU_SEL_M (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S) -#define IO_MUX_GPIO23_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO23_MCU_SEL_S 12 -/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO23_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO23_FILTER_EN_M (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S) -#define IO_MUX_GPIO23_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO23_FILTER_EN_S 15 - -/** IO_MUX_gpio24_REG register - * iomux control register for gpio24 - */ -#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64) -/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_OE (BIT(0)) -#define IO_MUX_GPIO24_MCU_OE_M (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S) -#define IO_MUX_GPIO24_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO24_MCU_OE_S 0 -/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO24_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO24_SLP_SEL_M (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S) -#define IO_MUX_GPIO24_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO24_SLP_SEL_S 1 -/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO24_MCU_WPD_M (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S) -#define IO_MUX_GPIO24_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO24_MCU_WPD_S 2 -/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO24_MCU_WPU_M (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S) -#define IO_MUX_GPIO24_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO24_MCU_WPU_S 3 -/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_IE (BIT(4)) -#define IO_MUX_GPIO24_MCU_IE_M (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S) -#define IO_MUX_GPIO24_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO24_MCU_IE_S 4 -/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO24_MCU_DRV 0x00000003U -#define IO_MUX_GPIO24_MCU_DRV_M (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S) -#define IO_MUX_GPIO24_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO24_MCU_DRV_S 5 -/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO24_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO24_FUN_WPD_M (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S) -#define IO_MUX_GPIO24_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO24_FUN_WPD_S 7 -/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO24_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO24_FUN_WPU_M (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S) -#define IO_MUX_GPIO24_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO24_FUN_WPU_S 8 -/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO24_FUN_IE (BIT(9)) -#define IO_MUX_GPIO24_FUN_IE_M (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S) -#define IO_MUX_GPIO24_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO24_FUN_IE_S 9 -/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO24_FUN_DRV 0x00000003U -#define IO_MUX_GPIO24_FUN_DRV_M (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S) -#define IO_MUX_GPIO24_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO24_FUN_DRV_S 10 -/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO24_MCU_SEL 0x00000007U -#define IO_MUX_GPIO24_MCU_SEL_M (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S) -#define IO_MUX_GPIO24_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO24_MCU_SEL_S 12 -/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO24_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO24_FILTER_EN_M (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S) -#define IO_MUX_GPIO24_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO24_FILTER_EN_S 15 - -/** IO_MUX_gpio25_REG register - * iomux control register for gpio25 - */ -#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68) -/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_OE (BIT(0)) -#define IO_MUX_GPIO25_MCU_OE_M (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S) -#define IO_MUX_GPIO25_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO25_MCU_OE_S 0 -/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO25_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO25_SLP_SEL_M (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S) -#define IO_MUX_GPIO25_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO25_SLP_SEL_S 1 -/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO25_MCU_WPD_M (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S) -#define IO_MUX_GPIO25_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO25_MCU_WPD_S 2 -/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO25_MCU_WPU_M (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S) -#define IO_MUX_GPIO25_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO25_MCU_WPU_S 3 -/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_IE (BIT(4)) -#define IO_MUX_GPIO25_MCU_IE_M (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S) -#define IO_MUX_GPIO25_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO25_MCU_IE_S 4 -/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO25_MCU_DRV 0x00000003U -#define IO_MUX_GPIO25_MCU_DRV_M (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S) -#define IO_MUX_GPIO25_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO25_MCU_DRV_S 5 -/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO25_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO25_FUN_WPD_M (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S) -#define IO_MUX_GPIO25_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO25_FUN_WPD_S 7 -/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO25_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO25_FUN_WPU_M (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S) -#define IO_MUX_GPIO25_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO25_FUN_WPU_S 8 -/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO25_FUN_IE (BIT(9)) -#define IO_MUX_GPIO25_FUN_IE_M (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S) -#define IO_MUX_GPIO25_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO25_FUN_IE_S 9 -/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO25_FUN_DRV 0x00000003U -#define IO_MUX_GPIO25_FUN_DRV_M (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S) -#define IO_MUX_GPIO25_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO25_FUN_DRV_S 10 -/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO25_MCU_SEL 0x00000007U -#define IO_MUX_GPIO25_MCU_SEL_M (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S) -#define IO_MUX_GPIO25_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO25_MCU_SEL_S 12 -/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO25_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO25_FILTER_EN_M (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S) -#define IO_MUX_GPIO25_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO25_FILTER_EN_S 15 - -/** IO_MUX_gpio26_REG register - * iomux control register for gpio26 - */ -#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c) -/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_OE (BIT(0)) -#define IO_MUX_GPIO26_MCU_OE_M (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S) -#define IO_MUX_GPIO26_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO26_MCU_OE_S 0 -/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO26_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO26_SLP_SEL_M (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S) -#define IO_MUX_GPIO26_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO26_SLP_SEL_S 1 -/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO26_MCU_WPD_M (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S) -#define IO_MUX_GPIO26_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO26_MCU_WPD_S 2 -/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO26_MCU_WPU_M (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S) -#define IO_MUX_GPIO26_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO26_MCU_WPU_S 3 -/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_IE (BIT(4)) -#define IO_MUX_GPIO26_MCU_IE_M (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S) -#define IO_MUX_GPIO26_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO26_MCU_IE_S 4 -/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO26_MCU_DRV 0x00000003U -#define IO_MUX_GPIO26_MCU_DRV_M (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S) -#define IO_MUX_GPIO26_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO26_MCU_DRV_S 5 -/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO26_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO26_FUN_WPD_M (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S) -#define IO_MUX_GPIO26_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO26_FUN_WPD_S 7 -/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO26_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO26_FUN_WPU_M (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S) -#define IO_MUX_GPIO26_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO26_FUN_WPU_S 8 -/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO26_FUN_IE (BIT(9)) -#define IO_MUX_GPIO26_FUN_IE_M (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S) -#define IO_MUX_GPIO26_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO26_FUN_IE_S 9 -/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO26_FUN_DRV 0x00000003U -#define IO_MUX_GPIO26_FUN_DRV_M (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S) -#define IO_MUX_GPIO26_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO26_FUN_DRV_S 10 -/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO26_MCU_SEL 0x00000007U -#define IO_MUX_GPIO26_MCU_SEL_M (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S) -#define IO_MUX_GPIO26_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO26_MCU_SEL_S 12 -/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO26_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO26_FILTER_EN_M (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S) -#define IO_MUX_GPIO26_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO26_FILTER_EN_S 15 - -/** IO_MUX_gpio27_REG register - * iomux control register for gpio27 - */ -#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70) -/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_OE (BIT(0)) -#define IO_MUX_GPIO27_MCU_OE_M (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S) -#define IO_MUX_GPIO27_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO27_MCU_OE_S 0 -/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO27_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO27_SLP_SEL_M (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S) -#define IO_MUX_GPIO27_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO27_SLP_SEL_S 1 -/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO27_MCU_WPD_M (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S) -#define IO_MUX_GPIO27_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO27_MCU_WPD_S 2 -/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO27_MCU_WPU_M (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S) -#define IO_MUX_GPIO27_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO27_MCU_WPU_S 3 -/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_IE (BIT(4)) -#define IO_MUX_GPIO27_MCU_IE_M (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S) -#define IO_MUX_GPIO27_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO27_MCU_IE_S 4 -/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO27_MCU_DRV 0x00000003U -#define IO_MUX_GPIO27_MCU_DRV_M (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S) -#define IO_MUX_GPIO27_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO27_MCU_DRV_S 5 -/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO27_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO27_FUN_WPD_M (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S) -#define IO_MUX_GPIO27_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO27_FUN_WPD_S 7 -/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO27_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO27_FUN_WPU_M (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S) -#define IO_MUX_GPIO27_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO27_FUN_WPU_S 8 -/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO27_FUN_IE (BIT(9)) -#define IO_MUX_GPIO27_FUN_IE_M (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S) -#define IO_MUX_GPIO27_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO27_FUN_IE_S 9 -/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO27_FUN_DRV 0x00000003U -#define IO_MUX_GPIO27_FUN_DRV_M (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S) -#define IO_MUX_GPIO27_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO27_FUN_DRV_S 10 -/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO27_MCU_SEL 0x00000007U -#define IO_MUX_GPIO27_MCU_SEL_M (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S) -#define IO_MUX_GPIO27_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO27_MCU_SEL_S 12 -/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO27_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO27_FILTER_EN_M (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S) -#define IO_MUX_GPIO27_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO27_FILTER_EN_S 15 - -/** IO_MUX_gpio28_REG register - * iomux control register for gpio28 - */ -#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74) -/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_OE (BIT(0)) -#define IO_MUX_GPIO28_MCU_OE_M (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S) -#define IO_MUX_GPIO28_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO28_MCU_OE_S 0 -/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO28_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO28_SLP_SEL_M (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S) -#define IO_MUX_GPIO28_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO28_SLP_SEL_S 1 -/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO28_MCU_WPD_M (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S) -#define IO_MUX_GPIO28_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO28_MCU_WPD_S 2 -/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO28_MCU_WPU_M (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S) -#define IO_MUX_GPIO28_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO28_MCU_WPU_S 3 -/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_IE (BIT(4)) -#define IO_MUX_GPIO28_MCU_IE_M (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S) -#define IO_MUX_GPIO28_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO28_MCU_IE_S 4 -/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO28_MCU_DRV 0x00000003U -#define IO_MUX_GPIO28_MCU_DRV_M (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S) -#define IO_MUX_GPIO28_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO28_MCU_DRV_S 5 -/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO28_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO28_FUN_WPD_M (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S) -#define IO_MUX_GPIO28_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO28_FUN_WPD_S 7 -/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO28_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO28_FUN_WPU_M (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S) -#define IO_MUX_GPIO28_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO28_FUN_WPU_S 8 -/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO28_FUN_IE (BIT(9)) -#define IO_MUX_GPIO28_FUN_IE_M (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S) -#define IO_MUX_GPIO28_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO28_FUN_IE_S 9 -/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO28_FUN_DRV 0x00000003U -#define IO_MUX_GPIO28_FUN_DRV_M (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S) -#define IO_MUX_GPIO28_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO28_FUN_DRV_S 10 -/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO28_MCU_SEL 0x00000007U -#define IO_MUX_GPIO28_MCU_SEL_M (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S) -#define IO_MUX_GPIO28_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO28_MCU_SEL_S 12 -/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO28_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO28_FILTER_EN_M (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S) -#define IO_MUX_GPIO28_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO28_FILTER_EN_S 15 - -/** IO_MUX_gpio29_REG register - * iomux control register for gpio29 - */ -#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78) -/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_OE (BIT(0)) -#define IO_MUX_GPIO29_MCU_OE_M (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S) -#define IO_MUX_GPIO29_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO29_MCU_OE_S 0 -/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO29_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO29_SLP_SEL_M (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S) -#define IO_MUX_GPIO29_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO29_SLP_SEL_S 1 -/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO29_MCU_WPD_M (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S) -#define IO_MUX_GPIO29_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO29_MCU_WPD_S 2 -/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO29_MCU_WPU_M (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S) -#define IO_MUX_GPIO29_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO29_MCU_WPU_S 3 -/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_IE (BIT(4)) -#define IO_MUX_GPIO29_MCU_IE_M (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S) -#define IO_MUX_GPIO29_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO29_MCU_IE_S 4 -/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO29_MCU_DRV 0x00000003U -#define IO_MUX_GPIO29_MCU_DRV_M (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S) -#define IO_MUX_GPIO29_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO29_MCU_DRV_S 5 -/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO29_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO29_FUN_WPD_M (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S) -#define IO_MUX_GPIO29_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO29_FUN_WPD_S 7 -/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO29_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO29_FUN_WPU_M (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S) -#define IO_MUX_GPIO29_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO29_FUN_WPU_S 8 -/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO29_FUN_IE (BIT(9)) -#define IO_MUX_GPIO29_FUN_IE_M (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S) -#define IO_MUX_GPIO29_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO29_FUN_IE_S 9 -/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO29_FUN_DRV 0x00000003U -#define IO_MUX_GPIO29_FUN_DRV_M (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S) -#define IO_MUX_GPIO29_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO29_FUN_DRV_S 10 -/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO29_MCU_SEL 0x00000007U -#define IO_MUX_GPIO29_MCU_SEL_M (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S) -#define IO_MUX_GPIO29_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO29_MCU_SEL_S 12 -/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO29_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO29_FILTER_EN_M (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S) -#define IO_MUX_GPIO29_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO29_FILTER_EN_S 15 - -/** IO_MUX_gpio30_REG register - * iomux control register for gpio30 - */ -#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c) -/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_OE (BIT(0)) -#define IO_MUX_GPIO30_MCU_OE_M (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S) -#define IO_MUX_GPIO30_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO30_MCU_OE_S 0 -/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO30_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO30_SLP_SEL_M (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S) -#define IO_MUX_GPIO30_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO30_SLP_SEL_S 1 -/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO30_MCU_WPD_M (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S) -#define IO_MUX_GPIO30_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO30_MCU_WPD_S 2 -/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO30_MCU_WPU_M (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S) -#define IO_MUX_GPIO30_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO30_MCU_WPU_S 3 -/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_IE (BIT(4)) -#define IO_MUX_GPIO30_MCU_IE_M (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S) -#define IO_MUX_GPIO30_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO30_MCU_IE_S 4 -/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO30_MCU_DRV 0x00000003U -#define IO_MUX_GPIO30_MCU_DRV_M (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S) -#define IO_MUX_GPIO30_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO30_MCU_DRV_S 5 -/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO30_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO30_FUN_WPD_M (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S) -#define IO_MUX_GPIO30_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO30_FUN_WPD_S 7 -/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO30_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO30_FUN_WPU_M (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S) -#define IO_MUX_GPIO30_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO30_FUN_WPU_S 8 -/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO30_FUN_IE (BIT(9)) -#define IO_MUX_GPIO30_FUN_IE_M (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S) -#define IO_MUX_GPIO30_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO30_FUN_IE_S 9 -/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO30_FUN_DRV 0x00000003U -#define IO_MUX_GPIO30_FUN_DRV_M (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S) -#define IO_MUX_GPIO30_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO30_FUN_DRV_S 10 -/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO30_MCU_SEL 0x00000007U -#define IO_MUX_GPIO30_MCU_SEL_M (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S) -#define IO_MUX_GPIO30_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO30_MCU_SEL_S 12 -/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO30_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO30_FILTER_EN_M (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S) -#define IO_MUX_GPIO30_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO30_FILTER_EN_S 15 - -/** IO_MUX_gpio31_REG register - * iomux control register for gpio31 - */ -#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80) -/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_OE (BIT(0)) -#define IO_MUX_GPIO31_MCU_OE_M (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S) -#define IO_MUX_GPIO31_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO31_MCU_OE_S 0 -/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO31_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO31_SLP_SEL_M (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S) -#define IO_MUX_GPIO31_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO31_SLP_SEL_S 1 -/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO31_MCU_WPD_M (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S) -#define IO_MUX_GPIO31_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO31_MCU_WPD_S 2 -/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO31_MCU_WPU_M (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S) -#define IO_MUX_GPIO31_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO31_MCU_WPU_S 3 -/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_IE (BIT(4)) -#define IO_MUX_GPIO31_MCU_IE_M (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S) -#define IO_MUX_GPIO31_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO31_MCU_IE_S 4 -/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO31_MCU_DRV 0x00000003U -#define IO_MUX_GPIO31_MCU_DRV_M (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S) -#define IO_MUX_GPIO31_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO31_MCU_DRV_S 5 -/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO31_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO31_FUN_WPD_M (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S) -#define IO_MUX_GPIO31_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO31_FUN_WPD_S 7 -/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO31_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO31_FUN_WPU_M (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S) -#define IO_MUX_GPIO31_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO31_FUN_WPU_S 8 -/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO31_FUN_IE (BIT(9)) -#define IO_MUX_GPIO31_FUN_IE_M (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S) -#define IO_MUX_GPIO31_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO31_FUN_IE_S 9 -/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO31_FUN_DRV 0x00000003U -#define IO_MUX_GPIO31_FUN_DRV_M (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S) -#define IO_MUX_GPIO31_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO31_FUN_DRV_S 10 -/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO31_MCU_SEL 0x00000007U -#define IO_MUX_GPIO31_MCU_SEL_M (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S) -#define IO_MUX_GPIO31_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO31_MCU_SEL_S 12 -/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO31_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO31_FILTER_EN_M (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S) -#define IO_MUX_GPIO31_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO31_FILTER_EN_S 15 - -/** IO_MUX_gpio32_REG register - * iomux control register for gpio32 - */ -#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84) -/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_OE (BIT(0)) -#define IO_MUX_GPIO32_MCU_OE_M (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S) -#define IO_MUX_GPIO32_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO32_MCU_OE_S 0 -/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO32_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO32_SLP_SEL_M (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S) -#define IO_MUX_GPIO32_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO32_SLP_SEL_S 1 -/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO32_MCU_WPD_M (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S) -#define IO_MUX_GPIO32_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO32_MCU_WPD_S 2 -/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO32_MCU_WPU_M (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S) -#define IO_MUX_GPIO32_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO32_MCU_WPU_S 3 -/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_IE (BIT(4)) -#define IO_MUX_GPIO32_MCU_IE_M (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S) -#define IO_MUX_GPIO32_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO32_MCU_IE_S 4 -/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO32_MCU_DRV 0x00000003U -#define IO_MUX_GPIO32_MCU_DRV_M (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S) -#define IO_MUX_GPIO32_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO32_MCU_DRV_S 5 -/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO32_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO32_FUN_WPD_M (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S) -#define IO_MUX_GPIO32_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO32_FUN_WPD_S 7 -/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO32_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO32_FUN_WPU_M (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S) -#define IO_MUX_GPIO32_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO32_FUN_WPU_S 8 -/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO32_FUN_IE (BIT(9)) -#define IO_MUX_GPIO32_FUN_IE_M (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S) -#define IO_MUX_GPIO32_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO32_FUN_IE_S 9 -/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO32_FUN_DRV 0x00000003U -#define IO_MUX_GPIO32_FUN_DRV_M (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S) -#define IO_MUX_GPIO32_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO32_FUN_DRV_S 10 -/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO32_MCU_SEL 0x00000007U -#define IO_MUX_GPIO32_MCU_SEL_M (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S) -#define IO_MUX_GPIO32_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO32_MCU_SEL_S 12 -/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO32_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO32_FILTER_EN_M (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S) -#define IO_MUX_GPIO32_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO32_FILTER_EN_S 15 -/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RUE_I3C (BIT(16)) -#define IO_MUX_GPIO32_RUE_I3C_M (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S) -#define IO_MUX_GPIO32_RUE_I3C_V 0x00000001U -#define IO_MUX_GPIO32_RUE_I3C_S 16 -/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RU_I3C 0x00000003U -#define IO_MUX_GPIO32_RU_I3C_M (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S) -#define IO_MUX_GPIO32_RU_I3C_V 0x00000003U -#define IO_MUX_GPIO32_RU_I3C_S 17 -/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RUE_SEL_I3C (BIT(19)) -#define IO_MUX_GPIO32_RUE_SEL_I3C_M (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S) -#define IO_MUX_GPIO32_RUE_SEL_I3C_V 0x00000001U -#define IO_MUX_GPIO32_RUE_SEL_I3C_S 19 - -/** IO_MUX_gpio33_REG register - * iomux control register for gpio33 - */ -#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88) -/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_OE (BIT(0)) -#define IO_MUX_GPIO33_MCU_OE_M (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S) -#define IO_MUX_GPIO33_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO33_MCU_OE_S 0 -/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO33_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO33_SLP_SEL_M (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S) -#define IO_MUX_GPIO33_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO33_SLP_SEL_S 1 -/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO33_MCU_WPD_M (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S) -#define IO_MUX_GPIO33_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO33_MCU_WPD_S 2 -/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO33_MCU_WPU_M (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S) -#define IO_MUX_GPIO33_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO33_MCU_WPU_S 3 -/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_IE (BIT(4)) -#define IO_MUX_GPIO33_MCU_IE_M (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S) -#define IO_MUX_GPIO33_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO33_MCU_IE_S 4 -/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO33_MCU_DRV 0x00000003U -#define IO_MUX_GPIO33_MCU_DRV_M (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S) -#define IO_MUX_GPIO33_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO33_MCU_DRV_S 5 -/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO33_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO33_FUN_WPD_M (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S) -#define IO_MUX_GPIO33_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO33_FUN_WPD_S 7 -/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO33_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO33_FUN_WPU_M (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S) -#define IO_MUX_GPIO33_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO33_FUN_WPU_S 8 -/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO33_FUN_IE (BIT(9)) -#define IO_MUX_GPIO33_FUN_IE_M (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S) -#define IO_MUX_GPIO33_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO33_FUN_IE_S 9 -/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO33_FUN_DRV 0x00000003U -#define IO_MUX_GPIO33_FUN_DRV_M (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S) -#define IO_MUX_GPIO33_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO33_FUN_DRV_S 10 -/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO33_MCU_SEL 0x00000007U -#define IO_MUX_GPIO33_MCU_SEL_M (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S) -#define IO_MUX_GPIO33_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO33_MCU_SEL_S 12 -/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO33_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO33_FILTER_EN_M (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S) -#define IO_MUX_GPIO33_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO33_FILTER_EN_S 15 -/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RUE_I3C (BIT(16)) -#define IO_MUX_GPIO33_RUE_I3C_M (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S) -#define IO_MUX_GPIO33_RUE_I3C_V 0x00000001U -#define IO_MUX_GPIO33_RUE_I3C_S 16 -/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RU_I3C 0x00000003U -#define IO_MUX_GPIO33_RU_I3C_M (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S) -#define IO_MUX_GPIO33_RU_I3C_V 0x00000003U -#define IO_MUX_GPIO33_RU_I3C_S 17 -/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RUE_SEL_I3C (BIT(19)) -#define IO_MUX_GPIO33_RUE_SEL_I3C_M (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S) -#define IO_MUX_GPIO33_RUE_SEL_I3C_V 0x00000001U -#define IO_MUX_GPIO33_RUE_SEL_I3C_S 19 - -/** IO_MUX_gpio34_REG register - * iomux control register for gpio34 - */ -#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c) -/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_OE (BIT(0)) -#define IO_MUX_GPIO34_MCU_OE_M (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S) -#define IO_MUX_GPIO34_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO34_MCU_OE_S 0 -/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO34_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO34_SLP_SEL_M (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S) -#define IO_MUX_GPIO34_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO34_SLP_SEL_S 1 -/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO34_MCU_WPD_M (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S) -#define IO_MUX_GPIO34_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO34_MCU_WPD_S 2 -/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO34_MCU_WPU_M (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S) -#define IO_MUX_GPIO34_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO34_MCU_WPU_S 3 -/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_IE (BIT(4)) -#define IO_MUX_GPIO34_MCU_IE_M (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S) -#define IO_MUX_GPIO34_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO34_MCU_IE_S 4 -/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO34_MCU_DRV 0x00000003U -#define IO_MUX_GPIO34_MCU_DRV_M (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S) -#define IO_MUX_GPIO34_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO34_MCU_DRV_S 5 -/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO34_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO34_FUN_WPD_M (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S) -#define IO_MUX_GPIO34_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO34_FUN_WPD_S 7 -/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO34_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO34_FUN_WPU_M (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S) -#define IO_MUX_GPIO34_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO34_FUN_WPU_S 8 -/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO34_FUN_IE (BIT(9)) -#define IO_MUX_GPIO34_FUN_IE_M (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S) -#define IO_MUX_GPIO34_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO34_FUN_IE_S 9 -/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO34_FUN_DRV 0x00000003U -#define IO_MUX_GPIO34_FUN_DRV_M (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S) -#define IO_MUX_GPIO34_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO34_FUN_DRV_S 10 -/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO34_MCU_SEL 0x00000007U -#define IO_MUX_GPIO34_MCU_SEL_M (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S) -#define IO_MUX_GPIO34_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO34_MCU_SEL_S 12 -/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO34_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO34_FILTER_EN_M (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S) -#define IO_MUX_GPIO34_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO34_FILTER_EN_S 15 - -/** IO_MUX_gpio35_REG register - * iomux control register for gpio35 - */ -#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90) -/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_OE (BIT(0)) -#define IO_MUX_GPIO35_MCU_OE_M (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S) -#define IO_MUX_GPIO35_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO35_MCU_OE_S 0 -/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO35_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO35_SLP_SEL_M (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S) -#define IO_MUX_GPIO35_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO35_SLP_SEL_S 1 -/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO35_MCU_WPD_M (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S) -#define IO_MUX_GPIO35_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO35_MCU_WPD_S 2 -/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO35_MCU_WPU_M (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S) -#define IO_MUX_GPIO35_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO35_MCU_WPU_S 3 -/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_IE (BIT(4)) -#define IO_MUX_GPIO35_MCU_IE_M (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S) -#define IO_MUX_GPIO35_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO35_MCU_IE_S 4 -/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO35_MCU_DRV 0x00000003U -#define IO_MUX_GPIO35_MCU_DRV_M (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S) -#define IO_MUX_GPIO35_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO35_MCU_DRV_S 5 -/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO35_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO35_FUN_WPD_M (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S) -#define IO_MUX_GPIO35_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO35_FUN_WPD_S 7 -/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO35_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO35_FUN_WPU_M (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S) -#define IO_MUX_GPIO35_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO35_FUN_WPU_S 8 -/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO35_FUN_IE (BIT(9)) -#define IO_MUX_GPIO35_FUN_IE_M (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S) -#define IO_MUX_GPIO35_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO35_FUN_IE_S 9 -/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO35_FUN_DRV 0x00000003U -#define IO_MUX_GPIO35_FUN_DRV_M (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S) -#define IO_MUX_GPIO35_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO35_FUN_DRV_S 10 -/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO35_MCU_SEL 0x00000007U -#define IO_MUX_GPIO35_MCU_SEL_M (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S) -#define IO_MUX_GPIO35_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO35_MCU_SEL_S 12 -/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO35_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO35_FILTER_EN_M (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S) -#define IO_MUX_GPIO35_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO35_FILTER_EN_S 15 - -/** IO_MUX_gpio36_REG register - * iomux control register for gpio36 - */ -#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94) -/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_OE (BIT(0)) -#define IO_MUX_GPIO36_MCU_OE_M (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S) -#define IO_MUX_GPIO36_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO36_MCU_OE_S 0 -/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO36_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO36_SLP_SEL_M (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S) -#define IO_MUX_GPIO36_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO36_SLP_SEL_S 1 -/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO36_MCU_WPD_M (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S) -#define IO_MUX_GPIO36_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO36_MCU_WPD_S 2 -/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO36_MCU_WPU_M (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S) -#define IO_MUX_GPIO36_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO36_MCU_WPU_S 3 -/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_IE (BIT(4)) -#define IO_MUX_GPIO36_MCU_IE_M (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S) -#define IO_MUX_GPIO36_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO36_MCU_IE_S 4 -/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO36_MCU_DRV 0x00000003U -#define IO_MUX_GPIO36_MCU_DRV_M (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S) -#define IO_MUX_GPIO36_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO36_MCU_DRV_S 5 -/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO36_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO36_FUN_WPD_M (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S) -#define IO_MUX_GPIO36_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO36_FUN_WPD_S 7 -/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO36_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO36_FUN_WPU_M (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S) -#define IO_MUX_GPIO36_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO36_FUN_WPU_S 8 -/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO36_FUN_IE (BIT(9)) -#define IO_MUX_GPIO36_FUN_IE_M (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S) -#define IO_MUX_GPIO36_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO36_FUN_IE_S 9 -/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO36_FUN_DRV 0x00000003U -#define IO_MUX_GPIO36_FUN_DRV_M (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S) -#define IO_MUX_GPIO36_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO36_FUN_DRV_S 10 -/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO36_MCU_SEL 0x00000007U -#define IO_MUX_GPIO36_MCU_SEL_M (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S) -#define IO_MUX_GPIO36_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO36_MCU_SEL_S 12 -/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO36_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO36_FILTER_EN_M (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S) -#define IO_MUX_GPIO36_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO36_FILTER_EN_S 15 - -/** IO_MUX_gpio37_REG register - * iomux control register for gpio37 - */ -#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98) -/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_OE (BIT(0)) -#define IO_MUX_GPIO37_MCU_OE_M (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S) -#define IO_MUX_GPIO37_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO37_MCU_OE_S 0 -/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO37_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO37_SLP_SEL_M (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S) -#define IO_MUX_GPIO37_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO37_SLP_SEL_S 1 -/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO37_MCU_WPD_M (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S) -#define IO_MUX_GPIO37_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO37_MCU_WPD_S 2 -/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO37_MCU_WPU_M (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S) -#define IO_MUX_GPIO37_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO37_MCU_WPU_S 3 -/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_IE (BIT(4)) -#define IO_MUX_GPIO37_MCU_IE_M (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S) -#define IO_MUX_GPIO37_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO37_MCU_IE_S 4 -/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO37_MCU_DRV 0x00000003U -#define IO_MUX_GPIO37_MCU_DRV_M (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S) -#define IO_MUX_GPIO37_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO37_MCU_DRV_S 5 -/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO37_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO37_FUN_WPD_M (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S) -#define IO_MUX_GPIO37_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO37_FUN_WPD_S 7 -/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO37_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO37_FUN_WPU_M (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S) -#define IO_MUX_GPIO37_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO37_FUN_WPU_S 8 -/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO37_FUN_IE (BIT(9)) -#define IO_MUX_GPIO37_FUN_IE_M (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S) -#define IO_MUX_GPIO37_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO37_FUN_IE_S 9 -/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO37_FUN_DRV 0x00000003U -#define IO_MUX_GPIO37_FUN_DRV_M (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S) -#define IO_MUX_GPIO37_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO37_FUN_DRV_S 10 -/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO37_MCU_SEL 0x00000007U -#define IO_MUX_GPIO37_MCU_SEL_M (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S) -#define IO_MUX_GPIO37_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO37_MCU_SEL_S 12 -/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO37_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO37_FILTER_EN_M (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S) -#define IO_MUX_GPIO37_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO37_FILTER_EN_S 15 - -/** IO_MUX_gpio38_REG register - * iomux control register for gpio38 - */ -#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c) -/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_OE (BIT(0)) -#define IO_MUX_GPIO38_MCU_OE_M (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S) -#define IO_MUX_GPIO38_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO38_MCU_OE_S 0 -/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO38_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO38_SLP_SEL_M (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S) -#define IO_MUX_GPIO38_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO38_SLP_SEL_S 1 -/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO38_MCU_WPD_M (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S) -#define IO_MUX_GPIO38_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO38_MCU_WPD_S 2 -/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO38_MCU_WPU_M (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S) -#define IO_MUX_GPIO38_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO38_MCU_WPU_S 3 -/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_IE (BIT(4)) -#define IO_MUX_GPIO38_MCU_IE_M (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S) -#define IO_MUX_GPIO38_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO38_MCU_IE_S 4 -/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO38_MCU_DRV 0x00000003U -#define IO_MUX_GPIO38_MCU_DRV_M (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S) -#define IO_MUX_GPIO38_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO38_MCU_DRV_S 5 -/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO38_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO38_FUN_WPD_M (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S) -#define IO_MUX_GPIO38_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO38_FUN_WPD_S 7 -/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO38_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO38_FUN_WPU_M (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S) -#define IO_MUX_GPIO38_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO38_FUN_WPU_S 8 -/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO38_FUN_IE (BIT(9)) -#define IO_MUX_GPIO38_FUN_IE_M (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S) -#define IO_MUX_GPIO38_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO38_FUN_IE_S 9 -/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO38_FUN_DRV 0x00000003U -#define IO_MUX_GPIO38_FUN_DRV_M (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S) -#define IO_MUX_GPIO38_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO38_FUN_DRV_S 10 -/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO38_MCU_SEL 0x00000007U -#define IO_MUX_GPIO38_MCU_SEL_M (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S) -#define IO_MUX_GPIO38_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO38_MCU_SEL_S 12 -/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO38_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO38_FILTER_EN_M (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S) -#define IO_MUX_GPIO38_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO38_FILTER_EN_S 15 - -/** IO_MUX_gpio39_REG register - * iomux control register for gpio39 - */ -#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0) -/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_OE (BIT(0)) -#define IO_MUX_GPIO39_MCU_OE_M (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S) -#define IO_MUX_GPIO39_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO39_MCU_OE_S 0 -/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO39_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO39_SLP_SEL_M (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S) -#define IO_MUX_GPIO39_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO39_SLP_SEL_S 1 -/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO39_MCU_WPD_M (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S) -#define IO_MUX_GPIO39_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO39_MCU_WPD_S 2 -/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO39_MCU_WPU_M (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S) -#define IO_MUX_GPIO39_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO39_MCU_WPU_S 3 -/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_IE (BIT(4)) -#define IO_MUX_GPIO39_MCU_IE_M (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S) -#define IO_MUX_GPIO39_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO39_MCU_IE_S 4 -/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO39_MCU_DRV 0x00000003U -#define IO_MUX_GPIO39_MCU_DRV_M (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S) -#define IO_MUX_GPIO39_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO39_MCU_DRV_S 5 -/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO39_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO39_FUN_WPD_M (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S) -#define IO_MUX_GPIO39_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO39_FUN_WPD_S 7 -/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO39_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO39_FUN_WPU_M (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S) -#define IO_MUX_GPIO39_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO39_FUN_WPU_S 8 -/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO39_FUN_IE (BIT(9)) -#define IO_MUX_GPIO39_FUN_IE_M (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S) -#define IO_MUX_GPIO39_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO39_FUN_IE_S 9 -/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO39_FUN_DRV 0x00000003U -#define IO_MUX_GPIO39_FUN_DRV_M (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S) -#define IO_MUX_GPIO39_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO39_FUN_DRV_S 10 -/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO39_MCU_SEL 0x00000007U -#define IO_MUX_GPIO39_MCU_SEL_M (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S) -#define IO_MUX_GPIO39_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO39_MCU_SEL_S 12 -/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO39_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO39_FILTER_EN_M (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S) -#define IO_MUX_GPIO39_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO39_FILTER_EN_S 15 - -/** IO_MUX_gpio40_REG register - * iomux control register for gpio40 - */ -#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4) -/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_OE (BIT(0)) -#define IO_MUX_GPIO40_MCU_OE_M (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S) -#define IO_MUX_GPIO40_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO40_MCU_OE_S 0 -/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO40_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO40_SLP_SEL_M (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S) -#define IO_MUX_GPIO40_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO40_SLP_SEL_S 1 -/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO40_MCU_WPD_M (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S) -#define IO_MUX_GPIO40_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO40_MCU_WPD_S 2 -/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO40_MCU_WPU_M (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S) -#define IO_MUX_GPIO40_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO40_MCU_WPU_S 3 -/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_IE (BIT(4)) -#define IO_MUX_GPIO40_MCU_IE_M (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S) -#define IO_MUX_GPIO40_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO40_MCU_IE_S 4 -/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO40_MCU_DRV 0x00000003U -#define IO_MUX_GPIO40_MCU_DRV_M (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S) -#define IO_MUX_GPIO40_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO40_MCU_DRV_S 5 -/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO40_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO40_FUN_WPD_M (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S) -#define IO_MUX_GPIO40_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO40_FUN_WPD_S 7 -/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO40_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO40_FUN_WPU_M (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S) -#define IO_MUX_GPIO40_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO40_FUN_WPU_S 8 -/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO40_FUN_IE (BIT(9)) -#define IO_MUX_GPIO40_FUN_IE_M (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S) -#define IO_MUX_GPIO40_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO40_FUN_IE_S 9 -/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO40_FUN_DRV 0x00000003U -#define IO_MUX_GPIO40_FUN_DRV_M (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S) -#define IO_MUX_GPIO40_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO40_FUN_DRV_S 10 -/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO40_MCU_SEL 0x00000007U -#define IO_MUX_GPIO40_MCU_SEL_M (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S) -#define IO_MUX_GPIO40_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO40_MCU_SEL_S 12 -/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO40_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO40_FILTER_EN_M (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S) -#define IO_MUX_GPIO40_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO40_FILTER_EN_S 15 - -/** IO_MUX_gpio41_REG register - * iomux control register for gpio41 - */ -#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8) -/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_OE (BIT(0)) -#define IO_MUX_GPIO41_MCU_OE_M (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S) -#define IO_MUX_GPIO41_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO41_MCU_OE_S 0 -/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO41_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO41_SLP_SEL_M (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S) -#define IO_MUX_GPIO41_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO41_SLP_SEL_S 1 -/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO41_MCU_WPD_M (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S) -#define IO_MUX_GPIO41_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO41_MCU_WPD_S 2 -/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO41_MCU_WPU_M (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S) -#define IO_MUX_GPIO41_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO41_MCU_WPU_S 3 -/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_IE (BIT(4)) -#define IO_MUX_GPIO41_MCU_IE_M (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S) -#define IO_MUX_GPIO41_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO41_MCU_IE_S 4 -/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO41_MCU_DRV 0x00000003U -#define IO_MUX_GPIO41_MCU_DRV_M (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S) -#define IO_MUX_GPIO41_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO41_MCU_DRV_S 5 -/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO41_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO41_FUN_WPD_M (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S) -#define IO_MUX_GPIO41_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO41_FUN_WPD_S 7 -/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO41_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO41_FUN_WPU_M (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S) -#define IO_MUX_GPIO41_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO41_FUN_WPU_S 8 -/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO41_FUN_IE (BIT(9)) -#define IO_MUX_GPIO41_FUN_IE_M (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S) -#define IO_MUX_GPIO41_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO41_FUN_IE_S 9 -/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO41_FUN_DRV 0x00000003U -#define IO_MUX_GPIO41_FUN_DRV_M (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S) -#define IO_MUX_GPIO41_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO41_FUN_DRV_S 10 -/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO41_MCU_SEL 0x00000007U -#define IO_MUX_GPIO41_MCU_SEL_M (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S) -#define IO_MUX_GPIO41_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO41_MCU_SEL_S 12 -/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO41_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO41_FILTER_EN_M (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S) -#define IO_MUX_GPIO41_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO41_FILTER_EN_S 15 - -/** IO_MUX_gpio42_REG register - * iomux control register for gpio42 - */ -#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac) -/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_OE (BIT(0)) -#define IO_MUX_GPIO42_MCU_OE_M (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S) -#define IO_MUX_GPIO42_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO42_MCU_OE_S 0 -/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO42_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO42_SLP_SEL_M (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S) -#define IO_MUX_GPIO42_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO42_SLP_SEL_S 1 -/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO42_MCU_WPD_M (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S) -#define IO_MUX_GPIO42_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO42_MCU_WPD_S 2 -/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO42_MCU_WPU_M (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S) -#define IO_MUX_GPIO42_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO42_MCU_WPU_S 3 -/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_IE (BIT(4)) -#define IO_MUX_GPIO42_MCU_IE_M (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S) -#define IO_MUX_GPIO42_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO42_MCU_IE_S 4 -/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO42_MCU_DRV 0x00000003U -#define IO_MUX_GPIO42_MCU_DRV_M (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S) -#define IO_MUX_GPIO42_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO42_MCU_DRV_S 5 -/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO42_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO42_FUN_WPD_M (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S) -#define IO_MUX_GPIO42_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO42_FUN_WPD_S 7 -/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO42_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO42_FUN_WPU_M (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S) -#define IO_MUX_GPIO42_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO42_FUN_WPU_S 8 -/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO42_FUN_IE (BIT(9)) -#define IO_MUX_GPIO42_FUN_IE_M (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S) -#define IO_MUX_GPIO42_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO42_FUN_IE_S 9 -/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO42_FUN_DRV 0x00000003U -#define IO_MUX_GPIO42_FUN_DRV_M (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S) -#define IO_MUX_GPIO42_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO42_FUN_DRV_S 10 -/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO42_MCU_SEL 0x00000007U -#define IO_MUX_GPIO42_MCU_SEL_M (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S) -#define IO_MUX_GPIO42_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO42_MCU_SEL_S 12 -/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO42_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO42_FILTER_EN_M (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S) -#define IO_MUX_GPIO42_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO42_FILTER_EN_S 15 - -/** IO_MUX_gpio43_REG register - * iomux control register for gpio43 - */ -#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0) -/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_OE (BIT(0)) -#define IO_MUX_GPIO43_MCU_OE_M (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S) -#define IO_MUX_GPIO43_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO43_MCU_OE_S 0 -/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO43_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO43_SLP_SEL_M (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S) -#define IO_MUX_GPIO43_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO43_SLP_SEL_S 1 -/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO43_MCU_WPD_M (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S) -#define IO_MUX_GPIO43_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO43_MCU_WPD_S 2 -/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO43_MCU_WPU_M (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S) -#define IO_MUX_GPIO43_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO43_MCU_WPU_S 3 -/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_IE (BIT(4)) -#define IO_MUX_GPIO43_MCU_IE_M (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S) -#define IO_MUX_GPIO43_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO43_MCU_IE_S 4 -/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO43_MCU_DRV 0x00000003U -#define IO_MUX_GPIO43_MCU_DRV_M (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S) -#define IO_MUX_GPIO43_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO43_MCU_DRV_S 5 -/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO43_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO43_FUN_WPD_M (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S) -#define IO_MUX_GPIO43_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO43_FUN_WPD_S 7 -/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO43_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO43_FUN_WPU_M (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S) -#define IO_MUX_GPIO43_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO43_FUN_WPU_S 8 -/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO43_FUN_IE (BIT(9)) -#define IO_MUX_GPIO43_FUN_IE_M (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S) -#define IO_MUX_GPIO43_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO43_FUN_IE_S 9 -/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO43_FUN_DRV 0x00000003U -#define IO_MUX_GPIO43_FUN_DRV_M (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S) -#define IO_MUX_GPIO43_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO43_FUN_DRV_S 10 -/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO43_MCU_SEL 0x00000007U -#define IO_MUX_GPIO43_MCU_SEL_M (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S) -#define IO_MUX_GPIO43_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO43_MCU_SEL_S 12 -/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO43_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO43_FILTER_EN_M (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S) -#define IO_MUX_GPIO43_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO43_FILTER_EN_S 15 - -/** IO_MUX_gpio44_REG register - * iomux control register for gpio44 - */ -#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4) -/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_OE (BIT(0)) -#define IO_MUX_GPIO44_MCU_OE_M (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S) -#define IO_MUX_GPIO44_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO44_MCU_OE_S 0 -/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO44_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO44_SLP_SEL_M (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S) -#define IO_MUX_GPIO44_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO44_SLP_SEL_S 1 -/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO44_MCU_WPD_M (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S) -#define IO_MUX_GPIO44_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO44_MCU_WPD_S 2 -/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO44_MCU_WPU_M (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S) -#define IO_MUX_GPIO44_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO44_MCU_WPU_S 3 -/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_IE (BIT(4)) -#define IO_MUX_GPIO44_MCU_IE_M (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S) -#define IO_MUX_GPIO44_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO44_MCU_IE_S 4 -/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO44_MCU_DRV 0x00000003U -#define IO_MUX_GPIO44_MCU_DRV_M (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S) -#define IO_MUX_GPIO44_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO44_MCU_DRV_S 5 -/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO44_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO44_FUN_WPD_M (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S) -#define IO_MUX_GPIO44_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO44_FUN_WPD_S 7 -/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO44_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO44_FUN_WPU_M (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S) -#define IO_MUX_GPIO44_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO44_FUN_WPU_S 8 -/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO44_FUN_IE (BIT(9)) -#define IO_MUX_GPIO44_FUN_IE_M (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S) -#define IO_MUX_GPIO44_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO44_FUN_IE_S 9 -/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO44_FUN_DRV 0x00000003U -#define IO_MUX_GPIO44_FUN_DRV_M (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S) -#define IO_MUX_GPIO44_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO44_FUN_DRV_S 10 -/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO44_MCU_SEL 0x00000007U -#define IO_MUX_GPIO44_MCU_SEL_M (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S) -#define IO_MUX_GPIO44_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO44_MCU_SEL_S 12 -/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO44_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO44_FILTER_EN_M (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S) -#define IO_MUX_GPIO44_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO44_FILTER_EN_S 15 - -/** IO_MUX_gpio45_REG register - * iomux control register for gpio45 - */ -#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8) -/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_OE (BIT(0)) -#define IO_MUX_GPIO45_MCU_OE_M (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S) -#define IO_MUX_GPIO45_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO45_MCU_OE_S 0 -/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO45_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO45_SLP_SEL_M (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S) -#define IO_MUX_GPIO45_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO45_SLP_SEL_S 1 -/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO45_MCU_WPD_M (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S) -#define IO_MUX_GPIO45_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO45_MCU_WPD_S 2 -/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO45_MCU_WPU_M (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S) -#define IO_MUX_GPIO45_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO45_MCU_WPU_S 3 -/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_IE (BIT(4)) -#define IO_MUX_GPIO45_MCU_IE_M (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S) -#define IO_MUX_GPIO45_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO45_MCU_IE_S 4 -/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO45_MCU_DRV 0x00000003U -#define IO_MUX_GPIO45_MCU_DRV_M (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S) -#define IO_MUX_GPIO45_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO45_MCU_DRV_S 5 -/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO45_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO45_FUN_WPD_M (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S) -#define IO_MUX_GPIO45_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO45_FUN_WPD_S 7 -/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO45_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO45_FUN_WPU_M (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S) -#define IO_MUX_GPIO45_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO45_FUN_WPU_S 8 -/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO45_FUN_IE (BIT(9)) -#define IO_MUX_GPIO45_FUN_IE_M (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S) -#define IO_MUX_GPIO45_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO45_FUN_IE_S 9 -/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO45_FUN_DRV 0x00000003U -#define IO_MUX_GPIO45_FUN_DRV_M (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S) -#define IO_MUX_GPIO45_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO45_FUN_DRV_S 10 -/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO45_MCU_SEL 0x00000007U -#define IO_MUX_GPIO45_MCU_SEL_M (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S) -#define IO_MUX_GPIO45_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO45_MCU_SEL_S 12 -/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO45_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO45_FILTER_EN_M (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S) -#define IO_MUX_GPIO45_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO45_FILTER_EN_S 15 - -/** IO_MUX_gpio46_REG register - * iomux control register for gpio46 - */ -#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc) -/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_OE (BIT(0)) -#define IO_MUX_GPIO46_MCU_OE_M (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S) -#define IO_MUX_GPIO46_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO46_MCU_OE_S 0 -/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO46_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO46_SLP_SEL_M (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S) -#define IO_MUX_GPIO46_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO46_SLP_SEL_S 1 -/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO46_MCU_WPD_M (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S) -#define IO_MUX_GPIO46_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO46_MCU_WPD_S 2 -/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO46_MCU_WPU_M (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S) -#define IO_MUX_GPIO46_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO46_MCU_WPU_S 3 -/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_IE (BIT(4)) -#define IO_MUX_GPIO46_MCU_IE_M (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S) -#define IO_MUX_GPIO46_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO46_MCU_IE_S 4 -/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO46_MCU_DRV 0x00000003U -#define IO_MUX_GPIO46_MCU_DRV_M (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S) -#define IO_MUX_GPIO46_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO46_MCU_DRV_S 5 -/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO46_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO46_FUN_WPD_M (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S) -#define IO_MUX_GPIO46_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO46_FUN_WPD_S 7 -/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO46_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO46_FUN_WPU_M (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S) -#define IO_MUX_GPIO46_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO46_FUN_WPU_S 8 -/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO46_FUN_IE (BIT(9)) -#define IO_MUX_GPIO46_FUN_IE_M (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S) -#define IO_MUX_GPIO46_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO46_FUN_IE_S 9 -/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO46_FUN_DRV 0x00000003U -#define IO_MUX_GPIO46_FUN_DRV_M (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S) -#define IO_MUX_GPIO46_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO46_FUN_DRV_S 10 -/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO46_MCU_SEL 0x00000007U -#define IO_MUX_GPIO46_MCU_SEL_M (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S) -#define IO_MUX_GPIO46_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO46_MCU_SEL_S 12 -/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO46_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO46_FILTER_EN_M (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S) -#define IO_MUX_GPIO46_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO46_FILTER_EN_S 15 - -/** IO_MUX_gpio47_REG register - * iomux control register for gpio47 - */ -#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0) -/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_OE (BIT(0)) -#define IO_MUX_GPIO47_MCU_OE_M (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S) -#define IO_MUX_GPIO47_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO47_MCU_OE_S 0 -/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO47_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO47_SLP_SEL_M (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S) -#define IO_MUX_GPIO47_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO47_SLP_SEL_S 1 -/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO47_MCU_WPD_M (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S) -#define IO_MUX_GPIO47_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO47_MCU_WPD_S 2 -/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO47_MCU_WPU_M (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S) -#define IO_MUX_GPIO47_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO47_MCU_WPU_S 3 -/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_IE (BIT(4)) -#define IO_MUX_GPIO47_MCU_IE_M (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S) -#define IO_MUX_GPIO47_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO47_MCU_IE_S 4 -/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO47_MCU_DRV 0x00000003U -#define IO_MUX_GPIO47_MCU_DRV_M (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S) -#define IO_MUX_GPIO47_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO47_MCU_DRV_S 5 -/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO47_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO47_FUN_WPD_M (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S) -#define IO_MUX_GPIO47_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO47_FUN_WPD_S 7 -/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO47_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO47_FUN_WPU_M (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S) -#define IO_MUX_GPIO47_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO47_FUN_WPU_S 8 -/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO47_FUN_IE (BIT(9)) -#define IO_MUX_GPIO47_FUN_IE_M (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S) -#define IO_MUX_GPIO47_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO47_FUN_IE_S 9 -/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO47_FUN_DRV 0x00000003U -#define IO_MUX_GPIO47_FUN_DRV_M (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S) -#define IO_MUX_GPIO47_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO47_FUN_DRV_S 10 -/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO47_MCU_SEL 0x00000007U -#define IO_MUX_GPIO47_MCU_SEL_M (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S) -#define IO_MUX_GPIO47_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO47_MCU_SEL_S 12 -/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO47_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO47_FILTER_EN_M (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S) -#define IO_MUX_GPIO47_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO47_FILTER_EN_S 15 - -/** IO_MUX_gpio48_REG register - * iomux control register for gpio48 - */ -#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4) -/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_OE (BIT(0)) -#define IO_MUX_GPIO48_MCU_OE_M (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S) -#define IO_MUX_GPIO48_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO48_MCU_OE_S 0 -/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO48_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO48_SLP_SEL_M (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S) -#define IO_MUX_GPIO48_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO48_SLP_SEL_S 1 -/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO48_MCU_WPD_M (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S) -#define IO_MUX_GPIO48_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO48_MCU_WPD_S 2 -/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO48_MCU_WPU_M (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S) -#define IO_MUX_GPIO48_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO48_MCU_WPU_S 3 -/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_IE (BIT(4)) -#define IO_MUX_GPIO48_MCU_IE_M (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S) -#define IO_MUX_GPIO48_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO48_MCU_IE_S 4 -/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO48_MCU_DRV 0x00000003U -#define IO_MUX_GPIO48_MCU_DRV_M (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S) -#define IO_MUX_GPIO48_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO48_MCU_DRV_S 5 -/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO48_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO48_FUN_WPD_M (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S) -#define IO_MUX_GPIO48_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO48_FUN_WPD_S 7 -/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO48_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO48_FUN_WPU_M (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S) -#define IO_MUX_GPIO48_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO48_FUN_WPU_S 8 -/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO48_FUN_IE (BIT(9)) -#define IO_MUX_GPIO48_FUN_IE_M (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S) -#define IO_MUX_GPIO48_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO48_FUN_IE_S 9 -/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO48_FUN_DRV 0x00000003U -#define IO_MUX_GPIO48_FUN_DRV_M (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S) -#define IO_MUX_GPIO48_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO48_FUN_DRV_S 10 -/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO48_MCU_SEL 0x00000007U -#define IO_MUX_GPIO48_MCU_SEL_M (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S) -#define IO_MUX_GPIO48_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO48_MCU_SEL_S 12 -/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO48_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO48_FILTER_EN_M (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S) -#define IO_MUX_GPIO48_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO48_FILTER_EN_S 15 - -/** IO_MUX_gpio49_REG register - * iomux control register for gpio49 - */ -#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8) -/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_OE (BIT(0)) -#define IO_MUX_GPIO49_MCU_OE_M (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S) -#define IO_MUX_GPIO49_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO49_MCU_OE_S 0 -/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO49_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO49_SLP_SEL_M (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S) -#define IO_MUX_GPIO49_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO49_SLP_SEL_S 1 -/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO49_MCU_WPD_M (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S) -#define IO_MUX_GPIO49_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO49_MCU_WPD_S 2 -/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO49_MCU_WPU_M (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S) -#define IO_MUX_GPIO49_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO49_MCU_WPU_S 3 -/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_IE (BIT(4)) -#define IO_MUX_GPIO49_MCU_IE_M (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S) -#define IO_MUX_GPIO49_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO49_MCU_IE_S 4 -/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO49_MCU_DRV 0x00000003U -#define IO_MUX_GPIO49_MCU_DRV_M (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S) -#define IO_MUX_GPIO49_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO49_MCU_DRV_S 5 -/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO49_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO49_FUN_WPD_M (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S) -#define IO_MUX_GPIO49_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO49_FUN_WPD_S 7 -/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO49_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO49_FUN_WPU_M (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S) -#define IO_MUX_GPIO49_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO49_FUN_WPU_S 8 -/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO49_FUN_IE (BIT(9)) -#define IO_MUX_GPIO49_FUN_IE_M (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S) -#define IO_MUX_GPIO49_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO49_FUN_IE_S 9 -/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO49_FUN_DRV 0x00000003U -#define IO_MUX_GPIO49_FUN_DRV_M (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S) -#define IO_MUX_GPIO49_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO49_FUN_DRV_S 10 -/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO49_MCU_SEL 0x00000007U -#define IO_MUX_GPIO49_MCU_SEL_M (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S) -#define IO_MUX_GPIO49_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO49_MCU_SEL_S 12 -/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO49_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO49_FILTER_EN_M (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S) -#define IO_MUX_GPIO49_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO49_FILTER_EN_S 15 - -/** IO_MUX_gpio50_REG register - * iomux control register for gpio50 - */ -#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc) -/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_OE (BIT(0)) -#define IO_MUX_GPIO50_MCU_OE_M (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S) -#define IO_MUX_GPIO50_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO50_MCU_OE_S 0 -/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO50_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO50_SLP_SEL_M (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S) -#define IO_MUX_GPIO50_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO50_SLP_SEL_S 1 -/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO50_MCU_WPD_M (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S) -#define IO_MUX_GPIO50_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO50_MCU_WPD_S 2 -/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO50_MCU_WPU_M (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S) -#define IO_MUX_GPIO50_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO50_MCU_WPU_S 3 -/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_IE (BIT(4)) -#define IO_MUX_GPIO50_MCU_IE_M (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S) -#define IO_MUX_GPIO50_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO50_MCU_IE_S 4 -/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO50_MCU_DRV 0x00000003U -#define IO_MUX_GPIO50_MCU_DRV_M (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S) -#define IO_MUX_GPIO50_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO50_MCU_DRV_S 5 -/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO50_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO50_FUN_WPD_M (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S) -#define IO_MUX_GPIO50_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO50_FUN_WPD_S 7 -/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO50_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO50_FUN_WPU_M (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S) -#define IO_MUX_GPIO50_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO50_FUN_WPU_S 8 -/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO50_FUN_IE (BIT(9)) -#define IO_MUX_GPIO50_FUN_IE_M (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S) -#define IO_MUX_GPIO50_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO50_FUN_IE_S 9 -/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO50_FUN_DRV 0x00000003U -#define IO_MUX_GPIO50_FUN_DRV_M (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S) -#define IO_MUX_GPIO50_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO50_FUN_DRV_S 10 -/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO50_MCU_SEL 0x00000007U -#define IO_MUX_GPIO50_MCU_SEL_M (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S) -#define IO_MUX_GPIO50_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO50_MCU_SEL_S 12 -/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO50_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO50_FILTER_EN_M (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S) -#define IO_MUX_GPIO50_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO50_FILTER_EN_S 15 - -/** IO_MUX_gpio51_REG register - * iomux control register for gpio51 - */ -#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0) -/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_OE (BIT(0)) -#define IO_MUX_GPIO51_MCU_OE_M (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S) -#define IO_MUX_GPIO51_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO51_MCU_OE_S 0 -/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO51_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO51_SLP_SEL_M (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S) -#define IO_MUX_GPIO51_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO51_SLP_SEL_S 1 -/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO51_MCU_WPD_M (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S) -#define IO_MUX_GPIO51_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO51_MCU_WPD_S 2 -/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO51_MCU_WPU_M (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S) -#define IO_MUX_GPIO51_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO51_MCU_WPU_S 3 -/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_IE (BIT(4)) -#define IO_MUX_GPIO51_MCU_IE_M (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S) -#define IO_MUX_GPIO51_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO51_MCU_IE_S 4 -/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO51_MCU_DRV 0x00000003U -#define IO_MUX_GPIO51_MCU_DRV_M (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S) -#define IO_MUX_GPIO51_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO51_MCU_DRV_S 5 -/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO51_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO51_FUN_WPD_M (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S) -#define IO_MUX_GPIO51_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO51_FUN_WPD_S 7 -/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO51_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO51_FUN_WPU_M (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S) -#define IO_MUX_GPIO51_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO51_FUN_WPU_S 8 -/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO51_FUN_IE (BIT(9)) -#define IO_MUX_GPIO51_FUN_IE_M (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S) -#define IO_MUX_GPIO51_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO51_FUN_IE_S 9 -/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO51_FUN_DRV 0x00000003U -#define IO_MUX_GPIO51_FUN_DRV_M (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S) -#define IO_MUX_GPIO51_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO51_FUN_DRV_S 10 -/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO51_MCU_SEL 0x00000007U -#define IO_MUX_GPIO51_MCU_SEL_M (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S) -#define IO_MUX_GPIO51_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO51_MCU_SEL_S 12 -/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO51_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO51_FILTER_EN_M (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S) -#define IO_MUX_GPIO51_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO51_FILTER_EN_S 15 - -/** IO_MUX_gpio52_REG register - * iomux control register for gpio52 - */ -#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4) -/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_OE (BIT(0)) -#define IO_MUX_GPIO52_MCU_OE_M (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S) -#define IO_MUX_GPIO52_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO52_MCU_OE_S 0 -/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO52_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO52_SLP_SEL_M (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S) -#define IO_MUX_GPIO52_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO52_SLP_SEL_S 1 -/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO52_MCU_WPD_M (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S) -#define IO_MUX_GPIO52_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO52_MCU_WPD_S 2 -/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO52_MCU_WPU_M (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S) -#define IO_MUX_GPIO52_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO52_MCU_WPU_S 3 -/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_IE (BIT(4)) -#define IO_MUX_GPIO52_MCU_IE_M (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S) -#define IO_MUX_GPIO52_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO52_MCU_IE_S 4 -/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO52_MCU_DRV 0x00000003U -#define IO_MUX_GPIO52_MCU_DRV_M (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S) -#define IO_MUX_GPIO52_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO52_MCU_DRV_S 5 -/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO52_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO52_FUN_WPD_M (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S) -#define IO_MUX_GPIO52_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO52_FUN_WPD_S 7 -/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO52_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO52_FUN_WPU_M (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S) -#define IO_MUX_GPIO52_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO52_FUN_WPU_S 8 -/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO52_FUN_IE (BIT(9)) -#define IO_MUX_GPIO52_FUN_IE_M (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S) -#define IO_MUX_GPIO52_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO52_FUN_IE_S 9 -/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO52_FUN_DRV 0x00000003U -#define IO_MUX_GPIO52_FUN_DRV_M (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S) -#define IO_MUX_GPIO52_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO52_FUN_DRV_S 10 -/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO52_MCU_SEL 0x00000007U -#define IO_MUX_GPIO52_MCU_SEL_M (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S) -#define IO_MUX_GPIO52_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO52_MCU_SEL_S 12 -/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO52_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO52_FILTER_EN_M (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S) -#define IO_MUX_GPIO52_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO52_FILTER_EN_S 15 - -/** IO_MUX_gpio53_REG register - * iomux control register for gpio53 - */ -#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8) -/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_OE (BIT(0)) -#define IO_MUX_GPIO53_MCU_OE_M (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S) -#define IO_MUX_GPIO53_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO53_MCU_OE_S 0 -/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO53_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO53_SLP_SEL_M (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S) -#define IO_MUX_GPIO53_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO53_SLP_SEL_S 1 -/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO53_MCU_WPD_M (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S) -#define IO_MUX_GPIO53_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO53_MCU_WPD_S 2 -/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO53_MCU_WPU_M (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S) -#define IO_MUX_GPIO53_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO53_MCU_WPU_S 3 -/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_IE (BIT(4)) -#define IO_MUX_GPIO53_MCU_IE_M (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S) -#define IO_MUX_GPIO53_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO53_MCU_IE_S 4 -/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO53_MCU_DRV 0x00000003U -#define IO_MUX_GPIO53_MCU_DRV_M (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S) -#define IO_MUX_GPIO53_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO53_MCU_DRV_S 5 -/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO53_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO53_FUN_WPD_M (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S) -#define IO_MUX_GPIO53_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO53_FUN_WPD_S 7 -/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO53_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO53_FUN_WPU_M (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S) -#define IO_MUX_GPIO53_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO53_FUN_WPU_S 8 -/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO53_FUN_IE (BIT(9)) -#define IO_MUX_GPIO53_FUN_IE_M (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S) -#define IO_MUX_GPIO53_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO53_FUN_IE_S 9 -/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO53_FUN_DRV 0x00000003U -#define IO_MUX_GPIO53_FUN_DRV_M (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S) -#define IO_MUX_GPIO53_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO53_FUN_DRV_S 10 -/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO53_MCU_SEL 0x00000007U -#define IO_MUX_GPIO53_MCU_SEL_M (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S) -#define IO_MUX_GPIO53_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO53_MCU_SEL_S 12 -/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO53_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO53_FILTER_EN_M (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S) -#define IO_MUX_GPIO53_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO53_FILTER_EN_S 15 - -/** IO_MUX_gpio54_REG register - * iomux control register for gpio54 - */ -#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc) -/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_OE (BIT(0)) -#define IO_MUX_GPIO54_MCU_OE_M (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S) -#define IO_MUX_GPIO54_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO54_MCU_OE_S 0 -/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO54_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO54_SLP_SEL_M (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S) -#define IO_MUX_GPIO54_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO54_SLP_SEL_S 1 -/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO54_MCU_WPD_M (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S) -#define IO_MUX_GPIO54_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO54_MCU_WPD_S 2 -/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO54_MCU_WPU_M (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S) -#define IO_MUX_GPIO54_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO54_MCU_WPU_S 3 -/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_IE (BIT(4)) -#define IO_MUX_GPIO54_MCU_IE_M (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S) -#define IO_MUX_GPIO54_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO54_MCU_IE_S 4 -/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO54_MCU_DRV 0x00000003U -#define IO_MUX_GPIO54_MCU_DRV_M (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S) -#define IO_MUX_GPIO54_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO54_MCU_DRV_S 5 -/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO54_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO54_FUN_WPD_M (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S) -#define IO_MUX_GPIO54_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO54_FUN_WPD_S 7 -/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO54_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO54_FUN_WPU_M (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S) -#define IO_MUX_GPIO54_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO54_FUN_WPU_S 8 -/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO54_FUN_IE (BIT(9)) -#define IO_MUX_GPIO54_FUN_IE_M (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S) -#define IO_MUX_GPIO54_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO54_FUN_IE_S 9 -/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO54_FUN_DRV 0x00000003U -#define IO_MUX_GPIO54_FUN_DRV_M (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S) -#define IO_MUX_GPIO54_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO54_FUN_DRV_S 10 -/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO54_MCU_SEL 0x00000007U -#define IO_MUX_GPIO54_MCU_SEL_M (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S) -#define IO_MUX_GPIO54_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO54_MCU_SEL_S 12 -/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO54_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO54_FILTER_EN_M (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S) -#define IO_MUX_GPIO54_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO54_FILTER_EN_S 15 - -/** IO_MUX_gpio55_REG register - * iomux control register for gpio55 - */ -#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0) -/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_OE (BIT(0)) -#define IO_MUX_GPIO55_MCU_OE_M (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S) -#define IO_MUX_GPIO55_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO55_MCU_OE_S 0 -/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO55_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO55_SLP_SEL_M (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S) -#define IO_MUX_GPIO55_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO55_SLP_SEL_S 1 -/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO55_MCU_WPD_M (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S) -#define IO_MUX_GPIO55_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO55_MCU_WPD_S 2 -/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO55_MCU_WPU_M (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S) -#define IO_MUX_GPIO55_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO55_MCU_WPU_S 3 -/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_IE (BIT(4)) -#define IO_MUX_GPIO55_MCU_IE_M (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S) -#define IO_MUX_GPIO55_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO55_MCU_IE_S 4 -/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO55_MCU_DRV 0x00000003U -#define IO_MUX_GPIO55_MCU_DRV_M (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S) -#define IO_MUX_GPIO55_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO55_MCU_DRV_S 5 -/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO55_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO55_FUN_WPD_M (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S) -#define IO_MUX_GPIO55_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO55_FUN_WPD_S 7 -/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO55_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO55_FUN_WPU_M (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S) -#define IO_MUX_GPIO55_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO55_FUN_WPU_S 8 -/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO55_FUN_IE (BIT(9)) -#define IO_MUX_GPIO55_FUN_IE_M (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S) -#define IO_MUX_GPIO55_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO55_FUN_IE_S 9 -/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO55_FUN_DRV 0x00000003U -#define IO_MUX_GPIO55_FUN_DRV_M (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S) -#define IO_MUX_GPIO55_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO55_FUN_DRV_S 10 -/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO55_MCU_SEL 0x00000007U -#define IO_MUX_GPIO55_MCU_SEL_M (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S) -#define IO_MUX_GPIO55_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO55_MCU_SEL_S 12 -/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO55_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO55_FILTER_EN_M (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S) -#define IO_MUX_GPIO55_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO55_FILTER_EN_S 15 - -/** IO_MUX_gpio56_REG register - * iomux control register for gpio56 - */ -#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4) -/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_OE (BIT(0)) -#define IO_MUX_GPIO56_MCU_OE_M (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S) -#define IO_MUX_GPIO56_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO56_MCU_OE_S 0 -/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO56_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO56_SLP_SEL_M (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S) -#define IO_MUX_GPIO56_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO56_SLP_SEL_S 1 -/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO56_MCU_WPD_M (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S) -#define IO_MUX_GPIO56_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO56_MCU_WPD_S 2 -/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO56_MCU_WPU_M (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S) -#define IO_MUX_GPIO56_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO56_MCU_WPU_S 3 -/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_IE (BIT(4)) -#define IO_MUX_GPIO56_MCU_IE_M (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S) -#define IO_MUX_GPIO56_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO56_MCU_IE_S 4 -/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ -#define IO_MUX_GPIO56_MCU_DRV 0x00000003U -#define IO_MUX_GPIO56_MCU_DRV_M (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S) -#define IO_MUX_GPIO56_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO56_MCU_DRV_S 5 -/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO56_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO56_FUN_WPD_M (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S) -#define IO_MUX_GPIO56_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO56_FUN_WPD_S 7 -/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO56_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO56_FUN_WPU_M (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S) -#define IO_MUX_GPIO56_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO56_FUN_WPU_S 8 -/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO56_FUN_IE (BIT(9)) -#define IO_MUX_GPIO56_FUN_IE_M (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S) -#define IO_MUX_GPIO56_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO56_FUN_IE_S 9 -/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO56_FUN_DRV 0x00000003U -#define IO_MUX_GPIO56_FUN_DRV_M (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S) -#define IO_MUX_GPIO56_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO56_FUN_DRV_S 10 -/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO56_MCU_SEL 0x00000007U -#define IO_MUX_GPIO56_MCU_SEL_M (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S) -#define IO_MUX_GPIO56_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO56_MCU_SEL_S 12 -/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO56_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO56_FILTER_EN_M (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S) -#define IO_MUX_GPIO56_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO56_FILTER_EN_S 15 - -/** IO_MUX_DATE_REG register - * iomux version - */ -#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104) -/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794; - * csv date - */ -#define IO_MUX_DATE 0x0FFFFFFFU -#define IO_MUX_DATE_M (IO_MUX_DATE_V << IO_MUX_DATE_S) -#define IO_MUX_DATE_V 0x0FFFFFFFU -#define IO_MUX_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/iomux_struct.h b/components/soc/esp32p4/include/soc/iomux_struct.h deleted file mode 100644 index 583b6dec07..0000000000 --- a/components/soc/esp32p4/include/soc/iomux_struct.h +++ /dev/null @@ -1,3429 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: IOMUX Register */ -/** Type of gpio0 register - * iomux control register for gpio0 - */ -typedef union { - struct { - /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio0_mcu_oe:1; - /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio0_slp_sel:1; - /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio0_mcu_wpd:1; - /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio0_mcu_wpu:1; - /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio0_mcu_ie:1; - /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio0_mcu_drv:2; - /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio0_fun_wpd:1; - /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio0_fun_wpu:1; - /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio0_fun_ie:1; - /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio0_fun_drv:2; - /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio0_mcu_sel:3; - /** gpio0_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio0_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio0_reg_t; - -/** Type of gpio1 register - * iomux control register for gpio1 - */ -typedef union { - struct { - /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio1_mcu_oe:1; - /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio1_slp_sel:1; - /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio1_mcu_wpd:1; - /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio1_mcu_wpu:1; - /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio1_mcu_ie:1; - /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio1_mcu_drv:2; - /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio1_fun_wpd:1; - /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio1_fun_wpu:1; - /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio1_fun_ie:1; - /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio1_fun_drv:2; - /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio1_mcu_sel:3; - /** gpio1_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio1_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio1_reg_t; - -/** Type of gpio2 register - * iomux control register for gpio2 - */ -typedef union { - struct { - /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio2_mcu_oe:1; - /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio2_slp_sel:1; - /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio2_mcu_wpd:1; - /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio2_mcu_wpu:1; - /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio2_mcu_ie:1; - /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio2_mcu_drv:2; - /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio2_fun_wpd:1; - /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio2_fun_wpu:1; - /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio2_fun_ie:1; - /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio2_fun_drv:2; - /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio2_mcu_sel:3; - /** gpio2_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio2_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio2_reg_t; - -/** Type of gpio3 register - * iomux control register for gpio3 - */ -typedef union { - struct { - /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio3_mcu_oe:1; - /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio3_slp_sel:1; - /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio3_mcu_wpd:1; - /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio3_mcu_wpu:1; - /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio3_mcu_ie:1; - /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio3_mcu_drv:2; - /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio3_fun_wpd:1; - /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio3_fun_wpu:1; - /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio3_fun_ie:1; - /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio3_fun_drv:2; - /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio3_mcu_sel:3; - /** gpio3_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio3_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio3_reg_t; - -/** Type of gpio4 register - * iomux control register for gpio4 - */ -typedef union { - struct { - /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio4_mcu_oe:1; - /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio4_slp_sel:1; - /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio4_mcu_wpd:1; - /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio4_mcu_wpu:1; - /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio4_mcu_ie:1; - /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio4_mcu_drv:2; - /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio4_fun_wpd:1; - /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio4_fun_wpu:1; - /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio4_fun_ie:1; - /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio4_fun_drv:2; - /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio4_mcu_sel:3; - /** gpio4_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio4_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio4_reg_t; - -/** Type of gpio5 register - * iomux control register for gpio5 - */ -typedef union { - struct { - /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio5_mcu_oe:1; - /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio5_slp_sel:1; - /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio5_mcu_wpd:1; - /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio5_mcu_wpu:1; - /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio5_mcu_ie:1; - /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio5_mcu_drv:2; - /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio5_fun_wpd:1; - /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio5_fun_wpu:1; - /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio5_fun_ie:1; - /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio5_fun_drv:2; - /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio5_mcu_sel:3; - /** gpio5_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio5_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio5_reg_t; - -/** Type of gpio6 register - * iomux control register for gpio6 - */ -typedef union { - struct { - /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio6_mcu_oe:1; - /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio6_slp_sel:1; - /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio6_mcu_wpd:1; - /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio6_mcu_wpu:1; - /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio6_mcu_ie:1; - /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio6_mcu_drv:2; - /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio6_fun_wpd:1; - /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio6_fun_wpu:1; - /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio6_fun_ie:1; - /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio6_fun_drv:2; - /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio6_mcu_sel:3; - /** gpio6_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio6_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio6_reg_t; - -/** Type of gpio7 register - * iomux control register for gpio7 - */ -typedef union { - struct { - /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio7_mcu_oe:1; - /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio7_slp_sel:1; - /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio7_mcu_wpd:1; - /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio7_mcu_wpu:1; - /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio7_mcu_ie:1; - /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio7_mcu_drv:2; - /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio7_fun_wpd:1; - /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio7_fun_wpu:1; - /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio7_fun_ie:1; - /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio7_fun_drv:2; - /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio7_mcu_sel:3; - /** gpio7_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio7_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio7_reg_t; - -/** Type of gpio8 register - * iomux control register for gpio8 - */ -typedef union { - struct { - /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio8_mcu_oe:1; - /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio8_slp_sel:1; - /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio8_mcu_wpd:1; - /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio8_mcu_wpu:1; - /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio8_mcu_ie:1; - /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio8_mcu_drv:2; - /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio8_fun_wpd:1; - /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio8_fun_wpu:1; - /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio8_fun_ie:1; - /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio8_fun_drv:2; - /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio8_mcu_sel:3; - /** gpio8_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio8_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio8_reg_t; - -/** Type of gpio9 register - * iomux control register for gpio9 - */ -typedef union { - struct { - /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio9_mcu_oe:1; - /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio9_slp_sel:1; - /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio9_mcu_wpd:1; - /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio9_mcu_wpu:1; - /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio9_mcu_ie:1; - /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio9_mcu_drv:2; - /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio9_fun_wpd:1; - /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio9_fun_wpu:1; - /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio9_fun_ie:1; - /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio9_fun_drv:2; - /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio9_mcu_sel:3; - /** gpio9_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio9_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio9_reg_t; - -/** Type of gpio10 register - * iomux control register for gpio10 - */ -typedef union { - struct { - /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio10_mcu_oe:1; - /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio10_slp_sel:1; - /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio10_mcu_wpd:1; - /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio10_mcu_wpu:1; - /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio10_mcu_ie:1; - /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio10_mcu_drv:2; - /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio10_fun_wpd:1; - /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio10_fun_wpu:1; - /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio10_fun_ie:1; - /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio10_fun_drv:2; - /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio10_mcu_sel:3; - /** gpio10_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio10_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio10_reg_t; - -/** Type of gpio11 register - * iomux control register for gpio11 - */ -typedef union { - struct { - /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio11_mcu_oe:1; - /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio11_slp_sel:1; - /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio11_mcu_wpd:1; - /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio11_mcu_wpu:1; - /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio11_mcu_ie:1; - /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio11_mcu_drv:2; - /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio11_fun_wpd:1; - /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio11_fun_wpu:1; - /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio11_fun_ie:1; - /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio11_fun_drv:2; - /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio11_mcu_sel:3; - /** gpio11_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio11_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio11_reg_t; - -/** Type of gpio12 register - * iomux control register for gpio12 - */ -typedef union { - struct { - /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio12_mcu_oe:1; - /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio12_slp_sel:1; - /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio12_mcu_wpd:1; - /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio12_mcu_wpu:1; - /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio12_mcu_ie:1; - /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio12_mcu_drv:2; - /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio12_fun_wpd:1; - /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio12_fun_wpu:1; - /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio12_fun_ie:1; - /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio12_fun_drv:2; - /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio12_mcu_sel:3; - /** gpio12_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio12_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio12_reg_t; - -/** Type of gpio13 register - * iomux control register for gpio13 - */ -typedef union { - struct { - /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio13_mcu_oe:1; - /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio13_slp_sel:1; - /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio13_mcu_wpd:1; - /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio13_mcu_wpu:1; - /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio13_mcu_ie:1; - /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio13_mcu_drv:2; - /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio13_fun_wpd:1; - /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio13_fun_wpu:1; - /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio13_fun_ie:1; - /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio13_fun_drv:2; - /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio13_mcu_sel:3; - /** gpio13_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio13_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio13_reg_t; - -/** Type of gpio14 register - * iomux control register for gpio14 - */ -typedef union { - struct { - /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio14_mcu_oe:1; - /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio14_slp_sel:1; - /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio14_mcu_wpd:1; - /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio14_mcu_wpu:1; - /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio14_mcu_ie:1; - /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio14_mcu_drv:2; - /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio14_fun_wpd:1; - /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio14_fun_wpu:1; - /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio14_fun_ie:1; - /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio14_fun_drv:2; - /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio14_mcu_sel:3; - /** gpio14_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio14_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio14_reg_t; - -/** Type of gpio15 register - * iomux control register for gpio15 - */ -typedef union { - struct { - /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio15_mcu_oe:1; - /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio15_slp_sel:1; - /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio15_mcu_wpd:1; - /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio15_mcu_wpu:1; - /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio15_mcu_ie:1; - /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio15_mcu_drv:2; - /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio15_fun_wpd:1; - /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio15_fun_wpu:1; - /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio15_fun_ie:1; - /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio15_fun_drv:2; - /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio15_mcu_sel:3; - /** gpio15_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio15_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio15_reg_t; - -/** Type of gpio16 register - * iomux control register for gpio16 - */ -typedef union { - struct { - /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio16_mcu_oe:1; - /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio16_slp_sel:1; - /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio16_mcu_wpd:1; - /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio16_mcu_wpu:1; - /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio16_mcu_ie:1; - /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio16_mcu_drv:2; - /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio16_fun_wpd:1; - /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio16_fun_wpu:1; - /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio16_fun_ie:1; - /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio16_fun_drv:2; - /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio16_mcu_sel:3; - /** gpio16_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio16_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio16_reg_t; - -/** Type of gpio17 register - * iomux control register for gpio17 - */ -typedef union { - struct { - /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio17_mcu_oe:1; - /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio17_slp_sel:1; - /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio17_mcu_wpd:1; - /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio17_mcu_wpu:1; - /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio17_mcu_ie:1; - /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio17_mcu_drv:2; - /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio17_fun_wpd:1; - /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio17_fun_wpu:1; - /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio17_fun_ie:1; - /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio17_fun_drv:2; - /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio17_mcu_sel:3; - /** gpio17_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio17_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio17_reg_t; - -/** Type of gpio18 register - * iomux control register for gpio18 - */ -typedef union { - struct { - /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio18_mcu_oe:1; - /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio18_slp_sel:1; - /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio18_mcu_wpd:1; - /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio18_mcu_wpu:1; - /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio18_mcu_ie:1; - /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio18_mcu_drv:2; - /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio18_fun_wpd:1; - /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio18_fun_wpu:1; - /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio18_fun_ie:1; - /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio18_fun_drv:2; - /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio18_mcu_sel:3; - /** gpio18_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio18_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio18_reg_t; - -/** Type of gpio19 register - * iomux control register for gpio19 - */ -typedef union { - struct { - /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio19_mcu_oe:1; - /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio19_slp_sel:1; - /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio19_mcu_wpd:1; - /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio19_mcu_wpu:1; - /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio19_mcu_ie:1; - /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio19_mcu_drv:2; - /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio19_fun_wpd:1; - /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio19_fun_wpu:1; - /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio19_fun_ie:1; - /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio19_fun_drv:2; - /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio19_mcu_sel:3; - /** gpio19_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio19_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio19_reg_t; - -/** Type of gpio20 register - * iomux control register for gpio20 - */ -typedef union { - struct { - /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio20_mcu_oe:1; - /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio20_slp_sel:1; - /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio20_mcu_wpd:1; - /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio20_mcu_wpu:1; - /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio20_mcu_ie:1; - /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio20_mcu_drv:2; - /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio20_fun_wpd:1; - /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio20_fun_wpu:1; - /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio20_fun_ie:1; - /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio20_fun_drv:2; - /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio20_mcu_sel:3; - /** gpio20_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio20_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio20_reg_t; - -/** Type of gpio21 register - * iomux control register for gpio21 - */ -typedef union { - struct { - /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio21_mcu_oe:1; - /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio21_slp_sel:1; - /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio21_mcu_wpd:1; - /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio21_mcu_wpu:1; - /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio21_mcu_ie:1; - /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio21_mcu_drv:2; - /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio21_fun_wpd:1; - /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio21_fun_wpu:1; - /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio21_fun_ie:1; - /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio21_fun_drv:2; - /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio21_mcu_sel:3; - /** gpio21_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio21_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio21_reg_t; - -/** Type of gpio22 register - * iomux control register for gpio22 - */ -typedef union { - struct { - /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio22_mcu_oe:1; - /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio22_slp_sel:1; - /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio22_mcu_wpd:1; - /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio22_mcu_wpu:1; - /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio22_mcu_ie:1; - /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio22_mcu_drv:2; - /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio22_fun_wpd:1; - /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio22_fun_wpu:1; - /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio22_fun_ie:1; - /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio22_fun_drv:2; - /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio22_mcu_sel:3; - /** gpio22_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio22_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio22_reg_t; - -/** Type of gpio23 register - * iomux control register for gpio23 - */ -typedef union { - struct { - /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio23_mcu_oe:1; - /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio23_slp_sel:1; - /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio23_mcu_wpd:1; - /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio23_mcu_wpu:1; - /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio23_mcu_ie:1; - /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio23_mcu_drv:2; - /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio23_fun_wpd:1; - /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio23_fun_wpu:1; - /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio23_fun_ie:1; - /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio23_fun_drv:2; - /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio23_mcu_sel:3; - /** gpio23_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio23_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio23_reg_t; - -/** Type of gpio24 register - * iomux control register for gpio24 - */ -typedef union { - struct { - /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio24_mcu_oe:1; - /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio24_slp_sel:1; - /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio24_mcu_wpd:1; - /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio24_mcu_wpu:1; - /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio24_mcu_ie:1; - /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio24_mcu_drv:2; - /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio24_fun_wpd:1; - /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio24_fun_wpu:1; - /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio24_fun_ie:1; - /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio24_fun_drv:2; - /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio24_mcu_sel:3; - /** gpio24_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio24_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio24_reg_t; - -/** Type of gpio25 register - * iomux control register for gpio25 - */ -typedef union { - struct { - /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio25_mcu_oe:1; - /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio25_slp_sel:1; - /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio25_mcu_wpd:1; - /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio25_mcu_wpu:1; - /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio25_mcu_ie:1; - /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio25_mcu_drv:2; - /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio25_fun_wpd:1; - /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio25_fun_wpu:1; - /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio25_fun_ie:1; - /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio25_fun_drv:2; - /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio25_mcu_sel:3; - /** gpio25_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio25_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio25_reg_t; - -/** Type of gpio26 register - * iomux control register for gpio26 - */ -typedef union { - struct { - /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio26_mcu_oe:1; - /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio26_slp_sel:1; - /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio26_mcu_wpd:1; - /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio26_mcu_wpu:1; - /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio26_mcu_ie:1; - /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio26_mcu_drv:2; - /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio26_fun_wpd:1; - /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio26_fun_wpu:1; - /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio26_fun_ie:1; - /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio26_fun_drv:2; - /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio26_mcu_sel:3; - /** gpio26_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio26_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio26_reg_t; - -/** Type of gpio27 register - * iomux control register for gpio27 - */ -typedef union { - struct { - /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio27_mcu_oe:1; - /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio27_slp_sel:1; - /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio27_mcu_wpd:1; - /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio27_mcu_wpu:1; - /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio27_mcu_ie:1; - /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio27_mcu_drv:2; - /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio27_fun_wpd:1; - /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio27_fun_wpu:1; - /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio27_fun_ie:1; - /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio27_fun_drv:2; - /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio27_mcu_sel:3; - /** gpio27_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio27_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio27_reg_t; - -/** Type of gpio28 register - * iomux control register for gpio28 - */ -typedef union { - struct { - /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio28_mcu_oe:1; - /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio28_slp_sel:1; - /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio28_mcu_wpd:1; - /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio28_mcu_wpu:1; - /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio28_mcu_ie:1; - /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio28_mcu_drv:2; - /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio28_fun_wpd:1; - /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio28_fun_wpu:1; - /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio28_fun_ie:1; - /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio28_fun_drv:2; - /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio28_mcu_sel:3; - /** gpio28_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio28_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio28_reg_t; - -/** Type of gpio29 register - * iomux control register for gpio29 - */ -typedef union { - struct { - /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio29_mcu_oe:1; - /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio29_slp_sel:1; - /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio29_mcu_wpd:1; - /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio29_mcu_wpu:1; - /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio29_mcu_ie:1; - /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio29_mcu_drv:2; - /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio29_fun_wpd:1; - /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio29_fun_wpu:1; - /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio29_fun_ie:1; - /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio29_fun_drv:2; - /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio29_mcu_sel:3; - /** gpio29_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio29_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio29_reg_t; - -/** Type of gpio30 register - * iomux control register for gpio30 - */ -typedef union { - struct { - /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio30_mcu_oe:1; - /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio30_slp_sel:1; - /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio30_mcu_wpd:1; - /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio30_mcu_wpu:1; - /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio30_mcu_ie:1; - /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio30_mcu_drv:2; - /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio30_fun_wpd:1; - /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio30_fun_wpu:1; - /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio30_fun_ie:1; - /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio30_fun_drv:2; - /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio30_mcu_sel:3; - /** gpio30_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio30_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio30_reg_t; - -/** Type of gpio31 register - * iomux control register for gpio31 - */ -typedef union { - struct { - /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio31_mcu_oe:1; - /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio31_slp_sel:1; - /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio31_mcu_wpd:1; - /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio31_mcu_wpu:1; - /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio31_mcu_ie:1; - /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio31_mcu_drv:2; - /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio31_fun_wpd:1; - /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio31_fun_wpu:1; - /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio31_fun_ie:1; - /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio31_fun_drv:2; - /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio31_mcu_sel:3; - /** gpio31_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio31_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio31_reg_t; - -/** Type of gpio32 register - * iomux control register for gpio32 - */ -typedef union { - struct { - /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio32_mcu_oe:1; - /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio32_slp_sel:1; - /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio32_mcu_wpd:1; - /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio32_mcu_wpu:1; - /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio32_mcu_ie:1; - /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio32_mcu_drv:2; - /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio32_fun_wpd:1; - /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio32_fun_wpu:1; - /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio32_fun_ie:1; - /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio32_fun_drv:2; - /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio32_mcu_sel:3; - /** gpio32_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio32_filter_en:1; - /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t gpio32_rue_i3c:1; - /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0; - * NA - */ - uint32_t gpio32_ru_i3c:2; - /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t gpio32_rue_sel_i3c:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} io_mux_gpio32_reg_t; - -/** Type of gpio33 register - * iomux control register for gpio33 - */ -typedef union { - struct { - /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio33_mcu_oe:1; - /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio33_slp_sel:1; - /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio33_mcu_wpd:1; - /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio33_mcu_wpu:1; - /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio33_mcu_ie:1; - /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio33_mcu_drv:2; - /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio33_fun_wpd:1; - /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio33_fun_wpu:1; - /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio33_fun_ie:1; - /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio33_fun_drv:2; - /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio33_mcu_sel:3; - /** gpio33_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio33_filter_en:1; - /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t gpio33_rue_i3c:1; - /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0; - * NA - */ - uint32_t gpio33_ru_i3c:2; - /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t gpio33_rue_sel_i3c:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} io_mux_gpio33_reg_t; - -/** Type of gpio34 register - * iomux control register for gpio34 - */ -typedef union { - struct { - /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio34_mcu_oe:1; - /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio34_slp_sel:1; - /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio34_mcu_wpd:1; - /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio34_mcu_wpu:1; - /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio34_mcu_ie:1; - /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio34_mcu_drv:2; - /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio34_fun_wpd:1; - /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio34_fun_wpu:1; - /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio34_fun_ie:1; - /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio34_fun_drv:2; - /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio34_mcu_sel:3; - /** gpio34_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio34_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio34_reg_t; - -/** Type of gpio35 register - * iomux control register for gpio35 - */ -typedef union { - struct { - /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio35_mcu_oe:1; - /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio35_slp_sel:1; - /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio35_mcu_wpd:1; - /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio35_mcu_wpu:1; - /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio35_mcu_ie:1; - /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio35_mcu_drv:2; - /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio35_fun_wpd:1; - /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio35_fun_wpu:1; - /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio35_fun_ie:1; - /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio35_fun_drv:2; - /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio35_mcu_sel:3; - /** gpio35_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio35_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio35_reg_t; - -/** Type of gpio36 register - * iomux control register for gpio36 - */ -typedef union { - struct { - /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio36_mcu_oe:1; - /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio36_slp_sel:1; - /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio36_mcu_wpd:1; - /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio36_mcu_wpu:1; - /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio36_mcu_ie:1; - /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio36_mcu_drv:2; - /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio36_fun_wpd:1; - /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio36_fun_wpu:1; - /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio36_fun_ie:1; - /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio36_fun_drv:2; - /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio36_mcu_sel:3; - /** gpio36_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio36_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio36_reg_t; - -/** Type of gpio37 register - * iomux control register for gpio37 - */ -typedef union { - struct { - /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio37_mcu_oe:1; - /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio37_slp_sel:1; - /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio37_mcu_wpd:1; - /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio37_mcu_wpu:1; - /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio37_mcu_ie:1; - /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio37_mcu_drv:2; - /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio37_fun_wpd:1; - /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio37_fun_wpu:1; - /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio37_fun_ie:1; - /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio37_fun_drv:2; - /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio37_mcu_sel:3; - /** gpio37_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio37_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio37_reg_t; - -/** Type of gpio38 register - * iomux control register for gpio38 - */ -typedef union { - struct { - /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio38_mcu_oe:1; - /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio38_slp_sel:1; - /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio38_mcu_wpd:1; - /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio38_mcu_wpu:1; - /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio38_mcu_ie:1; - /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio38_mcu_drv:2; - /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio38_fun_wpd:1; - /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio38_fun_wpu:1; - /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio38_fun_ie:1; - /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio38_fun_drv:2; - /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio38_mcu_sel:3; - /** gpio38_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio38_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio38_reg_t; - -/** Type of gpio39 register - * iomux control register for gpio39 - */ -typedef union { - struct { - /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio39_mcu_oe:1; - /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio39_slp_sel:1; - /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio39_mcu_wpd:1; - /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio39_mcu_wpu:1; - /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio39_mcu_ie:1; - /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio39_mcu_drv:2; - /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio39_fun_wpd:1; - /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio39_fun_wpu:1; - /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio39_fun_ie:1; - /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio39_fun_drv:2; - /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio39_mcu_sel:3; - /** gpio39_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio39_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio39_reg_t; - -/** Type of gpio40 register - * iomux control register for gpio40 - */ -typedef union { - struct { - /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio40_mcu_oe:1; - /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio40_slp_sel:1; - /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio40_mcu_wpd:1; - /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio40_mcu_wpu:1; - /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio40_mcu_ie:1; - /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio40_mcu_drv:2; - /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio40_fun_wpd:1; - /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio40_fun_wpu:1; - /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio40_fun_ie:1; - /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio40_fun_drv:2; - /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio40_mcu_sel:3; - /** gpio40_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio40_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio40_reg_t; - -/** Type of gpio41 register - * iomux control register for gpio41 - */ -typedef union { - struct { - /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio41_mcu_oe:1; - /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio41_slp_sel:1; - /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio41_mcu_wpd:1; - /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio41_mcu_wpu:1; - /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio41_mcu_ie:1; - /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio41_mcu_drv:2; - /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio41_fun_wpd:1; - /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio41_fun_wpu:1; - /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio41_fun_ie:1; - /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio41_fun_drv:2; - /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio41_mcu_sel:3; - /** gpio41_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio41_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio41_reg_t; - -/** Type of gpio42 register - * iomux control register for gpio42 - */ -typedef union { - struct { - /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio42_mcu_oe:1; - /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio42_slp_sel:1; - /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio42_mcu_wpd:1; - /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio42_mcu_wpu:1; - /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio42_mcu_ie:1; - /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio42_mcu_drv:2; - /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio42_fun_wpd:1; - /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio42_fun_wpu:1; - /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio42_fun_ie:1; - /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio42_fun_drv:2; - /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio42_mcu_sel:3; - /** gpio42_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio42_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio42_reg_t; - -/** Type of gpio43 register - * iomux control register for gpio43 - */ -typedef union { - struct { - /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio43_mcu_oe:1; - /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio43_slp_sel:1; - /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio43_mcu_wpd:1; - /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio43_mcu_wpu:1; - /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio43_mcu_ie:1; - /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio43_mcu_drv:2; - /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio43_fun_wpd:1; - /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio43_fun_wpu:1; - /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio43_fun_ie:1; - /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio43_fun_drv:2; - /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio43_mcu_sel:3; - /** gpio43_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio43_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio43_reg_t; - -/** Type of gpio44 register - * iomux control register for gpio44 - */ -typedef union { - struct { - /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio44_mcu_oe:1; - /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio44_slp_sel:1; - /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio44_mcu_wpd:1; - /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio44_mcu_wpu:1; - /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio44_mcu_ie:1; - /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio44_mcu_drv:2; - /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio44_fun_wpd:1; - /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio44_fun_wpu:1; - /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio44_fun_ie:1; - /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio44_fun_drv:2; - /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio44_mcu_sel:3; - /** gpio44_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio44_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio44_reg_t; - -/** Type of gpio45 register - * iomux control register for gpio45 - */ -typedef union { - struct { - /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio45_mcu_oe:1; - /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio45_slp_sel:1; - /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio45_mcu_wpd:1; - /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio45_mcu_wpu:1; - /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio45_mcu_ie:1; - /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio45_mcu_drv:2; - /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio45_fun_wpd:1; - /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio45_fun_wpu:1; - /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio45_fun_ie:1; - /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio45_fun_drv:2; - /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio45_mcu_sel:3; - /** gpio45_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio45_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio45_reg_t; - -/** Type of gpio46 register - * iomux control register for gpio46 - */ -typedef union { - struct { - /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio46_mcu_oe:1; - /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio46_slp_sel:1; - /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio46_mcu_wpd:1; - /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio46_mcu_wpu:1; - /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio46_mcu_ie:1; - /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio46_mcu_drv:2; - /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio46_fun_wpd:1; - /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio46_fun_wpu:1; - /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio46_fun_ie:1; - /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio46_fun_drv:2; - /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio46_mcu_sel:3; - /** gpio46_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio46_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio46_reg_t; - -/** Type of gpio47 register - * iomux control register for gpio47 - */ -typedef union { - struct { - /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio47_mcu_oe:1; - /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio47_slp_sel:1; - /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio47_mcu_wpd:1; - /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio47_mcu_wpu:1; - /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio47_mcu_ie:1; - /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio47_mcu_drv:2; - /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio47_fun_wpd:1; - /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio47_fun_wpu:1; - /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio47_fun_ie:1; - /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio47_fun_drv:2; - /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio47_mcu_sel:3; - /** gpio47_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio47_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio47_reg_t; - -/** Type of gpio48 register - * iomux control register for gpio48 - */ -typedef union { - struct { - /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio48_mcu_oe:1; - /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio48_slp_sel:1; - /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio48_mcu_wpd:1; - /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio48_mcu_wpu:1; - /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio48_mcu_ie:1; - /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio48_mcu_drv:2; - /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio48_fun_wpd:1; - /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio48_fun_wpu:1; - /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio48_fun_ie:1; - /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio48_fun_drv:2; - /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio48_mcu_sel:3; - /** gpio48_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio48_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio48_reg_t; - -/** Type of gpio49 register - * iomux control register for gpio49 - */ -typedef union { - struct { - /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio49_mcu_oe:1; - /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio49_slp_sel:1; - /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio49_mcu_wpd:1; - /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio49_mcu_wpu:1; - /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio49_mcu_ie:1; - /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio49_mcu_drv:2; - /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio49_fun_wpd:1; - /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio49_fun_wpu:1; - /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio49_fun_ie:1; - /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio49_fun_drv:2; - /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio49_mcu_sel:3; - /** gpio49_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio49_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio49_reg_t; - -/** Type of gpio50 register - * iomux control register for gpio50 - */ -typedef union { - struct { - /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio50_mcu_oe:1; - /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio50_slp_sel:1; - /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio50_mcu_wpd:1; - /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio50_mcu_wpu:1; - /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio50_mcu_ie:1; - /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio50_mcu_drv:2; - /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio50_fun_wpd:1; - /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio50_fun_wpu:1; - /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio50_fun_ie:1; - /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio50_fun_drv:2; - /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio50_mcu_sel:3; - /** gpio50_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio50_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio50_reg_t; - -/** Type of gpio51 register - * iomux control register for gpio51 - */ -typedef union { - struct { - /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio51_mcu_oe:1; - /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio51_slp_sel:1; - /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio51_mcu_wpd:1; - /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio51_mcu_wpu:1; - /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio51_mcu_ie:1; - /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio51_mcu_drv:2; - /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio51_fun_wpd:1; - /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio51_fun_wpu:1; - /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio51_fun_ie:1; - /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio51_fun_drv:2; - /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio51_mcu_sel:3; - /** gpio51_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio51_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio51_reg_t; - -/** Type of gpio52 register - * iomux control register for gpio52 - */ -typedef union { - struct { - /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio52_mcu_oe:1; - /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio52_slp_sel:1; - /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio52_mcu_wpd:1; - /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio52_mcu_wpu:1; - /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio52_mcu_ie:1; - /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio52_mcu_drv:2; - /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio52_fun_wpd:1; - /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio52_fun_wpu:1; - /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio52_fun_ie:1; - /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio52_fun_drv:2; - /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio52_mcu_sel:3; - /** gpio52_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio52_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio52_reg_t; - -/** Type of gpio53 register - * iomux control register for gpio53 - */ -typedef union { - struct { - /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio53_mcu_oe:1; - /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio53_slp_sel:1; - /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio53_mcu_wpd:1; - /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio53_mcu_wpu:1; - /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio53_mcu_ie:1; - /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio53_mcu_drv:2; - /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio53_fun_wpd:1; - /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio53_fun_wpu:1; - /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio53_fun_ie:1; - /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio53_fun_drv:2; - /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio53_mcu_sel:3; - /** gpio53_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio53_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio53_reg_t; - -/** Type of gpio54 register - * iomux control register for gpio54 - */ -typedef union { - struct { - /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio54_mcu_oe:1; - /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio54_slp_sel:1; - /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio54_mcu_wpd:1; - /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio54_mcu_wpu:1; - /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio54_mcu_ie:1; - /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio54_mcu_drv:2; - /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio54_fun_wpd:1; - /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio54_fun_wpu:1; - /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio54_fun_ie:1; - /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio54_fun_drv:2; - /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio54_mcu_sel:3; - /** gpio54_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio54_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio54_reg_t; - -/** Type of gpio55 register - * iomux control register for gpio55 - */ -typedef union { - struct { - /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio55_mcu_oe:1; - /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio55_slp_sel:1; - /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio55_mcu_wpd:1; - /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio55_mcu_wpu:1; - /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio55_mcu_ie:1; - /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio55_mcu_drv:2; - /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio55_fun_wpd:1; - /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio55_fun_wpu:1; - /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio55_fun_ie:1; - /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio55_fun_drv:2; - /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio55_mcu_sel:3; - /** gpio55_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio55_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio55_reg_t; - -/** Type of gpio56 register - * iomux control register for gpio56 - */ -typedef union { - struct { - /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio56_mcu_oe:1; - /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio56_slp_sel:1; - /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio56_mcu_wpd:1; - /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio56_mcu_wpu:1; - /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio56_mcu_ie:1; - /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strenth on sleep mode - */ - uint32_t gpio56_mcu_drv:2; - /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio56_fun_wpd:1; - /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio56_fun_wpu:1; - /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio56_fun_ie:1; - /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio56_fun_drv:2; - /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio56_mcu_sel:3; - /** gpio56_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio56_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio56_reg_t; - -/** Type of date register - * iomux version - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 2101794; - * csv date - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} io_mux_date_reg_t; - - -typedef struct { - uint32_t reserved_000; - volatile io_mux_gpio0_reg_t gpio0; - volatile io_mux_gpio1_reg_t gpio1; - volatile io_mux_gpio2_reg_t gpio2; - volatile io_mux_gpio3_reg_t gpio3; - volatile io_mux_gpio4_reg_t gpio4; - volatile io_mux_gpio5_reg_t gpio5; - volatile io_mux_gpio6_reg_t gpio6; - volatile io_mux_gpio7_reg_t gpio7; - volatile io_mux_gpio8_reg_t gpio8; - volatile io_mux_gpio9_reg_t gpio9; - volatile io_mux_gpio10_reg_t gpio10; - volatile io_mux_gpio11_reg_t gpio11; - volatile io_mux_gpio12_reg_t gpio12; - volatile io_mux_gpio13_reg_t gpio13; - volatile io_mux_gpio14_reg_t gpio14; - volatile io_mux_gpio15_reg_t gpio15; - volatile io_mux_gpio16_reg_t gpio16; - volatile io_mux_gpio17_reg_t gpio17; - volatile io_mux_gpio18_reg_t gpio18; - volatile io_mux_gpio19_reg_t gpio19; - volatile io_mux_gpio20_reg_t gpio20; - volatile io_mux_gpio21_reg_t gpio21; - volatile io_mux_gpio22_reg_t gpio22; - volatile io_mux_gpio23_reg_t gpio23; - volatile io_mux_gpio24_reg_t gpio24; - volatile io_mux_gpio25_reg_t gpio25; - volatile io_mux_gpio26_reg_t gpio26; - volatile io_mux_gpio27_reg_t gpio27; - volatile io_mux_gpio28_reg_t gpio28; - volatile io_mux_gpio29_reg_t gpio29; - volatile io_mux_gpio30_reg_t gpio30; - volatile io_mux_gpio31_reg_t gpio31; - volatile io_mux_gpio32_reg_t gpio32; - volatile io_mux_gpio33_reg_t gpio33; - volatile io_mux_gpio34_reg_t gpio34; - volatile io_mux_gpio35_reg_t gpio35; - volatile io_mux_gpio36_reg_t gpio36; - volatile io_mux_gpio37_reg_t gpio37; - volatile io_mux_gpio38_reg_t gpio38; - volatile io_mux_gpio39_reg_t gpio39; - volatile io_mux_gpio40_reg_t gpio40; - volatile io_mux_gpio41_reg_t gpio41; - volatile io_mux_gpio42_reg_t gpio42; - volatile io_mux_gpio43_reg_t gpio43; - volatile io_mux_gpio44_reg_t gpio44; - volatile io_mux_gpio45_reg_t gpio45; - volatile io_mux_gpio46_reg_t gpio46; - volatile io_mux_gpio47_reg_t gpio47; - volatile io_mux_gpio48_reg_t gpio48; - volatile io_mux_gpio49_reg_t gpio49; - volatile io_mux_gpio50_reg_t gpio50; - volatile io_mux_gpio51_reg_t gpio51; - volatile io_mux_gpio52_reg_t gpio52; - volatile io_mux_gpio53_reg_t gpio53; - volatile io_mux_gpio54_reg_t gpio54; - volatile io_mux_gpio55_reg_t gpio55; - volatile io_mux_gpio56_reg_t gpio56; - uint32_t reserved_0e8[7]; - volatile io_mux_date_reg_t date; -} io_mux_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lcd_cam_reg.h b/components/soc/esp32p4/include/soc/lcd_cam_reg.h index 715dc51396..7a2f8ed19a 100644 --- a/components/soc/esp32p4/include/soc/lcd_cam_reg.h +++ b/components/soc/esp32p4/include/soc/lcd_cam_reg.h @@ -1,962 +1,1145 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_LCD_CAM_REG_H_ -#define _SOC_LCD_CAM_REG_H_ - +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x0) -/* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit to enable clk gate.*/ -#define LCD_CAM_CLK_EN (BIT(31)) -#define LCD_CAM_CLK_EN_M (BIT(31)) -#define LCD_CAM_CLK_EN_V 0x1 -#define LCD_CAM_CLK_EN_S 31 -/* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ -/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/ -#define LCD_CAM_LCD_CLK_SEL 0x00000003 -#define LCD_CAM_LCD_CLK_SEL_M ((LCD_CAM_LCD_CLK_SEL_V)<<(LCD_CAM_LCD_CLK_SEL_S)) -#define LCD_CAM_LCD_CLK_SEL_V 0x3 -#define LCD_CAM_LCD_CLK_SEL_S 29 -/* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */ -/*description: Fractional clock divider denominator value.*/ -#define LCD_CAM_LCD_CLKM_DIV_A 0x0000003F -#define LCD_CAM_LCD_CLKM_DIV_A_M ((LCD_CAM_LCD_CLKM_DIV_A_V)<<(LCD_CAM_LCD_CLKM_DIV_A_S)) -#define LCD_CAM_LCD_CLKM_DIV_A_V 0x3F -#define LCD_CAM_LCD_CLKM_DIV_A_S 23 -/* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */ -/*description: Fractional clock divider numerator value.*/ -#define LCD_CAM_LCD_CLKM_DIV_B 0x0000003F -#define LCD_CAM_LCD_CLKM_DIV_B_M ((LCD_CAM_LCD_CLKM_DIV_B_V)<<(LCD_CAM_LCD_CLKM_DIV_B_S)) -#define LCD_CAM_LCD_CLKM_DIV_B_V 0x3F -#define LCD_CAM_LCD_CLKM_DIV_B_S 17 -/* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */ -/*description: Integral LCD clock divider value.*/ -#define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FF -#define LCD_CAM_LCD_CLKM_DIV_NUM_M ((LCD_CAM_LCD_CLKM_DIV_NUM_V)<<(LCD_CAM_LCD_CLKM_DIV_NUM_S)) -#define LCD_CAM_LCD_CLKM_DIV_NUM_V 0xFF -#define LCD_CAM_LCD_CLKM_DIV_NUM_S 9 -/* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is l -ow in the second half data cycle..*/ -#define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8)) -#define LCD_CAM_LCD_CK_OUT_EDGE_M (BIT(8)) -#define LCD_CAM_LCD_CK_OUT_EDGE_V 0x1 -#define LCD_CAM_LCD_CK_OUT_EDGE_S 8 -/* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle..*/ -#define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7)) -#define LCD_CAM_LCD_CK_IDLE_EDGE_M (BIT(7)) -#define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x1 -#define LCD_CAM_LCD_CK_IDLE_EDGE_S 7 -/* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */ -/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)..*/ -#define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6)) -#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (BIT(6)) -#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x1 -#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6 -/* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0..*/ -#define LCD_CAM_LCD_CLKCNT_N 0x0000003F -#define LCD_CAM_LCD_CLKCNT_N_M ((LCD_CAM_LCD_CLKCNT_N_V)<<(LCD_CAM_LCD_CLKCNT_N_S)) -#define LCD_CAM_LCD_CLKCNT_N_V 0x3F -#define LCD_CAM_LCD_CLKCNT_N_S 0 +/** LCDCAM_LCD_CLOCK_REG register + * LCD clock config register. + */ +#define LCDCAM_LCD_CLOCK_REG (DR_REG_LCDCAM_BASE + 0x0) +/** LCDCAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3; + * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + */ +#define LCDCAM_LCD_CLKCNT_N 0x0000003FU +#define LCDCAM_LCD_CLKCNT_N_M (LCDCAM_LCD_CLKCNT_N_V << LCDCAM_LCD_CLKCNT_N_S) +#define LCDCAM_LCD_CLKCNT_N_V 0x0000003FU +#define LCDCAM_LCD_CLKCNT_N_S 0 +/** LCDCAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1; + * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + */ +#define LCDCAM_LCD_CLK_EQU_SYSCLK (BIT(6)) +#define LCDCAM_LCD_CLK_EQU_SYSCLK_M (LCDCAM_LCD_CLK_EQU_SYSCLK_V << LCDCAM_LCD_CLK_EQU_SYSCLK_S) +#define LCDCAM_LCD_CLK_EQU_SYSCLK_V 0x00000001U +#define LCDCAM_LCD_CLK_EQU_SYSCLK_S 6 +/** LCDCAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0; + * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + */ +#define LCDCAM_LCD_CK_IDLE_EDGE (BIT(7)) +#define LCDCAM_LCD_CK_IDLE_EDGE_M (LCDCAM_LCD_CK_IDLE_EDGE_V << LCDCAM_LCD_CK_IDLE_EDGE_S) +#define LCDCAM_LCD_CK_IDLE_EDGE_V 0x00000001U +#define LCDCAM_LCD_CK_IDLE_EDGE_S 7 +/** LCDCAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0; + * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low + * in the second half data cycle. + */ +#define LCDCAM_LCD_CK_OUT_EDGE (BIT(8)) +#define LCDCAM_LCD_CK_OUT_EDGE_M (LCDCAM_LCD_CK_OUT_EDGE_V << LCDCAM_LCD_CK_OUT_EDGE_S) +#define LCDCAM_LCD_CK_OUT_EDGE_V 0x00000001U +#define LCDCAM_LCD_CK_OUT_EDGE_S 8 +/** LCDCAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; + * Integral LCD clock divider value + */ +#define LCDCAM_LCD_CLKM_DIV_NUM 0x000000FFU +#define LCDCAM_LCD_CLKM_DIV_NUM_M (LCDCAM_LCD_CLKM_DIV_NUM_V << LCDCAM_LCD_CLKM_DIV_NUM_S) +#define LCDCAM_LCD_CLKM_DIV_NUM_V 0x000000FFU +#define LCDCAM_LCD_CLKM_DIV_NUM_S 9 +/** LCDCAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ +#define LCDCAM_LCD_CLKM_DIV_B 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_B_M (LCDCAM_LCD_CLKM_DIV_B_V << LCDCAM_LCD_CLKM_DIV_B_S) +#define LCDCAM_LCD_CLKM_DIV_B_V 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_B_S 17 +/** LCDCAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ +#define LCDCAM_LCD_CLKM_DIV_A 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_A_M (LCDCAM_LCD_CLKM_DIV_A_V << LCDCAM_LCD_CLKM_DIV_A_S) +#define LCDCAM_LCD_CLKM_DIV_A_V 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_A_S 23 +/** LCDCAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0; + * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ +#define LCDCAM_LCD_CLK_SEL 0x00000003U +#define LCDCAM_LCD_CLK_SEL_M (LCDCAM_LCD_CLK_SEL_V << LCDCAM_LCD_CLK_SEL_S) +#define LCDCAM_LCD_CLK_SEL_V 0x00000003U +#define LCDCAM_LCD_CLK_SEL_S 29 +/** LCDCAM_CLK_EN : R/W; bitpos: [31]; default: 0; + * Set this bit to enable clk gate + */ +#define LCDCAM_CLK_EN (BIT(31)) +#define LCDCAM_CLK_EN_M (LCDCAM_CLK_EN_V << LCDCAM_CLK_EN_S) +#define LCDCAM_CLK_EN_V 0x00000001U +#define LCDCAM_CLK_EN_S 31 -#define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x4) -/* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ -/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/ -#define LCD_CAM_CAM_CLK_SEL 0x00000003 -#define LCD_CAM_CAM_CLK_SEL_M ((LCD_CAM_CAM_CLK_SEL_V)<<(LCD_CAM_CAM_CLK_SEL_S)) -#define LCD_CAM_CAM_CLK_SEL_V 0x3 -#define LCD_CAM_CAM_CLK_SEL_S 29 -/* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */ -/*description: Fractional clock divider denominator value.*/ -#define LCD_CAM_CAM_CLKM_DIV_A 0x0000003F -#define LCD_CAM_CAM_CLKM_DIV_A_M ((LCD_CAM_CAM_CLKM_DIV_A_V)<<(LCD_CAM_CAM_CLKM_DIV_A_S)) -#define LCD_CAM_CAM_CLKM_DIV_A_V 0x3F -#define LCD_CAM_CAM_CLKM_DIV_A_S 23 -/* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */ -/*description: Fractional clock divider numerator value.*/ -#define LCD_CAM_CAM_CLKM_DIV_B 0x0000003F -#define LCD_CAM_CAM_CLKM_DIV_B_M ((LCD_CAM_CAM_CLKM_DIV_B_V)<<(LCD_CAM_CAM_CLKM_DIV_B_S)) -#define LCD_CAM_CAM_CLKM_DIV_B_V 0x3F -#define LCD_CAM_CAM_CLKM_DIV_B_S 17 -/* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */ -/*description: Integral Camera clock divider value.*/ -#define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FF -#define LCD_CAM_CAM_CLKM_DIV_NUM_M ((LCD_CAM_CAM_CLKM_DIV_NUM_V)<<(LCD_CAM_CAM_CLKM_DIV_NUM_S)) -#define LCD_CAM_CAM_CLKM_DIV_NUM_V 0xFF -#define LCD_CAM_CAM_CLKM_DIV_NUM_S 9 -/* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_ -data_cyclelen..*/ -#define LCD_CAM_CAM_VS_EOF_EN (BIT(8)) -#define LCD_CAM_CAM_VS_EOF_EN_M (BIT(8)) -#define LCD_CAM_CAM_VS_EOF_EN_V 0x1 -#define LCD_CAM_CAM_VS_EOF_EN_S 8 -/* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: 1: Enable to generate CAM_HS_INT. 0: Disable..*/ -#define LCD_CAM_CAM_LINE_INT_EN (BIT(7)) -#define LCD_CAM_CAM_LINE_INT_EN_M (BIT(7)) -#define LCD_CAM_CAM_LINE_INT_EN_V 0x1 -#define LCD_CAM_CAM_LINE_INT_EN_S 7 -/* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/ -#define LCD_CAM_CAM_BIT_ORDER (BIT(6)) -#define LCD_CAM_CAM_BIT_ORDER_M (BIT(6)) -#define LCD_CAM_CAM_BIT_ORDER_V 0x1 -#define LCD_CAM_CAM_BIT_ORDER_S 6 -/* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byt -e mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change..*/ -#define LCD_CAM_CAM_BYTE_ORDER (BIT(5)) -#define LCD_CAM_CAM_BYTE_ORDER_M (BIT(5)) -#define LCD_CAM_CAM_BYTE_ORDER_V 0x1 -#define LCD_CAM_CAM_BYTE_ORDER_S 5 -/* LCD_CAM_CAM_UPDATE_REG : R/W/SC ;bitpos:[4] ;default: 1'h0 ; */ -/*description: 1: Update Camera registers, will be cleared by hardware. 0 : Not care..*/ -#define LCD_CAM_CAM_UPDATE_REG (BIT(4)) -#define LCD_CAM_CAM_UPDATE_REG_M (BIT(4)) -#define LCD_CAM_CAM_UPDATE_REG_V 0x1 -#define LCD_CAM_CAM_UPDATE_REG_S 4 -/* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */ -/*description: Filter threshold value for CAM_VSYNC signal..*/ -#define LCD_CAM_CAM_VSYNC_FILTER_THRES 0x00000007 -#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V)<<(LCD_CAM_CAM_VSYNC_FILTER_THRES_S)) -#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x7 -#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1 -/* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop -..*/ -#define LCD_CAM_CAM_STOP_EN (BIT(0)) -#define LCD_CAM_CAM_STOP_EN_M (BIT(0)) -#define LCD_CAM_CAM_STOP_EN_V 0x1 -#define LCD_CAM_CAM_STOP_EN_S 0 +/** LCDCAM_CAM_CTRL_REG register + * CAM config register. + */ +#define LCDCAM_CAM_CTRL_REG (DR_REG_LCDCAM_BASE + 0x4) +/** LCDCAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0; + * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + */ +#define LCDCAM_CAM_STOP_EN (BIT(0)) +#define LCDCAM_CAM_STOP_EN_M (LCDCAM_CAM_STOP_EN_V << LCDCAM_CAM_STOP_EN_S) +#define LCDCAM_CAM_STOP_EN_V 0x00000001U +#define LCDCAM_CAM_STOP_EN_S 0 +/** LCDCAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0; + * Filter threshold value for CAM_VSYNC signal. + */ +#define LCDCAM_CAM_VSYNC_FILTER_THRES 0x00000007U +#define LCDCAM_CAM_VSYNC_FILTER_THRES_M (LCDCAM_CAM_VSYNC_FILTER_THRES_V << LCDCAM_CAM_VSYNC_FILTER_THRES_S) +#define LCDCAM_CAM_VSYNC_FILTER_THRES_V 0x00000007U +#define LCDCAM_CAM_VSYNC_FILTER_THRES_S 1 +/** LCDCAM_CAM_UPDATE_REG : R/W/SC; bitpos: [4]; default: 0; + * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + */ +#define LCDCAM_CAM_UPDATE_REG (BIT(4)) +#define LCDCAM_CAM_UPDATE_REG_M (LCDCAM_CAM_UPDATE_REG_V << LCDCAM_CAM_UPDATE_REG_S) +#define LCDCAM_CAM_UPDATE_REG_V 0x00000001U +#define LCDCAM_CAM_UPDATE_REG_S 4 +/** LCDCAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0; + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ +#define LCDCAM_CAM_BYTE_ORDER (BIT(5)) +#define LCDCAM_CAM_BYTE_ORDER_M (LCDCAM_CAM_BYTE_ORDER_V << LCDCAM_CAM_BYTE_ORDER_S) +#define LCDCAM_CAM_BYTE_ORDER_V 0x00000001U +#define LCDCAM_CAM_BYTE_ORDER_S 5 +/** LCDCAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ +#define LCDCAM_CAM_BIT_ORDER (BIT(6)) +#define LCDCAM_CAM_BIT_ORDER_M (LCDCAM_CAM_BIT_ORDER_V << LCDCAM_CAM_BIT_ORDER_S) +#define LCDCAM_CAM_BIT_ORDER_V 0x00000001U +#define LCDCAM_CAM_BIT_ORDER_S 6 +/** LCDCAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0; + * 1: Enable to generate CAM_HS_INT. 0: Disable. + */ +#define LCDCAM_CAM_LINE_INT_EN (BIT(7)) +#define LCDCAM_CAM_LINE_INT_EN_M (LCDCAM_CAM_LINE_INT_EN_V << LCDCAM_CAM_LINE_INT_EN_S) +#define LCDCAM_CAM_LINE_INT_EN_V 0x00000001U +#define LCDCAM_CAM_LINE_INT_EN_S 7 +/** LCDCAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0; + * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by + * reg_cam_rec_data_cyclelen. + */ +#define LCDCAM_CAM_VS_EOF_EN (BIT(8)) +#define LCDCAM_CAM_VS_EOF_EN_M (LCDCAM_CAM_VS_EOF_EN_V << LCDCAM_CAM_VS_EOF_EN_S) +#define LCDCAM_CAM_VS_EOF_EN_V 0x00000001U +#define LCDCAM_CAM_VS_EOF_EN_S 8 +/** LCDCAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; + * Integral Camera clock divider value + */ +#define LCDCAM_CAM_CLKM_DIV_NUM 0x000000FFU +#define LCDCAM_CAM_CLKM_DIV_NUM_M (LCDCAM_CAM_CLKM_DIV_NUM_V << LCDCAM_CAM_CLKM_DIV_NUM_S) +#define LCDCAM_CAM_CLKM_DIV_NUM_V 0x000000FFU +#define LCDCAM_CAM_CLKM_DIV_NUM_S 9 +/** LCDCAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ +#define LCDCAM_CAM_CLKM_DIV_B 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_B_M (LCDCAM_CAM_CLKM_DIV_B_V << LCDCAM_CAM_CLKM_DIV_B_S) +#define LCDCAM_CAM_CLKM_DIV_B_V 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_B_S 17 +/** LCDCAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ +#define LCDCAM_CAM_CLKM_DIV_A 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_A_M (LCDCAM_CAM_CLKM_DIV_A_V << LCDCAM_CAM_CLKM_DIV_A_S) +#define LCDCAM_CAM_CLKM_DIV_A_V 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_A_S 23 +/** LCDCAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0; + * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ +#define LCDCAM_CAM_CLK_SEL 0x00000003U +#define LCDCAM_CAM_CLK_SEL_M (LCDCAM_CAM_CLK_SEL_V << LCDCAM_CAM_CLK_SEL_S) +#define LCDCAM_CAM_CLK_SEL_V 0x00000003U +#define LCDCAM_CAM_CLK_SEL_S 29 -#define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x8) -/* LCD_CAM_CAM_AFIFO_RESET : WT ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Camera AFIFO reset signal..*/ -#define LCD_CAM_CAM_AFIFO_RESET (BIT(31)) -#define LCD_CAM_CAM_AFIFO_RESET_M (BIT(31)) -#define LCD_CAM_CAM_AFIFO_RESET_V 0x1 -#define LCD_CAM_CAM_AFIFO_RESET_S 31 -/* LCD_CAM_CAM_RESET : WT ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Camera module reset signal..*/ -#define LCD_CAM_CAM_RESET (BIT(30)) -#define LCD_CAM_CAM_RESET_M (BIT(30)) -#define LCD_CAM_CAM_RESET_V 0x1 -#define LCD_CAM_CAM_RESET_S 30 -/* LCD_CAM_CAM_START : R/W/SC ;bitpos:[29] ;default: 1'h0 ; */ -/*description: Camera module start signal..*/ -#define LCD_CAM_CAM_START (BIT(29)) -#define LCD_CAM_CAM_START_M (BIT(29)) -#define LCD_CAM_CAM_START_V 0x1 -#define LCD_CAM_CAM_START_S 29 -/* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ -/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control si -gnals are CAM_DE and CAM_VSYNC..*/ -#define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28)) -#define LCD_CAM_CAM_VH_DE_MODE_EN_M (BIT(28)) -#define LCD_CAM_CAM_VH_DE_MODE_EN_V 0x1 -#define LCD_CAM_CAM_VH_DE_MODE_EN_S 28 -/* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */ -/*description: CAM_VSYNC invert enable signal, valid in high level..*/ -#define LCD_CAM_CAM_VSYNC_INV (BIT(27)) -#define LCD_CAM_CAM_VSYNC_INV_M (BIT(27)) -#define LCD_CAM_CAM_VSYNC_INV_V 0x1 -#define LCD_CAM_CAM_VSYNC_INV_S 27 -/* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: CAM_HSYNC invert enable signal, valid in high level..*/ -#define LCD_CAM_CAM_HSYNC_INV (BIT(26)) -#define LCD_CAM_CAM_HSYNC_INV_M (BIT(26)) -#define LCD_CAM_CAM_HSYNC_INV_V 0x1 -#define LCD_CAM_CAM_HSYNC_INV_S 26 -/* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: CAM_DE invert enable signal, valid in high level..*/ -#define LCD_CAM_CAM_DE_INV (BIT(25)) -#define LCD_CAM_CAM_DE_INV_M (BIT(25)) -#define LCD_CAM_CAM_DE_INV_V 0x1 -#define LCD_CAM_CAM_DE_INV_S 25 -/* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8 -..*/ -#define LCD_CAM_CAM_2BYTE_EN (BIT(24)) -#define LCD_CAM_CAM_2BYTE_EN_M (BIT(24)) -#define LCD_CAM_CAM_2BYTE_EN_V 0x1 -#define LCD_CAM_CAM_2BYTE_EN_S 24 -/* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: 1: Enable CAM_VSYNC filter function. 0: bypass..*/ -#define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23)) -#define LCD_CAM_CAM_VSYNC_FILTER_EN_M (BIT(23)) -#define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x1 -#define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23 -/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: 1: Invert the input signal CAM_PCLK. 0: Not invert..*/ -#define LCD_CAM_CAM_CLK_INV (BIT(22)) -#define LCD_CAM_CAM_CLK_INV_M (BIT(22)) -#define LCD_CAM_CAM_CLK_INV_V 0x1 -#define LCD_CAM_CAM_CLK_INV_S 22 -/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[21:16] ;default: 6'h0 ; */ -/*description: The line number minus 1 to generate cam_hs_int..*/ -#define LCD_CAM_CAM_LINE_INT_NUM 0x0000003F -#define LCD_CAM_CAM_LINE_INT_NUM_M ((LCD_CAM_CAM_LINE_INT_NUM_V)<<(LCD_CAM_CAM_LINE_INT_NUM_S)) -#define LCD_CAM_CAM_LINE_INT_NUM_V 0x3F -#define LCD_CAM_CAM_LINE_INT_NUM_S 16 -/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int..*/ -#define LCD_CAM_CAM_REC_DATA_BYTELEN 0x0000FFFF -#define LCD_CAM_CAM_REC_DATA_BYTELEN_M ((LCD_CAM_CAM_REC_DATA_BYTELEN_V)<<(LCD_CAM_CAM_REC_DATA_BYTELEN_S)) -#define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0xFFFF -#define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0 +/** LCDCAM_CAM_CTRL1_REG register + * CAM config register. + */ +#define LCDCAM_CAM_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x8) +/** LCDCAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0; + * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + */ +#define LCDCAM_CAM_REC_DATA_BYTELEN 0x0000FFFFU +#define LCDCAM_CAM_REC_DATA_BYTELEN_M (LCDCAM_CAM_REC_DATA_BYTELEN_V << LCDCAM_CAM_REC_DATA_BYTELEN_S) +#define LCDCAM_CAM_REC_DATA_BYTELEN_V 0x0000FFFFU +#define LCDCAM_CAM_REC_DATA_BYTELEN_S 0 +/** LCDCAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0; + * The line number minus 1 to generate cam_hs_int. + */ +#define LCDCAM_CAM_LINE_INT_NUM 0x0000003FU +#define LCDCAM_CAM_LINE_INT_NUM_M (LCDCAM_CAM_LINE_INT_NUM_V << LCDCAM_CAM_LINE_INT_NUM_S) +#define LCDCAM_CAM_LINE_INT_NUM_V 0x0000003FU +#define LCDCAM_CAM_LINE_INT_NUM_S 16 +/** LCDCAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0; + * 1: Invert the input signal CAM_PCLK. 0: Not invert. + */ +#define LCDCAM_CAM_CLK_INV (BIT(22)) +#define LCDCAM_CAM_CLK_INV_M (LCDCAM_CAM_CLK_INV_V << LCDCAM_CAM_CLK_INV_S) +#define LCDCAM_CAM_CLK_INV_V 0x00000001U +#define LCDCAM_CAM_CLK_INV_S 22 +/** LCDCAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0; + * 1: Enable CAM_VSYNC filter function. 0: bypass. + */ +#define LCDCAM_CAM_VSYNC_FILTER_EN (BIT(23)) +#define LCDCAM_CAM_VSYNC_FILTER_EN_M (LCDCAM_CAM_VSYNC_FILTER_EN_V << LCDCAM_CAM_VSYNC_FILTER_EN_S) +#define LCDCAM_CAM_VSYNC_FILTER_EN_V 0x00000001U +#define LCDCAM_CAM_VSYNC_FILTER_EN_S 23 +/** LCDCAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0; + * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + */ +#define LCDCAM_CAM_2BYTE_EN (BIT(24)) +#define LCDCAM_CAM_2BYTE_EN_M (LCDCAM_CAM_2BYTE_EN_V << LCDCAM_CAM_2BYTE_EN_S) +#define LCDCAM_CAM_2BYTE_EN_V 0x00000001U +#define LCDCAM_CAM_2BYTE_EN_S 24 +/** LCDCAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0; + * CAM_DE invert enable signal, valid in high level. + */ +#define LCDCAM_CAM_DE_INV (BIT(25)) +#define LCDCAM_CAM_DE_INV_M (LCDCAM_CAM_DE_INV_V << LCDCAM_CAM_DE_INV_S) +#define LCDCAM_CAM_DE_INV_V 0x00000001U +#define LCDCAM_CAM_DE_INV_S 25 +/** LCDCAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0; + * CAM_HSYNC invert enable signal, valid in high level. + */ +#define LCDCAM_CAM_HSYNC_INV (BIT(26)) +#define LCDCAM_CAM_HSYNC_INV_M (LCDCAM_CAM_HSYNC_INV_V << LCDCAM_CAM_HSYNC_INV_S) +#define LCDCAM_CAM_HSYNC_INV_V 0x00000001U +#define LCDCAM_CAM_HSYNC_INV_S 26 +/** LCDCAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0; + * CAM_VSYNC invert enable signal, valid in high level. + */ +#define LCDCAM_CAM_VSYNC_INV (BIT(27)) +#define LCDCAM_CAM_VSYNC_INV_M (LCDCAM_CAM_VSYNC_INV_V << LCDCAM_CAM_VSYNC_INV_S) +#define LCDCAM_CAM_VSYNC_INV_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INV_S 27 +/** LCDCAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0; + * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control + * signals are CAM_DE and CAM_VSYNC. + */ +#define LCDCAM_CAM_VH_DE_MODE_EN (BIT(28)) +#define LCDCAM_CAM_VH_DE_MODE_EN_M (LCDCAM_CAM_VH_DE_MODE_EN_V << LCDCAM_CAM_VH_DE_MODE_EN_S) +#define LCDCAM_CAM_VH_DE_MODE_EN_V 0x00000001U +#define LCDCAM_CAM_VH_DE_MODE_EN_S 28 +/** LCDCAM_CAM_START : R/W/SC; bitpos: [29]; default: 0; + * Camera module start signal. + */ +#define LCDCAM_CAM_START (BIT(29)) +#define LCDCAM_CAM_START_M (LCDCAM_CAM_START_V << LCDCAM_CAM_START_S) +#define LCDCAM_CAM_START_V 0x00000001U +#define LCDCAM_CAM_START_S 29 +/** LCDCAM_CAM_RESET : WT; bitpos: [30]; default: 0; + * Camera module reset signal. + */ +#define LCDCAM_CAM_RESET (BIT(30)) +#define LCDCAM_CAM_RESET_M (LCDCAM_CAM_RESET_V << LCDCAM_CAM_RESET_S) +#define LCDCAM_CAM_RESET_V 0x00000001U +#define LCDCAM_CAM_RESET_S 30 +/** LCDCAM_CAM_AFIFO_RESET : WT; bitpos: [31]; default: 0; + * Camera AFIFO reset signal. + */ +#define LCDCAM_CAM_AFIFO_RESET (BIT(31)) +#define LCDCAM_CAM_AFIFO_RESET_M (LCDCAM_CAM_AFIFO_RESET_V << LCDCAM_CAM_AFIFO_RESET_S) +#define LCDCAM_CAM_AFIFO_RESET_V 0x00000001U +#define LCDCAM_CAM_AFIFO_RESET_S 31 -#define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0xC) -/* LCD_CAM_CAM_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Bypass converter. 1: Enable converter..*/ -#define LCD_CAM_CAM_CONV_ENABLE (BIT(31)) -#define LCD_CAM_CAM_CONV_ENABLE_M (BIT(31)) -#define LCD_CAM_CAM_CONV_ENABLE_V 0x1 -#define LCD_CAM_CAM_CONV_ENABLE_S 31 -/* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: YUV to RGB. 1: RGB to YUV..*/ -#define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30)) -#define LCD_CAM_CAM_CONV_TRANS_MODE_M (BIT(30)) -#define LCD_CAM_CAM_CONV_TRANS_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_TRANS_MODE_S 30 -/* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 0: 16bits mode. 1: 8bits mode..*/ -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (BIT(29)) -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x1 -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29 -/* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/ -#define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28)) -#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (BIT(28)) -#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28 -/* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/ -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (BIT(27)) -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27 -/* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 0:BT601. 1:BT709..*/ -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (BIT(26)) -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26 -/* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ -/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv -mode of Data_in.*/ -#define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003 -#define LCD_CAM_CAM_CONV_YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV_MODE_S)) -#define LCD_CAM_CAM_CONV_YUV_MODE_V 0x3 -#define LCD_CAM_CAM_CONV_YUV_MODE_S 24 -/* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */ -/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, -trans_mode must be set to 1..*/ -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003 -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV2YUV_MODE_S)) -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x3 -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22 -/* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 1:invert every two 8bits input data. 2. disabled..*/ -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (BIT(21)) -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x1 -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21 +/** LCDCAM_CAM_RGB_YUV_REG register + * CAM YUV/RGB converter configuration register. + */ +#define LCDCAM_CAM_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0xc) +/** LCDCAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ +#define LCDCAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) +#define LCDCAM_CAM_CONV_8BITS_DATA_INV_M (LCDCAM_CAM_CONV_8BITS_DATA_INV_V << LCDCAM_CAM_CONV_8BITS_DATA_INV_S) +#define LCDCAM_CAM_CONV_8BITS_DATA_INV_V 0x00000001U +#define LCDCAM_CAM_CONV_8BITS_DATA_INV_S 21 +/** LCDCAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ +#define LCDCAM_CAM_CONV_YUV2YUV_MODE 0x00000003U +#define LCDCAM_CAM_CONV_YUV2YUV_MODE_M (LCDCAM_CAM_CONV_YUV2YUV_MODE_V << LCDCAM_CAM_CONV_YUV2YUV_MODE_S) +#define LCDCAM_CAM_CONV_YUV2YUV_MODE_V 0x00000003U +#define LCDCAM_CAM_CONV_YUV2YUV_MODE_S 22 +/** LCDCAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ +#define LCDCAM_CAM_CONV_YUV_MODE 0x00000003U +#define LCDCAM_CAM_CONV_YUV_MODE_M (LCDCAM_CAM_CONV_YUV_MODE_V << LCDCAM_CAM_CONV_YUV_MODE_S) +#define LCDCAM_CAM_CONV_YUV_MODE_V 0x00000003U +#define LCDCAM_CAM_CONV_YUV_MODE_S 24 +/** LCDCAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ +#define LCDCAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) +#define LCDCAM_CAM_CONV_PROTOCOL_MODE_M (LCDCAM_CAM_CONV_PROTOCOL_MODE_V << LCDCAM_CAM_CONV_PROTOCOL_MODE_S) +#define LCDCAM_CAM_CONV_PROTOCOL_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_PROTOCOL_MODE_S 26 +/** LCDCAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ +#define LCDCAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) +#define LCDCAM_CAM_CONV_DATA_OUT_MODE_M (LCDCAM_CAM_CONV_DATA_OUT_MODE_V << LCDCAM_CAM_CONV_DATA_OUT_MODE_S) +#define LCDCAM_CAM_CONV_DATA_OUT_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_DATA_OUT_MODE_S 27 +/** LCDCAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ +#define LCDCAM_CAM_CONV_DATA_IN_MODE (BIT(28)) +#define LCDCAM_CAM_CONV_DATA_IN_MODE_M (LCDCAM_CAM_CONV_DATA_IN_MODE_V << LCDCAM_CAM_CONV_DATA_IN_MODE_S) +#define LCDCAM_CAM_CONV_DATA_IN_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_DATA_IN_MODE_S 28 +/** LCDCAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ +#define LCDCAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) +#define LCDCAM_CAM_CONV_MODE_8BITS_ON_M (LCDCAM_CAM_CONV_MODE_8BITS_ON_V << LCDCAM_CAM_CONV_MODE_8BITS_ON_S) +#define LCDCAM_CAM_CONV_MODE_8BITS_ON_V 0x00000001U +#define LCDCAM_CAM_CONV_MODE_8BITS_ON_S 29 +/** LCDCAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ +#define LCDCAM_CAM_CONV_TRANS_MODE (BIT(30)) +#define LCDCAM_CAM_CONV_TRANS_MODE_M (LCDCAM_CAM_CONV_TRANS_MODE_V << LCDCAM_CAM_CONV_TRANS_MODE_S) +#define LCDCAM_CAM_CONV_TRANS_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_TRANS_MODE_S 30 +/** LCDCAM_CAM_CONV_ENABLE : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ +#define LCDCAM_CAM_CONV_ENABLE (BIT(31)) +#define LCDCAM_CAM_CONV_ENABLE_M (LCDCAM_CAM_CONV_ENABLE_V << LCDCAM_CAM_CONV_ENABLE_S) +#define LCDCAM_CAM_CONV_ENABLE_V 0x00000001U +#define LCDCAM_CAM_CONV_ENABLE_S 31 -#define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x10) -/* LCD_CAM_LCD_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Bypass converter. 1: Enable converter..*/ -#define LCD_CAM_LCD_CONV_ENABLE (BIT(31)) -#define LCD_CAM_LCD_CONV_ENABLE_M (BIT(31)) -#define LCD_CAM_LCD_CONV_ENABLE_V 0x1 -#define LCD_CAM_LCD_CONV_ENABLE_S 31 -/* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: YUV to RGB. 1: RGB to YUV..*/ -#define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30)) -#define LCD_CAM_LCD_CONV_TRANS_MODE_M (BIT(30)) -#define LCD_CAM_LCD_CONV_TRANS_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_TRANS_MODE_S 30 -/* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 0: 16bits mode. 1: 8bits mode..*/ -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (BIT(29)) -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x1 -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29 -/* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/ -#define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28)) -#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (BIT(28)) -#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28 -/* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/ -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (BIT(27)) -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27 -/* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 0:BT601. 1:BT709..*/ -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (BIT(26)) -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26 -/* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ -/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv -mode of Data_in.*/ -#define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003 -#define LCD_CAM_LCD_CONV_YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV_MODE_S)) -#define LCD_CAM_LCD_CONV_YUV_MODE_V 0x3 -#define LCD_CAM_LCD_CONV_YUV_MODE_S 24 -/* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */ -/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, -trans_mode must be set to 1..*/ -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003 -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV2YUV_MODE_S)) -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x3 -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22 -/* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 0: txtorx mode off. 1: txtorx mode on..*/ -#define LCD_CAM_LCD_CONV_TXTORX (BIT(21)) -#define LCD_CAM_LCD_CONV_TXTORX_M (BIT(21)) -#define LCD_CAM_LCD_CONV_TXTORX_V 0x1 -#define LCD_CAM_LCD_CONV_TXTORX_S 21 -/* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: 1:invert every two 8bits input data. 2. disabled..*/ -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (BIT(20)) -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V 0x1 -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S 20 +/** LCDCAM_LCD_RGB_YUV_REG register + * LCD YUV/RGB converter configuration register. + */ +#define LCDCAM_LCD_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0x10) +/** LCDCAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ +#define LCDCAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) +#define LCDCAM_LCD_CONV_8BITS_DATA_INV_M (LCDCAM_LCD_CONV_8BITS_DATA_INV_V << LCDCAM_LCD_CONV_8BITS_DATA_INV_S) +#define LCDCAM_LCD_CONV_8BITS_DATA_INV_V 0x00000001U +#define LCDCAM_LCD_CONV_8BITS_DATA_INV_S 20 +/** LCDCAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0; + * 0: txtorx mode off. 1: txtorx mode on. + */ +#define LCDCAM_LCD_CONV_TXTORX (BIT(21)) +#define LCDCAM_LCD_CONV_TXTORX_M (LCDCAM_LCD_CONV_TXTORX_V << LCDCAM_LCD_CONV_TXTORX_S) +#define LCDCAM_LCD_CONV_TXTORX_V 0x00000001U +#define LCDCAM_LCD_CONV_TXTORX_S 21 +/** LCDCAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ +#define LCDCAM_LCD_CONV_YUV2YUV_MODE 0x00000003U +#define LCDCAM_LCD_CONV_YUV2YUV_MODE_M (LCDCAM_LCD_CONV_YUV2YUV_MODE_V << LCDCAM_LCD_CONV_YUV2YUV_MODE_S) +#define LCDCAM_LCD_CONV_YUV2YUV_MODE_V 0x00000003U +#define LCDCAM_LCD_CONV_YUV2YUV_MODE_S 22 +/** LCDCAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ +#define LCDCAM_LCD_CONV_YUV_MODE 0x00000003U +#define LCDCAM_LCD_CONV_YUV_MODE_M (LCDCAM_LCD_CONV_YUV_MODE_V << LCDCAM_LCD_CONV_YUV_MODE_S) +#define LCDCAM_LCD_CONV_YUV_MODE_V 0x00000003U +#define LCDCAM_LCD_CONV_YUV_MODE_S 24 +/** LCDCAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ +#define LCDCAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) +#define LCDCAM_LCD_CONV_PROTOCOL_MODE_M (LCDCAM_LCD_CONV_PROTOCOL_MODE_V << LCDCAM_LCD_CONV_PROTOCOL_MODE_S) +#define LCDCAM_LCD_CONV_PROTOCOL_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_PROTOCOL_MODE_S 26 +/** LCDCAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ +#define LCDCAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) +#define LCDCAM_LCD_CONV_DATA_OUT_MODE_M (LCDCAM_LCD_CONV_DATA_OUT_MODE_V << LCDCAM_LCD_CONV_DATA_OUT_MODE_S) +#define LCDCAM_LCD_CONV_DATA_OUT_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_DATA_OUT_MODE_S 27 +/** LCDCAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ +#define LCDCAM_LCD_CONV_DATA_IN_MODE (BIT(28)) +#define LCDCAM_LCD_CONV_DATA_IN_MODE_M (LCDCAM_LCD_CONV_DATA_IN_MODE_V << LCDCAM_LCD_CONV_DATA_IN_MODE_S) +#define LCDCAM_LCD_CONV_DATA_IN_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_DATA_IN_MODE_S 28 +/** LCDCAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ +#define LCDCAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) +#define LCDCAM_LCD_CONV_MODE_8BITS_ON_M (LCDCAM_LCD_CONV_MODE_8BITS_ON_V << LCDCAM_LCD_CONV_MODE_8BITS_ON_S) +#define LCDCAM_LCD_CONV_MODE_8BITS_ON_V 0x00000001U +#define LCDCAM_LCD_CONV_MODE_8BITS_ON_S 29 +/** LCDCAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ +#define LCDCAM_LCD_CONV_TRANS_MODE (BIT(30)) +#define LCDCAM_LCD_CONV_TRANS_MODE_M (LCDCAM_LCD_CONV_TRANS_MODE_V << LCDCAM_LCD_CONV_TRANS_MODE_S) +#define LCDCAM_LCD_CONV_TRANS_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_TRANS_MODE_S 30 +/** LCDCAM_LCD_CONV_ENABLE : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ +#define LCDCAM_LCD_CONV_ENABLE (BIT(31)) +#define LCDCAM_LCD_CONV_ENABLE_M (LCDCAM_LCD_CONV_ENABLE_V << LCDCAM_LCD_CONV_ENABLE_S) +#define LCDCAM_LCD_CONV_ENABLE_V 0x00000001U +#define LCDCAM_LCD_CONV_ENABLE_S 31 -#define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x14) -/* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: The cycle length of command phase. 1: 2 cycles. 0: 1 cycle..*/ -#define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31)) -#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (BIT(31)) -#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V 0x1 -#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31 -/* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ -/*description: The dummy cycle length minus 1..*/ -#define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003 -#define LCD_CAM_LCD_DUMMY_CYCLELEN_M ((LCD_CAM_LCD_DUMMY_CYCLELEN_V)<<(LCD_CAM_LCD_DUMMY_CYCLELEN_S)) -#define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x3 -#define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29 -/* LCD_CAM_LCD_RESET : WT ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The value of command..*/ -#define LCD_CAM_LCD_RESET (BIT(28)) -#define LCD_CAM_LCD_RESET_M (BIT(28)) -#define LCD_CAM_LCD_RESET_V 0x1 -#define LCD_CAM_LCD_RESET_S 28 -/* LCD_CAM_LCD_START : R/W/SC ;bitpos:[27] ;default: 1'h0 ; */ -/*description: LCD start sending data enable signal, valid in high level..*/ -#define LCD_CAM_LCD_START (BIT(27)) -#define LCD_CAM_LCD_START_M (BIT(27)) -#define LCD_CAM_LCD_START_V 0x1 -#define LCD_CAM_LCD_START_S 27 -/* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable..*/ -#define LCD_CAM_LCD_CMD (BIT(26)) -#define LCD_CAM_LCD_CMD_M (BIT(26)) -#define LCD_CAM_LCD_CMD_V 0x1 -#define LCD_CAM_LCD_CMD_S 26 -/* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable..*/ -#define LCD_CAM_LCD_DUMMY (BIT(25)) -#define LCD_CAM_LCD_DUMMY_M (BIT(25)) -#define LCD_CAM_LCD_DUMMY_V 0x1 -#define LCD_CAM_LCD_DUMMY_S 25 -/* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable..*/ -#define LCD_CAM_LCD_DOUT (BIT(24)) -#define LCD_CAM_LCD_DOUT_M (BIT(24)) -#define LCD_CAM_LCD_DOUT_V 0x1 -#define LCD_CAM_LCD_DOUT_S 24 -/* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/ -#define LCD_CAM_LCD_BYTE_ORDER (BIT(23)) -#define LCD_CAM_LCD_BYTE_ORDER_M (BIT(23)) -#define LCD_CAM_LCD_BYTE_ORDER_V 0x1 -#define LCD_CAM_LCD_BYTE_ORDER_S 23 -/* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one b -yte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change..*/ -#define LCD_CAM_LCD_BIT_ORDER (BIT(22)) -#define LCD_CAM_LCD_BIT_ORDER_M (BIT(22)) -#define LCD_CAM_LCD_BIT_ORDER_V 0x1 -#define LCD_CAM_LCD_BIT_ORDER_S 22 -/* LCD_CAM_LCD_UPDATE_REG : R/W/SC ;bitpos:[21] ;default: 1'h0 ; */ -/*description: 1: Update LCD registers, will be cleared by hardware. 0 : Not care..*/ -#define LCD_CAM_LCD_UPDATE_REG (BIT(21)) -#define LCD_CAM_LCD_UPDATE_REG_M (BIT(21)) -#define LCD_CAM_LCD_UPDATE_REG_V 0x1 -#define LCD_CAM_LCD_UPDATE_REG_S 21 -/* LCD_CAM_LCD_BYTE_MODE : R/W ;bitpos:[20:19] ;default: 2'h0 ; */ -/*description: 2: 24bit mode. 1: 16bit mode. 0: 8bit mode.*/ -#define LCD_CAM_LCD_BYTE_MODE 0x00000003 -#define LCD_CAM_LCD_BYTE_MODE_M ((LCD_CAM_LCD_BYTE_MODE_V)<<(LCD_CAM_LCD_BYTE_MODE_S)) -#define LCD_CAM_LCD_BYTE_MODE_V 0x3 -#define LCD_CAM_LCD_BYTE_MODE_S 19 -/* LCD_CAM_LCD_DOUT_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: 1: change bit order in every byte. 0: Not change..*/ -#define LCD_CAM_LCD_DOUT_BIT_ORDER (BIT(18)) -#define LCD_CAM_LCD_DOUT_BIT_ORDER_M (BIT(18)) -#define LCD_CAM_LCD_DOUT_BIT_ORDER_V 0x1 -#define LCD_CAM_LCD_DOUT_BIT_ORDER_S 18 -/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: 1: enable byte swizzle 0: disable.*/ -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE (BIT(17)) -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M (BIT(17)) -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V 0x1 -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S 17 -/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W ;bitpos:[16:14] ;default: 3'h0 ; */ -/*description: 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA.*/ -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE 0x00000007 -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M ((LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V)<<(LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S)) -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V 0x7 -#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S 14 -/* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */ -/*description: LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared - or reg_lcd_reset is set..*/ -#define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13)) -#define LCD_CAM_LCD_ALWAYS_OUT_EN_M (BIT(13)) -#define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x1 -#define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13 -/* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */ -/*description: The output data cycles minus 1 of LCD module..*/ -#define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFF -#define LCD_CAM_LCD_DOUT_CYCLELEN_M ((LCD_CAM_LCD_DOUT_CYCLELEN_V)<<(LCD_CAM_LCD_DOUT_CYCLELEN_S)) -#define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x1FFF -#define LCD_CAM_LCD_DOUT_CYCLELEN_S 0 +/** LCDCAM_LCD_USER_REG register + * LCD config register. + */ +#define LCDCAM_LCD_USER_REG (DR_REG_LCDCAM_BASE + 0x14) +/** LCDCAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1; + * The output data cycles minus 1 of LCD module. + */ +#define LCDCAM_LCD_DOUT_CYCLELEN 0x00001FFFU +#define LCDCAM_LCD_DOUT_CYCLELEN_M (LCDCAM_LCD_DOUT_CYCLELEN_V << LCDCAM_LCD_DOUT_CYCLELEN_S) +#define LCDCAM_LCD_DOUT_CYCLELEN_V 0x00001FFFU +#define LCDCAM_LCD_DOUT_CYCLELEN_S 0 +/** LCDCAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0; + * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or + * reg_lcd_reset is set. + */ +#define LCDCAM_LCD_ALWAYS_OUT_EN (BIT(13)) +#define LCDCAM_LCD_ALWAYS_OUT_EN_M (LCDCAM_LCD_ALWAYS_OUT_EN_V << LCDCAM_LCD_ALWAYS_OUT_EN_S) +#define LCDCAM_LCD_ALWAYS_OUT_EN_V 0x00000001U +#define LCDCAM_LCD_ALWAYS_OUT_EN_S 13 +/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W; bitpos: [16:14]; default: 0; + * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + */ +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE 0x00000007U +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S) +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V 0x00000007U +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S 14 +/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W; bitpos: [17]; default: 0; + * 1: enable byte swizzle 0: disable + */ +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE (BIT(17)) +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S) +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V 0x00000001U +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S 17 +/** LCDCAM_LCD_DOUT_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * 1: change bit order in every byte. 0: Not change. + */ +#define LCDCAM_LCD_DOUT_BIT_ORDER (BIT(18)) +#define LCDCAM_LCD_DOUT_BIT_ORDER_M (LCDCAM_LCD_DOUT_BIT_ORDER_V << LCDCAM_LCD_DOUT_BIT_ORDER_S) +#define LCDCAM_LCD_DOUT_BIT_ORDER_V 0x00000001U +#define LCDCAM_LCD_DOUT_BIT_ORDER_S 18 +/** LCDCAM_LCD_BYTE_MODE : R/W; bitpos: [20:19]; default: 0; + * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + */ +#define LCDCAM_LCD_BYTE_MODE 0x00000003U +#define LCDCAM_LCD_BYTE_MODE_M (LCDCAM_LCD_BYTE_MODE_V << LCDCAM_LCD_BYTE_MODE_S) +#define LCDCAM_LCD_BYTE_MODE_V 0x00000003U +#define LCDCAM_LCD_BYTE_MODE_S 19 +/** LCDCAM_LCD_UPDATE_REG : R/W/SC; bitpos: [21]; default: 0; + * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + */ +#define LCDCAM_LCD_UPDATE_REG (BIT(21)) +#define LCDCAM_LCD_UPDATE_REG_M (LCDCAM_LCD_UPDATE_REG_V << LCDCAM_LCD_UPDATE_REG_S) +#define LCDCAM_LCD_UPDATE_REG_V 0x00000001U +#define LCDCAM_LCD_UPDATE_REG_S 21 +/** LCDCAM_LCD_BIT_ORDER : R/W; bitpos: [22]; default: 0; + * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ +#define LCDCAM_LCD_BIT_ORDER (BIT(22)) +#define LCDCAM_LCD_BIT_ORDER_M (LCDCAM_LCD_BIT_ORDER_V << LCDCAM_LCD_BIT_ORDER_S) +#define LCDCAM_LCD_BIT_ORDER_V 0x00000001U +#define LCDCAM_LCD_BIT_ORDER_S 22 +/** LCDCAM_LCD_BYTE_ORDER : R/W; bitpos: [23]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ +#define LCDCAM_LCD_BYTE_ORDER (BIT(23)) +#define LCDCAM_LCD_BYTE_ORDER_M (LCDCAM_LCD_BYTE_ORDER_V << LCDCAM_LCD_BYTE_ORDER_S) +#define LCDCAM_LCD_BYTE_ORDER_V 0x00000001U +#define LCDCAM_LCD_BYTE_ORDER_S 23 +/** LCDCAM_LCD_DOUT : R/W; bitpos: [24]; default: 0; + * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + */ +#define LCDCAM_LCD_DOUT (BIT(24)) +#define LCDCAM_LCD_DOUT_M (LCDCAM_LCD_DOUT_V << LCDCAM_LCD_DOUT_S) +#define LCDCAM_LCD_DOUT_V 0x00000001U +#define LCDCAM_LCD_DOUT_S 24 +/** LCDCAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0; + * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + */ +#define LCDCAM_LCD_DUMMY (BIT(25)) +#define LCDCAM_LCD_DUMMY_M (LCDCAM_LCD_DUMMY_V << LCDCAM_LCD_DUMMY_S) +#define LCDCAM_LCD_DUMMY_V 0x00000001U +#define LCDCAM_LCD_DUMMY_S 25 +/** LCDCAM_LCD_CMD : R/W; bitpos: [26]; default: 0; + * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + */ +#define LCDCAM_LCD_CMD (BIT(26)) +#define LCDCAM_LCD_CMD_M (LCDCAM_LCD_CMD_V << LCDCAM_LCD_CMD_S) +#define LCDCAM_LCD_CMD_V 0x00000001U +#define LCDCAM_LCD_CMD_S 26 +/** LCDCAM_LCD_START : R/W/SC; bitpos: [27]; default: 0; + * LCD start sending data enable signal, valid in high level. + */ +#define LCDCAM_LCD_START (BIT(27)) +#define LCDCAM_LCD_START_M (LCDCAM_LCD_START_V << LCDCAM_LCD_START_S) +#define LCDCAM_LCD_START_V 0x00000001U +#define LCDCAM_LCD_START_S 27 +/** LCDCAM_LCD_RESET : WT; bitpos: [28]; default: 0; + * The value of command. + */ +#define LCDCAM_LCD_RESET (BIT(28)) +#define LCDCAM_LCD_RESET_M (LCDCAM_LCD_RESET_V << LCDCAM_LCD_RESET_S) +#define LCDCAM_LCD_RESET_V 0x00000001U +#define LCDCAM_LCD_RESET_S 28 +/** LCDCAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0; + * The dummy cycle length minus 1. + */ +#define LCDCAM_LCD_DUMMY_CYCLELEN 0x00000003U +#define LCDCAM_LCD_DUMMY_CYCLELEN_M (LCDCAM_LCD_DUMMY_CYCLELEN_V << LCDCAM_LCD_DUMMY_CYCLELEN_S) +#define LCDCAM_LCD_DUMMY_CYCLELEN_V 0x00000003U +#define LCDCAM_LCD_DUMMY_CYCLELEN_S 29 +/** LCDCAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0; + * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + */ +#define LCDCAM_LCD_CMD_2_CYCLE_EN (BIT(31)) +#define LCDCAM_LCD_CMD_2_CYCLE_EN_M (LCDCAM_LCD_CMD_2_CYCLE_EN_V << LCDCAM_LCD_CMD_2_CYCLE_EN_S) +#define LCDCAM_LCD_CMD_2_CYCLE_EN_V 0x00000001U +#define LCDCAM_LCD_CMD_2_CYCLE_EN_S 31 -#define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x18) -/* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: The default value of LCD_CD..*/ -#define LCD_CAM_LCD_CD_IDLE_EDGE (BIT(31)) -#define LCD_CAM_LCD_CD_IDLE_EDGE_M (BIT(31)) -#define LCD_CAM_LCD_CD_IDLE_EDGE_V 0x1 -#define LCD_CAM_LCD_CD_IDLE_EDGE_S 31 -/* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = - reg_cd_idle_edge..*/ -#define LCD_CAM_LCD_CD_CMD_SET (BIT(30)) -#define LCD_CAM_LCD_CD_CMD_SET_M (BIT(30)) -#define LCD_CAM_LCD_CD_CMD_SET_V 0x1 -#define LCD_CAM_LCD_CD_CMD_SET_S 30 -/* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */ -/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD - = reg_cd_idle_edge..*/ -#define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29)) -#define LCD_CAM_LCD_CD_DUMMY_SET_M (BIT(29)) -#define LCD_CAM_LCD_CD_DUMMY_SET_V 0x1 -#define LCD_CAM_LCD_CD_DUMMY_SET_S 29 -/* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD -= reg_cd_idle_edge..*/ -#define LCD_CAM_LCD_CD_DATA_SET (BIT(28)) -#define LCD_CAM_LCD_CD_DATA_SET_M (BIT(28)) -#define LCD_CAM_LCD_CD_DATA_SET_V 0x1 -#define LCD_CAM_LCD_CD_DATA_SET_S 28 -/* LCD_CAM_LCD_AFIFO_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */ -/*description: LCD AFIFO reset signal..*/ -#define LCD_CAM_LCD_AFIFO_RESET (BIT(27)) -#define LCD_CAM_LCD_AFIFO_RESET_M (BIT(27)) -#define LCD_CAM_LCD_AFIFO_RESET_V 0x1 -#define LCD_CAM_LCD_AFIFO_RESET_S 27 -/* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: Enable blank region when LCD sends data out. 0: No blank region..*/ -#define LCD_CAM_LCD_BK_EN (BIT(26)) -#define LCD_CAM_LCD_BK_EN_M (BIT(26)) -#define LCD_CAM_LCD_BK_EN_V 0x1 -#define LCD_CAM_LCD_BK_EN_S 26 -/* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: Send the next frame data when the current frame is sent out. 0: LCD stops whe -n the current frame is sent out..*/ -#define LCD_CAM_LCD_NEXT_FRAME_EN (BIT(25)) -#define LCD_CAM_LCD_NEXT_FRAME_EN_M (BIT(25)) -#define LCD_CAM_LCD_NEXT_FRAME_EN_V 0x1 -#define LCD_CAM_LCD_NEXT_FRAME_EN_S 25 -/* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */ -/*description: The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold - time cycle length in LCD non-RGB mode..*/ -#define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFF -#define LCD_CAM_LCD_VBK_CYCLELEN_M ((LCD_CAM_LCD_VBK_CYCLELEN_V)<<(LCD_CAM_LCD_VBK_CYCLELEN_S)) -#define LCD_CAM_LCD_VBK_CYCLELEN_V 0x1FFF -#define LCD_CAM_LCD_VBK_CYCLELEN_S 12 -/* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */ -/*description: The setup cycle length minus 1 in LCD non-RGB mode..*/ -#define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003F -#define LCD_CAM_LCD_VFK_CYCLELEN_M ((LCD_CAM_LCD_VFK_CYCLELEN_V)<<(LCD_CAM_LCD_VFK_CYCLELEN_S)) -#define LCD_CAM_LCD_VFK_CYCLELEN_V 0x3F -#define LCD_CAM_LCD_VFK_CYCLELEN_S 6 -/* LCD_CAM_LCD_WIRE_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit.*/ -#define LCD_CAM_LCD_WIRE_MODE 0x00000003 -#define LCD_CAM_LCD_WIRE_MODE_M ((LCD_CAM_LCD_WIRE_MODE_V)<<(LCD_CAM_LCD_WIRE_MODE_S)) -#define LCD_CAM_LCD_WIRE_MODE_V 0x3 -#define LCD_CAM_LCD_WIRE_MODE_S 4 +/** LCDCAM_LCD_MISC_REG register + * LCD config register. + */ +#define LCDCAM_LCD_MISC_REG (DR_REG_LCDCAM_BASE + 0x18) +/** LCDCAM_LCD_WIRE_MODE : R/W; bitpos: [5:4]; default: 0; + * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + */ +#define LCDCAM_LCD_WIRE_MODE 0x00000003U +#define LCDCAM_LCD_WIRE_MODE_M (LCDCAM_LCD_WIRE_MODE_V << LCDCAM_LCD_WIRE_MODE_S) +#define LCDCAM_LCD_WIRE_MODE_V 0x00000003U +#define LCDCAM_LCD_WIRE_MODE_S 4 +/** LCDCAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3; + * The setup cycle length minus 1 in LCD non-RGB mode. + */ +#define LCDCAM_LCD_VFK_CYCLELEN 0x0000003FU +#define LCDCAM_LCD_VFK_CYCLELEN_M (LCDCAM_LCD_VFK_CYCLELEN_V << LCDCAM_LCD_VFK_CYCLELEN_S) +#define LCDCAM_LCD_VFK_CYCLELEN_V 0x0000003FU +#define LCDCAM_LCD_VFK_CYCLELEN_S 6 +/** LCDCAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0; + * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold + * time cycle length in LCD non-RGB mode. + */ +#define LCDCAM_LCD_VBK_CYCLELEN 0x00001FFFU +#define LCDCAM_LCD_VBK_CYCLELEN_M (LCDCAM_LCD_VBK_CYCLELEN_V << LCDCAM_LCD_VBK_CYCLELEN_S) +#define LCDCAM_LCD_VBK_CYCLELEN_V 0x00001FFFU +#define LCDCAM_LCD_VBK_CYCLELEN_S 12 +/** LCDCAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0; + * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when + * the current frame is sent out. + */ +#define LCDCAM_LCD_NEXT_FRAME_EN (BIT(25)) +#define LCDCAM_LCD_NEXT_FRAME_EN_M (LCDCAM_LCD_NEXT_FRAME_EN_V << LCDCAM_LCD_NEXT_FRAME_EN_S) +#define LCDCAM_LCD_NEXT_FRAME_EN_V 0x00000001U +#define LCDCAM_LCD_NEXT_FRAME_EN_S 25 +/** LCDCAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0; + * 1: Enable blank region when LCD sends data out. 0: No blank region. + */ +#define LCDCAM_LCD_BK_EN (BIT(26)) +#define LCDCAM_LCD_BK_EN_M (LCDCAM_LCD_BK_EN_V << LCDCAM_LCD_BK_EN_S) +#define LCDCAM_LCD_BK_EN_V 0x00000001U +#define LCDCAM_LCD_BK_EN_S 26 +/** LCDCAM_LCD_AFIFO_RESET : WT; bitpos: [27]; default: 0; + * LCD AFIFO reset signal. + */ +#define LCDCAM_LCD_AFIFO_RESET (BIT(27)) +#define LCDCAM_LCD_AFIFO_RESET_M (LCDCAM_LCD_AFIFO_RESET_V << LCDCAM_LCD_AFIFO_RESET_S) +#define LCDCAM_LCD_AFIFO_RESET_V 0x00000001U +#define LCDCAM_LCD_AFIFO_RESET_S 27 +/** LCDCAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = + * reg_cd_idle_edge. + */ +#define LCDCAM_LCD_CD_DATA_SET (BIT(28)) +#define LCDCAM_LCD_CD_DATA_SET_M (LCDCAM_LCD_CD_DATA_SET_V << LCDCAM_LCD_CD_DATA_SET_S) +#define LCDCAM_LCD_CD_DATA_SET_V 0x00000001U +#define LCDCAM_LCD_CD_DATA_SET_S 28 +/** LCDCAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = + * reg_cd_idle_edge. + */ +#define LCDCAM_LCD_CD_DUMMY_SET (BIT(29)) +#define LCDCAM_LCD_CD_DUMMY_SET_M (LCDCAM_LCD_CD_DUMMY_SET_V << LCDCAM_LCD_CD_DUMMY_SET_S) +#define LCDCAM_LCD_CD_DUMMY_SET_V 0x00000001U +#define LCDCAM_LCD_CD_DUMMY_SET_S 29 +/** LCDCAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = + * reg_cd_idle_edge. + */ +#define LCDCAM_LCD_CD_CMD_SET (BIT(30)) +#define LCDCAM_LCD_CD_CMD_SET_M (LCDCAM_LCD_CD_CMD_SET_V << LCDCAM_LCD_CD_CMD_SET_S) +#define LCDCAM_LCD_CD_CMD_SET_V 0x00000001U +#define LCDCAM_LCD_CD_CMD_SET_S 30 +/** LCDCAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0; + * The default value of LCD_CD. + */ +#define LCDCAM_LCD_CD_IDLE_EDGE (BIT(31)) +#define LCDCAM_LCD_CD_IDLE_EDGE_M (LCDCAM_LCD_CD_IDLE_EDGE_V << LCDCAM_LCD_CD_IDLE_EDGE_S) +#define LCDCAM_LCD_CD_IDLE_EDGE_V 0x00000001U +#define LCDCAM_LCD_CD_IDLE_EDGE_S 31 -#define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x1C) -/* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: Enable LCD RGB mode. 0: Disable LCD RGB mode..*/ -#define LCD_CAM_LCD_RGB_MODE_EN (BIT(31)) -#define LCD_CAM_LCD_RGB_MODE_EN_M (BIT(31)) -#define LCD_CAM_LCD_RGB_MODE_EN_V 0x1 -#define LCD_CAM_LCD_RGB_MODE_EN_S 31 -/* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */ -/*description: It is the vertical total height of a frame..*/ -#define LCD_CAM_LCD_VT_HEIGHT 0x000003FF -#define LCD_CAM_LCD_VT_HEIGHT_M ((LCD_CAM_LCD_VT_HEIGHT_V)<<(LCD_CAM_LCD_VT_HEIGHT_S)) -#define LCD_CAM_LCD_VT_HEIGHT_V 0x3FF -#define LCD_CAM_LCD_VT_HEIGHT_S 21 -/* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */ -/*description: It is the vertical active height of a frame..*/ -#define LCD_CAM_LCD_VA_HEIGHT 0x000003FF -#define LCD_CAM_LCD_VA_HEIGHT_M ((LCD_CAM_LCD_VA_HEIGHT_V)<<(LCD_CAM_LCD_VA_HEIGHT_S)) -#define LCD_CAM_LCD_VA_HEIGHT_V 0x3FF -#define LCD_CAM_LCD_VA_HEIGHT_S 11 -/* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */ -/*description: It is the horizontal blank front porch of a frame..*/ -#define LCD_CAM_LCD_HB_FRONT 0x000007FF -#define LCD_CAM_LCD_HB_FRONT_M ((LCD_CAM_LCD_HB_FRONT_V)<<(LCD_CAM_LCD_HB_FRONT_S)) -#define LCD_CAM_LCD_HB_FRONT_V 0x7FF -#define LCD_CAM_LCD_HB_FRONT_S 0 +/** LCDCAM_LCD_CTRL_REG register + * LCD config register. + */ +#define LCDCAM_LCD_CTRL_REG (DR_REG_LCDCAM_BASE + 0x1c) +/** LCDCAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. + */ +#define LCDCAM_LCD_HB_FRONT 0x000007FFU +#define LCDCAM_LCD_HB_FRONT_M (LCDCAM_LCD_HB_FRONT_V << LCDCAM_LCD_HB_FRONT_S) +#define LCDCAM_LCD_HB_FRONT_V 0x000007FFU +#define LCDCAM_LCD_HB_FRONT_S 0 +/** LCDCAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. + */ +#define LCDCAM_LCD_VA_HEIGHT 0x000003FFU +#define LCDCAM_LCD_VA_HEIGHT_M (LCDCAM_LCD_VA_HEIGHT_V << LCDCAM_LCD_VA_HEIGHT_S) +#define LCDCAM_LCD_VA_HEIGHT_V 0x000003FFU +#define LCDCAM_LCD_VA_HEIGHT_S 11 +/** LCDCAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. + */ +#define LCDCAM_LCD_VT_HEIGHT 0x000003FFU +#define LCDCAM_LCD_VT_HEIGHT_M (LCDCAM_LCD_VT_HEIGHT_V << LCDCAM_LCD_VT_HEIGHT_S) +#define LCDCAM_LCD_VT_HEIGHT_V 0x000003FFU +#define LCDCAM_LCD_VT_HEIGHT_S 21 +/** LCDCAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + */ +#define LCDCAM_LCD_RGB_MODE_EN (BIT(31)) +#define LCDCAM_LCD_RGB_MODE_EN_M (LCDCAM_LCD_RGB_MODE_EN_V << LCDCAM_LCD_RGB_MODE_EN_S) +#define LCDCAM_LCD_RGB_MODE_EN_V 0x00000001U +#define LCDCAM_LCD_RGB_MODE_EN_S 31 -#define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x20) -/* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */ -/*description: It is the horizontal total width of a frame..*/ -#define LCD_CAM_LCD_HT_WIDTH 0x00000FFF -#define LCD_CAM_LCD_HT_WIDTH_M ((LCD_CAM_LCD_HT_WIDTH_V)<<(LCD_CAM_LCD_HT_WIDTH_S)) -#define LCD_CAM_LCD_HT_WIDTH_V 0xFFF -#define LCD_CAM_LCD_HT_WIDTH_S 20 -/* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */ -/*description: It is the horizontal active width of a frame..*/ -#define LCD_CAM_LCD_HA_WIDTH 0x00000FFF -#define LCD_CAM_LCD_HA_WIDTH_M ((LCD_CAM_LCD_HA_WIDTH_V)<<(LCD_CAM_LCD_HA_WIDTH_S)) -#define LCD_CAM_LCD_HA_WIDTH_V 0xFFF -#define LCD_CAM_LCD_HA_WIDTH_S 8 -/* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ -/*description: It is the vertical blank front porch of a frame..*/ -#define LCD_CAM_LCD_VB_FRONT 0x000000FF -#define LCD_CAM_LCD_VB_FRONT_M ((LCD_CAM_LCD_VB_FRONT_V)<<(LCD_CAM_LCD_VB_FRONT_S)) -#define LCD_CAM_LCD_VB_FRONT_V 0xFF -#define LCD_CAM_LCD_VB_FRONT_S 0 +/** LCDCAM_LCD_CTRL1_REG register + * LCD config register. + */ +#define LCDCAM_LCD_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x20) +/** LCDCAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. + */ +#define LCDCAM_LCD_VB_FRONT 0x000000FFU +#define LCDCAM_LCD_VB_FRONT_M (LCDCAM_LCD_VB_FRONT_V << LCDCAM_LCD_VB_FRONT_S) +#define LCDCAM_LCD_VB_FRONT_V 0x000000FFU +#define LCDCAM_LCD_VB_FRONT_S 0 +/** LCDCAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. + */ +#define LCDCAM_LCD_HA_WIDTH 0x00000FFFU +#define LCDCAM_LCD_HA_WIDTH_M (LCDCAM_LCD_HA_WIDTH_V << LCDCAM_LCD_HA_WIDTH_S) +#define LCDCAM_LCD_HA_WIDTH_V 0x00000FFFU +#define LCDCAM_LCD_HA_WIDTH_S 8 +/** LCDCAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. + */ +#define LCDCAM_LCD_HT_WIDTH 0x00000FFFU +#define LCDCAM_LCD_HT_WIDTH_M (LCDCAM_LCD_HT_WIDTH_V << LCDCAM_LCD_HT_WIDTH_S) +#define LCDCAM_LCD_HT_WIDTH_V 0x00000FFFU +#define LCDCAM_LCD_HT_WIDTH_S 20 -#define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x24) -/* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ -/*description: It is the position of LCD_HSYNC active pulse in a line..*/ -#define LCD_CAM_LCD_HSYNC_POSITION 0x000000FF -#define LCD_CAM_LCD_HSYNC_POSITION_M ((LCD_CAM_LCD_HSYNC_POSITION_V)<<(LCD_CAM_LCD_HSYNC_POSITION_S)) -#define LCD_CAM_LCD_HSYNC_POSITION_V 0xFF -#define LCD_CAM_LCD_HSYNC_POSITION_S 24 -/* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: It is the idle value of LCD_HSYNC..*/ -#define LCD_CAM_LCD_HSYNC_IDLE_POL (BIT(23)) -#define LCD_CAM_LCD_HSYNC_IDLE_POL_M (BIT(23)) -#define LCD_CAM_LCD_HSYNC_IDLE_POL_V 0x1 -#define LCD_CAM_LCD_HSYNC_IDLE_POL_S 23 -/* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */ -/*description: It is the position of LCD_HSYNC active pulse in a line..*/ -#define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007F -#define LCD_CAM_LCD_HSYNC_WIDTH_M ((LCD_CAM_LCD_HSYNC_WIDTH_V)<<(LCD_CAM_LCD_HSYNC_WIDTH_S)) -#define LCD_CAM_LCD_HSYNC_WIDTH_V 0x7F -#define LCD_CAM_LCD_HSYNC_WIDTH_S 16 -/* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSY -NC pulse is valid only in active region lines in RGB mode..*/ -#define LCD_CAM_LCD_HS_BLANK_EN (BIT(9)) -#define LCD_CAM_LCD_HS_BLANK_EN_M (BIT(9)) -#define LCD_CAM_LCD_HS_BLANK_EN_V 0x1 -#define LCD_CAM_LCD_HS_BLANK_EN_S 9 -/* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: It is the idle value of LCD_DE..*/ -#define LCD_CAM_LCD_DE_IDLE_POL (BIT(8)) -#define LCD_CAM_LCD_DE_IDLE_POL_M (BIT(8)) -#define LCD_CAM_LCD_DE_IDLE_POL_V 0x1 -#define LCD_CAM_LCD_DE_IDLE_POL_S 8 -/* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: It is the idle value of LCD_VSYNC..*/ -#define LCD_CAM_LCD_VSYNC_IDLE_POL (BIT(7)) -#define LCD_CAM_LCD_VSYNC_IDLE_POL_M (BIT(7)) -#define LCD_CAM_LCD_VSYNC_IDLE_POL_V 0x1 -#define LCD_CAM_LCD_VSYNC_IDLE_POL_S 7 -/* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ -/*description: It is the position of LCD_VSYNC active pulse in a line..*/ -#define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007F -#define LCD_CAM_LCD_VSYNC_WIDTH_M ((LCD_CAM_LCD_VSYNC_WIDTH_V)<<(LCD_CAM_LCD_VSYNC_WIDTH_S)) -#define LCD_CAM_LCD_VSYNC_WIDTH_V 0x7F -#define LCD_CAM_LCD_VSYNC_WIDTH_S 0 +/** LCDCAM_LCD_CTRL2_REG register + * LCD config register. + */ +#define LCDCAM_LCD_CTRL2_REG (DR_REG_LCDCAM_BASE + 0x24) +/** LCDCAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1; + * It is the position of LCD_VSYNC active pulse in a line. + */ +#define LCDCAM_LCD_VSYNC_WIDTH 0x0000007FU +#define LCDCAM_LCD_VSYNC_WIDTH_M (LCDCAM_LCD_VSYNC_WIDTH_V << LCDCAM_LCD_VSYNC_WIDTH_S) +#define LCDCAM_LCD_VSYNC_WIDTH_V 0x0000007FU +#define LCDCAM_LCD_VSYNC_WIDTH_S 0 +/** LCDCAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0; + * It is the idle value of LCD_VSYNC. + */ +#define LCDCAM_LCD_VSYNC_IDLE_POL (BIT(7)) +#define LCDCAM_LCD_VSYNC_IDLE_POL_M (LCDCAM_LCD_VSYNC_IDLE_POL_V << LCDCAM_LCD_VSYNC_IDLE_POL_S) +#define LCDCAM_LCD_VSYNC_IDLE_POL_V 0x00000001U +#define LCDCAM_LCD_VSYNC_IDLE_POL_S 7 +/** LCDCAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0; + * It is the idle value of LCD_DE. + */ +#define LCDCAM_LCD_DE_IDLE_POL (BIT(8)) +#define LCDCAM_LCD_DE_IDLE_POL_M (LCDCAM_LCD_DE_IDLE_POL_V << LCDCAM_LCD_DE_IDLE_POL_S) +#define LCDCAM_LCD_DE_IDLE_POL_V 0x00000001U +#define LCDCAM_LCD_DE_IDLE_POL_S 8 +/** LCDCAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0; + * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC + * pulse is valid only in active region lines in RGB mode. + */ +#define LCDCAM_LCD_HS_BLANK_EN (BIT(9)) +#define LCDCAM_LCD_HS_BLANK_EN_M (LCDCAM_LCD_HS_BLANK_EN_V << LCDCAM_LCD_HS_BLANK_EN_S) +#define LCDCAM_LCD_HS_BLANK_EN_V 0x00000001U +#define LCDCAM_LCD_HS_BLANK_EN_S 9 +/** LCDCAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1; + * It is the position of LCD_HSYNC active pulse in a line. + */ +#define LCDCAM_LCD_HSYNC_WIDTH 0x0000007FU +#define LCDCAM_LCD_HSYNC_WIDTH_M (LCDCAM_LCD_HSYNC_WIDTH_V << LCDCAM_LCD_HSYNC_WIDTH_S) +#define LCDCAM_LCD_HSYNC_WIDTH_V 0x0000007FU +#define LCDCAM_LCD_HSYNC_WIDTH_S 16 +/** LCDCAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0; + * It is the idle value of LCD_HSYNC. + */ +#define LCDCAM_LCD_HSYNC_IDLE_POL (BIT(23)) +#define LCDCAM_LCD_HSYNC_IDLE_POL_M (LCDCAM_LCD_HSYNC_IDLE_POL_V << LCDCAM_LCD_HSYNC_IDLE_POL_S) +#define LCDCAM_LCD_HSYNC_IDLE_POL_V 0x00000001U +#define LCDCAM_LCD_HSYNC_IDLE_POL_S 23 +/** LCDCAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0; + * It is the position of LCD_HSYNC active pulse in a line. + */ +#define LCDCAM_LCD_HSYNC_POSITION 0x000000FFU +#define LCDCAM_LCD_HSYNC_POSITION_M (LCDCAM_LCD_HSYNC_POSITION_V << LCDCAM_LCD_HSYNC_POSITION_S) +#define LCDCAM_LCD_HSYNC_POSITION_V 0x000000FFU +#define LCDCAM_LCD_HSYNC_POSITION_S 24 -#define LCD_CAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x28) -/* LCD_CAM_LCD_FIRST_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The LCD write command value of first cmd cycle..*/ -#define LCD_CAM_LCD_FIRST_CMD_VALUE 0xFFFFFFFF -#define LCD_CAM_LCD_FIRST_CMD_VALUE_M ((LCD_CAM_LCD_FIRST_CMD_VALUE_V)<<(LCD_CAM_LCD_FIRST_CMD_VALUE_S)) -#define LCD_CAM_LCD_FIRST_CMD_VALUE_V 0xFFFFFFFF -#define LCD_CAM_LCD_FIRST_CMD_VALUE_S 0 +/** LCDCAM_LCD_FIRST_CMD_VAL_REG register + * LCD config register. + */ +#define LCDCAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x28) +/** LCDCAM_LCD_FIRST_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of first cmd cycle. + */ +#define LCDCAM_LCD_FIRST_CMD_VALUE 0xFFFFFFFFU +#define LCDCAM_LCD_FIRST_CMD_VALUE_M (LCDCAM_LCD_FIRST_CMD_VALUE_V << LCDCAM_LCD_FIRST_CMD_VALUE_S) +#define LCDCAM_LCD_FIRST_CMD_VALUE_V 0xFFFFFFFFU +#define LCDCAM_LCD_FIRST_CMD_VALUE_S 0 -#define LCD_CAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x2C) -/* LCD_CAM_LCD_LATTER_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The LCD write command value of latter cmd cycle..*/ -#define LCD_CAM_LCD_LATTER_CMD_VALUE 0xFFFFFFFF -#define LCD_CAM_LCD_LATTER_CMD_VALUE_M ((LCD_CAM_LCD_LATTER_CMD_VALUE_V)<<(LCD_CAM_LCD_LATTER_CMD_VALUE_S)) -#define LCD_CAM_LCD_LATTER_CMD_VALUE_V 0xFFFFFFFF -#define LCD_CAM_LCD_LATTER_CMD_VALUE_S 0 +/** LCDCAM_LCD_LATTER_CMD_VAL_REG register + * LCD config register. + */ +#define LCDCAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x2c) +/** LCDCAM_LCD_LATTER_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of latter cmd cycle. + */ +#define LCDCAM_LCD_LATTER_CMD_VALUE 0xFFFFFFFFU +#define LCDCAM_LCD_LATTER_CMD_VALUE_M (LCDCAM_LCD_LATTER_CMD_VALUE_V << LCDCAM_LCD_LATTER_CMD_VALUE_S) +#define LCDCAM_LCD_LATTER_CMD_VALUE_V 0xFFFFFFFFU +#define LCDCAM_LCD_LATTER_CMD_VALUE_S 0 -#define LCD_CAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCD_CAM_BASE + 0x30) -/* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay -ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L -CD_CLK..*/ -#define LCD_CAM_LCD_VSYNC_MODE 0x00000003 -#define LCD_CAM_LCD_VSYNC_MODE_M ((LCD_CAM_LCD_VSYNC_MODE_V)<<(LCD_CAM_LCD_VSYNC_MODE_S)) -#define LCD_CAM_LCD_VSYNC_MODE_V 0x3 -#define LCD_CAM_LCD_VSYNC_MODE_S 22 -/* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay -ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L -CD_CLK..*/ -#define LCD_CAM_LCD_HSYNC_MODE 0x00000003 -#define LCD_CAM_LCD_HSYNC_MODE_M ((LCD_CAM_LCD_HSYNC_MODE_V)<<(LCD_CAM_LCD_HSYNC_MODE_S)) -#define LCD_CAM_LCD_HSYNC_MODE_V 0x3 -#define LCD_CAM_LCD_HSYNC_MODE_S 20 -/* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */ -/*description: The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. - 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_ -CLK..*/ -#define LCD_CAM_LCD_DE_MODE 0x00000003 -#define LCD_CAM_LCD_DE_MODE_M ((LCD_CAM_LCD_DE_MODE_V)<<(LCD_CAM_LCD_DE_MODE_S)) -#define LCD_CAM_LCD_DE_MODE_V 0x3 -#define LCD_CAM_LCD_DE_MODE_S 18 -/* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. - 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_ -CLK..*/ -#define LCD_CAM_LCD_CD_MODE 0x00000003 -#define LCD_CAM_LCD_CD_MODE_M ((LCD_CAM_LCD_CD_MODE_V)<<(LCD_CAM_LCD_CD_MODE_S)) -#define LCD_CAM_LCD_CD_MODE_V 0x3 -#define LCD_CAM_LCD_CD_MODE_S 16 -/* LCD_CAM_DOUT23_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT23_MODE 0x00000003 -#define LCD_CAM_DOUT23_MODE_M ((LCD_CAM_DOUT23_MODE_V)<<(LCD_CAM_DOUT23_MODE_S)) -#define LCD_CAM_DOUT23_MODE_V 0x3 -#define LCD_CAM_DOUT23_MODE_S 14 -/* LCD_CAM_DOUT22_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT22_MODE 0x00000003 -#define LCD_CAM_DOUT22_MODE_M ((LCD_CAM_DOUT22_MODE_V)<<(LCD_CAM_DOUT22_MODE_S)) -#define LCD_CAM_DOUT22_MODE_V 0x3 -#define LCD_CAM_DOUT22_MODE_S 12 -/* LCD_CAM_DOUT21_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT21_MODE 0x00000003 -#define LCD_CAM_DOUT21_MODE_M ((LCD_CAM_DOUT21_MODE_V)<<(LCD_CAM_DOUT21_MODE_S)) -#define LCD_CAM_DOUT21_MODE_V 0x3 -#define LCD_CAM_DOUT21_MODE_S 10 -/* LCD_CAM_DOUT20_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT20_MODE 0x00000003 -#define LCD_CAM_DOUT20_MODE_M ((LCD_CAM_DOUT20_MODE_V)<<(LCD_CAM_DOUT20_MODE_S)) -#define LCD_CAM_DOUT20_MODE_V 0x3 -#define LCD_CAM_DOUT20_MODE_S 8 -/* LCD_CAM_DOUT19_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT19_MODE 0x00000003 -#define LCD_CAM_DOUT19_MODE_M ((LCD_CAM_DOUT19_MODE_V)<<(LCD_CAM_DOUT19_MODE_S)) -#define LCD_CAM_DOUT19_MODE_V 0x3 -#define LCD_CAM_DOUT19_MODE_S 6 -/* LCD_CAM_DOUT18_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT18_MODE 0x00000003 -#define LCD_CAM_DOUT18_MODE_M ((LCD_CAM_DOUT18_MODE_V)<<(LCD_CAM_DOUT18_MODE_S)) -#define LCD_CAM_DOUT18_MODE_V 0x3 -#define LCD_CAM_DOUT18_MODE_S 4 -/* LCD_CAM_DOUT17_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT17_MODE 0x00000003 -#define LCD_CAM_DOUT17_MODE_M ((LCD_CAM_DOUT17_MODE_V)<<(LCD_CAM_DOUT17_MODE_S)) -#define LCD_CAM_DOUT17_MODE_V 0x3 -#define LCD_CAM_DOUT17_MODE_S 2 -/* LCD_CAM_DOUT16_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT16_MODE 0x00000003 -#define LCD_CAM_DOUT16_MODE_M ((LCD_CAM_DOUT16_MODE_V)<<(LCD_CAM_DOUT16_MODE_S)) -#define LCD_CAM_DOUT16_MODE_V 0x3 -#define LCD_CAM_DOUT16_MODE_S 0 +/** LCDCAM_LCD_DLY_MODE_CFG1_REG register + * LCD config register. + */ +#define LCDCAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCDCAM_BASE + 0x30) +/** LCDCAM_DOUT16_MODE : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT16_MODE 0x00000003U +#define LCDCAM_DOUT16_MODE_M (LCDCAM_DOUT16_MODE_V << LCDCAM_DOUT16_MODE_S) +#define LCDCAM_DOUT16_MODE_V 0x00000003U +#define LCDCAM_DOUT16_MODE_S 0 +/** LCDCAM_DOUT17_MODE : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT17_MODE 0x00000003U +#define LCDCAM_DOUT17_MODE_M (LCDCAM_DOUT17_MODE_V << LCDCAM_DOUT17_MODE_S) +#define LCDCAM_DOUT17_MODE_V 0x00000003U +#define LCDCAM_DOUT17_MODE_S 2 +/** LCDCAM_DOUT18_MODE : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT18_MODE 0x00000003U +#define LCDCAM_DOUT18_MODE_M (LCDCAM_DOUT18_MODE_V << LCDCAM_DOUT18_MODE_S) +#define LCDCAM_DOUT18_MODE_V 0x00000003U +#define LCDCAM_DOUT18_MODE_S 4 +/** LCDCAM_DOUT19_MODE : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT19_MODE 0x00000003U +#define LCDCAM_DOUT19_MODE_M (LCDCAM_DOUT19_MODE_V << LCDCAM_DOUT19_MODE_S) +#define LCDCAM_DOUT19_MODE_V 0x00000003U +#define LCDCAM_DOUT19_MODE_S 6 +/** LCDCAM_DOUT20_MODE : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT20_MODE 0x00000003U +#define LCDCAM_DOUT20_MODE_M (LCDCAM_DOUT20_MODE_V << LCDCAM_DOUT20_MODE_S) +#define LCDCAM_DOUT20_MODE_V 0x00000003U +#define LCDCAM_DOUT20_MODE_S 8 +/** LCDCAM_DOUT21_MODE : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT21_MODE 0x00000003U +#define LCDCAM_DOUT21_MODE_M (LCDCAM_DOUT21_MODE_V << LCDCAM_DOUT21_MODE_S) +#define LCDCAM_DOUT21_MODE_V 0x00000003U +#define LCDCAM_DOUT21_MODE_S 10 +/** LCDCAM_DOUT22_MODE : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT22_MODE 0x00000003U +#define LCDCAM_DOUT22_MODE_M (LCDCAM_DOUT22_MODE_V << LCDCAM_DOUT22_MODE_S) +#define LCDCAM_DOUT22_MODE_V 0x00000003U +#define LCDCAM_DOUT22_MODE_S 12 +/** LCDCAM_DOUT23_MODE : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT23_MODE 0x00000003U +#define LCDCAM_DOUT23_MODE_M (LCDCAM_DOUT23_MODE_V << LCDCAM_DOUT23_MODE_S) +#define LCDCAM_DOUT23_MODE_V 0x00000003U +#define LCDCAM_DOUT23_MODE_S 14 +/** LCDCAM_LCD_CD_MODE : R/W; bitpos: [17:16]; default: 0; + * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_CD_MODE 0x00000003U +#define LCDCAM_LCD_CD_MODE_M (LCDCAM_LCD_CD_MODE_V << LCDCAM_LCD_CD_MODE_S) +#define LCDCAM_LCD_CD_MODE_V 0x00000003U +#define LCDCAM_LCD_CD_MODE_S 16 +/** LCDCAM_LCD_DE_MODE : R/W; bitpos: [19:18]; default: 0; + * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_DE_MODE 0x00000003U +#define LCDCAM_LCD_DE_MODE_M (LCDCAM_LCD_DE_MODE_V << LCDCAM_LCD_DE_MODE_S) +#define LCDCAM_LCD_DE_MODE_V 0x00000003U +#define LCDCAM_LCD_DE_MODE_S 18 +/** LCDCAM_LCD_HSYNC_MODE : R/W; bitpos: [21:20]; default: 0; + * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_HSYNC_MODE 0x00000003U +#define LCDCAM_LCD_HSYNC_MODE_M (LCDCAM_LCD_HSYNC_MODE_V << LCDCAM_LCD_HSYNC_MODE_S) +#define LCDCAM_LCD_HSYNC_MODE_V 0x00000003U +#define LCDCAM_LCD_HSYNC_MODE_S 20 +/** LCDCAM_LCD_VSYNC_MODE : R/W; bitpos: [23:22]; default: 0; + * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_VSYNC_MODE 0x00000003U +#define LCDCAM_LCD_VSYNC_MODE_M (LCDCAM_LCD_VSYNC_MODE_V << LCDCAM_LCD_VSYNC_MODE_S) +#define LCDCAM_LCD_VSYNC_MODE_V 0x00000003U +#define LCDCAM_LCD_VSYNC_MODE_S 22 -#define LCD_CAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCD_CAM_BASE + 0x38) -/* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT15_MODE 0x00000003 -#define LCD_CAM_DOUT15_MODE_M ((LCD_CAM_DOUT15_MODE_V)<<(LCD_CAM_DOUT15_MODE_S)) -#define LCD_CAM_DOUT15_MODE_V 0x3 -#define LCD_CAM_DOUT15_MODE_S 30 -/* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT14_MODE 0x00000003 -#define LCD_CAM_DOUT14_MODE_M ((LCD_CAM_DOUT14_MODE_V)<<(LCD_CAM_DOUT14_MODE_S)) -#define LCD_CAM_DOUT14_MODE_V 0x3 -#define LCD_CAM_DOUT14_MODE_S 28 -/* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT13_MODE 0x00000003 -#define LCD_CAM_DOUT13_MODE_M ((LCD_CAM_DOUT13_MODE_V)<<(LCD_CAM_DOUT13_MODE_S)) -#define LCD_CAM_DOUT13_MODE_V 0x3 -#define LCD_CAM_DOUT13_MODE_S 26 -/* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT12_MODE 0x00000003 -#define LCD_CAM_DOUT12_MODE_M ((LCD_CAM_DOUT12_MODE_V)<<(LCD_CAM_DOUT12_MODE_S)) -#define LCD_CAM_DOUT12_MODE_V 0x3 -#define LCD_CAM_DOUT12_MODE_S 24 -/* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT11_MODE 0x00000003 -#define LCD_CAM_DOUT11_MODE_M ((LCD_CAM_DOUT11_MODE_V)<<(LCD_CAM_DOUT11_MODE_S)) -#define LCD_CAM_DOUT11_MODE_V 0x3 -#define LCD_CAM_DOUT11_MODE_S 22 -/* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT10_MODE 0x00000003 -#define LCD_CAM_DOUT10_MODE_M ((LCD_CAM_DOUT10_MODE_V)<<(LCD_CAM_DOUT10_MODE_S)) -#define LCD_CAM_DOUT10_MODE_V 0x3 -#define LCD_CAM_DOUT10_MODE_S 20 -/* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT9_MODE 0x00000003 -#define LCD_CAM_DOUT9_MODE_M ((LCD_CAM_DOUT9_MODE_V)<<(LCD_CAM_DOUT9_MODE_S)) -#define LCD_CAM_DOUT9_MODE_V 0x3 -#define LCD_CAM_DOUT9_MODE_S 18 -/* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT8_MODE 0x00000003 -#define LCD_CAM_DOUT8_MODE_M ((LCD_CAM_DOUT8_MODE_V)<<(LCD_CAM_DOUT8_MODE_S)) -#define LCD_CAM_DOUT8_MODE_V 0x3 -#define LCD_CAM_DOUT8_MODE_S 16 -/* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT7_MODE 0x00000003 -#define LCD_CAM_DOUT7_MODE_M ((LCD_CAM_DOUT7_MODE_V)<<(LCD_CAM_DOUT7_MODE_S)) -#define LCD_CAM_DOUT7_MODE_V 0x3 -#define LCD_CAM_DOUT7_MODE_S 14 -/* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT6_MODE 0x00000003 -#define LCD_CAM_DOUT6_MODE_M ((LCD_CAM_DOUT6_MODE_V)<<(LCD_CAM_DOUT6_MODE_S)) -#define LCD_CAM_DOUT6_MODE_V 0x3 -#define LCD_CAM_DOUT6_MODE_S 12 -/* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT5_MODE 0x00000003 -#define LCD_CAM_DOUT5_MODE_M ((LCD_CAM_DOUT5_MODE_V)<<(LCD_CAM_DOUT5_MODE_S)) -#define LCD_CAM_DOUT5_MODE_V 0x3 -#define LCD_CAM_DOUT5_MODE_S 10 -/* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT4_MODE 0x00000003 -#define LCD_CAM_DOUT4_MODE_M ((LCD_CAM_DOUT4_MODE_V)<<(LCD_CAM_DOUT4_MODE_S)) -#define LCD_CAM_DOUT4_MODE_V 0x3 -#define LCD_CAM_DOUT4_MODE_S 8 -/* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT3_MODE 0x00000003 -#define LCD_CAM_DOUT3_MODE_M ((LCD_CAM_DOUT3_MODE_V)<<(LCD_CAM_DOUT3_MODE_S)) -#define LCD_CAM_DOUT3_MODE_V 0x3 -#define LCD_CAM_DOUT3_MODE_S 6 -/* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT2_MODE 0x00000003 -#define LCD_CAM_DOUT2_MODE_M ((LCD_CAM_DOUT2_MODE_V)<<(LCD_CAM_DOUT2_MODE_S)) -#define LCD_CAM_DOUT2_MODE_V 0x3 -#define LCD_CAM_DOUT2_MODE_S 4 -/* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT1_MODE 0x00000003 -#define LCD_CAM_DOUT1_MODE_M ((LCD_CAM_DOUT1_MODE_V)<<(LCD_CAM_DOUT1_MODE_S)) -#define LCD_CAM_DOUT1_MODE_V 0x3 -#define LCD_CAM_DOUT1_MODE_S 2 -/* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del -ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - LCD_CLK..*/ -#define LCD_CAM_DOUT0_MODE 0x00000003 -#define LCD_CAM_DOUT0_MODE_M ((LCD_CAM_DOUT0_MODE_V)<<(LCD_CAM_DOUT0_MODE_S)) -#define LCD_CAM_DOUT0_MODE_V 0x3 -#define LCD_CAM_DOUT0_MODE_S 0 +/** LCDCAM_LCD_DLY_MODE_CFG2_REG register + * LCD config register. + */ +#define LCDCAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCDCAM_BASE + 0x38) +/** LCDCAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT0_MODE 0x00000003U +#define LCDCAM_DOUT0_MODE_M (LCDCAM_DOUT0_MODE_V << LCDCAM_DOUT0_MODE_S) +#define LCDCAM_DOUT0_MODE_V 0x00000003U +#define LCDCAM_DOUT0_MODE_S 0 +/** LCDCAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT1_MODE 0x00000003U +#define LCDCAM_DOUT1_MODE_M (LCDCAM_DOUT1_MODE_V << LCDCAM_DOUT1_MODE_S) +#define LCDCAM_DOUT1_MODE_V 0x00000003U +#define LCDCAM_DOUT1_MODE_S 2 +/** LCDCAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT2_MODE 0x00000003U +#define LCDCAM_DOUT2_MODE_M (LCDCAM_DOUT2_MODE_V << LCDCAM_DOUT2_MODE_S) +#define LCDCAM_DOUT2_MODE_V 0x00000003U +#define LCDCAM_DOUT2_MODE_S 4 +/** LCDCAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT3_MODE 0x00000003U +#define LCDCAM_DOUT3_MODE_M (LCDCAM_DOUT3_MODE_V << LCDCAM_DOUT3_MODE_S) +#define LCDCAM_DOUT3_MODE_V 0x00000003U +#define LCDCAM_DOUT3_MODE_S 6 +/** LCDCAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT4_MODE 0x00000003U +#define LCDCAM_DOUT4_MODE_M (LCDCAM_DOUT4_MODE_V << LCDCAM_DOUT4_MODE_S) +#define LCDCAM_DOUT4_MODE_V 0x00000003U +#define LCDCAM_DOUT4_MODE_S 8 +/** LCDCAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT5_MODE 0x00000003U +#define LCDCAM_DOUT5_MODE_M (LCDCAM_DOUT5_MODE_V << LCDCAM_DOUT5_MODE_S) +#define LCDCAM_DOUT5_MODE_V 0x00000003U +#define LCDCAM_DOUT5_MODE_S 10 +/** LCDCAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT6_MODE 0x00000003U +#define LCDCAM_DOUT6_MODE_M (LCDCAM_DOUT6_MODE_V << LCDCAM_DOUT6_MODE_S) +#define LCDCAM_DOUT6_MODE_V 0x00000003U +#define LCDCAM_DOUT6_MODE_S 12 +/** LCDCAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT7_MODE 0x00000003U +#define LCDCAM_DOUT7_MODE_M (LCDCAM_DOUT7_MODE_V << LCDCAM_DOUT7_MODE_S) +#define LCDCAM_DOUT7_MODE_V 0x00000003U +#define LCDCAM_DOUT7_MODE_S 14 +/** LCDCAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT8_MODE 0x00000003U +#define LCDCAM_DOUT8_MODE_M (LCDCAM_DOUT8_MODE_V << LCDCAM_DOUT8_MODE_S) +#define LCDCAM_DOUT8_MODE_V 0x00000003U +#define LCDCAM_DOUT8_MODE_S 16 +/** LCDCAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT9_MODE 0x00000003U +#define LCDCAM_DOUT9_MODE_M (LCDCAM_DOUT9_MODE_V << LCDCAM_DOUT9_MODE_S) +#define LCDCAM_DOUT9_MODE_V 0x00000003U +#define LCDCAM_DOUT9_MODE_S 18 +/** LCDCAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT10_MODE 0x00000003U +#define LCDCAM_DOUT10_MODE_M (LCDCAM_DOUT10_MODE_V << LCDCAM_DOUT10_MODE_S) +#define LCDCAM_DOUT10_MODE_V 0x00000003U +#define LCDCAM_DOUT10_MODE_S 20 +/** LCDCAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT11_MODE 0x00000003U +#define LCDCAM_DOUT11_MODE_M (LCDCAM_DOUT11_MODE_V << LCDCAM_DOUT11_MODE_S) +#define LCDCAM_DOUT11_MODE_V 0x00000003U +#define LCDCAM_DOUT11_MODE_S 22 +/** LCDCAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT12_MODE 0x00000003U +#define LCDCAM_DOUT12_MODE_M (LCDCAM_DOUT12_MODE_V << LCDCAM_DOUT12_MODE_S) +#define LCDCAM_DOUT12_MODE_V 0x00000003U +#define LCDCAM_DOUT12_MODE_S 24 +/** LCDCAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT13_MODE 0x00000003U +#define LCDCAM_DOUT13_MODE_M (LCDCAM_DOUT13_MODE_V << LCDCAM_DOUT13_MODE_S) +#define LCDCAM_DOUT13_MODE_V 0x00000003U +#define LCDCAM_DOUT13_MODE_S 26 +/** LCDCAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT14_MODE 0x00000003U +#define LCDCAM_DOUT14_MODE_M (LCDCAM_DOUT14_MODE_V << LCDCAM_DOUT14_MODE_S) +#define LCDCAM_DOUT14_MODE_V 0x00000003U +#define LCDCAM_DOUT14_MODE_S 28 +/** LCDCAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT15_MODE 0x00000003U +#define LCDCAM_DOUT15_MODE_M (LCDCAM_DOUT15_MODE_V << LCDCAM_DOUT15_MODE_S) +#define LCDCAM_DOUT15_MODE_V 0x00000003U +#define LCDCAM_DOUT15_MODE_S 30 -#define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x64) -/* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for Camera line interrupt..*/ -#define LCD_CAM_CAM_HS_INT_ENA (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ENA_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ENA_V 0x1 -#define LCD_CAM_CAM_HS_INT_ENA_S 3 -/* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for Camera frame end interrupt..*/ -#define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ENA_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_ENA_S 2 -/* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for lcd transfer end interrupt..*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1 -/* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for LCD frame end interrupt..*/ -#define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ENA_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_ENA_S 0 +/** LCDCAM_LC_DMA_INT_ENA_REG register + * LCDCAM interrupt enable register. + */ +#define LCDCAM_LC_DMA_INT_ENA_REG (DR_REG_LCDCAM_BASE + 0x64) +/** LCDCAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_ENA (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_ENA_M (LCDCAM_LCD_VSYNC_INT_ENA_V << LCDCAM_LCD_VSYNC_INT_ENA_S) +#define LCDCAM_LCD_VSYNC_INT_ENA_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_ENA_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_ENA_M (LCDCAM_LCD_TRANS_DONE_INT_ENA_V << LCDCAM_LCD_TRANS_DONE_INT_ENA_S) +#define LCDCAM_LCD_TRANS_DONE_INT_ENA_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_ENA_S 1 +/** LCDCAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_ENA (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_ENA_M (LCDCAM_CAM_VSYNC_INT_ENA_V << LCDCAM_CAM_VSYNC_INT_ENA_S) +#define LCDCAM_CAM_VSYNC_INT_ENA_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_ENA_S 2 +/** LCDCAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for Camera line interrupt. + */ +#define LCDCAM_CAM_HS_INT_ENA (BIT(3)) +#define LCDCAM_CAM_HS_INT_ENA_M (LCDCAM_CAM_HS_INT_ENA_V << LCDCAM_CAM_HS_INT_ENA_S) +#define LCDCAM_CAM_HS_INT_ENA_V 0x00000001U +#define LCDCAM_CAM_HS_INT_ENA_S 3 -#define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x68) -/* LCD_CAM_CAM_HS_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for Camera line interrupt..*/ -#define LCD_CAM_CAM_HS_INT_RAW (BIT(3)) -#define LCD_CAM_CAM_HS_INT_RAW_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_RAW_V 0x1 -#define LCD_CAM_CAM_HS_INT_RAW_S 3 -/* LCD_CAM_CAM_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for Camera frame end interrupt..*/ -#define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_RAW_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_RAW_S 2 -/* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit for lcd transfer end interrupt..*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1 -/* LCD_CAM_LCD_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit for LCD frame end interrupt..*/ -#define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_RAW_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_RAW_S 0 +/** LCDCAM_LC_DMA_INT_RAW_REG register + * LCDCAM interrupt raw register, valid in level. + */ +#define LCDCAM_LC_DMA_INT_RAW_REG (DR_REG_LCDCAM_BASE + 0x68) +/** LCDCAM_LCD_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_RAW (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_RAW_M (LCDCAM_LCD_VSYNC_INT_RAW_V << LCDCAM_LCD_VSYNC_INT_RAW_S) +#define LCDCAM_LCD_VSYNC_INT_RAW_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_RAW_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_RAW_M (LCDCAM_LCD_TRANS_DONE_INT_RAW_V << LCDCAM_LCD_TRANS_DONE_INT_RAW_S) +#define LCDCAM_LCD_TRANS_DONE_INT_RAW_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_RAW_S 1 +/** LCDCAM_CAM_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_RAW (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_RAW_M (LCDCAM_CAM_VSYNC_INT_RAW_V << LCDCAM_CAM_VSYNC_INT_RAW_S) +#define LCDCAM_CAM_VSYNC_INT_RAW_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_RAW_S 2 +/** LCDCAM_CAM_HS_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for Camera line interrupt. + */ +#define LCDCAM_CAM_HS_INT_RAW (BIT(3)) +#define LCDCAM_CAM_HS_INT_RAW_M (LCDCAM_CAM_HS_INT_RAW_V << LCDCAM_CAM_HS_INT_RAW_S) +#define LCDCAM_CAM_HS_INT_RAW_V 0x00000001U +#define LCDCAM_CAM_HS_INT_RAW_S 3 -#define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x6C) -/* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The status bit for Camera transfer end interrupt..*/ -#define LCD_CAM_CAM_HS_INT_ST (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ST_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ST_V 0x1 -#define LCD_CAM_CAM_HS_INT_ST_S 3 -/* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The status bit for Camera frame end interrupt..*/ -#define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ST_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ST_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_ST_S 2 -/* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status bit for lcd transfer end interrupt..*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1 -/* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status bit for LCD frame end interrupt..*/ -#define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ST_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ST_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_ST_S 0 +/** LCDCAM_LC_DMA_INT_ST_REG register + * LCDCAM interrupt status register. + */ +#define LCDCAM_LC_DMA_INT_ST_REG (DR_REG_LCDCAM_BASE + 0x6c) +/** LCDCAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_ST (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_ST_M (LCDCAM_LCD_VSYNC_INT_ST_V << LCDCAM_LCD_VSYNC_INT_ST_S) +#define LCDCAM_LCD_VSYNC_INT_ST_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_ST_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_ST (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_ST_M (LCDCAM_LCD_TRANS_DONE_INT_ST_V << LCDCAM_LCD_TRANS_DONE_INT_ST_S) +#define LCDCAM_LCD_TRANS_DONE_INT_ST_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_ST_S 1 +/** LCDCAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_ST (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_ST_M (LCDCAM_CAM_VSYNC_INT_ST_V << LCDCAM_CAM_VSYNC_INT_ST_S) +#define LCDCAM_CAM_VSYNC_INT_ST_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_ST_S 2 +/** LCDCAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for Camera transfer end interrupt. + */ +#define LCDCAM_CAM_HS_INT_ST (BIT(3)) +#define LCDCAM_CAM_HS_INT_ST_M (LCDCAM_CAM_HS_INT_ST_V << LCDCAM_CAM_HS_INT_ST_S) +#define LCDCAM_CAM_HS_INT_ST_V 0x00000001U +#define LCDCAM_CAM_HS_INT_ST_S 3 -#define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x70) -/* LCD_CAM_CAM_HS_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for Camera line interrupt..*/ -#define LCD_CAM_CAM_HS_INT_CLR (BIT(3)) -#define LCD_CAM_CAM_HS_INT_CLR_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_CLR_V 0x1 -#define LCD_CAM_CAM_HS_INT_CLR_S 3 -/* LCD_CAM_CAM_VSYNC_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for Camera frame end interrupt..*/ -#define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_CLR_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_CLR_S 2 -/* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for lcd transfer end interrupt..*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1 -/* LCD_CAM_LCD_VSYNC_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for LCD frame end interrupt..*/ -#define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_CLR_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_CLR_S 0 - -#define LCD_CAM_LC_REG_DATE_REG (DR_REG_LCD_CAM_BASE + 0xFC) -/* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2303090 ; */ -/*description: LCD_CAM version control register.*/ -#define LCD_CAM_LC_DATE 0x0FFFFFFF -#define LCD_CAM_LC_DATE_M ((LCD_CAM_LC_DATE_V)<<(LCD_CAM_LC_DATE_S)) -#define LCD_CAM_LC_DATE_V 0xFFFFFFF -#define LCD_CAM_LC_DATE_S 0 +/** LCDCAM_LC_DMA_INT_CLR_REG register + * LCDCAM interrupt clear register. + */ +#define LCDCAM_LC_DMA_INT_CLR_REG (DR_REG_LCDCAM_BASE + 0x70) +/** LCDCAM_LCD_VSYNC_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_CLR (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_CLR_M (LCDCAM_LCD_VSYNC_INT_CLR_V << LCDCAM_LCD_VSYNC_INT_CLR_S) +#define LCDCAM_LCD_VSYNC_INT_CLR_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_CLR_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_CLR_M (LCDCAM_LCD_TRANS_DONE_INT_CLR_V << LCDCAM_LCD_TRANS_DONE_INT_CLR_S) +#define LCDCAM_LCD_TRANS_DONE_INT_CLR_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_CLR_S 1 +/** LCDCAM_CAM_VSYNC_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_CLR (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_CLR_M (LCDCAM_CAM_VSYNC_INT_CLR_V << LCDCAM_CAM_VSYNC_INT_CLR_S) +#define LCDCAM_CAM_VSYNC_INT_CLR_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_CLR_S 2 +/** LCDCAM_CAM_HS_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for Camera line interrupt. + */ +#define LCDCAM_CAM_HS_INT_CLR (BIT(3)) +#define LCDCAM_CAM_HS_INT_CLR_M (LCDCAM_CAM_HS_INT_CLR_V << LCDCAM_CAM_HS_INT_CLR_S) +#define LCDCAM_CAM_HS_INT_CLR_V 0x00000001U +#define LCDCAM_CAM_HS_INT_CLR_S 3 +/** LCDCAM_LC_REG_DATE_REG register + * Version register + */ +#define LCDCAM_LC_REG_DATE_REG (DR_REG_LCDCAM_BASE + 0xfc) +/** LCDCAM_LC_DATE : R/W; bitpos: [27:0]; default: 36712592; + * LCD_CAM version control register + */ +#define LCDCAM_LC_DATE 0x0FFFFFFFU +#define LCDCAM_LC_DATE_M (LCDCAM_LC_DATE_V << LCDCAM_LC_DATE_S) +#define LCDCAM_LC_DATE_V 0x0FFFFFFFU +#define LCDCAM_LC_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_LCD_CAM_REG_H_ */ diff --git a/components/soc/esp32p4/include/soc/lcd_cam_struct.h b/components/soc/esp32p4/include/soc/lcd_cam_struct.h index ed787f0761..2ce7658d43 100644 --- a/components/soc/esp32p4/include/soc/lcd_cam_struct.h +++ b/components/soc/esp32p4/include/soc/lcd_cam_struct.h @@ -1,303 +1,855 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_LCD_CAM_STRUCT_H_ -#define _SOC_LCD_CAM_STRUCT_H_ - +#pragma once +#include #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -typedef volatile struct { - union { - struct { - uint32_t lcd_clkcnt_n : 6; /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/ - uint32_t lcd_clk_equ_sysclk : 1; /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/ - uint32_t lcd_ck_idle_edge : 1; /*1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. */ - uint32_t lcd_ck_out_edge : 1; /*1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle. */ - uint32_t lcd_clkm_div_num : 8; /*Integral LCD clock divider value*/ - uint32_t lcd_clkm_div_b : 6; /*Fractional clock divider numerator value*/ - uint32_t lcd_clkm_div_a : 6; /*Fractional clock divider denominator value*/ - uint32_t lcd_clk_sel : 2; /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ - uint32_t clk_en : 1; /*Set this bit to enable clk gate*/ - }; - uint32_t val; - } lcd_clock; - union { - struct { - uint32_t cam_stop_en : 1; /*Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/ - uint32_t cam_vsync_filter_thres : 3; /*Filter threshold value for CAM_VSYNC signal.*/ - uint32_t cam_update : 1; /*1: Update Camera registers, will be cleared by hardware. 0 : Not care.*/ - uint32_t cam_byte_order : 1; /*1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ - uint32_t cam_bit_order : 1; /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/ - uint32_t cam_line_int_en : 1; /*1: Enable to generate CAM_HS_INT. 0: Disable.*/ - uint32_t cam_vs_eof_en : 1; /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/ - uint32_t cam_clkm_div_num : 8; /*Integral Camera clock divider value*/ - uint32_t cam_clkm_div_b : 6; /*Fractional clock divider numerator value*/ - uint32_t cam_clkm_div_a : 6; /*Fractional clock divider denominator value*/ - uint32_t cam_clk_sel : 2; /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ - uint32_t reserved31 : 1; /*reserved*/ - }; - uint32_t val; - } cam_ctrl; - union { - struct { - uint32_t cam_rec_data_bytelen : 16; /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/ - uint32_t cam_line_int_num : 6; /*The line number minus 1 to generate cam_hs_int.*/ - uint32_t cam_clk_inv : 1; /*1: Invert the input signal CAM_PCLK. 0: Not invert.*/ - uint32_t cam_vsync_filter_en : 1; /*1: Enable CAM_VSYNC filter function. 0: bypass.*/ - uint32_t cam_2byte_en : 1; /*1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. */ - uint32_t cam_de_inv : 1; /*CAM_DE invert enable signal, valid in high level.*/ - uint32_t cam_hsync_inv : 1; /*CAM_HSYNC invert enable signal, valid in high level.*/ - uint32_t cam_vsync_inv : 1; /*CAM_VSYNC invert enable signal, valid in high level.*/ - uint32_t cam_vh_de_mode_en : 1; /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC.*/ - uint32_t cam_start : 1; /*Camera module start signal.*/ - uint32_t cam_reset : 1; /*Camera module reset signal.*/ - uint32_t cam_afifo_reset : 1; /*Camera AFIFO reset signal.*/ - }; - uint32_t val; - } cam_ctrl1; - union { - struct { - uint32_t reserved0 : 21; /*reserved*/ - uint32_t cam_conv_8bits_data_inv : 1; /*1:invert every two 8bits input data. 2. disabled.*/ - uint32_t cam_conv_yuv2yuv_mode : 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. */ - uint32_t cam_conv_yuv_mode : 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/ - uint32_t cam_conv_protocol_mode : 1; /*0:BT601. 1:BT709.*/ - uint32_t cam_conv_data_out_mode : 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/ - uint32_t cam_conv_data_in_mode : 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/ - uint32_t cam_conv_mode_8bits_on : 1; /*0: 16bits mode. 1: 8bits mode.*/ - uint32_t cam_conv_trans_mode : 1; /*0: YUV to RGB. 1: RGB to YUV.*/ - uint32_t cam_conv_enable : 1; /*0: Bypass converter. 1: Enable converter.*/ - }; - uint32_t val; - } cam_rgb_yuv; - union { - struct { - uint32_t reserved0 : 20; /*reserved*/ - uint32_t lcd_conv_8bits_data_inv : 1; /*1:invert every two 8bits input data. 2. disabled.*/ - uint32_t lcd_conv_txtorx : 1; /*0: txtorx mode off. 1: txtorx mode on.*/ - uint32_t lcd_conv_yuv2yuv_mode : 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. */ - uint32_t lcd_conv_yuv_mode : 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/ - uint32_t lcd_conv_protocol_mode : 1; /*0:BT601. 1:BT709.*/ - uint32_t lcd_conv_data_out_mode : 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/ - uint32_t lcd_conv_data_in_mode : 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/ - uint32_t lcd_conv_mode_8bits_on : 1; /*0: 16bits mode. 1: 8bits mode.*/ - uint32_t lcd_conv_trans_mode : 1; /*0: YUV to RGB. 1: RGB to YUV.*/ - uint32_t lcd_conv_enable : 1; /*0: Bypass converter. 1: Enable converter.*/ - }; - uint32_t val; - } lcd_rgb_yuv; - union { - struct { - uint32_t lcd_dout_cyclelen : 13; /*The output data cycles minus 1 of LCD module.*/ - uint32_t lcd_always_out_en : 1; /*LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set.*/ - uint32_t lcd_dout_byte_swizzle_mode : 3; /*0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA*/ - uint32_t lcd_dout_byte_swizzle_enable : 1; /*1: enable byte swizzle 0: disable*/ - uint32_t lcd_dout_bit_order : 1; /*1: change bit order in every byte. 0: Not change.*/ - uint32_t lcd_byte_mode : 2; /*2: 24bit mode. 1: 16bit mode. 0: 8bit mode*/ - uint32_t lcd_update : 1; /*1: Update LCD registers, will be cleared by hardware. 0 : Not care.*/ - uint32_t lcd_bit_order : 1; /*1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ - uint32_t lcd_byte_order : 1; /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/ - uint32_t lcd_dout : 1; /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/ - uint32_t lcd_dummy : 1; /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/ - uint32_t lcd_cmd : 1; /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/ - uint32_t lcd_start : 1; /*LCD start sending data enable signal, valid in high level.*/ - uint32_t lcd_reset : 1; /*The value of command. */ - uint32_t lcd_dummy_cyclelen : 2; /*The dummy cycle length minus 1.*/ - uint32_t lcd_cmd_2_cycle_en : 1; /*The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */ - }; - uint32_t val; - } lcd_user; - union { - struct { - uint32_t reserved0 : 4; /*reserved*/ - uint32_t lcd_wire_mode : 2; /*The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit*/ - uint32_t lcd_vfk_cyclelen : 6; /*The setup cycle length minus 1 in LCD non-RGB mode.*/ - uint32_t lcd_vbk_cyclelen : 13; /*The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode.*/ - uint32_t lcd_next_frame_en : 1; /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/ - uint32_t lcd_bk_en : 1; /*1: Enable blank region when LCD sends data out. 0: No blank region.*/ - uint32_t lcd_afifo_reset : 1; /*LCD AFIFO reset signal.*/ - uint32_t lcd_cd_data_set : 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. */ - uint32_t lcd_cd_dummy_set : 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. */ - uint32_t lcd_cd_cmd_set : 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. */ - uint32_t lcd_cd_idle_edge : 1; /*The default value of LCD_CD. */ - }; - uint32_t val; - } lcd_misc; - union { - struct { - uint32_t lcd_hb_front : 11; /*It is the horizontal blank front porch of a frame. */ - uint32_t lcd_va_height : 10; /*It is the vertical active height of a frame. */ - uint32_t lcd_vt_height : 10; /*It is the vertical total height of a frame. */ - uint32_t lcd_rgb_mode_en : 1; /*1: Enable LCD RGB mode. 0: Disable LCD RGB mode.*/ - }; - uint32_t val; - } lcd_ctrl; - union { - struct { - uint32_t lcd_vb_front : 8; /*It is the vertical blank front porch of a frame. */ - uint32_t lcd_ha_width : 12; /*It is the horizontal active width of a frame. */ - uint32_t lcd_ht_width : 12; /*It is the horizontal total width of a frame. */ - }; - uint32_t val; - } lcd_ctrl1; - union { - struct { - uint32_t lcd_vsync_width : 7; /*It is the position of LCD_VSYNC active pulse in a line. */ - uint32_t lcd_vsync_idle_pol : 1; /*It is the idle value of LCD_VSYNC. */ - uint32_t lcd_de_idle_pol : 1; /*It is the idle value of LCD_DE. */ - uint32_t lcd_hs_blank_en : 1; /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. */ - uint32_t reserved10 : 6; /*reserved*/ - uint32_t lcd_hsync_width : 7; /*It is the position of LCD_HSYNC active pulse in a line. */ - uint32_t lcd_hsync_idle_pol : 1; /*It is the idle value of LCD_HSYNC. */ - uint32_t lcd_hsync_position : 8; /*It is the position of LCD_HSYNC active pulse in a line. */ - }; - uint32_t val; - } lcd_ctrl2; - uint32_t lcd_first_cmd_val; - uint32_t lcd_latter_cmd_val; - union { - struct { - uint32_t dout16_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout17_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout18_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout19_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout20_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout21_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout22_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout23_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t lcd_cd_mode : 2; /*The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t lcd_de_mode : 2; /*The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t lcd_hsync_mode : 2; /*The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t lcd_vsync_mode : 2; /*The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t reserved24 : 8; /*reserved*/ - }; - uint32_t val; - } lcd_dly_mode_cfg1; - uint32_t reserved_34; - union { - struct { - uint32_t dout0_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout1_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout2_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout3_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout4_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout5_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout6_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout7_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout8_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout9_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout10_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout11_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout12_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout13_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout14_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - uint32_t dout15_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/ - }; - uint32_t val; - } lcd_dly_mode_cfg2; - uint32_t reserved_3c; - uint32_t reserved_40; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - union { - struct { - uint32_t lcd_vsync : 1; /*The enable bit for LCD frame end interrupt.*/ - uint32_t lcd_trans_done : 1; /*The enable bit for lcd transfer end interrupt.*/ - uint32_t cam_vsync : 1; /*The enable bit for Camera frame end interrupt.*/ - uint32_t cam_hs : 1; /*The enable bit for Camera line interrupt.*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } dma_int_ena; - union { - struct { - uint32_t lcd_vsync : 1; /*The raw bit for LCD frame end interrupt.*/ - uint32_t lcd_trans_done : 1; /*The raw bit for lcd transfer end interrupt.*/ - uint32_t cam_vsync : 1; /*The raw bit for Camera frame end interrupt.*/ - uint32_t cam_hs : 1; /*The raw bit for Camera line interrupt.*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } dma_int_raw; - union { - struct { - uint32_t lcd_vsync : 1; /*The status bit for LCD frame end interrupt.*/ - uint32_t lcd_trans_done : 1; /*The status bit for lcd transfer end interrupt.*/ - uint32_t cam_vsync : 1; /*The status bit for Camera frame end interrupt.*/ - uint32_t cam_hs : 1; /*The status bit for Camera transfer end interrupt.*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } dma_int_st; - union { - struct { - uint32_t lcd_vsync : 1; /*The clear bit for LCD frame end interrupt.*/ - uint32_t lcd_trans_done : 1; /*The clear bit for lcd transfer end interrupt.*/ - uint32_t cam_vsync : 1; /*The clear bit for Camera frame end interrupt.*/ - uint32_t cam_hs : 1; /*The clear bit for Camera line interrupt.*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } dma_int_clr; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - union { - struct { - uint32_t date : 28; /*LCD_CAM version control register*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } date; -} lcd_cam_dev_t; -extern lcd_cam_dev_t LCD_CAM; +/** Group: lcd configuration registers */ +/** Type of lcd_clock register + * LCD clock config register. + */ +typedef union { + struct { + /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3; + * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + */ + uint32_t lcd_clkcnt_n:6; + /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1; + * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + */ + uint32_t lcd_clk_equ_sysclk:1; + /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0; + * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + */ + uint32_t lcd_ck_idle_edge:1; + /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0; + * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low + * in the second half data cycle. + */ + uint32_t lcd_ck_out_edge:1; + /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4; + * Integral LCD clock divider value + */ + uint32_t lcd_clkm_div_num:8; + /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t lcd_clkm_div_b:6; + /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t lcd_clkm_div_a:6; + /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0; + * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ + uint32_t lcd_clk_sel:2; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lcdcam_lcd_clock_reg_t; + +/** Type of lcd_rgb_yuv register + * LCD YUV/RGB converter configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ + uint32_t lcd_conv_8bits_data_inv:1; + /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0; + * 0: txtorx mode off. 1: txtorx mode on. + */ + uint32_t lcd_conv_txtorx:1; + /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ + uint32_t lcd_conv_yuv2yuv_mode:2; + /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ + uint32_t lcd_conv_yuv_mode:2; + /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ + uint32_t lcd_conv_protocol_mode:1; + /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ + uint32_t lcd_conv_data_out_mode:1; + /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ + uint32_t lcd_conv_data_in_mode:1; + /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ + uint32_t lcd_conv_mode_8bits_on:1; + /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ + uint32_t lcd_conv_trans_mode:1; + /** lcd_conv_enable : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ + uint32_t lcd_conv_enable:1; + }; + uint32_t val; +} lcdcam_lcd_rgb_yuv_reg_t; + +/** Type of lcd_user register + * LCD config register. + */ +typedef union { + struct { + /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1; + * The output data cycles minus 1 of LCD module. + */ + uint32_t lcd_dout_cyclelen:13; + /** lcd_always_out_en : R/W; bitpos: [13]; default: 0; + * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or + * reg_lcd_reset is set. + */ + uint32_t lcd_always_out_en:1; + /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0; + * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + */ + uint32_t lcd_dout_byte_swizzle_mode:3; + /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0; + * 1: enable byte swizzle 0: disable + */ + uint32_t lcd_dout_byte_swizzle_enable:1; + /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0; + * 1: change bit order in every byte. 0: Not change. + */ + uint32_t lcd_dout_bit_order:1; + /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0; + * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + */ + uint32_t lcd_byte_mode:2; + /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0; + * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + */ + uint32_t lcd_update_reg:1; + /** lcd_bit_order : R/W; bitpos: [22]; default: 0; + * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ + uint32_t lcd_bit_order:1; + /** lcd_byte_order : R/W; bitpos: [23]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ + uint32_t lcd_byte_order:1; + /** lcd_dout : R/W; bitpos: [24]; default: 0; + * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_dout:1; + /** lcd_dummy : R/W; bitpos: [25]; default: 0; + * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_dummy:1; + /** lcd_cmd : R/W; bitpos: [26]; default: 0; + * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_cmd:1; + /** lcd_start : R/W/SC; bitpos: [27]; default: 0; + * LCD start sending data enable signal, valid in high level. + */ + uint32_t lcd_start:1; + /** lcd_reset : WT; bitpos: [28]; default: 0; + * The value of command. + */ + uint32_t lcd_reset:1; + /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0; + * The dummy cycle length minus 1. + */ + uint32_t lcd_dummy_cyclelen:2; + /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0; + * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + */ + uint32_t lcd_cmd_2_cycle_en:1; + }; + uint32_t val; +} lcdcam_lcd_user_reg_t; + +/** Type of lcd_misc register + * LCD config register. + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0; + * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + */ + uint32_t lcd_wire_mode:2; + /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3; + * The setup cycle length minus 1 in LCD non-RGB mode. + */ + uint32_t lcd_vfk_cyclelen:6; + /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0; + * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold + * time cycle length in LCD non-RGB mode. + */ + uint32_t lcd_vbk_cyclelen:13; + /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0; + * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when + * the current frame is sent out. + */ + uint32_t lcd_next_frame_en:1; + /** lcd_bk_en : R/W; bitpos: [26]; default: 0; + * 1: Enable blank region when LCD sends data out. 0: No blank region. + */ + uint32_t lcd_bk_en:1; + /** lcd_afifo_reset : WT; bitpos: [27]; default: 0; + * LCD AFIFO reset signal. + */ + uint32_t lcd_afifo_reset:1; + /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_data_set:1; + /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_dummy_set:1; + /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_cmd_set:1; + /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0; + * The default value of LCD_CD. + */ + uint32_t lcd_cd_idle_edge:1; + }; + uint32_t val; +} lcdcam_lcd_misc_reg_t; + +/** Type of lcd_ctrl register + * LCD config register. + */ +typedef union { + struct { + /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. + */ + uint32_t lcd_hb_front:11; + /** lcd_va_height : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. + */ + uint32_t lcd_va_height:10; + /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. + */ + uint32_t lcd_vt_height:10; + /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + */ + uint32_t lcd_rgb_mode_en:1; + }; + uint32_t val; +} lcdcam_lcd_ctrl_reg_t; + +/** Type of lcd_ctrl1 register + * LCD config register. + */ +typedef union { + struct { + /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. + */ + uint32_t lcd_vb_front:8; + /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. + */ + uint32_t lcd_ha_width:12; + /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. + */ + uint32_t lcd_ht_width:12; + }; + uint32_t val; +} lcdcam_lcd_ctrl1_reg_t; + +/** Type of lcd_ctrl2 register + * LCD config register. + */ +typedef union { + struct { + /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; + * It is the position of LCD_VSYNC active pulse in a line. + */ + uint32_t lcd_vsync_width:7; + /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0; + * It is the idle value of LCD_VSYNC. + */ + uint32_t lcd_vsync_idle_pol:1; + /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0; + * It is the idle value of LCD_DE. + */ + uint32_t lcd_de_idle_pol:1; + /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0; + * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC + * pulse is valid only in active region lines in RGB mode. + */ + uint32_t lcd_hs_blank_en:1; + uint32_t reserved_10:6; + /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; + * It is the position of LCD_HSYNC active pulse in a line. + */ + uint32_t lcd_hsync_width:7; + /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0; + * It is the idle value of LCD_HSYNC. + */ + uint32_t lcd_hsync_idle_pol:1; + /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0; + * It is the position of LCD_HSYNC active pulse in a line. + */ + uint32_t lcd_hsync_position:8; + }; + uint32_t val; +} lcdcam_lcd_ctrl2_reg_t; + +/** Type of lcd_first_cmd_val register + * LCD config register. + */ +typedef union { + struct { + /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of first cmd cycle. + */ + uint32_t lcd_first_cmd_value:32; + }; + uint32_t val; +} lcdcam_lcd_first_cmd_val_reg_t; + +/** Type of lcd_latter_cmd_val register + * LCD config register. + */ +typedef union { + struct { + /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of latter cmd cycle. + */ + uint32_t lcd_latter_cmd_value:32; + }; + uint32_t val; +} lcdcam_lcd_latter_cmd_val_reg_t; + +/** Type of lcd_dly_mode_cfg1 register + * LCD config register. + */ +typedef union { + struct { + /** dout16_mode : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout16_mode:2; + /** dout17_mode : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout17_mode:2; + /** dout18_mode : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout18_mode:2; + /** dout19_mode : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout19_mode:2; + /** dout20_mode : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout20_mode:2; + /** dout21_mode : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout21_mode:2; + /** dout22_mode : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout22_mode:2; + /** dout23_mode : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout23_mode:2; + /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0; + * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_cd_mode:2; + /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0; + * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_de_mode:2; + /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0; + * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_hsync_mode:2; + /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0; + * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_vsync_mode:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} lcdcam_lcd_dly_mode_cfg1_reg_t; + +/** Type of lcd_dly_mode_cfg2 register + * LCD config register. + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout0_mode:2; + /** dout1_mode : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout1_mode:2; + /** dout2_mode : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout2_mode:2; + /** dout3_mode : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout3_mode:2; + /** dout4_mode : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout4_mode:2; + /** dout5_mode : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout5_mode:2; + /** dout6_mode : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout6_mode:2; + /** dout7_mode : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout7_mode:2; + /** dout8_mode : R/W; bitpos: [17:16]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout8_mode:2; + /** dout9_mode : R/W; bitpos: [19:18]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout9_mode:2; + /** dout10_mode : R/W; bitpos: [21:20]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout10_mode:2; + /** dout11_mode : R/W; bitpos: [23:22]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout11_mode:2; + /** dout12_mode : R/W; bitpos: [25:24]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout12_mode:2; + /** dout13_mode : R/W; bitpos: [27:26]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout13_mode:2; + /** dout14_mode : R/W; bitpos: [29:28]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout14_mode:2; + /** dout15_mode : R/W; bitpos: [31:30]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout15_mode:2; + }; + uint32_t val; +} lcdcam_lcd_dly_mode_cfg2_reg_t; + + +/** Group: cam configuration registers */ +/** Type of cam_ctrl register + * CAM config register. + */ +typedef union { + struct { + /** cam_stop_en : R/W; bitpos: [0]; default: 0; + * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + */ + uint32_t cam_stop_en:1; + /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0; + * Filter threshold value for CAM_VSYNC signal. + */ + uint32_t cam_vsync_filter_thres:3; + /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0; + * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + */ + uint32_t cam_update_reg:1; + /** cam_byte_order : R/W; bitpos: [5]; default: 0; + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ + uint32_t cam_byte_order:1; + /** cam_bit_order : R/W; bitpos: [6]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ + uint32_t cam_bit_order:1; + /** cam_line_int_en : R/W; bitpos: [7]; default: 0; + * 1: Enable to generate CAM_HS_INT. 0: Disable. + */ + uint32_t cam_line_int_en:1; + /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0; + * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by + * reg_cam_rec_data_cyclelen. + */ + uint32_t cam_vs_eof_en:1; + /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4; + * Integral Camera clock divider value + */ + uint32_t cam_clkm_div_num:8; + /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t cam_clkm_div_b:6; + /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t cam_clkm_div_a:6; + /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0; + * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ + uint32_t cam_clk_sel:2; + uint32_t reserved_31:1; + }; + uint32_t val; +} lcdcam_cam_ctrl_reg_t; + +/** Type of cam_ctrl1 register + * CAM config register. + */ +typedef union { + struct { + /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0; + * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + */ + uint32_t cam_rec_data_bytelen:16; + /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0; + * The line number minus 1 to generate cam_hs_int. + */ + uint32_t cam_line_int_num:6; + /** cam_clk_inv : R/W; bitpos: [22]; default: 0; + * 1: Invert the input signal CAM_PCLK. 0: Not invert. + */ + uint32_t cam_clk_inv:1; + /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0; + * 1: Enable CAM_VSYNC filter function. 0: bypass. + */ + uint32_t cam_vsync_filter_en:1; + /** cam_2byte_en : R/W; bitpos: [24]; default: 0; + * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + */ + uint32_t cam_2byte_en:1; + /** cam_de_inv : R/W; bitpos: [25]; default: 0; + * CAM_DE invert enable signal, valid in high level. + */ + uint32_t cam_de_inv:1; + /** cam_hsync_inv : R/W; bitpos: [26]; default: 0; + * CAM_HSYNC invert enable signal, valid in high level. + */ + uint32_t cam_hsync_inv:1; + /** cam_vsync_inv : R/W; bitpos: [27]; default: 0; + * CAM_VSYNC invert enable signal, valid in high level. + */ + uint32_t cam_vsync_inv:1; + /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0; + * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control + * signals are CAM_DE and CAM_VSYNC. + */ + uint32_t cam_vh_de_mode_en:1; + /** cam_start : R/W/SC; bitpos: [29]; default: 0; + * Camera module start signal. + */ + uint32_t cam_start:1; + /** cam_reset : WT; bitpos: [30]; default: 0; + * Camera module reset signal. + */ + uint32_t cam_reset:1; + /** cam_afifo_reset : WT; bitpos: [31]; default: 0; + * Camera AFIFO reset signal. + */ + uint32_t cam_afifo_reset:1; + }; + uint32_t val; +} lcdcam_cam_ctrl1_reg_t; + +/** Type of cam_rgb_yuv register + * CAM YUV/RGB converter configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ + uint32_t cam_conv_8bits_data_inv:1; + /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ + uint32_t cam_conv_yuv2yuv_mode:2; + /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ + uint32_t cam_conv_yuv_mode:2; + /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ + uint32_t cam_conv_protocol_mode:1; + /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ + uint32_t cam_conv_data_out_mode:1; + /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ + uint32_t cam_conv_data_in_mode:1; + /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ + uint32_t cam_conv_mode_8bits_on:1; + /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ + uint32_t cam_conv_trans_mode:1; + /** cam_conv_enable : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ + uint32_t cam_conv_enable:1; + }; + uint32_t val; +} lcdcam_cam_rgb_yuv_reg_t; + + +/** Group: Interrupt registers */ +/** Type of lc_dma_int_ena register + * LCDCAM interrupt enable register. + */ +typedef union { + struct { + /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_ena:1; + /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_ena:1; + /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_ena:1; + /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for Camera line interrupt. + */ + uint32_t cam_hs_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_ena_reg_t; + +/** Type of lc_dma_int_raw register + * LCDCAM interrupt raw register, valid in level. + */ +typedef union { + struct { + /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_raw:1; + /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_raw:1; + /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_raw:1; + /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for Camera line interrupt. + */ + uint32_t cam_hs_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_raw_reg_t; + +/** Type of lc_dma_int_st register + * LCDCAM interrupt status register. + */ +typedef union { + struct { + /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0; + * The status bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_st:1; + /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0; + * The status bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_st:1; + /** cam_vsync_int_st : RO; bitpos: [2]; default: 0; + * The status bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_st:1; + /** cam_hs_int_st : RO; bitpos: [3]; default: 0; + * The status bit for Camera transfer end interrupt. + */ + uint32_t cam_hs_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_st_reg_t; + +/** Type of lc_dma_int_clr register + * LCDCAM interrupt clear register. + */ +typedef union { + struct { + /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_clr:1; + /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_clr:1; + /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_clr:1; + /** cam_hs_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for Camera line interrupt. + */ + uint32_t cam_hs_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_clr_reg_t; + + +/** Group: Version register */ +/** Type of lc_reg_date register + * Version register + */ +typedef union { + struct { + /** lc_date : R/W; bitpos: [27:0]; default: 36712592; + * LCD_CAM version control register + */ + uint32_t lc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lcdcam_lc_reg_date_reg_t; + + +typedef struct lcdcam_dev_t { + volatile lcdcam_lcd_clock_reg_t lcd_clock; + volatile lcdcam_cam_ctrl_reg_t cam_ctrl; + volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1; + volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv; + volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv; + volatile lcdcam_lcd_user_reg_t lcd_user; + volatile lcdcam_lcd_misc_reg_t lcd_misc; + volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl; + volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1; + volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2; + volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val; + volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val; + volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1; + uint32_t reserved_034; + volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2; + uint32_t reserved_03c[10]; + volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena; + volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw; + volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st; + volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr; + uint32_t reserved_074[34]; + volatile lcdcam_lc_reg_date_reg_t lc_reg_date; +} lcdcam_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_LCD_CAM_STRUCT_H_ */ diff --git a/components/soc/esp32p4/include/soc/lcdcam_reg.h b/components/soc/esp32p4/include/soc/lcdcam_reg.h deleted file mode 100644 index 7a2f8ed19a..0000000000 --- a/components/soc/esp32p4/include/soc/lcdcam_reg.h +++ /dev/null @@ -1,1145 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LCDCAM_LCD_CLOCK_REG register - * LCD clock config register. - */ -#define LCDCAM_LCD_CLOCK_REG (DR_REG_LCDCAM_BASE + 0x0) -/** LCDCAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3; - * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. - */ -#define LCDCAM_LCD_CLKCNT_N 0x0000003FU -#define LCDCAM_LCD_CLKCNT_N_M (LCDCAM_LCD_CLKCNT_N_V << LCDCAM_LCD_CLKCNT_N_S) -#define LCDCAM_LCD_CLKCNT_N_V 0x0000003FU -#define LCDCAM_LCD_CLKCNT_N_S 0 -/** LCDCAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1; - * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). - */ -#define LCDCAM_LCD_CLK_EQU_SYSCLK (BIT(6)) -#define LCDCAM_LCD_CLK_EQU_SYSCLK_M (LCDCAM_LCD_CLK_EQU_SYSCLK_V << LCDCAM_LCD_CLK_EQU_SYSCLK_S) -#define LCDCAM_LCD_CLK_EQU_SYSCLK_V 0x00000001U -#define LCDCAM_LCD_CLK_EQU_SYSCLK_S 6 -/** LCDCAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0; - * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. - */ -#define LCDCAM_LCD_CK_IDLE_EDGE (BIT(7)) -#define LCDCAM_LCD_CK_IDLE_EDGE_M (LCDCAM_LCD_CK_IDLE_EDGE_V << LCDCAM_LCD_CK_IDLE_EDGE_S) -#define LCDCAM_LCD_CK_IDLE_EDGE_V 0x00000001U -#define LCDCAM_LCD_CK_IDLE_EDGE_S 7 -/** LCDCAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0; - * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low - * in the second half data cycle. - */ -#define LCDCAM_LCD_CK_OUT_EDGE (BIT(8)) -#define LCDCAM_LCD_CK_OUT_EDGE_M (LCDCAM_LCD_CK_OUT_EDGE_V << LCDCAM_LCD_CK_OUT_EDGE_S) -#define LCDCAM_LCD_CK_OUT_EDGE_V 0x00000001U -#define LCDCAM_LCD_CK_OUT_EDGE_S 8 -/** LCDCAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; - * Integral LCD clock divider value - */ -#define LCDCAM_LCD_CLKM_DIV_NUM 0x000000FFU -#define LCDCAM_LCD_CLKM_DIV_NUM_M (LCDCAM_LCD_CLKM_DIV_NUM_V << LCDCAM_LCD_CLKM_DIV_NUM_S) -#define LCDCAM_LCD_CLKM_DIV_NUM_V 0x000000FFU -#define LCDCAM_LCD_CLKM_DIV_NUM_S 9 -/** LCDCAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value - */ -#define LCDCAM_LCD_CLKM_DIV_B 0x0000003FU -#define LCDCAM_LCD_CLKM_DIV_B_M (LCDCAM_LCD_CLKM_DIV_B_V << LCDCAM_LCD_CLKM_DIV_B_S) -#define LCDCAM_LCD_CLKM_DIV_B_V 0x0000003FU -#define LCDCAM_LCD_CLKM_DIV_B_S 17 -/** LCDCAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value - */ -#define LCDCAM_LCD_CLKM_DIV_A 0x0000003FU -#define LCDCAM_LCD_CLKM_DIV_A_M (LCDCAM_LCD_CLKM_DIV_A_V << LCDCAM_LCD_CLKM_DIV_A_S) -#define LCDCAM_LCD_CLKM_DIV_A_V 0x0000003FU -#define LCDCAM_LCD_CLKM_DIV_A_S 23 -/** LCDCAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0; - * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - */ -#define LCDCAM_LCD_CLK_SEL 0x00000003U -#define LCDCAM_LCD_CLK_SEL_M (LCDCAM_LCD_CLK_SEL_V << LCDCAM_LCD_CLK_SEL_S) -#define LCDCAM_LCD_CLK_SEL_V 0x00000003U -#define LCDCAM_LCD_CLK_SEL_S 29 -/** LCDCAM_CLK_EN : R/W; bitpos: [31]; default: 0; - * Set this bit to enable clk gate - */ -#define LCDCAM_CLK_EN (BIT(31)) -#define LCDCAM_CLK_EN_M (LCDCAM_CLK_EN_V << LCDCAM_CLK_EN_S) -#define LCDCAM_CLK_EN_V 0x00000001U -#define LCDCAM_CLK_EN_S 31 - -/** LCDCAM_CAM_CTRL_REG register - * CAM config register. - */ -#define LCDCAM_CAM_CTRL_REG (DR_REG_LCDCAM_BASE + 0x4) -/** LCDCAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0; - * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. - */ -#define LCDCAM_CAM_STOP_EN (BIT(0)) -#define LCDCAM_CAM_STOP_EN_M (LCDCAM_CAM_STOP_EN_V << LCDCAM_CAM_STOP_EN_S) -#define LCDCAM_CAM_STOP_EN_V 0x00000001U -#define LCDCAM_CAM_STOP_EN_S 0 -/** LCDCAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0; - * Filter threshold value for CAM_VSYNC signal. - */ -#define LCDCAM_CAM_VSYNC_FILTER_THRES 0x00000007U -#define LCDCAM_CAM_VSYNC_FILTER_THRES_M (LCDCAM_CAM_VSYNC_FILTER_THRES_V << LCDCAM_CAM_VSYNC_FILTER_THRES_S) -#define LCDCAM_CAM_VSYNC_FILTER_THRES_V 0x00000007U -#define LCDCAM_CAM_VSYNC_FILTER_THRES_S 1 -/** LCDCAM_CAM_UPDATE_REG : R/W/SC; bitpos: [4]; default: 0; - * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. - */ -#define LCDCAM_CAM_UPDATE_REG (BIT(4)) -#define LCDCAM_CAM_UPDATE_REG_M (LCDCAM_CAM_UPDATE_REG_V << LCDCAM_CAM_UPDATE_REG_S) -#define LCDCAM_CAM_UPDATE_REG_V 0x00000001U -#define LCDCAM_CAM_UPDATE_REG_S 4 -/** LCDCAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0; - * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - */ -#define LCDCAM_CAM_BYTE_ORDER (BIT(5)) -#define LCDCAM_CAM_BYTE_ORDER_M (LCDCAM_CAM_BYTE_ORDER_V << LCDCAM_CAM_BYTE_ORDER_S) -#define LCDCAM_CAM_BYTE_ORDER_V 0x00000001U -#define LCDCAM_CAM_BYTE_ORDER_S 5 -/** LCDCAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. - */ -#define LCDCAM_CAM_BIT_ORDER (BIT(6)) -#define LCDCAM_CAM_BIT_ORDER_M (LCDCAM_CAM_BIT_ORDER_V << LCDCAM_CAM_BIT_ORDER_S) -#define LCDCAM_CAM_BIT_ORDER_V 0x00000001U -#define LCDCAM_CAM_BIT_ORDER_S 6 -/** LCDCAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0; - * 1: Enable to generate CAM_HS_INT. 0: Disable. - */ -#define LCDCAM_CAM_LINE_INT_EN (BIT(7)) -#define LCDCAM_CAM_LINE_INT_EN_M (LCDCAM_CAM_LINE_INT_EN_V << LCDCAM_CAM_LINE_INT_EN_S) -#define LCDCAM_CAM_LINE_INT_EN_V 0x00000001U -#define LCDCAM_CAM_LINE_INT_EN_S 7 -/** LCDCAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0; - * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by - * reg_cam_rec_data_cyclelen. - */ -#define LCDCAM_CAM_VS_EOF_EN (BIT(8)) -#define LCDCAM_CAM_VS_EOF_EN_M (LCDCAM_CAM_VS_EOF_EN_V << LCDCAM_CAM_VS_EOF_EN_S) -#define LCDCAM_CAM_VS_EOF_EN_V 0x00000001U -#define LCDCAM_CAM_VS_EOF_EN_S 8 -/** LCDCAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; - * Integral Camera clock divider value - */ -#define LCDCAM_CAM_CLKM_DIV_NUM 0x000000FFU -#define LCDCAM_CAM_CLKM_DIV_NUM_M (LCDCAM_CAM_CLKM_DIV_NUM_V << LCDCAM_CAM_CLKM_DIV_NUM_S) -#define LCDCAM_CAM_CLKM_DIV_NUM_V 0x000000FFU -#define LCDCAM_CAM_CLKM_DIV_NUM_S 9 -/** LCDCAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value - */ -#define LCDCAM_CAM_CLKM_DIV_B 0x0000003FU -#define LCDCAM_CAM_CLKM_DIV_B_M (LCDCAM_CAM_CLKM_DIV_B_V << LCDCAM_CAM_CLKM_DIV_B_S) -#define LCDCAM_CAM_CLKM_DIV_B_V 0x0000003FU -#define LCDCAM_CAM_CLKM_DIV_B_S 17 -/** LCDCAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value - */ -#define LCDCAM_CAM_CLKM_DIV_A 0x0000003FU -#define LCDCAM_CAM_CLKM_DIV_A_M (LCDCAM_CAM_CLKM_DIV_A_V << LCDCAM_CAM_CLKM_DIV_A_S) -#define LCDCAM_CAM_CLKM_DIV_A_V 0x0000003FU -#define LCDCAM_CAM_CLKM_DIV_A_S 23 -/** LCDCAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0; - * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - */ -#define LCDCAM_CAM_CLK_SEL 0x00000003U -#define LCDCAM_CAM_CLK_SEL_M (LCDCAM_CAM_CLK_SEL_V << LCDCAM_CAM_CLK_SEL_S) -#define LCDCAM_CAM_CLK_SEL_V 0x00000003U -#define LCDCAM_CAM_CLK_SEL_S 29 - -/** LCDCAM_CAM_CTRL1_REG register - * CAM config register. - */ -#define LCDCAM_CAM_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x8) -/** LCDCAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0; - * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. - */ -#define LCDCAM_CAM_REC_DATA_BYTELEN 0x0000FFFFU -#define LCDCAM_CAM_REC_DATA_BYTELEN_M (LCDCAM_CAM_REC_DATA_BYTELEN_V << LCDCAM_CAM_REC_DATA_BYTELEN_S) -#define LCDCAM_CAM_REC_DATA_BYTELEN_V 0x0000FFFFU -#define LCDCAM_CAM_REC_DATA_BYTELEN_S 0 -/** LCDCAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0; - * The line number minus 1 to generate cam_hs_int. - */ -#define LCDCAM_CAM_LINE_INT_NUM 0x0000003FU -#define LCDCAM_CAM_LINE_INT_NUM_M (LCDCAM_CAM_LINE_INT_NUM_V << LCDCAM_CAM_LINE_INT_NUM_S) -#define LCDCAM_CAM_LINE_INT_NUM_V 0x0000003FU -#define LCDCAM_CAM_LINE_INT_NUM_S 16 -/** LCDCAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0; - * 1: Invert the input signal CAM_PCLK. 0: Not invert. - */ -#define LCDCAM_CAM_CLK_INV (BIT(22)) -#define LCDCAM_CAM_CLK_INV_M (LCDCAM_CAM_CLK_INV_V << LCDCAM_CAM_CLK_INV_S) -#define LCDCAM_CAM_CLK_INV_V 0x00000001U -#define LCDCAM_CAM_CLK_INV_S 22 -/** LCDCAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0; - * 1: Enable CAM_VSYNC filter function. 0: bypass. - */ -#define LCDCAM_CAM_VSYNC_FILTER_EN (BIT(23)) -#define LCDCAM_CAM_VSYNC_FILTER_EN_M (LCDCAM_CAM_VSYNC_FILTER_EN_V << LCDCAM_CAM_VSYNC_FILTER_EN_S) -#define LCDCAM_CAM_VSYNC_FILTER_EN_V 0x00000001U -#define LCDCAM_CAM_VSYNC_FILTER_EN_S 23 -/** LCDCAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0; - * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. - */ -#define LCDCAM_CAM_2BYTE_EN (BIT(24)) -#define LCDCAM_CAM_2BYTE_EN_M (LCDCAM_CAM_2BYTE_EN_V << LCDCAM_CAM_2BYTE_EN_S) -#define LCDCAM_CAM_2BYTE_EN_V 0x00000001U -#define LCDCAM_CAM_2BYTE_EN_S 24 -/** LCDCAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0; - * CAM_DE invert enable signal, valid in high level. - */ -#define LCDCAM_CAM_DE_INV (BIT(25)) -#define LCDCAM_CAM_DE_INV_M (LCDCAM_CAM_DE_INV_V << LCDCAM_CAM_DE_INV_S) -#define LCDCAM_CAM_DE_INV_V 0x00000001U -#define LCDCAM_CAM_DE_INV_S 25 -/** LCDCAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0; - * CAM_HSYNC invert enable signal, valid in high level. - */ -#define LCDCAM_CAM_HSYNC_INV (BIT(26)) -#define LCDCAM_CAM_HSYNC_INV_M (LCDCAM_CAM_HSYNC_INV_V << LCDCAM_CAM_HSYNC_INV_S) -#define LCDCAM_CAM_HSYNC_INV_V 0x00000001U -#define LCDCAM_CAM_HSYNC_INV_S 26 -/** LCDCAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0; - * CAM_VSYNC invert enable signal, valid in high level. - */ -#define LCDCAM_CAM_VSYNC_INV (BIT(27)) -#define LCDCAM_CAM_VSYNC_INV_M (LCDCAM_CAM_VSYNC_INV_V << LCDCAM_CAM_VSYNC_INV_S) -#define LCDCAM_CAM_VSYNC_INV_V 0x00000001U -#define LCDCAM_CAM_VSYNC_INV_S 27 -/** LCDCAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0; - * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control - * signals are CAM_DE and CAM_VSYNC. - */ -#define LCDCAM_CAM_VH_DE_MODE_EN (BIT(28)) -#define LCDCAM_CAM_VH_DE_MODE_EN_M (LCDCAM_CAM_VH_DE_MODE_EN_V << LCDCAM_CAM_VH_DE_MODE_EN_S) -#define LCDCAM_CAM_VH_DE_MODE_EN_V 0x00000001U -#define LCDCAM_CAM_VH_DE_MODE_EN_S 28 -/** LCDCAM_CAM_START : R/W/SC; bitpos: [29]; default: 0; - * Camera module start signal. - */ -#define LCDCAM_CAM_START (BIT(29)) -#define LCDCAM_CAM_START_M (LCDCAM_CAM_START_V << LCDCAM_CAM_START_S) -#define LCDCAM_CAM_START_V 0x00000001U -#define LCDCAM_CAM_START_S 29 -/** LCDCAM_CAM_RESET : WT; bitpos: [30]; default: 0; - * Camera module reset signal. - */ -#define LCDCAM_CAM_RESET (BIT(30)) -#define LCDCAM_CAM_RESET_M (LCDCAM_CAM_RESET_V << LCDCAM_CAM_RESET_S) -#define LCDCAM_CAM_RESET_V 0x00000001U -#define LCDCAM_CAM_RESET_S 30 -/** LCDCAM_CAM_AFIFO_RESET : WT; bitpos: [31]; default: 0; - * Camera AFIFO reset signal. - */ -#define LCDCAM_CAM_AFIFO_RESET (BIT(31)) -#define LCDCAM_CAM_AFIFO_RESET_M (LCDCAM_CAM_AFIFO_RESET_V << LCDCAM_CAM_AFIFO_RESET_S) -#define LCDCAM_CAM_AFIFO_RESET_V 0x00000001U -#define LCDCAM_CAM_AFIFO_RESET_S 31 - -/** LCDCAM_CAM_RGB_YUV_REG register - * CAM YUV/RGB converter configuration register. - */ -#define LCDCAM_CAM_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0xc) -/** LCDCAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. - */ -#define LCDCAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) -#define LCDCAM_CAM_CONV_8BITS_DATA_INV_M (LCDCAM_CAM_CONV_8BITS_DATA_INV_V << LCDCAM_CAM_CONV_8BITS_DATA_INV_S) -#define LCDCAM_CAM_CONV_8BITS_DATA_INV_V 0x00000001U -#define LCDCAM_CAM_CONV_8BITS_DATA_INV_S 21 -/** LCDCAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. - */ -#define LCDCAM_CAM_CONV_YUV2YUV_MODE 0x00000003U -#define LCDCAM_CAM_CONV_YUV2YUV_MODE_M (LCDCAM_CAM_CONV_YUV2YUV_MODE_V << LCDCAM_CAM_CONV_YUV2YUV_MODE_S) -#define LCDCAM_CAM_CONV_YUV2YUV_MODE_V 0x00000003U -#define LCDCAM_CAM_CONV_YUV2YUV_MODE_S 22 -/** LCDCAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in - */ -#define LCDCAM_CAM_CONV_YUV_MODE 0x00000003U -#define LCDCAM_CAM_CONV_YUV_MODE_M (LCDCAM_CAM_CONV_YUV_MODE_V << LCDCAM_CAM_CONV_YUV_MODE_S) -#define LCDCAM_CAM_CONV_YUV_MODE_V 0x00000003U -#define LCDCAM_CAM_CONV_YUV_MODE_S 24 -/** LCDCAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. - */ -#define LCDCAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) -#define LCDCAM_CAM_CONV_PROTOCOL_MODE_M (LCDCAM_CAM_CONV_PROTOCOL_MODE_V << LCDCAM_CAM_CONV_PROTOCOL_MODE_S) -#define LCDCAM_CAM_CONV_PROTOCOL_MODE_V 0x00000001U -#define LCDCAM_CAM_CONV_PROTOCOL_MODE_S 26 -/** LCDCAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full - */ -#define LCDCAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) -#define LCDCAM_CAM_CONV_DATA_OUT_MODE_M (LCDCAM_CAM_CONV_DATA_OUT_MODE_V << LCDCAM_CAM_CONV_DATA_OUT_MODE_S) -#define LCDCAM_CAM_CONV_DATA_OUT_MODE_V 0x00000001U -#define LCDCAM_CAM_CONV_DATA_OUT_MODE_S 27 -/** LCDCAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full - */ -#define LCDCAM_CAM_CONV_DATA_IN_MODE (BIT(28)) -#define LCDCAM_CAM_CONV_DATA_IN_MODE_M (LCDCAM_CAM_CONV_DATA_IN_MODE_V << LCDCAM_CAM_CONV_DATA_IN_MODE_S) -#define LCDCAM_CAM_CONV_DATA_IN_MODE_V 0x00000001U -#define LCDCAM_CAM_CONV_DATA_IN_MODE_S 28 -/** LCDCAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. - */ -#define LCDCAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) -#define LCDCAM_CAM_CONV_MODE_8BITS_ON_M (LCDCAM_CAM_CONV_MODE_8BITS_ON_V << LCDCAM_CAM_CONV_MODE_8BITS_ON_S) -#define LCDCAM_CAM_CONV_MODE_8BITS_ON_V 0x00000001U -#define LCDCAM_CAM_CONV_MODE_8BITS_ON_S 29 -/** LCDCAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. - */ -#define LCDCAM_CAM_CONV_TRANS_MODE (BIT(30)) -#define LCDCAM_CAM_CONV_TRANS_MODE_M (LCDCAM_CAM_CONV_TRANS_MODE_V << LCDCAM_CAM_CONV_TRANS_MODE_S) -#define LCDCAM_CAM_CONV_TRANS_MODE_V 0x00000001U -#define LCDCAM_CAM_CONV_TRANS_MODE_S 30 -/** LCDCAM_CAM_CONV_ENABLE : R/W; bitpos: [31]; default: 0; - * 0: Bypass converter. 1: Enable converter. - */ -#define LCDCAM_CAM_CONV_ENABLE (BIT(31)) -#define LCDCAM_CAM_CONV_ENABLE_M (LCDCAM_CAM_CONV_ENABLE_V << LCDCAM_CAM_CONV_ENABLE_S) -#define LCDCAM_CAM_CONV_ENABLE_V 0x00000001U -#define LCDCAM_CAM_CONV_ENABLE_S 31 - -/** LCDCAM_LCD_RGB_YUV_REG register - * LCD YUV/RGB converter configuration register. - */ -#define LCDCAM_LCD_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0x10) -/** LCDCAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. - */ -#define LCDCAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) -#define LCDCAM_LCD_CONV_8BITS_DATA_INV_M (LCDCAM_LCD_CONV_8BITS_DATA_INV_V << LCDCAM_LCD_CONV_8BITS_DATA_INV_S) -#define LCDCAM_LCD_CONV_8BITS_DATA_INV_V 0x00000001U -#define LCDCAM_LCD_CONV_8BITS_DATA_INV_S 20 -/** LCDCAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0; - * 0: txtorx mode off. 1: txtorx mode on. - */ -#define LCDCAM_LCD_CONV_TXTORX (BIT(21)) -#define LCDCAM_LCD_CONV_TXTORX_M (LCDCAM_LCD_CONV_TXTORX_V << LCDCAM_LCD_CONV_TXTORX_S) -#define LCDCAM_LCD_CONV_TXTORX_V 0x00000001U -#define LCDCAM_LCD_CONV_TXTORX_S 21 -/** LCDCAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. - */ -#define LCDCAM_LCD_CONV_YUV2YUV_MODE 0x00000003U -#define LCDCAM_LCD_CONV_YUV2YUV_MODE_M (LCDCAM_LCD_CONV_YUV2YUV_MODE_V << LCDCAM_LCD_CONV_YUV2YUV_MODE_S) -#define LCDCAM_LCD_CONV_YUV2YUV_MODE_V 0x00000003U -#define LCDCAM_LCD_CONV_YUV2YUV_MODE_S 22 -/** LCDCAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in - */ -#define LCDCAM_LCD_CONV_YUV_MODE 0x00000003U -#define LCDCAM_LCD_CONV_YUV_MODE_M (LCDCAM_LCD_CONV_YUV_MODE_V << LCDCAM_LCD_CONV_YUV_MODE_S) -#define LCDCAM_LCD_CONV_YUV_MODE_V 0x00000003U -#define LCDCAM_LCD_CONV_YUV_MODE_S 24 -/** LCDCAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. - */ -#define LCDCAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) -#define LCDCAM_LCD_CONV_PROTOCOL_MODE_M (LCDCAM_LCD_CONV_PROTOCOL_MODE_V << LCDCAM_LCD_CONV_PROTOCOL_MODE_S) -#define LCDCAM_LCD_CONV_PROTOCOL_MODE_V 0x00000001U -#define LCDCAM_LCD_CONV_PROTOCOL_MODE_S 26 -/** LCDCAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full - */ -#define LCDCAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) -#define LCDCAM_LCD_CONV_DATA_OUT_MODE_M (LCDCAM_LCD_CONV_DATA_OUT_MODE_V << LCDCAM_LCD_CONV_DATA_OUT_MODE_S) -#define LCDCAM_LCD_CONV_DATA_OUT_MODE_V 0x00000001U -#define LCDCAM_LCD_CONV_DATA_OUT_MODE_S 27 -/** LCDCAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full - */ -#define LCDCAM_LCD_CONV_DATA_IN_MODE (BIT(28)) -#define LCDCAM_LCD_CONV_DATA_IN_MODE_M (LCDCAM_LCD_CONV_DATA_IN_MODE_V << LCDCAM_LCD_CONV_DATA_IN_MODE_S) -#define LCDCAM_LCD_CONV_DATA_IN_MODE_V 0x00000001U -#define LCDCAM_LCD_CONV_DATA_IN_MODE_S 28 -/** LCDCAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. - */ -#define LCDCAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) -#define LCDCAM_LCD_CONV_MODE_8BITS_ON_M (LCDCAM_LCD_CONV_MODE_8BITS_ON_V << LCDCAM_LCD_CONV_MODE_8BITS_ON_S) -#define LCDCAM_LCD_CONV_MODE_8BITS_ON_V 0x00000001U -#define LCDCAM_LCD_CONV_MODE_8BITS_ON_S 29 -/** LCDCAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. - */ -#define LCDCAM_LCD_CONV_TRANS_MODE (BIT(30)) -#define LCDCAM_LCD_CONV_TRANS_MODE_M (LCDCAM_LCD_CONV_TRANS_MODE_V << LCDCAM_LCD_CONV_TRANS_MODE_S) -#define LCDCAM_LCD_CONV_TRANS_MODE_V 0x00000001U -#define LCDCAM_LCD_CONV_TRANS_MODE_S 30 -/** LCDCAM_LCD_CONV_ENABLE : R/W; bitpos: [31]; default: 0; - * 0: Bypass converter. 1: Enable converter. - */ -#define LCDCAM_LCD_CONV_ENABLE (BIT(31)) -#define LCDCAM_LCD_CONV_ENABLE_M (LCDCAM_LCD_CONV_ENABLE_V << LCDCAM_LCD_CONV_ENABLE_S) -#define LCDCAM_LCD_CONV_ENABLE_V 0x00000001U -#define LCDCAM_LCD_CONV_ENABLE_S 31 - -/** LCDCAM_LCD_USER_REG register - * LCD config register. - */ -#define LCDCAM_LCD_USER_REG (DR_REG_LCDCAM_BASE + 0x14) -/** LCDCAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1; - * The output data cycles minus 1 of LCD module. - */ -#define LCDCAM_LCD_DOUT_CYCLELEN 0x00001FFFU -#define LCDCAM_LCD_DOUT_CYCLELEN_M (LCDCAM_LCD_DOUT_CYCLELEN_V << LCDCAM_LCD_DOUT_CYCLELEN_S) -#define LCDCAM_LCD_DOUT_CYCLELEN_V 0x00001FFFU -#define LCDCAM_LCD_DOUT_CYCLELEN_S 0 -/** LCDCAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0; - * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or - * reg_lcd_reset is set. - */ -#define LCDCAM_LCD_ALWAYS_OUT_EN (BIT(13)) -#define LCDCAM_LCD_ALWAYS_OUT_EN_M (LCDCAM_LCD_ALWAYS_OUT_EN_V << LCDCAM_LCD_ALWAYS_OUT_EN_S) -#define LCDCAM_LCD_ALWAYS_OUT_EN_V 0x00000001U -#define LCDCAM_LCD_ALWAYS_OUT_EN_S 13 -/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W; bitpos: [16:14]; default: 0; - * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA - */ -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE 0x00000007U -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S) -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V 0x00000007U -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S 14 -/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W; bitpos: [17]; default: 0; - * 1: enable byte swizzle 0: disable - */ -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE (BIT(17)) -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S) -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V 0x00000001U -#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S 17 -/** LCDCAM_LCD_DOUT_BIT_ORDER : R/W; bitpos: [18]; default: 0; - * 1: change bit order in every byte. 0: Not change. - */ -#define LCDCAM_LCD_DOUT_BIT_ORDER (BIT(18)) -#define LCDCAM_LCD_DOUT_BIT_ORDER_M (LCDCAM_LCD_DOUT_BIT_ORDER_V << LCDCAM_LCD_DOUT_BIT_ORDER_S) -#define LCDCAM_LCD_DOUT_BIT_ORDER_V 0x00000001U -#define LCDCAM_LCD_DOUT_BIT_ORDER_S 18 -/** LCDCAM_LCD_BYTE_MODE : R/W; bitpos: [20:19]; default: 0; - * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode - */ -#define LCDCAM_LCD_BYTE_MODE 0x00000003U -#define LCDCAM_LCD_BYTE_MODE_M (LCDCAM_LCD_BYTE_MODE_V << LCDCAM_LCD_BYTE_MODE_S) -#define LCDCAM_LCD_BYTE_MODE_V 0x00000003U -#define LCDCAM_LCD_BYTE_MODE_S 19 -/** LCDCAM_LCD_UPDATE_REG : R/W/SC; bitpos: [21]; default: 0; - * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. - */ -#define LCDCAM_LCD_UPDATE_REG (BIT(21)) -#define LCDCAM_LCD_UPDATE_REG_M (LCDCAM_LCD_UPDATE_REG_V << LCDCAM_LCD_UPDATE_REG_S) -#define LCDCAM_LCD_UPDATE_REG_V 0x00000001U -#define LCDCAM_LCD_UPDATE_REG_S 21 -/** LCDCAM_LCD_BIT_ORDER : R/W; bitpos: [22]; default: 0; - * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - */ -#define LCDCAM_LCD_BIT_ORDER (BIT(22)) -#define LCDCAM_LCD_BIT_ORDER_M (LCDCAM_LCD_BIT_ORDER_V << LCDCAM_LCD_BIT_ORDER_S) -#define LCDCAM_LCD_BIT_ORDER_V 0x00000001U -#define LCDCAM_LCD_BIT_ORDER_S 22 -/** LCDCAM_LCD_BYTE_ORDER : R/W; bitpos: [23]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. - */ -#define LCDCAM_LCD_BYTE_ORDER (BIT(23)) -#define LCDCAM_LCD_BYTE_ORDER_M (LCDCAM_LCD_BYTE_ORDER_V << LCDCAM_LCD_BYTE_ORDER_S) -#define LCDCAM_LCD_BYTE_ORDER_V 0x00000001U -#define LCDCAM_LCD_BYTE_ORDER_S 23 -/** LCDCAM_LCD_DOUT : R/W; bitpos: [24]; default: 0; - * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. - */ -#define LCDCAM_LCD_DOUT (BIT(24)) -#define LCDCAM_LCD_DOUT_M (LCDCAM_LCD_DOUT_V << LCDCAM_LCD_DOUT_S) -#define LCDCAM_LCD_DOUT_V 0x00000001U -#define LCDCAM_LCD_DOUT_S 24 -/** LCDCAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0; - * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. - */ -#define LCDCAM_LCD_DUMMY (BIT(25)) -#define LCDCAM_LCD_DUMMY_M (LCDCAM_LCD_DUMMY_V << LCDCAM_LCD_DUMMY_S) -#define LCDCAM_LCD_DUMMY_V 0x00000001U -#define LCDCAM_LCD_DUMMY_S 25 -/** LCDCAM_LCD_CMD : R/W; bitpos: [26]; default: 0; - * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. - */ -#define LCDCAM_LCD_CMD (BIT(26)) -#define LCDCAM_LCD_CMD_M (LCDCAM_LCD_CMD_V << LCDCAM_LCD_CMD_S) -#define LCDCAM_LCD_CMD_V 0x00000001U -#define LCDCAM_LCD_CMD_S 26 -/** LCDCAM_LCD_START : R/W/SC; bitpos: [27]; default: 0; - * LCD start sending data enable signal, valid in high level. - */ -#define LCDCAM_LCD_START (BIT(27)) -#define LCDCAM_LCD_START_M (LCDCAM_LCD_START_V << LCDCAM_LCD_START_S) -#define LCDCAM_LCD_START_V 0x00000001U -#define LCDCAM_LCD_START_S 27 -/** LCDCAM_LCD_RESET : WT; bitpos: [28]; default: 0; - * The value of command. - */ -#define LCDCAM_LCD_RESET (BIT(28)) -#define LCDCAM_LCD_RESET_M (LCDCAM_LCD_RESET_V << LCDCAM_LCD_RESET_S) -#define LCDCAM_LCD_RESET_V 0x00000001U -#define LCDCAM_LCD_RESET_S 28 -/** LCDCAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0; - * The dummy cycle length minus 1. - */ -#define LCDCAM_LCD_DUMMY_CYCLELEN 0x00000003U -#define LCDCAM_LCD_DUMMY_CYCLELEN_M (LCDCAM_LCD_DUMMY_CYCLELEN_V << LCDCAM_LCD_DUMMY_CYCLELEN_S) -#define LCDCAM_LCD_DUMMY_CYCLELEN_V 0x00000003U -#define LCDCAM_LCD_DUMMY_CYCLELEN_S 29 -/** LCDCAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0; - * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. - */ -#define LCDCAM_LCD_CMD_2_CYCLE_EN (BIT(31)) -#define LCDCAM_LCD_CMD_2_CYCLE_EN_M (LCDCAM_LCD_CMD_2_CYCLE_EN_V << LCDCAM_LCD_CMD_2_CYCLE_EN_S) -#define LCDCAM_LCD_CMD_2_CYCLE_EN_V 0x00000001U -#define LCDCAM_LCD_CMD_2_CYCLE_EN_S 31 - -/** LCDCAM_LCD_MISC_REG register - * LCD config register. - */ -#define LCDCAM_LCD_MISC_REG (DR_REG_LCDCAM_BASE + 0x18) -/** LCDCAM_LCD_WIRE_MODE : R/W; bitpos: [5:4]; default: 0; - * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit - */ -#define LCDCAM_LCD_WIRE_MODE 0x00000003U -#define LCDCAM_LCD_WIRE_MODE_M (LCDCAM_LCD_WIRE_MODE_V << LCDCAM_LCD_WIRE_MODE_S) -#define LCDCAM_LCD_WIRE_MODE_V 0x00000003U -#define LCDCAM_LCD_WIRE_MODE_S 4 -/** LCDCAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3; - * The setup cycle length minus 1 in LCD non-RGB mode. - */ -#define LCDCAM_LCD_VFK_CYCLELEN 0x0000003FU -#define LCDCAM_LCD_VFK_CYCLELEN_M (LCDCAM_LCD_VFK_CYCLELEN_V << LCDCAM_LCD_VFK_CYCLELEN_S) -#define LCDCAM_LCD_VFK_CYCLELEN_V 0x0000003FU -#define LCDCAM_LCD_VFK_CYCLELEN_S 6 -/** LCDCAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0; - * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold - * time cycle length in LCD non-RGB mode. - */ -#define LCDCAM_LCD_VBK_CYCLELEN 0x00001FFFU -#define LCDCAM_LCD_VBK_CYCLELEN_M (LCDCAM_LCD_VBK_CYCLELEN_V << LCDCAM_LCD_VBK_CYCLELEN_S) -#define LCDCAM_LCD_VBK_CYCLELEN_V 0x00001FFFU -#define LCDCAM_LCD_VBK_CYCLELEN_S 12 -/** LCDCAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0; - * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when - * the current frame is sent out. - */ -#define LCDCAM_LCD_NEXT_FRAME_EN (BIT(25)) -#define LCDCAM_LCD_NEXT_FRAME_EN_M (LCDCAM_LCD_NEXT_FRAME_EN_V << LCDCAM_LCD_NEXT_FRAME_EN_S) -#define LCDCAM_LCD_NEXT_FRAME_EN_V 0x00000001U -#define LCDCAM_LCD_NEXT_FRAME_EN_S 25 -/** LCDCAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0; - * 1: Enable blank region when LCD sends data out. 0: No blank region. - */ -#define LCDCAM_LCD_BK_EN (BIT(26)) -#define LCDCAM_LCD_BK_EN_M (LCDCAM_LCD_BK_EN_V << LCDCAM_LCD_BK_EN_S) -#define LCDCAM_LCD_BK_EN_V 0x00000001U -#define LCDCAM_LCD_BK_EN_S 26 -/** LCDCAM_LCD_AFIFO_RESET : WT; bitpos: [27]; default: 0; - * LCD AFIFO reset signal. - */ -#define LCDCAM_LCD_AFIFO_RESET (BIT(27)) -#define LCDCAM_LCD_AFIFO_RESET_M (LCDCAM_LCD_AFIFO_RESET_V << LCDCAM_LCD_AFIFO_RESET_S) -#define LCDCAM_LCD_AFIFO_RESET_V 0x00000001U -#define LCDCAM_LCD_AFIFO_RESET_S 27 -/** LCDCAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = - * reg_cd_idle_edge. - */ -#define LCDCAM_LCD_CD_DATA_SET (BIT(28)) -#define LCDCAM_LCD_CD_DATA_SET_M (LCDCAM_LCD_CD_DATA_SET_V << LCDCAM_LCD_CD_DATA_SET_S) -#define LCDCAM_LCD_CD_DATA_SET_V 0x00000001U -#define LCDCAM_LCD_CD_DATA_SET_S 28 -/** LCDCAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = - * reg_cd_idle_edge. - */ -#define LCDCAM_LCD_CD_DUMMY_SET (BIT(29)) -#define LCDCAM_LCD_CD_DUMMY_SET_M (LCDCAM_LCD_CD_DUMMY_SET_V << LCDCAM_LCD_CD_DUMMY_SET_S) -#define LCDCAM_LCD_CD_DUMMY_SET_V 0x00000001U -#define LCDCAM_LCD_CD_DUMMY_SET_S 29 -/** LCDCAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = - * reg_cd_idle_edge. - */ -#define LCDCAM_LCD_CD_CMD_SET (BIT(30)) -#define LCDCAM_LCD_CD_CMD_SET_M (LCDCAM_LCD_CD_CMD_SET_V << LCDCAM_LCD_CD_CMD_SET_S) -#define LCDCAM_LCD_CD_CMD_SET_V 0x00000001U -#define LCDCAM_LCD_CD_CMD_SET_S 30 -/** LCDCAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0; - * The default value of LCD_CD. - */ -#define LCDCAM_LCD_CD_IDLE_EDGE (BIT(31)) -#define LCDCAM_LCD_CD_IDLE_EDGE_M (LCDCAM_LCD_CD_IDLE_EDGE_V << LCDCAM_LCD_CD_IDLE_EDGE_S) -#define LCDCAM_LCD_CD_IDLE_EDGE_V 0x00000001U -#define LCDCAM_LCD_CD_IDLE_EDGE_S 31 - -/** LCDCAM_LCD_CTRL_REG register - * LCD config register. - */ -#define LCDCAM_LCD_CTRL_REG (DR_REG_LCDCAM_BASE + 0x1c) -/** LCDCAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0; - * It is the horizontal blank front porch of a frame. - */ -#define LCDCAM_LCD_HB_FRONT 0x000007FFU -#define LCDCAM_LCD_HB_FRONT_M (LCDCAM_LCD_HB_FRONT_V << LCDCAM_LCD_HB_FRONT_S) -#define LCDCAM_LCD_HB_FRONT_V 0x000007FFU -#define LCDCAM_LCD_HB_FRONT_S 0 -/** LCDCAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0; - * It is the vertical active height of a frame. - */ -#define LCDCAM_LCD_VA_HEIGHT 0x000003FFU -#define LCDCAM_LCD_VA_HEIGHT_M (LCDCAM_LCD_VA_HEIGHT_V << LCDCAM_LCD_VA_HEIGHT_S) -#define LCDCAM_LCD_VA_HEIGHT_V 0x000003FFU -#define LCDCAM_LCD_VA_HEIGHT_S 11 -/** LCDCAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0; - * It is the vertical total height of a frame. - */ -#define LCDCAM_LCD_VT_HEIGHT 0x000003FFU -#define LCDCAM_LCD_VT_HEIGHT_M (LCDCAM_LCD_VT_HEIGHT_V << LCDCAM_LCD_VT_HEIGHT_S) -#define LCDCAM_LCD_VT_HEIGHT_V 0x000003FFU -#define LCDCAM_LCD_VT_HEIGHT_S 21 -/** LCDCAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0; - * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. - */ -#define LCDCAM_LCD_RGB_MODE_EN (BIT(31)) -#define LCDCAM_LCD_RGB_MODE_EN_M (LCDCAM_LCD_RGB_MODE_EN_V << LCDCAM_LCD_RGB_MODE_EN_S) -#define LCDCAM_LCD_RGB_MODE_EN_V 0x00000001U -#define LCDCAM_LCD_RGB_MODE_EN_S 31 - -/** LCDCAM_LCD_CTRL1_REG register - * LCD config register. - */ -#define LCDCAM_LCD_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x20) -/** LCDCAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0; - * It is the vertical blank front porch of a frame. - */ -#define LCDCAM_LCD_VB_FRONT 0x000000FFU -#define LCDCAM_LCD_VB_FRONT_M (LCDCAM_LCD_VB_FRONT_V << LCDCAM_LCD_VB_FRONT_S) -#define LCDCAM_LCD_VB_FRONT_V 0x000000FFU -#define LCDCAM_LCD_VB_FRONT_S 0 -/** LCDCAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0; - * It is the horizontal active width of a frame. - */ -#define LCDCAM_LCD_HA_WIDTH 0x00000FFFU -#define LCDCAM_LCD_HA_WIDTH_M (LCDCAM_LCD_HA_WIDTH_V << LCDCAM_LCD_HA_WIDTH_S) -#define LCDCAM_LCD_HA_WIDTH_V 0x00000FFFU -#define LCDCAM_LCD_HA_WIDTH_S 8 -/** LCDCAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0; - * It is the horizontal total width of a frame. - */ -#define LCDCAM_LCD_HT_WIDTH 0x00000FFFU -#define LCDCAM_LCD_HT_WIDTH_M (LCDCAM_LCD_HT_WIDTH_V << LCDCAM_LCD_HT_WIDTH_S) -#define LCDCAM_LCD_HT_WIDTH_V 0x00000FFFU -#define LCDCAM_LCD_HT_WIDTH_S 20 - -/** LCDCAM_LCD_CTRL2_REG register - * LCD config register. - */ -#define LCDCAM_LCD_CTRL2_REG (DR_REG_LCDCAM_BASE + 0x24) -/** LCDCAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1; - * It is the position of LCD_VSYNC active pulse in a line. - */ -#define LCDCAM_LCD_VSYNC_WIDTH 0x0000007FU -#define LCDCAM_LCD_VSYNC_WIDTH_M (LCDCAM_LCD_VSYNC_WIDTH_V << LCDCAM_LCD_VSYNC_WIDTH_S) -#define LCDCAM_LCD_VSYNC_WIDTH_V 0x0000007FU -#define LCDCAM_LCD_VSYNC_WIDTH_S 0 -/** LCDCAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0; - * It is the idle value of LCD_VSYNC. - */ -#define LCDCAM_LCD_VSYNC_IDLE_POL (BIT(7)) -#define LCDCAM_LCD_VSYNC_IDLE_POL_M (LCDCAM_LCD_VSYNC_IDLE_POL_V << LCDCAM_LCD_VSYNC_IDLE_POL_S) -#define LCDCAM_LCD_VSYNC_IDLE_POL_V 0x00000001U -#define LCDCAM_LCD_VSYNC_IDLE_POL_S 7 -/** LCDCAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0; - * It is the idle value of LCD_DE. - */ -#define LCDCAM_LCD_DE_IDLE_POL (BIT(8)) -#define LCDCAM_LCD_DE_IDLE_POL_M (LCDCAM_LCD_DE_IDLE_POL_V << LCDCAM_LCD_DE_IDLE_POL_S) -#define LCDCAM_LCD_DE_IDLE_POL_V 0x00000001U -#define LCDCAM_LCD_DE_IDLE_POL_S 8 -/** LCDCAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0; - * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC - * pulse is valid only in active region lines in RGB mode. - */ -#define LCDCAM_LCD_HS_BLANK_EN (BIT(9)) -#define LCDCAM_LCD_HS_BLANK_EN_M (LCDCAM_LCD_HS_BLANK_EN_V << LCDCAM_LCD_HS_BLANK_EN_S) -#define LCDCAM_LCD_HS_BLANK_EN_V 0x00000001U -#define LCDCAM_LCD_HS_BLANK_EN_S 9 -/** LCDCAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1; - * It is the position of LCD_HSYNC active pulse in a line. - */ -#define LCDCAM_LCD_HSYNC_WIDTH 0x0000007FU -#define LCDCAM_LCD_HSYNC_WIDTH_M (LCDCAM_LCD_HSYNC_WIDTH_V << LCDCAM_LCD_HSYNC_WIDTH_S) -#define LCDCAM_LCD_HSYNC_WIDTH_V 0x0000007FU -#define LCDCAM_LCD_HSYNC_WIDTH_S 16 -/** LCDCAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0; - * It is the idle value of LCD_HSYNC. - */ -#define LCDCAM_LCD_HSYNC_IDLE_POL (BIT(23)) -#define LCDCAM_LCD_HSYNC_IDLE_POL_M (LCDCAM_LCD_HSYNC_IDLE_POL_V << LCDCAM_LCD_HSYNC_IDLE_POL_S) -#define LCDCAM_LCD_HSYNC_IDLE_POL_V 0x00000001U -#define LCDCAM_LCD_HSYNC_IDLE_POL_S 23 -/** LCDCAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0; - * It is the position of LCD_HSYNC active pulse in a line. - */ -#define LCDCAM_LCD_HSYNC_POSITION 0x000000FFU -#define LCDCAM_LCD_HSYNC_POSITION_M (LCDCAM_LCD_HSYNC_POSITION_V << LCDCAM_LCD_HSYNC_POSITION_S) -#define LCDCAM_LCD_HSYNC_POSITION_V 0x000000FFU -#define LCDCAM_LCD_HSYNC_POSITION_S 24 - -/** LCDCAM_LCD_FIRST_CMD_VAL_REG register - * LCD config register. - */ -#define LCDCAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x28) -/** LCDCAM_LCD_FIRST_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; - * The LCD write command value of first cmd cycle. - */ -#define LCDCAM_LCD_FIRST_CMD_VALUE 0xFFFFFFFFU -#define LCDCAM_LCD_FIRST_CMD_VALUE_M (LCDCAM_LCD_FIRST_CMD_VALUE_V << LCDCAM_LCD_FIRST_CMD_VALUE_S) -#define LCDCAM_LCD_FIRST_CMD_VALUE_V 0xFFFFFFFFU -#define LCDCAM_LCD_FIRST_CMD_VALUE_S 0 - -/** LCDCAM_LCD_LATTER_CMD_VAL_REG register - * LCD config register. - */ -#define LCDCAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x2c) -/** LCDCAM_LCD_LATTER_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; - * The LCD write command value of latter cmd cycle. - */ -#define LCDCAM_LCD_LATTER_CMD_VALUE 0xFFFFFFFFU -#define LCDCAM_LCD_LATTER_CMD_VALUE_M (LCDCAM_LCD_LATTER_CMD_VALUE_V << LCDCAM_LCD_LATTER_CMD_VALUE_S) -#define LCDCAM_LCD_LATTER_CMD_VALUE_V 0xFFFFFFFFU -#define LCDCAM_LCD_LATTER_CMD_VALUE_S 0 - -/** LCDCAM_LCD_DLY_MODE_CFG1_REG register - * LCD config register. - */ -#define LCDCAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCDCAM_BASE + 0x30) -/** LCDCAM_DOUT16_MODE : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT16_MODE 0x00000003U -#define LCDCAM_DOUT16_MODE_M (LCDCAM_DOUT16_MODE_V << LCDCAM_DOUT16_MODE_S) -#define LCDCAM_DOUT16_MODE_V 0x00000003U -#define LCDCAM_DOUT16_MODE_S 0 -/** LCDCAM_DOUT17_MODE : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT17_MODE 0x00000003U -#define LCDCAM_DOUT17_MODE_M (LCDCAM_DOUT17_MODE_V << LCDCAM_DOUT17_MODE_S) -#define LCDCAM_DOUT17_MODE_V 0x00000003U -#define LCDCAM_DOUT17_MODE_S 2 -/** LCDCAM_DOUT18_MODE : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT18_MODE 0x00000003U -#define LCDCAM_DOUT18_MODE_M (LCDCAM_DOUT18_MODE_V << LCDCAM_DOUT18_MODE_S) -#define LCDCAM_DOUT18_MODE_V 0x00000003U -#define LCDCAM_DOUT18_MODE_S 4 -/** LCDCAM_DOUT19_MODE : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT19_MODE 0x00000003U -#define LCDCAM_DOUT19_MODE_M (LCDCAM_DOUT19_MODE_V << LCDCAM_DOUT19_MODE_S) -#define LCDCAM_DOUT19_MODE_V 0x00000003U -#define LCDCAM_DOUT19_MODE_S 6 -/** LCDCAM_DOUT20_MODE : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT20_MODE 0x00000003U -#define LCDCAM_DOUT20_MODE_M (LCDCAM_DOUT20_MODE_V << LCDCAM_DOUT20_MODE_S) -#define LCDCAM_DOUT20_MODE_V 0x00000003U -#define LCDCAM_DOUT20_MODE_S 8 -/** LCDCAM_DOUT21_MODE : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT21_MODE 0x00000003U -#define LCDCAM_DOUT21_MODE_M (LCDCAM_DOUT21_MODE_V << LCDCAM_DOUT21_MODE_S) -#define LCDCAM_DOUT21_MODE_V 0x00000003U -#define LCDCAM_DOUT21_MODE_S 10 -/** LCDCAM_DOUT22_MODE : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT22_MODE 0x00000003U -#define LCDCAM_DOUT22_MODE_M (LCDCAM_DOUT22_MODE_V << LCDCAM_DOUT22_MODE_S) -#define LCDCAM_DOUT22_MODE_V 0x00000003U -#define LCDCAM_DOUT22_MODE_S 12 -/** LCDCAM_DOUT23_MODE : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT23_MODE 0x00000003U -#define LCDCAM_DOUT23_MODE_M (LCDCAM_DOUT23_MODE_V << LCDCAM_DOUT23_MODE_S) -#define LCDCAM_DOUT23_MODE_V 0x00000003U -#define LCDCAM_DOUT23_MODE_S 14 -/** LCDCAM_LCD_CD_MODE : R/W; bitpos: [17:16]; default: 0; - * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ -#define LCDCAM_LCD_CD_MODE 0x00000003U -#define LCDCAM_LCD_CD_MODE_M (LCDCAM_LCD_CD_MODE_V << LCDCAM_LCD_CD_MODE_S) -#define LCDCAM_LCD_CD_MODE_V 0x00000003U -#define LCDCAM_LCD_CD_MODE_S 16 -/** LCDCAM_LCD_DE_MODE : R/W; bitpos: [19:18]; default: 0; - * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ -#define LCDCAM_LCD_DE_MODE 0x00000003U -#define LCDCAM_LCD_DE_MODE_M (LCDCAM_LCD_DE_MODE_V << LCDCAM_LCD_DE_MODE_S) -#define LCDCAM_LCD_DE_MODE_V 0x00000003U -#define LCDCAM_LCD_DE_MODE_S 18 -/** LCDCAM_LCD_HSYNC_MODE : R/W; bitpos: [21:20]; default: 0; - * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ -#define LCDCAM_LCD_HSYNC_MODE 0x00000003U -#define LCDCAM_LCD_HSYNC_MODE_M (LCDCAM_LCD_HSYNC_MODE_V << LCDCAM_LCD_HSYNC_MODE_S) -#define LCDCAM_LCD_HSYNC_MODE_V 0x00000003U -#define LCDCAM_LCD_HSYNC_MODE_S 20 -/** LCDCAM_LCD_VSYNC_MODE : R/W; bitpos: [23:22]; default: 0; - * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ -#define LCDCAM_LCD_VSYNC_MODE 0x00000003U -#define LCDCAM_LCD_VSYNC_MODE_M (LCDCAM_LCD_VSYNC_MODE_V << LCDCAM_LCD_VSYNC_MODE_S) -#define LCDCAM_LCD_VSYNC_MODE_V 0x00000003U -#define LCDCAM_LCD_VSYNC_MODE_S 22 - -/** LCDCAM_LCD_DLY_MODE_CFG2_REG register - * LCD config register. - */ -#define LCDCAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCDCAM_BASE + 0x38) -/** LCDCAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT0_MODE 0x00000003U -#define LCDCAM_DOUT0_MODE_M (LCDCAM_DOUT0_MODE_V << LCDCAM_DOUT0_MODE_S) -#define LCDCAM_DOUT0_MODE_V 0x00000003U -#define LCDCAM_DOUT0_MODE_S 0 -/** LCDCAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT1_MODE 0x00000003U -#define LCDCAM_DOUT1_MODE_M (LCDCAM_DOUT1_MODE_V << LCDCAM_DOUT1_MODE_S) -#define LCDCAM_DOUT1_MODE_V 0x00000003U -#define LCDCAM_DOUT1_MODE_S 2 -/** LCDCAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT2_MODE 0x00000003U -#define LCDCAM_DOUT2_MODE_M (LCDCAM_DOUT2_MODE_V << LCDCAM_DOUT2_MODE_S) -#define LCDCAM_DOUT2_MODE_V 0x00000003U -#define LCDCAM_DOUT2_MODE_S 4 -/** LCDCAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT3_MODE 0x00000003U -#define LCDCAM_DOUT3_MODE_M (LCDCAM_DOUT3_MODE_V << LCDCAM_DOUT3_MODE_S) -#define LCDCAM_DOUT3_MODE_V 0x00000003U -#define LCDCAM_DOUT3_MODE_S 6 -/** LCDCAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT4_MODE 0x00000003U -#define LCDCAM_DOUT4_MODE_M (LCDCAM_DOUT4_MODE_V << LCDCAM_DOUT4_MODE_S) -#define LCDCAM_DOUT4_MODE_V 0x00000003U -#define LCDCAM_DOUT4_MODE_S 8 -/** LCDCAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT5_MODE 0x00000003U -#define LCDCAM_DOUT5_MODE_M (LCDCAM_DOUT5_MODE_V << LCDCAM_DOUT5_MODE_S) -#define LCDCAM_DOUT5_MODE_V 0x00000003U -#define LCDCAM_DOUT5_MODE_S 10 -/** LCDCAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT6_MODE 0x00000003U -#define LCDCAM_DOUT6_MODE_M (LCDCAM_DOUT6_MODE_V << LCDCAM_DOUT6_MODE_S) -#define LCDCAM_DOUT6_MODE_V 0x00000003U -#define LCDCAM_DOUT6_MODE_S 12 -/** LCDCAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT7_MODE 0x00000003U -#define LCDCAM_DOUT7_MODE_M (LCDCAM_DOUT7_MODE_V << LCDCAM_DOUT7_MODE_S) -#define LCDCAM_DOUT7_MODE_V 0x00000003U -#define LCDCAM_DOUT7_MODE_S 14 -/** LCDCAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT8_MODE 0x00000003U -#define LCDCAM_DOUT8_MODE_M (LCDCAM_DOUT8_MODE_V << LCDCAM_DOUT8_MODE_S) -#define LCDCAM_DOUT8_MODE_V 0x00000003U -#define LCDCAM_DOUT8_MODE_S 16 -/** LCDCAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT9_MODE 0x00000003U -#define LCDCAM_DOUT9_MODE_M (LCDCAM_DOUT9_MODE_V << LCDCAM_DOUT9_MODE_S) -#define LCDCAM_DOUT9_MODE_V 0x00000003U -#define LCDCAM_DOUT9_MODE_S 18 -/** LCDCAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT10_MODE 0x00000003U -#define LCDCAM_DOUT10_MODE_M (LCDCAM_DOUT10_MODE_V << LCDCAM_DOUT10_MODE_S) -#define LCDCAM_DOUT10_MODE_V 0x00000003U -#define LCDCAM_DOUT10_MODE_S 20 -/** LCDCAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT11_MODE 0x00000003U -#define LCDCAM_DOUT11_MODE_M (LCDCAM_DOUT11_MODE_V << LCDCAM_DOUT11_MODE_S) -#define LCDCAM_DOUT11_MODE_V 0x00000003U -#define LCDCAM_DOUT11_MODE_S 22 -/** LCDCAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT12_MODE 0x00000003U -#define LCDCAM_DOUT12_MODE_M (LCDCAM_DOUT12_MODE_V << LCDCAM_DOUT12_MODE_S) -#define LCDCAM_DOUT12_MODE_V 0x00000003U -#define LCDCAM_DOUT12_MODE_S 24 -/** LCDCAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT13_MODE 0x00000003U -#define LCDCAM_DOUT13_MODE_M (LCDCAM_DOUT13_MODE_V << LCDCAM_DOUT13_MODE_S) -#define LCDCAM_DOUT13_MODE_V 0x00000003U -#define LCDCAM_DOUT13_MODE_S 26 -/** LCDCAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT14_MODE 0x00000003U -#define LCDCAM_DOUT14_MODE_M (LCDCAM_DOUT14_MODE_V << LCDCAM_DOUT14_MODE_S) -#define LCDCAM_DOUT14_MODE_V 0x00000003U -#define LCDCAM_DOUT14_MODE_S 28 -/** LCDCAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ -#define LCDCAM_DOUT15_MODE 0x00000003U -#define LCDCAM_DOUT15_MODE_M (LCDCAM_DOUT15_MODE_V << LCDCAM_DOUT15_MODE_S) -#define LCDCAM_DOUT15_MODE_V 0x00000003U -#define LCDCAM_DOUT15_MODE_S 30 - -/** LCDCAM_LC_DMA_INT_ENA_REG register - * LCDCAM interrupt enable register. - */ -#define LCDCAM_LC_DMA_INT_ENA_REG (DR_REG_LCDCAM_BASE + 0x64) -/** LCDCAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable bit for LCD frame end interrupt. - */ -#define LCDCAM_LCD_VSYNC_INT_ENA (BIT(0)) -#define LCDCAM_LCD_VSYNC_INT_ENA_M (LCDCAM_LCD_VSYNC_INT_ENA_V << LCDCAM_LCD_VSYNC_INT_ENA_S) -#define LCDCAM_LCD_VSYNC_INT_ENA_V 0x00000001U -#define LCDCAM_LCD_VSYNC_INT_ENA_S 0 -/** LCDCAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable bit for lcd transfer end interrupt. - */ -#define LCDCAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) -#define LCDCAM_LCD_TRANS_DONE_INT_ENA_M (LCDCAM_LCD_TRANS_DONE_INT_ENA_V << LCDCAM_LCD_TRANS_DONE_INT_ENA_S) -#define LCDCAM_LCD_TRANS_DONE_INT_ENA_V 0x00000001U -#define LCDCAM_LCD_TRANS_DONE_INT_ENA_S 1 -/** LCDCAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0; - * The enable bit for Camera frame end interrupt. - */ -#define LCDCAM_CAM_VSYNC_INT_ENA (BIT(2)) -#define LCDCAM_CAM_VSYNC_INT_ENA_M (LCDCAM_CAM_VSYNC_INT_ENA_V << LCDCAM_CAM_VSYNC_INT_ENA_S) -#define LCDCAM_CAM_VSYNC_INT_ENA_V 0x00000001U -#define LCDCAM_CAM_VSYNC_INT_ENA_S 2 -/** LCDCAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0; - * The enable bit for Camera line interrupt. - */ -#define LCDCAM_CAM_HS_INT_ENA (BIT(3)) -#define LCDCAM_CAM_HS_INT_ENA_M (LCDCAM_CAM_HS_INT_ENA_V << LCDCAM_CAM_HS_INT_ENA_S) -#define LCDCAM_CAM_HS_INT_ENA_V 0x00000001U -#define LCDCAM_CAM_HS_INT_ENA_S 3 - -/** LCDCAM_LC_DMA_INT_RAW_REG register - * LCDCAM interrupt raw register, valid in level. - */ -#define LCDCAM_LC_DMA_INT_RAW_REG (DR_REG_LCDCAM_BASE + 0x68) -/** LCDCAM_LCD_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw bit for LCD frame end interrupt. - */ -#define LCDCAM_LCD_VSYNC_INT_RAW (BIT(0)) -#define LCDCAM_LCD_VSYNC_INT_RAW_M (LCDCAM_LCD_VSYNC_INT_RAW_V << LCDCAM_LCD_VSYNC_INT_RAW_S) -#define LCDCAM_LCD_VSYNC_INT_RAW_V 0x00000001U -#define LCDCAM_LCD_VSYNC_INT_RAW_S 0 -/** LCDCAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw bit for lcd transfer end interrupt. - */ -#define LCDCAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) -#define LCDCAM_LCD_TRANS_DONE_INT_RAW_M (LCDCAM_LCD_TRANS_DONE_INT_RAW_V << LCDCAM_LCD_TRANS_DONE_INT_RAW_S) -#define LCDCAM_LCD_TRANS_DONE_INT_RAW_V 0x00000001U -#define LCDCAM_LCD_TRANS_DONE_INT_RAW_S 1 -/** LCDCAM_CAM_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for Camera frame end interrupt. - */ -#define LCDCAM_CAM_VSYNC_INT_RAW (BIT(2)) -#define LCDCAM_CAM_VSYNC_INT_RAW_M (LCDCAM_CAM_VSYNC_INT_RAW_V << LCDCAM_CAM_VSYNC_INT_RAW_S) -#define LCDCAM_CAM_VSYNC_INT_RAW_V 0x00000001U -#define LCDCAM_CAM_VSYNC_INT_RAW_S 2 -/** LCDCAM_CAM_HS_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for Camera line interrupt. - */ -#define LCDCAM_CAM_HS_INT_RAW (BIT(3)) -#define LCDCAM_CAM_HS_INT_RAW_M (LCDCAM_CAM_HS_INT_RAW_V << LCDCAM_CAM_HS_INT_RAW_S) -#define LCDCAM_CAM_HS_INT_RAW_V 0x00000001U -#define LCDCAM_CAM_HS_INT_RAW_S 3 - -/** LCDCAM_LC_DMA_INT_ST_REG register - * LCDCAM interrupt status register. - */ -#define LCDCAM_LC_DMA_INT_ST_REG (DR_REG_LCDCAM_BASE + 0x6c) -/** LCDCAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0; - * The status bit for LCD frame end interrupt. - */ -#define LCDCAM_LCD_VSYNC_INT_ST (BIT(0)) -#define LCDCAM_LCD_VSYNC_INT_ST_M (LCDCAM_LCD_VSYNC_INT_ST_V << LCDCAM_LCD_VSYNC_INT_ST_S) -#define LCDCAM_LCD_VSYNC_INT_ST_V 0x00000001U -#define LCDCAM_LCD_VSYNC_INT_ST_S 0 -/** LCDCAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status bit for lcd transfer end interrupt. - */ -#define LCDCAM_LCD_TRANS_DONE_INT_ST (BIT(1)) -#define LCDCAM_LCD_TRANS_DONE_INT_ST_M (LCDCAM_LCD_TRANS_DONE_INT_ST_V << LCDCAM_LCD_TRANS_DONE_INT_ST_S) -#define LCDCAM_LCD_TRANS_DONE_INT_ST_V 0x00000001U -#define LCDCAM_LCD_TRANS_DONE_INT_ST_S 1 -/** LCDCAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0; - * The status bit for Camera frame end interrupt. - */ -#define LCDCAM_CAM_VSYNC_INT_ST (BIT(2)) -#define LCDCAM_CAM_VSYNC_INT_ST_M (LCDCAM_CAM_VSYNC_INT_ST_V << LCDCAM_CAM_VSYNC_INT_ST_S) -#define LCDCAM_CAM_VSYNC_INT_ST_V 0x00000001U -#define LCDCAM_CAM_VSYNC_INT_ST_S 2 -/** LCDCAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0; - * The status bit for Camera transfer end interrupt. - */ -#define LCDCAM_CAM_HS_INT_ST (BIT(3)) -#define LCDCAM_CAM_HS_INT_ST_M (LCDCAM_CAM_HS_INT_ST_V << LCDCAM_CAM_HS_INT_ST_S) -#define LCDCAM_CAM_HS_INT_ST_V 0x00000001U -#define LCDCAM_CAM_HS_INT_ST_S 3 - -/** LCDCAM_LC_DMA_INT_CLR_REG register - * LCDCAM interrupt clear register. - */ -#define LCDCAM_LC_DMA_INT_CLR_REG (DR_REG_LCDCAM_BASE + 0x70) -/** LCDCAM_LCD_VSYNC_INT_CLR : WT; bitpos: [0]; default: 0; - * The clear bit for LCD frame end interrupt. - */ -#define LCDCAM_LCD_VSYNC_INT_CLR (BIT(0)) -#define LCDCAM_LCD_VSYNC_INT_CLR_M (LCDCAM_LCD_VSYNC_INT_CLR_V << LCDCAM_LCD_VSYNC_INT_CLR_S) -#define LCDCAM_LCD_VSYNC_INT_CLR_V 0x00000001U -#define LCDCAM_LCD_VSYNC_INT_CLR_S 0 -/** LCDCAM_LCD_TRANS_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * The clear bit for lcd transfer end interrupt. - */ -#define LCDCAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) -#define LCDCAM_LCD_TRANS_DONE_INT_CLR_M (LCDCAM_LCD_TRANS_DONE_INT_CLR_V << LCDCAM_LCD_TRANS_DONE_INT_CLR_S) -#define LCDCAM_LCD_TRANS_DONE_INT_CLR_V 0x00000001U -#define LCDCAM_LCD_TRANS_DONE_INT_CLR_S 1 -/** LCDCAM_CAM_VSYNC_INT_CLR : WT; bitpos: [2]; default: 0; - * The clear bit for Camera frame end interrupt. - */ -#define LCDCAM_CAM_VSYNC_INT_CLR (BIT(2)) -#define LCDCAM_CAM_VSYNC_INT_CLR_M (LCDCAM_CAM_VSYNC_INT_CLR_V << LCDCAM_CAM_VSYNC_INT_CLR_S) -#define LCDCAM_CAM_VSYNC_INT_CLR_V 0x00000001U -#define LCDCAM_CAM_VSYNC_INT_CLR_S 2 -/** LCDCAM_CAM_HS_INT_CLR : WT; bitpos: [3]; default: 0; - * The clear bit for Camera line interrupt. - */ -#define LCDCAM_CAM_HS_INT_CLR (BIT(3)) -#define LCDCAM_CAM_HS_INT_CLR_M (LCDCAM_CAM_HS_INT_CLR_V << LCDCAM_CAM_HS_INT_CLR_S) -#define LCDCAM_CAM_HS_INT_CLR_V 0x00000001U -#define LCDCAM_CAM_HS_INT_CLR_S 3 - -/** LCDCAM_LC_REG_DATE_REG register - * Version register - */ -#define LCDCAM_LC_REG_DATE_REG (DR_REG_LCDCAM_BASE + 0xfc) -/** LCDCAM_LC_DATE : R/W; bitpos: [27:0]; default: 36712592; - * LCD_CAM version control register - */ -#define LCDCAM_LC_DATE 0x0FFFFFFFU -#define LCDCAM_LC_DATE_M (LCDCAM_LC_DATE_V << LCDCAM_LC_DATE_S) -#define LCDCAM_LC_DATE_V 0x0FFFFFFFU -#define LCDCAM_LC_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lcdcam_struct.h b/components/soc/esp32p4/include/soc/lcdcam_struct.h deleted file mode 100644 index 7d79afce3c..0000000000 --- a/components/soc/esp32p4/include/soc/lcdcam_struct.h +++ /dev/null @@ -1,855 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: lcd configuration registers */ -/** Type of lcd_clock register - * LCD clock config register. - */ -typedef union { - struct { - /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3; - * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. - */ - uint32_t lcd_clkcnt_n:6; - /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1; - * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). - */ - uint32_t lcd_clk_equ_sysclk:1; - /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0; - * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. - */ - uint32_t lcd_ck_idle_edge:1; - /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0; - * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low - * in the second half data cycle. - */ - uint32_t lcd_ck_out_edge:1; - /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4; - * Integral LCD clock divider value - */ - uint32_t lcd_clkm_div_num:8; - /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value - */ - uint32_t lcd_clkm_div_b:6; - /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value - */ - uint32_t lcd_clkm_div_a:6; - /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0; - * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - */ - uint32_t lcd_clk_sel:2; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Set this bit to enable clk gate - */ - uint32_t clk_en:1; - }; - uint32_t val; -} lcdcam_lcd_clock_reg_t; - -/** Type of lcd_rgb_yuv register - * LCD YUV/RGB converter configuration register. - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. - */ - uint32_t lcd_conv_8bits_data_inv:1; - /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0; - * 0: txtorx mode off. 1: txtorx mode on. - */ - uint32_t lcd_conv_txtorx:1; - /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. - */ - uint32_t lcd_conv_yuv2yuv_mode:2; - /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in - */ - uint32_t lcd_conv_yuv_mode:2; - /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. - */ - uint32_t lcd_conv_protocol_mode:1; - /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full - */ - uint32_t lcd_conv_data_out_mode:1; - /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full - */ - uint32_t lcd_conv_data_in_mode:1; - /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. - */ - uint32_t lcd_conv_mode_8bits_on:1; - /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. - */ - uint32_t lcd_conv_trans_mode:1; - /** lcd_conv_enable : R/W; bitpos: [31]; default: 0; - * 0: Bypass converter. 1: Enable converter. - */ - uint32_t lcd_conv_enable:1; - }; - uint32_t val; -} lcdcam_lcd_rgb_yuv_reg_t; - -/** Type of lcd_user register - * LCD config register. - */ -typedef union { - struct { - /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1; - * The output data cycles minus 1 of LCD module. - */ - uint32_t lcd_dout_cyclelen:13; - /** lcd_always_out_en : R/W; bitpos: [13]; default: 0; - * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or - * reg_lcd_reset is set. - */ - uint32_t lcd_always_out_en:1; - /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0; - * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA - */ - uint32_t lcd_dout_byte_swizzle_mode:3; - /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0; - * 1: enable byte swizzle 0: disable - */ - uint32_t lcd_dout_byte_swizzle_enable:1; - /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0; - * 1: change bit order in every byte. 0: Not change. - */ - uint32_t lcd_dout_bit_order:1; - /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0; - * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode - */ - uint32_t lcd_byte_mode:2; - /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0; - * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. - */ - uint32_t lcd_update_reg:1; - /** lcd_bit_order : R/W; bitpos: [22]; default: 0; - * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - */ - uint32_t lcd_bit_order:1; - /** lcd_byte_order : R/W; bitpos: [23]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. - */ - uint32_t lcd_byte_order:1; - /** lcd_dout : R/W; bitpos: [24]; default: 0; - * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. - */ - uint32_t lcd_dout:1; - /** lcd_dummy : R/W; bitpos: [25]; default: 0; - * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. - */ - uint32_t lcd_dummy:1; - /** lcd_cmd : R/W; bitpos: [26]; default: 0; - * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. - */ - uint32_t lcd_cmd:1; - /** lcd_start : R/W/SC; bitpos: [27]; default: 0; - * LCD start sending data enable signal, valid in high level. - */ - uint32_t lcd_start:1; - /** lcd_reset : WT; bitpos: [28]; default: 0; - * The value of command. - */ - uint32_t lcd_reset:1; - /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0; - * The dummy cycle length minus 1. - */ - uint32_t lcd_dummy_cyclelen:2; - /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0; - * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. - */ - uint32_t lcd_cmd_2_cycle_en:1; - }; - uint32_t val; -} lcdcam_lcd_user_reg_t; - -/** Type of lcd_misc register - * LCD config register. - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0; - * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit - */ - uint32_t lcd_wire_mode:2; - /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3; - * The setup cycle length minus 1 in LCD non-RGB mode. - */ - uint32_t lcd_vfk_cyclelen:6; - /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0; - * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold - * time cycle length in LCD non-RGB mode. - */ - uint32_t lcd_vbk_cyclelen:13; - /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0; - * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when - * the current frame is sent out. - */ - uint32_t lcd_next_frame_en:1; - /** lcd_bk_en : R/W; bitpos: [26]; default: 0; - * 1: Enable blank region when LCD sends data out. 0: No blank region. - */ - uint32_t lcd_bk_en:1; - /** lcd_afifo_reset : WT; bitpos: [27]; default: 0; - * LCD AFIFO reset signal. - */ - uint32_t lcd_afifo_reset:1; - /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = - * reg_cd_idle_edge. - */ - uint32_t lcd_cd_data_set:1; - /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = - * reg_cd_idle_edge. - */ - uint32_t lcd_cd_dummy_set:1; - /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = - * reg_cd_idle_edge. - */ - uint32_t lcd_cd_cmd_set:1; - /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0; - * The default value of LCD_CD. - */ - uint32_t lcd_cd_idle_edge:1; - }; - uint32_t val; -} lcdcam_lcd_misc_reg_t; - -/** Type of lcd_ctrl register - * LCD config register. - */ -typedef union { - struct { - /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0; - * It is the horizontal blank front porch of a frame. - */ - uint32_t lcd_hb_front:11; - /** lcd_va_height : R/W; bitpos: [20:11]; default: 0; - * It is the vertical active height of a frame. - */ - uint32_t lcd_va_height:10; - /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0; - * It is the vertical total height of a frame. - */ - uint32_t lcd_vt_height:10; - /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0; - * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. - */ - uint32_t lcd_rgb_mode_en:1; - }; - uint32_t val; -} lcdcam_lcd_ctrl_reg_t; - -/** Type of lcd_ctrl1 register - * LCD config register. - */ -typedef union { - struct { - /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0; - * It is the vertical blank front porch of a frame. - */ - uint32_t lcd_vb_front:8; - /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0; - * It is the horizontal active width of a frame. - */ - uint32_t lcd_ha_width:12; - /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0; - * It is the horizontal total width of a frame. - */ - uint32_t lcd_ht_width:12; - }; - uint32_t val; -} lcdcam_lcd_ctrl1_reg_t; - -/** Type of lcd_ctrl2 register - * LCD config register. - */ -typedef union { - struct { - /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; - * It is the position of LCD_VSYNC active pulse in a line. - */ - uint32_t lcd_vsync_width:7; - /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0; - * It is the idle value of LCD_VSYNC. - */ - uint32_t lcd_vsync_idle_pol:1; - /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0; - * It is the idle value of LCD_DE. - */ - uint32_t lcd_de_idle_pol:1; - /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0; - * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC - * pulse is valid only in active region lines in RGB mode. - */ - uint32_t lcd_hs_blank_en:1; - uint32_t reserved_10:6; - /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; - * It is the position of LCD_HSYNC active pulse in a line. - */ - uint32_t lcd_hsync_width:7; - /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0; - * It is the idle value of LCD_HSYNC. - */ - uint32_t lcd_hsync_idle_pol:1; - /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0; - * It is the position of LCD_HSYNC active pulse in a line. - */ - uint32_t lcd_hsync_position:8; - }; - uint32_t val; -} lcdcam_lcd_ctrl2_reg_t; - -/** Type of lcd_first_cmd_val register - * LCD config register. - */ -typedef union { - struct { - /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0; - * The LCD write command value of first cmd cycle. - */ - uint32_t lcd_first_cmd_value:32; - }; - uint32_t val; -} lcdcam_lcd_first_cmd_val_reg_t; - -/** Type of lcd_latter_cmd_val register - * LCD config register. - */ -typedef union { - struct { - /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0; - * The LCD write command value of latter cmd cycle. - */ - uint32_t lcd_latter_cmd_value:32; - }; - uint32_t val; -} lcdcam_lcd_latter_cmd_val_reg_t; - -/** Type of lcd_dly_mode_cfg1 register - * LCD config register. - */ -typedef union { - struct { - /** dout16_mode : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout16_mode:2; - /** dout17_mode : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout17_mode:2; - /** dout18_mode : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout18_mode:2; - /** dout19_mode : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout19_mode:2; - /** dout20_mode : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout20_mode:2; - /** dout21_mode : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout21_mode:2; - /** dout22_mode : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout22_mode:2; - /** dout23_mode : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout23_mode:2; - /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0; - * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_cd_mode:2; - /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0; - * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_de_mode:2; - /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0; - * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_hsync_mode:2; - /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0; - * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_vsync_mode:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} lcdcam_lcd_dly_mode_cfg1_reg_t; - -/** Type of lcd_dly_mode_cfg2 register - * LCD config register. - */ -typedef union { - struct { - /** dout0_mode : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout0_mode:2; - /** dout1_mode : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout1_mode:2; - /** dout2_mode : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout2_mode:2; - /** dout3_mode : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout3_mode:2; - /** dout4_mode : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout4_mode:2; - /** dout5_mode : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout5_mode:2; - /** dout6_mode : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout6_mode:2; - /** dout7_mode : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout7_mode:2; - /** dout8_mode : R/W; bitpos: [17:16]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout8_mode:2; - /** dout9_mode : R/W; bitpos: [19:18]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout9_mode:2; - /** dout10_mode : R/W; bitpos: [21:20]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout10_mode:2; - /** dout11_mode : R/W; bitpos: [23:22]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout11_mode:2; - /** dout12_mode : R/W; bitpos: [25:24]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout12_mode:2; - /** dout13_mode : R/W; bitpos: [27:26]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout13_mode:2; - /** dout14_mode : R/W; bitpos: [29:28]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout14_mode:2; - /** dout15_mode : R/W; bitpos: [31:30]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout15_mode:2; - }; - uint32_t val; -} lcdcam_lcd_dly_mode_cfg2_reg_t; - - -/** Group: cam configuration registers */ -/** Type of cam_ctrl register - * CAM config register. - */ -typedef union { - struct { - /** cam_stop_en : R/W; bitpos: [0]; default: 0; - * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. - */ - uint32_t cam_stop_en:1; - /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0; - * Filter threshold value for CAM_VSYNC signal. - */ - uint32_t cam_vsync_filter_thres:3; - /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0; - * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. - */ - uint32_t cam_update_reg:1; - /** cam_byte_order : R/W; bitpos: [5]; default: 0; - * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - */ - uint32_t cam_byte_order:1; - /** cam_bit_order : R/W; bitpos: [6]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. - */ - uint32_t cam_bit_order:1; - /** cam_line_int_en : R/W; bitpos: [7]; default: 0; - * 1: Enable to generate CAM_HS_INT. 0: Disable. - */ - uint32_t cam_line_int_en:1; - /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0; - * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by - * reg_cam_rec_data_cyclelen. - */ - uint32_t cam_vs_eof_en:1; - /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4; - * Integral Camera clock divider value - */ - uint32_t cam_clkm_div_num:8; - /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value - */ - uint32_t cam_clkm_div_b:6; - /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value - */ - uint32_t cam_clkm_div_a:6; - /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0; - * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - */ - uint32_t cam_clk_sel:2; - uint32_t reserved_31:1; - }; - uint32_t val; -} lcdcam_cam_ctrl_reg_t; - -/** Type of cam_ctrl1 register - * CAM config register. - */ -typedef union { - struct { - /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0; - * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. - */ - uint32_t cam_rec_data_bytelen:16; - /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0; - * The line number minus 1 to generate cam_hs_int. - */ - uint32_t cam_line_int_num:6; - /** cam_clk_inv : R/W; bitpos: [22]; default: 0; - * 1: Invert the input signal CAM_PCLK. 0: Not invert. - */ - uint32_t cam_clk_inv:1; - /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0; - * 1: Enable CAM_VSYNC filter function. 0: bypass. - */ - uint32_t cam_vsync_filter_en:1; - /** cam_2byte_en : R/W; bitpos: [24]; default: 0; - * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. - */ - uint32_t cam_2byte_en:1; - /** cam_de_inv : R/W; bitpos: [25]; default: 0; - * CAM_DE invert enable signal, valid in high level. - */ - uint32_t cam_de_inv:1; - /** cam_hsync_inv : R/W; bitpos: [26]; default: 0; - * CAM_HSYNC invert enable signal, valid in high level. - */ - uint32_t cam_hsync_inv:1; - /** cam_vsync_inv : R/W; bitpos: [27]; default: 0; - * CAM_VSYNC invert enable signal, valid in high level. - */ - uint32_t cam_vsync_inv:1; - /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0; - * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control - * signals are CAM_DE and CAM_VSYNC. - */ - uint32_t cam_vh_de_mode_en:1; - /** cam_start : R/W/SC; bitpos: [29]; default: 0; - * Camera module start signal. - */ - uint32_t cam_start:1; - /** cam_reset : WT; bitpos: [30]; default: 0; - * Camera module reset signal. - */ - uint32_t cam_reset:1; - /** cam_afifo_reset : WT; bitpos: [31]; default: 0; - * Camera AFIFO reset signal. - */ - uint32_t cam_afifo_reset:1; - }; - uint32_t val; -} lcdcam_cam_ctrl1_reg_t; - -/** Type of cam_rgb_yuv register - * CAM YUV/RGB converter configuration register. - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. - */ - uint32_t cam_conv_8bits_data_inv:1; - /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. - */ - uint32_t cam_conv_yuv2yuv_mode:2; - /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in - */ - uint32_t cam_conv_yuv_mode:2; - /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. - */ - uint32_t cam_conv_protocol_mode:1; - /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full - */ - uint32_t cam_conv_data_out_mode:1; - /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full - */ - uint32_t cam_conv_data_in_mode:1; - /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. - */ - uint32_t cam_conv_mode_8bits_on:1; - /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. - */ - uint32_t cam_conv_trans_mode:1; - /** cam_conv_enable : R/W; bitpos: [31]; default: 0; - * 0: Bypass converter. 1: Enable converter. - */ - uint32_t cam_conv_enable:1; - }; - uint32_t val; -} lcdcam_cam_rgb_yuv_reg_t; - - -/** Group: Interrupt registers */ -/** Type of lc_dma_int_ena register - * LCDCAM interrupt enable register. - */ -typedef union { - struct { - /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0; - * The enable bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_ena:1; - /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_ena:1; - /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0; - * The enable bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_ena:1; - /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for Camera line interrupt. - */ - uint32_t cam_hs_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} lcdcam_lc_dma_int_ena_reg_t; - -/** Type of lc_dma_int_raw register - * LCDCAM interrupt raw register, valid in level. - */ -typedef union { - struct { - /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_raw:1; - /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_raw:1; - /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_raw:1; - /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for Camera line interrupt. - */ - uint32_t cam_hs_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} lcdcam_lc_dma_int_raw_reg_t; - -/** Type of lc_dma_int_st register - * LCDCAM interrupt status register. - */ -typedef union { - struct { - /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0; - * The status bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_st:1; - /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0; - * The status bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_st:1; - /** cam_vsync_int_st : RO; bitpos: [2]; default: 0; - * The status bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_st:1; - /** cam_hs_int_st : RO; bitpos: [3]; default: 0; - * The status bit for Camera transfer end interrupt. - */ - uint32_t cam_hs_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} lcdcam_lc_dma_int_st_reg_t; - -/** Type of lc_dma_int_clr register - * LCDCAM interrupt clear register. - */ -typedef union { - struct { - /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0; - * The clear bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_clr:1; - /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0; - * The clear bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_clr:1; - /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0; - * The clear bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_clr:1; - /** cam_hs_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for Camera line interrupt. - */ - uint32_t cam_hs_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} lcdcam_lc_dma_int_clr_reg_t; - - -/** Group: Version register */ -/** Type of lc_reg_date register - * Version register - */ -typedef union { - struct { - /** lc_date : R/W; bitpos: [27:0]; default: 36712592; - * LCD_CAM version control register - */ - uint32_t lc_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} lcdcam_lc_reg_date_reg_t; - - -typedef struct lcd_cam_dev_s { - volatile lcdcam_lcd_clock_reg_t lcd_clock; - volatile lcdcam_cam_ctrl_reg_t cam_ctrl; - volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1; - volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv; - volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv; - volatile lcdcam_lcd_user_reg_t lcd_user; - volatile lcdcam_lcd_misc_reg_t lcd_misc; - volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl; - volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1; - volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2; - volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val; - volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val; - volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1; - uint32_t reserved_034; - volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2; - uint32_t reserved_03c[10]; - volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena; - volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw; - volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st; - volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr; - uint32_t reserved_074[34]; - volatile lcdcam_lc_reg_date_reg_t lc_reg_date; -} lcdcam_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_aon_reg.h b/components/soc/esp32p4/include/soc/lp_aon_reg.h deleted file mode 100644 index 07d035f462..0000000000 --- a/components/soc/esp32p4/include/soc/lp_aon_reg.h +++ /dev/null @@ -1,418 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_AON_STORE0_REG register - * need_des - */ -#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) -/** LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE0 0xFFFFFFFFU -#define LP_AON_STORE0_M (LP_AON_STORE0_V << LP_AON_STORE0_S) -#define LP_AON_STORE0_V 0xFFFFFFFFU -#define LP_AON_STORE0_S 0 - -/** LP_AON_STORE1_REG register - * need_des - */ -#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) -/** LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE1 0xFFFFFFFFU -#define LP_AON_STORE1_M (LP_AON_STORE1_V << LP_AON_STORE1_S) -#define LP_AON_STORE1_V 0xFFFFFFFFU -#define LP_AON_STORE1_S 0 - -/** LP_AON_STORE2_REG register - * need_des - */ -#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) -/** LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE2 0xFFFFFFFFU -#define LP_AON_STORE2_M (LP_AON_STORE2_V << LP_AON_STORE2_S) -#define LP_AON_STORE2_V 0xFFFFFFFFU -#define LP_AON_STORE2_S 0 - -/** LP_AON_STORE3_REG register - * need_des - */ -#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) -/** LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE3 0xFFFFFFFFU -#define LP_AON_STORE3_M (LP_AON_STORE3_V << LP_AON_STORE3_S) -#define LP_AON_STORE3_V 0xFFFFFFFFU -#define LP_AON_STORE3_S 0 - -/** LP_AON_STORE4_REG register - * need_des - */ -#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) -/** LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE4 0xFFFFFFFFU -#define LP_AON_STORE4_M (LP_AON_STORE4_V << LP_AON_STORE4_S) -#define LP_AON_STORE4_V 0xFFFFFFFFU -#define LP_AON_STORE4_S 0 - -/** LP_AON_STORE5_REG register - * need_des - */ -#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) -/** LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE5 0xFFFFFFFFU -#define LP_AON_STORE5_M (LP_AON_STORE5_V << LP_AON_STORE5_S) -#define LP_AON_STORE5_V 0xFFFFFFFFU -#define LP_AON_STORE5_S 0 - -/** LP_AON_STORE6_REG register - * need_des - */ -#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) -/** LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE6 0xFFFFFFFFU -#define LP_AON_STORE6_M (LP_AON_STORE6_V << LP_AON_STORE6_S) -#define LP_AON_STORE6_V 0xFFFFFFFFU -#define LP_AON_STORE6_S 0 - -/** LP_AON_STORE7_REG register - * need_des - */ -#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) -/** LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE7 0xFFFFFFFFU -#define LP_AON_STORE7_M (LP_AON_STORE7_V << LP_AON_STORE7_S) -#define LP_AON_STORE7_V 0xFFFFFFFFU -#define LP_AON_STORE7_S 0 - -/** LP_AON_STORE8_REG register - * need_des - */ -#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) -/** LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE8 0xFFFFFFFFU -#define LP_AON_STORE8_M (LP_AON_STORE8_V << LP_AON_STORE8_S) -#define LP_AON_STORE8_V 0xFFFFFFFFU -#define LP_AON_STORE8_S 0 - -/** LP_AON_STORE9_REG register - * need_des - */ -#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) -/** LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_STORE9 0xFFFFFFFFU -#define LP_AON_STORE9_M (LP_AON_STORE9_V << LP_AON_STORE9_S) -#define LP_AON_STORE9_V 0xFFFFFFFFU -#define LP_AON_STORE9_S 0 - -/** LP_AON_GPIO_MUX_REG register - * need_des - */ -#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) -/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; - * need_des - */ -#define LP_AON_GPIO_MUX_SEL 0x000000FFU -#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) -#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU -#define LP_AON_GPIO_MUX_SEL_S 0 - -/** LP_AON_GPIO_HOLD0_REG register - * need_des - */ -#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) -/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU -#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) -#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU -#define LP_AON_GPIO_HOLD0_S 0 - -/** LP_AON_GPIO_HOLD1_REG register - * need_des - */ -#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) -/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU -#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) -#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU -#define LP_AON_GPIO_HOLD1_S 0 - -/** LP_AON_SYS_CFG_REG register - * need_des - */ -#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) -/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) -#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) -#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U -#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 -/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AON_HPSYS_SW_RESET (BIT(31)) -#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) -#define LP_AON_HPSYS_SW_RESET_V 0x00000001U -#define LP_AON_HPSYS_SW_RESET_S 31 - -/** LP_AON_CPUCORE0_CFG_REG register - * need_des - */ -#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) -/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; - * need_des - */ -#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU -#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) -#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU -#define LP_AON_CPU_CORE0_SW_STALL_S 0 -/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) -#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) -#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U -#define LP_AON_CPU_CORE0_SW_RESET_S 28 -/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 -/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 -/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) -#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) -#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U -#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 - -/** LP_AON_IO_MUX_REG register - * need_des - */ -#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) -/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) -#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) -#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U -#define LP_AON_IO_MUX_RESET_DISABLE_S 31 - -/** LP_AON_EXT_WAKEUP_CNTL_REG register - * need_des - */ -#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) -/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; - * need_des - */ -#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU -#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) -#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU -#define LP_AON_EXT_WAKEUP_STATUS_S 0 -/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; - * need_des - */ -#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) -#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) -#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U -#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 -/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; - * need_des - */ -#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU -#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) -#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU -#define LP_AON_EXT_WAKEUP_SEL_S 15 -/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; - * need_des - */ -#define LP_AON_EXT_WAKEUP_LV 0x000000FFU -#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) -#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU -#define LP_AON_EXT_WAKEUP_LV_S 23 -/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) -#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) -#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U -#define LP_AON_EXT_WAKEUP_FILTER_S 31 - -/** LP_AON_USB_REG register - * need_des - */ -#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) -/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AON_USB_RESET_DISABLE (BIT(31)) -#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) -#define LP_AON_USB_RESET_DISABLE_V 0x00000001U -#define LP_AON_USB_RESET_DISABLE_S 31 - -/** LP_AON_LPBUS_REG register - * need_des - */ -#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) -/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; - * This field controls fast memory WPULSE parameter. - */ -#define LP_AON_FAST_MEM_WPULSE 0x00000007U -#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) -#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U -#define LP_AON_FAST_MEM_WPULSE_S 16 -/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4; - * This field controls fast memory WA parameter. - */ -#define LP_AON_FAST_MEM_WA 0x00000007U -#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) -#define LP_AON_FAST_MEM_WA_V 0x00000007U -#define LP_AON_FAST_MEM_WA_S 19 -/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; - * This field controls fast memory RA parameter. - */ -#define LP_AON_FAST_MEM_RA 0x00000003U -#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) -#define LP_AON_FAST_MEM_RA_V 0x00000003U -#define LP_AON_FAST_MEM_RA_S 22 -/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1; - * need_des - */ -#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) -#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) -#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U -#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 -/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1; - * need_des - */ -#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) -#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) -#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U -#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 -/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 -/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1; - * need_des - */ -#define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) -#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) -#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U -#define LP_AON_FAST_MEM_MUX_SEL_S 31 - -/** LP_AON_SDIO_ACTIVE_REG register - * need_des - */ -#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) -/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; - * need_des - */ -#define LP_AON_SDIO_ACT_DNUM 0x000003FFU -#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) -#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU -#define LP_AON_SDIO_ACT_DNUM_S 22 - -/** LP_AON_LPCORE_REG register - * need_des - */ -#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) -/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; - * need_des - */ -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 -/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; - * need_des - */ -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 -/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AON_LPCORE_DISABLE (BIT(31)) -#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) -#define LP_AON_LPCORE_DISABLE_V 0x00000001U -#define LP_AON_LPCORE_DISABLE_S 31 - -/** LP_AON_SAR_CCT_REG register - * need_des - */ -#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) -/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; - * need_des - */ -#define LP_AON_SAR2_PWDET_CCT 0x00000007U -#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) -#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U -#define LP_AON_SAR2_PWDET_CCT_S 29 - -/** LP_AON_DATE_REG register - * need_des - */ -#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) -/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704; - * need_des - */ -#define LP_AON_DATE 0x7FFFFFFFU -#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) -#define LP_AON_DATE_V 0x7FFFFFFFU -#define LP_AON_DATE_S 0 -/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AON_CLK_EN (BIT(31)) -#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) -#define LP_AON_CLK_EN_V 0x00000001U -#define LP_AON_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_aon_struct.h b/components/soc/esp32p4/include/soc/lp_aon_struct.h deleted file mode 100644 index 372d3b06ea..0000000000 --- a/components/soc/esp32p4/include/soc/lp_aon_struct.h +++ /dev/null @@ -1,306 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of store register - * need_des - */ -typedef union { - struct { - /** store : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t store:32; - }; - uint32_t val; -} lp_aon_store_reg_t; - -/** Type of gpio_mux register - * need_des - */ -typedef union { - struct { - /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t gpio_mux_sel:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_aon_gpio_mux_reg_t; - -/** Type of gpio_hold0 register - * need_des - */ -typedef union { - struct { - /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t gpio_hold0:32; - }; - uint32_t val; -} lp_aon_gpio_hold0_reg_t; - -/** Type of gpio_hold1 register - * need_des - */ -typedef union { - struct { - /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t gpio_hold1:32; - }; - uint32_t val; -} lp_aon_gpio_hold1_reg_t; - -/** Type of sys_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** force_download_boot : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t force_download_boot:1; - /** hpsys_sw_reset : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hpsys_sw_reset:1; - }; - uint32_t val; -} lp_aon_sys_cfg_reg_t; - -/** Type of cpucore0_cfg register - * need_des - */ -typedef union { - struct { - /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t cpu_core0_sw_stall:8; - uint32_t reserved_8:20; - /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t cpu_core0_sw_reset:1; - /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t cpu_core0_ocd_halt_on_reset:1; - /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t cpu_core0_stat_vector_sel:1; - /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t cpu_core0_dreset_mask:1; - }; - uint32_t val; -} lp_aon_cpucore0_cfg_reg_t; - -/** Type of io_mux register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t io_mux_reset_disable:1; - }; - uint32_t val; -} lp_aon_io_mux_reg_t; - -/** Type of ext_wakeup_cntl register - * need_des - */ -typedef union { - struct { - /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t ext_wakeup_status:8; - uint32_t reserved_8:6; - /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; - * need_des - */ - uint32_t ext_wakeup_status_clr:1; - /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; - * need_des - */ - uint32_t ext_wakeup_sel:8; - /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; - * need_des - */ - uint32_t ext_wakeup_lv:8; - /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t ext_wakeup_filter:1; - }; - uint32_t val; -} lp_aon_ext_wakeup_cntl_reg_t; - -/** Type of usb register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** usb_reset_disable : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t usb_reset_disable:1; - }; - uint32_t val; -} lp_aon_usb_reg_t; - -/** Type of lpbus register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0; - * This field controls fast memory WPULSE parameter. - */ - uint32_t fast_mem_wpulse:3; - /** fast_mem_wa : R/W; bitpos: [21:19]; default: 4; - * This field controls fast memory WA parameter. - */ - uint32_t fast_mem_wa:3; - /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0; - * This field controls fast memory RA parameter. - */ - uint32_t fast_mem_ra:2; - uint32_t reserved_24:4; - /** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1; - * need_des - */ - uint32_t fast_mem_mux_fsm_idle:1; - /** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1; - * need_des - */ - uint32_t fast_mem_mux_sel_status:1; - /** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t fast_mem_mux_sel_update:1; - /** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t fast_mem_mux_sel:1; - }; - uint32_t val; -} lp_aon_lpbus_reg_t; - -/** Type of sdio_active register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; - * need_des - */ - uint32_t sdio_act_dnum:10; - }; - uint32_t val; -} lp_aon_sdio_active_reg_t; - -/** Type of lpcore register - * need_des - */ -typedef union { - struct { - /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lpcore_etm_wakeup_flag_clr:1; - /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lpcore_etm_wakeup_flag:1; - uint32_t reserved_2:29; - /** lpcore_disable : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lpcore_disable:1; - }; - uint32_t val; -} lp_aon_lpcore_reg_t; - -/** Type of sar_cct register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:29; - /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; - * need_des - */ - uint32_t sar2_pwdet_cct:3; - }; - uint32_t val; -} lp_aon_sar_cct_reg_t; - -/** Type of date register - * need_des - */ -typedef union { - struct { - /** date : R/W; bitpos: [30:0]; default: 35672704; - * need_des - */ - uint32_t date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} lp_aon_date_reg_t; - - -typedef struct lp_aon_dev_t { - volatile lp_aon_store_reg_t store[10]; - volatile lp_aon_gpio_mux_reg_t gpio_mux; - volatile lp_aon_gpio_hold0_reg_t gpio_hold0; - volatile lp_aon_gpio_hold1_reg_t gpio_hold1; - volatile lp_aon_sys_cfg_reg_t sys_cfg; - volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; - volatile lp_aon_io_mux_reg_t io_mux; - volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; - volatile lp_aon_usb_reg_t usb; - volatile lp_aon_lpbus_reg_t lpbus; - volatile lp_aon_sdio_active_reg_t sdio_active; - volatile lp_aon_lpcore_reg_t lpcore; - volatile lp_aon_sar_cct_reg_t sar_cct; - uint32_t reserved_058[233]; - volatile lp_aon_date_reg_t date; -} lp_aon_dev_t; - -extern lp_aon_dev_t LP_AON; - -#ifndef __cplusplus -_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h b/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h deleted file mode 100644 index 901915903a..0000000000 --- a/components/soc/esp32p4/include/soc/lp_aonclkrst_reg.h +++ /dev/null @@ -1,1036 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_AONCLKRST_LP_CLK_CONF_REG register - * need_des - */ -#define LP_AONCLKRST_LP_CLK_CONF_REG (DR_REG_LP_AONCLKRST_BASE + 0x0) -/** LP_AONCLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * need_des - */ -#define LP_AONCLKRST_SLOW_CLK_SEL 0x00000003U -#define LP_AONCLKRST_SLOW_CLK_SEL_M (LP_AONCLKRST_SLOW_CLK_SEL_V << LP_AONCLKRST_SLOW_CLK_SEL_S) -#define LP_AONCLKRST_SLOW_CLK_SEL_V 0x00000003U -#define LP_AONCLKRST_SLOW_CLK_SEL_S 0 -/** LP_AONCLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; - * need_des - */ -#define LP_AONCLKRST_FAST_CLK_SEL 0x00000003U -#define LP_AONCLKRST_FAST_CLK_SEL_M (LP_AONCLKRST_FAST_CLK_SEL_V << LP_AONCLKRST_FAST_CLK_SEL_S) -#define LP_AONCLKRST_FAST_CLK_SEL_V 0x00000003U -#define LP_AONCLKRST_FAST_CLK_SEL_S 2 -/** LP_AONCLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LP_PERI_DIV_NUM 0x0000003FU -#define LP_AONCLKRST_LP_PERI_DIV_NUM_M (LP_AONCLKRST_LP_PERI_DIV_NUM_V << LP_AONCLKRST_LP_PERI_DIV_NUM_S) -#define LP_AONCLKRST_LP_PERI_DIV_NUM_V 0x0000003FU -#define LP_AONCLKRST_LP_PERI_DIV_NUM_S 4 -/** LP_AONCLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M (BIT(10)) -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_M (LP_AONCLKRST_ANA_SEL_REF_PLL8M_V << LP_AONCLKRST_ANA_SEL_REF_PLL8M_S) -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_V 0x00000001U -#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_S 10 - -/** LP_AONCLKRST_LP_CLK_PO_EN_REG register - * need_des - */ -#define LP_AONCLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0x4) -/** LP_AONCLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN (BIT(0)) -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_M (LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V << LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S) -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S 0 -/** LP_AONCLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_LP_BUS_OEN (BIT(1)) -#define LP_AONCLKRST_CLK_LP_BUS_OEN_M (LP_AONCLKRST_CLK_LP_BUS_OEN_V << LP_AONCLKRST_CLK_LP_BUS_OEN_S) -#define LP_AONCLKRST_CLK_LP_BUS_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_LP_BUS_OEN_S 1 -/** LP_AONCLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_AON_SLOW_OEN (BIT(2)) -#define LP_AONCLKRST_CLK_AON_SLOW_OEN_M (LP_AONCLKRST_CLK_AON_SLOW_OEN_V << LP_AONCLKRST_CLK_AON_SLOW_OEN_S) -#define LP_AONCLKRST_CLK_AON_SLOW_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_AON_SLOW_OEN_S 2 -/** LP_AONCLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_AON_FAST_OEN (BIT(3)) -#define LP_AONCLKRST_CLK_AON_FAST_OEN_M (LP_AONCLKRST_CLK_AON_FAST_OEN_V << LP_AONCLKRST_CLK_AON_FAST_OEN_S) -#define LP_AONCLKRST_CLK_AON_FAST_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_AON_FAST_OEN_S 3 -/** LP_AONCLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_SLOW_OEN (BIT(4)) -#define LP_AONCLKRST_CLK_SLOW_OEN_M (LP_AONCLKRST_CLK_SLOW_OEN_V << LP_AONCLKRST_CLK_SLOW_OEN_S) -#define LP_AONCLKRST_CLK_SLOW_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_SLOW_OEN_S 4 -/** LP_AONCLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_FAST_OEN (BIT(5)) -#define LP_AONCLKRST_CLK_FAST_OEN_M (LP_AONCLKRST_CLK_FAST_OEN_V << LP_AONCLKRST_CLK_FAST_OEN_S) -#define LP_AONCLKRST_CLK_FAST_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_FAST_OEN_S 5 -/** LP_AONCLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_FOSC_OEN (BIT(6)) -#define LP_AONCLKRST_CLK_FOSC_OEN_M (LP_AONCLKRST_CLK_FOSC_OEN_V << LP_AONCLKRST_CLK_FOSC_OEN_S) -#define LP_AONCLKRST_CLK_FOSC_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_FOSC_OEN_S 6 -/** LP_AONCLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_RC32K_OEN (BIT(7)) -#define LP_AONCLKRST_CLK_RC32K_OEN_M (LP_AONCLKRST_CLK_RC32K_OEN_V << LP_AONCLKRST_CLK_RC32K_OEN_S) -#define LP_AONCLKRST_CLK_RC32K_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_RC32K_OEN_S 7 -/** LP_AONCLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_SXTAL_OEN (BIT(8)) -#define LP_AONCLKRST_CLK_SXTAL_OEN_M (LP_AONCLKRST_CLK_SXTAL_OEN_V << LP_AONCLKRST_CLK_SXTAL_OEN_S) -#define LP_AONCLKRST_CLK_SXTAL_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_SXTAL_OEN_S 8 -/** LP_AONCLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0; - * 1'b1: probe sosc clk on - * 1'b0: probe sosc clk off - */ -#define LP_AONCLKRST_CLK_SOSC_OEN (BIT(9)) -#define LP_AONCLKRST_CLK_SOSC_OEN_M (LP_AONCLKRST_CLK_SOSC_OEN_V << LP_AONCLKRST_CLK_SOSC_OEN_S) -#define LP_AONCLKRST_CLK_SOSC_OEN_V 0x00000001U -#define LP_AONCLKRST_CLK_SOSC_OEN_S 9 - -/** LP_AONCLKRST_LP_CLK_EN_REG register - * need_des - */ -#define LP_AONCLKRST_LP_CLK_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0x8) -/** LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON (BIT(26)) -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_M (LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_S) -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_S 26 -/** LP_AONCLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1; - * need_des - */ -#define LP_AONCLKRST_CK_EN_LP_RAM (BIT(27)) -#define LP_AONCLKRST_CK_EN_LP_RAM_M (LP_AONCLKRST_CK_EN_LP_RAM_V << LP_AONCLKRST_CK_EN_LP_RAM_S) -#define LP_AONCLKRST_CK_EN_LP_RAM_V 0x00000001U -#define LP_AONCLKRST_CK_EN_LP_RAM_S 27 -/** LP_AONCLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_ETM_EVENT_TICK_EN (BIT(28)) -#define LP_AONCLKRST_ETM_EVENT_TICK_EN_M (LP_AONCLKRST_ETM_EVENT_TICK_EN_V << LP_AONCLKRST_ETM_EVENT_TICK_EN_S) -#define LP_AONCLKRST_ETM_EVENT_TICK_EN_V 0x00000001U -#define LP_AONCLKRST_ETM_EVENT_TICK_EN_S 28 -/** LP_AONCLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON (BIT(29)) -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_M (LP_AONCLKRST_PLL8M_CLK_FORCE_ON_V << LP_AONCLKRST_PLL8M_CLK_FORCE_ON_S) -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_PLL8M_CLK_FORCE_ON_S 29 -/** LP_AONCLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON (BIT(30)) -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_M (LP_AONCLKRST_XTAL_CLK_FORCE_ON_V << LP_AONCLKRST_XTAL_CLK_FORCE_ON_S) -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_S 30 -/** LP_AONCLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON (BIT(31)) -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_M (LP_AONCLKRST_FOSC_CLK_FORCE_ON_V << LP_AONCLKRST_FOSC_CLK_FORCE_ON_S) -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_S 31 - -/** LP_AONCLKRST_LP_RST_EN_REG register - * need_des - */ -#define LP_AONCLKRST_LP_RST_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0xc) -/** LP_AONCLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_HUK (BIT(24)) -#define LP_AONCLKRST_RST_EN_LP_HUK_M (LP_AONCLKRST_RST_EN_LP_HUK_V << LP_AONCLKRST_RST_EN_LP_HUK_S) -#define LP_AONCLKRST_RST_EN_LP_HUK_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_HUK_S 24 -/** LP_AONCLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_ANAPERI (BIT(25)) -#define LP_AONCLKRST_RST_EN_LP_ANAPERI_M (LP_AONCLKRST_RST_EN_LP_ANAPERI_V << LP_AONCLKRST_RST_EN_LP_ANAPERI_S) -#define LP_AONCLKRST_RST_EN_LP_ANAPERI_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_ANAPERI_S 25 -/** LP_AONCLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_WDT (BIT(26)) -#define LP_AONCLKRST_RST_EN_LP_WDT_M (LP_AONCLKRST_RST_EN_LP_WDT_V << LP_AONCLKRST_RST_EN_LP_WDT_S) -#define LP_AONCLKRST_RST_EN_LP_WDT_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_WDT_S 26 -/** LP_AONCLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_TIMER (BIT(27)) -#define LP_AONCLKRST_RST_EN_LP_TIMER_M (LP_AONCLKRST_RST_EN_LP_TIMER_V << LP_AONCLKRST_RST_EN_LP_TIMER_S) -#define LP_AONCLKRST_RST_EN_LP_TIMER_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_TIMER_S 27 -/** LP_AONCLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_RTC (BIT(28)) -#define LP_AONCLKRST_RST_EN_LP_RTC_M (LP_AONCLKRST_RST_EN_LP_RTC_V << LP_AONCLKRST_RST_EN_LP_RTC_S) -#define LP_AONCLKRST_RST_EN_LP_RTC_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_RTC_S 28 -/** LP_AONCLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_MAILBOX (BIT(29)) -#define LP_AONCLKRST_RST_EN_LP_MAILBOX_M (LP_AONCLKRST_RST_EN_LP_MAILBOX_V << LP_AONCLKRST_RST_EN_LP_MAILBOX_S) -#define LP_AONCLKRST_RST_EN_LP_MAILBOX_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_MAILBOX_S 29 -/** LP_AONCLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG (BIT(30)) -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_M (LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_V << LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_S) -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_S 30 -/** LP_AONCLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_RST_EN_LP_RAM (BIT(31)) -#define LP_AONCLKRST_RST_EN_LP_RAM_M (LP_AONCLKRST_RST_EN_LP_RAM_V << LP_AONCLKRST_RST_EN_LP_RAM_S) -#define LP_AONCLKRST_RST_EN_LP_RAM_V 0x00000001U -#define LP_AONCLKRST_RST_EN_LP_RAM_S 31 - -/** LP_AONCLKRST_RESET_CAUSE_REG register - * need_des - */ -#define LP_AONCLKRST_RESET_CAUSE_REG (DR_REG_LP_AONCLKRST_BASE + 0x10) -/** LP_AONCLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0; - * 6'h1: POR reset - * 6'h9: PMU LP PERI power down reset - * 6'ha: PMU LP CPU reset - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: software reset - */ -#define LP_AONCLKRST_LPCORE_RESET_CAUSE 0x0000003FU -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_M (LP_AONCLKRST_LPCORE_RESET_CAUSE_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_S) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_V 0x0000003FU -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_S 0 -/** LP_AONCLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LPCORE_RESET_FLAG (BIT(6)) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_M (LP_AONCLKRST_LPCORE_RESET_FLAG_V << LP_AONCLKRST_LPCORE_RESET_FLAG_S) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_FLAG_S 6 -/** LP_AONCLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0; - * 6'h1: POR reset - * 6'h3: digital system software reset - * 6'h5: PMU HP system power down reset - * 6'h7: HP system reset from HP watchdog - * 6'h9: HP system reset from LP watchdog - * 6'hb: HP core reset from HP watchdog - * 6'hc: HP core software reset - * 6'hd: HP core reset from LP watchdog - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: efuse crc error reset - * 6'h16: HP usb jtag chip reset - * 6'h17: HP usb uart chip reset - * 6'h18: HP jtag reset - * 6'h1a: HP core lockup - */ -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE 0x0000003FU -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_M (LP_AONCLKRST_HPCORE0_RESET_CAUSE_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_S) -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_V 0x0000003FU -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_S 7 -/** LP_AONCLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_RESET_FLAG (BIT(13)) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_M (LP_AONCLKRST_HPCORE0_RESET_FLAG_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_S) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_S 13 -/** LP_AONCLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0; - * 6'h1: POR reset - * 6'h3: digital system software reset - * 6'h5: PMU HP system power down reset - * 6'h7: HP system reset from HP watchdog - * 6'h9: HP system reset from LP watchdog - * 6'hb: HP core reset from HP watchdog - * 6'hc: HP core software reset - * 6'hd: HP core reset from LP watchdog - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: efuse crc error reset - * 6'h16: HP usb jtag chip reset - * 6'h17: HP usb uart chip reset - * 6'h18: HP jtag reset - * 6'h1a: HP core lockup - */ -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE 0x0000003FU -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_M (LP_AONCLKRST_HPCORE1_RESET_CAUSE_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_S) -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_V 0x0000003FU -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_S 14 -/** LP_AONCLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_RESET_FLAG (BIT(20)) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_M (LP_AONCLKRST_HPCORE1_RESET_FLAG_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_S) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_S 20 -/** LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1; - * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore - * pmu_lp_cpu_reset reset_cause - */ -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK (BIT(25)) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M (LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S 25 -/** LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR (BIT(26)) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_M (LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S) -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S 26 -/** LP_AONCLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0; - * need_des - */ -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR (BIT(27)) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_M (LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V << LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S) -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V 0x00000001U -#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S 27 -/** LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR (BIT(28)) -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_M (LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S) -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S 28 -/** LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR (BIT(29)) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_M (LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S) -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S 29 -/** LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR (BIT(30)) -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_M (LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S) -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S 30 -/** LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR (BIT(31)) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_M (LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S) -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S 31 - -/** LP_AONCLKRST_HPCPU_RESET_CTRL0_REG register - * need_des - */ -#define LP_AONCLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_AONCLKRST_BASE + 0x14) -/** LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0; - * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup - * reset feature - */ -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(0)) -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S) -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S 0 -/** LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1; - * need_des - */ -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M (LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S) -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S 1 -/** LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0; - * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset - * hpcore0 feature - */ -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN (BIT(4)) -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_M (LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_S) -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_S 4 -/** LP_AONCLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_STALL_WAIT 0x0000007FU -#define LP_AONCLKRST_HPCORE0_STALL_WAIT_M (LP_AONCLKRST_HPCORE0_STALL_WAIT_V << LP_AONCLKRST_HPCORE0_STALL_WAIT_S) -#define LP_AONCLKRST_HPCORE0_STALL_WAIT_V 0x0000007FU -#define LP_AONCLKRST_HPCORE0_STALL_WAIT_S 5 -/** LP_AONCLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_STALL_EN (BIT(12)) -#define LP_AONCLKRST_HPCORE0_STALL_EN_M (LP_AONCLKRST_HPCORE0_STALL_EN_V << LP_AONCLKRST_HPCORE0_STALL_EN_S) -#define LP_AONCLKRST_HPCORE0_STALL_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_STALL_EN_S 12 -/** LP_AONCLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_SW_RESET (BIT(13)) -#define LP_AONCLKRST_HPCORE0_SW_RESET_M (LP_AONCLKRST_HPCORE0_SW_RESET_V << LP_AONCLKRST_HPCORE0_SW_RESET_S) -#define LP_AONCLKRST_HPCORE0_SW_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_SW_RESET_S 13 -/** LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET (BIT(14)) -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_M (LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S) -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S 14 -/** LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1; - * 1'b1: boot from HP TCM ROM: 0x4FC00000 - * 1'b0: boot from LP TCM RAM: 0x50108000 - */ -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL (BIT(15)) -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_M (LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S) -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V 0x00000001U -#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S 15 -/** LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0; - * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup - * reset feature - */ -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(16)) -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S) -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S 16 -/** LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1; - * need_des - */ -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M (LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S) -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V 0x00000007U -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S 17 -/** LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0; - * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset - * hpcore1 feature - */ -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN (BIT(20)) -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_M (LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_S) -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_V 0x00000001U -#define LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_S 20 -/** LP_AONCLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_STALL_WAIT 0x0000007FU -#define LP_AONCLKRST_HPCORE1_STALL_WAIT_M (LP_AONCLKRST_HPCORE1_STALL_WAIT_V << LP_AONCLKRST_HPCORE1_STALL_WAIT_S) -#define LP_AONCLKRST_HPCORE1_STALL_WAIT_V 0x0000007FU -#define LP_AONCLKRST_HPCORE1_STALL_WAIT_S 21 -/** LP_AONCLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_STALL_EN (BIT(28)) -#define LP_AONCLKRST_HPCORE1_STALL_EN_M (LP_AONCLKRST_HPCORE1_STALL_EN_V << LP_AONCLKRST_HPCORE1_STALL_EN_S) -#define LP_AONCLKRST_HPCORE1_STALL_EN_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_STALL_EN_S 28 -/** LP_AONCLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_SW_RESET (BIT(29)) -#define LP_AONCLKRST_HPCORE1_SW_RESET_M (LP_AONCLKRST_HPCORE1_SW_RESET_V << LP_AONCLKRST_HPCORE1_SW_RESET_S) -#define LP_AONCLKRST_HPCORE1_SW_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_SW_RESET_S 29 -/** LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET (BIT(30)) -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_M (LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S) -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S 30 -/** LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1; - * 1'b1: boot from HP TCM ROM: 0x4FC00000 - * 1'b0: boot from LP TCM RAM: 0x50108000 - */ -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL (BIT(31)) -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_M (LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S) -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V 0x00000001U -#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S 31 - -/** LP_AONCLKRST_HPCPU_RESET_CTRL1_REG register - * need_des - */ -#define LP_AONCLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_AONCLKRST_BASE + 0x18) -/** LP_AONCLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; - * HP core0 software stall when set to 8'h86 - */ -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE 0x000000FFU -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_M (LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S) -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V 0x000000FFU -#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S 16 -/** LP_AONCLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; - * HP core1 software stall when set to 8'h86 - */ -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE 0x000000FFU -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_M (LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S) -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V 0x000000FFU -#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S 24 - -/** LP_AONCLKRST_FOSC_CNTL_REG register - * need_des - */ -#define LP_AONCLKRST_FOSC_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x1c) -/** LP_AONCLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400; - * need_des - */ -#define LP_AONCLKRST_FOSC_DFREQ 0x000003FFU -#define LP_AONCLKRST_FOSC_DFREQ_M (LP_AONCLKRST_FOSC_DFREQ_V << LP_AONCLKRST_FOSC_DFREQ_S) -#define LP_AONCLKRST_FOSC_DFREQ_V 0x000003FFU -#define LP_AONCLKRST_FOSC_DFREQ_S 22 - -/** LP_AONCLKRST_RC32K_CNTL_REG register - * need_des - */ -#define LP_AONCLKRST_RC32K_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x20) -/** LP_AONCLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650; - * need_des - */ -#define LP_AONCLKRST_RC32K_DFREQ 0xFFFFFFFFU -#define LP_AONCLKRST_RC32K_DFREQ_M (LP_AONCLKRST_RC32K_DFREQ_V << LP_AONCLKRST_RC32K_DFREQ_S) -#define LP_AONCLKRST_RC32K_DFREQ_V 0xFFFFFFFFU -#define LP_AONCLKRST_RC32K_DFREQ_S 0 - -/** LP_AONCLKRST_SOSC_CNTL_REG register - * need_des - */ -#define LP_AONCLKRST_SOSC_CNTL_REG (DR_REG_LP_AONCLKRST_BASE + 0x24) -/** LP_AONCLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; - * need_des - */ -#define LP_AONCLKRST_SOSC_DFREQ 0x000003FFU -#define LP_AONCLKRST_SOSC_DFREQ_M (LP_AONCLKRST_SOSC_DFREQ_V << LP_AONCLKRST_SOSC_DFREQ_S) -#define LP_AONCLKRST_SOSC_DFREQ_V 0x000003FFU -#define LP_AONCLKRST_SOSC_DFREQ_S 22 - -/** LP_AONCLKRST_CLK_TO_HP_REG register - * need_des - */ -#define LP_AONCLKRST_CLK_TO_HP_REG (DR_REG_LP_AONCLKRST_BASE + 0x28) -/** LP_AONCLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_XTAL32K (BIT(28)) -#define LP_AONCLKRST_ICG_HP_XTAL32K_M (LP_AONCLKRST_ICG_HP_XTAL32K_V << LP_AONCLKRST_ICG_HP_XTAL32K_S) -#define LP_AONCLKRST_ICG_HP_XTAL32K_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_XTAL32K_S 28 -/** LP_AONCLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_SOSC (BIT(29)) -#define LP_AONCLKRST_ICG_HP_SOSC_M (LP_AONCLKRST_ICG_HP_SOSC_V << LP_AONCLKRST_ICG_HP_SOSC_S) -#define LP_AONCLKRST_ICG_HP_SOSC_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_SOSC_S 29 -/** LP_AONCLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_OSC32K (BIT(30)) -#define LP_AONCLKRST_ICG_HP_OSC32K_M (LP_AONCLKRST_ICG_HP_OSC32K_V << LP_AONCLKRST_ICG_HP_OSC32K_S) -#define LP_AONCLKRST_ICG_HP_OSC32K_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_OSC32K_S 30 -/** LP_AONCLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; - * reserved - */ -#define LP_AONCLKRST_ICG_HP_FOSC (BIT(31)) -#define LP_AONCLKRST_ICG_HP_FOSC_M (LP_AONCLKRST_ICG_HP_FOSC_V << LP_AONCLKRST_ICG_HP_FOSC_S) -#define LP_AONCLKRST_ICG_HP_FOSC_V 0x00000001U -#define LP_AONCLKRST_ICG_HP_FOSC_S 31 - -/** LP_AONCLKRST_LPMEM_FORCE_REG register - * need_des - */ -#define LP_AONCLKRST_LPMEM_FORCE_REG (DR_REG_LP_AONCLKRST_BASE + 0x2c) -/** LP_AONCLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; - * reserved - */ -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_M (LP_AONCLKRST_LPMEM_CLK_FORCE_ON_V << LP_AONCLKRST_LPMEM_CLK_FORCE_ON_S) -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U -#define LP_AONCLKRST_LPMEM_CLK_FORCE_ON_S 31 - -/** LP_AONCLKRST_XTAL32K_REG register - * need_des - */ -#define LP_AONCLKRST_XTAL32K_REG (DR_REG_LP_AONCLKRST_BASE + 0x30) -/** LP_AONCLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; - * need_des - */ -#define LP_AONCLKRST_DRES_XTAL32K 0x00000007U -#define LP_AONCLKRST_DRES_XTAL32K_M (LP_AONCLKRST_DRES_XTAL32K_V << LP_AONCLKRST_DRES_XTAL32K_S) -#define LP_AONCLKRST_DRES_XTAL32K_V 0x00000007U -#define LP_AONCLKRST_DRES_XTAL32K_S 22 -/** LP_AONCLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; - * need_des - */ -#define LP_AONCLKRST_DGM_XTAL32K 0x00000007U -#define LP_AONCLKRST_DGM_XTAL32K_M (LP_AONCLKRST_DGM_XTAL32K_V << LP_AONCLKRST_DGM_XTAL32K_S) -#define LP_AONCLKRST_DGM_XTAL32K_V 0x00000007U -#define LP_AONCLKRST_DGM_XTAL32K_S 25 -/** LP_AONCLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_AONCLKRST_DBUF_XTAL32K (BIT(28)) -#define LP_AONCLKRST_DBUF_XTAL32K_M (LP_AONCLKRST_DBUF_XTAL32K_V << LP_AONCLKRST_DBUF_XTAL32K_S) -#define LP_AONCLKRST_DBUF_XTAL32K_V 0x00000001U -#define LP_AONCLKRST_DBUF_XTAL32K_S 28 -/** LP_AONCLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; - * need_des - */ -#define LP_AONCLKRST_DAC_XTAL32K 0x00000007U -#define LP_AONCLKRST_DAC_XTAL32K_M (LP_AONCLKRST_DAC_XTAL32K_V << LP_AONCLKRST_DAC_XTAL32K_S) -#define LP_AONCLKRST_DAC_XTAL32K_V 0x00000007U -#define LP_AONCLKRST_DAC_XTAL32K_S 29 - -/** LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_REG register - * need_des - */ -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x34) -/** LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS 0xFFFFFFFFU -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_M (LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_S) -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_V 0xFFFFFFFFU -#define LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_S 0 - -/** LP_AONCLKRST_HPSYS_0_RESET_BYPASS_REG register - * need_des - */ -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x38) -/** LP_AONCLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_M (LP_AONCLKRST_HPSYS_0_RESET_BYPASS_V << LP_AONCLKRST_HPSYS_0_RESET_BYPASS_S) -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_V 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_0_RESET_BYPASS_S 0 - -/** LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_REG register - * need_des - */ -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_AONCLKRST_BASE + 0x3c) -/** LP_AONCLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_M (LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_V << LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_S) -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_V 0xFFFFFFFFU -#define LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_S 0 - -/** LP_AONCLKRST_HP_CLK_CTRL_REG register - * HP Clock Control Register. - */ -#define LP_AONCLKRST_HP_CLK_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x40) -/** LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0; - * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. - */ -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL 0x00000003U -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_M (LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_S) -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_V 0x00000003U -#define LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_S 0 -/** LP_AONCLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1; - * HP SoC Root Clock Enable. - */ -#define LP_AONCLKRST_HP_ROOT_CLK_EN (BIT(2)) -#define LP_AONCLKRST_HP_ROOT_CLK_EN_M (LP_AONCLKRST_HP_ROOT_CLK_EN_V << LP_AONCLKRST_HP_ROOT_CLK_EN_S) -#define LP_AONCLKRST_HP_ROOT_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_ROOT_CLK_EN_S 2 -/** LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1; - * PARLIO TX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN (BIT(3)) -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_M (LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_S 3 -/** LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1; - * PARLIO RX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN (BIT(4)) -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_M (LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_S 4 -/** LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1; - * UART4 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN (BIT(5)) -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_S 5 -/** LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1; - * UART3 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN (BIT(6)) -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_S 6 -/** LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1; - * UART2 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN (BIT(7)) -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_S 7 -/** LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1; - * UART1 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN (BIT(8)) -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_S 8 -/** LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1; - * UART0 SLP Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN (BIT(9)) -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_M (LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_S 9 -/** LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1; - * I2S2 MCLK Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN (BIT(10)) -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_M (LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_S) -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_S 10 -/** LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1; - * I2S1 MCLK Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN (BIT(11)) -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_M (LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_S) -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_S 11 -/** LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1; - * I2S0 MCLK Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN (BIT(12)) -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_M (LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_S) -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_S 12 -/** LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1; - * EMAC RX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN (BIT(13)) -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_M (LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_S 13 -/** LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1; - * EMAC TX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN (BIT(14)) -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_M (LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_S 14 -/** LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1; - * EMAC TXRX Clock From Pad Enable. - */ -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN (BIT(15)) -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M (LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S) -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S 15 -/** LP_AONCLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1; - * XTAL 32K Clock Enable. - */ -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN (BIT(16)) -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_M (LP_AONCLKRST_HP_XTAL_32K_CLK_EN_V << LP_AONCLKRST_HP_XTAL_32K_CLK_EN_S) -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_XTAL_32K_CLK_EN_S 16 -/** LP_AONCLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1; - * RC 32K Clock Enable. - */ -#define LP_AONCLKRST_HP_RC_32K_CLK_EN (BIT(17)) -#define LP_AONCLKRST_HP_RC_32K_CLK_EN_M (LP_AONCLKRST_HP_RC_32K_CLK_EN_V << LP_AONCLKRST_HP_RC_32K_CLK_EN_S) -#define LP_AONCLKRST_HP_RC_32K_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_RC_32K_CLK_EN_S 17 -/** LP_AONCLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1; - * SOSC 150K Clock Enable. - */ -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN (BIT(18)) -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_M (LP_AONCLKRST_HP_SOSC_150K_CLK_EN_V << LP_AONCLKRST_HP_SOSC_150K_CLK_EN_S) -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SOSC_150K_CLK_EN_S 18 -/** LP_AONCLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1; - * PLL 8M Clock Enable. - */ -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN (BIT(19)) -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_M (LP_AONCLKRST_HP_PLL_8M_CLK_EN_V << LP_AONCLKRST_HP_PLL_8M_CLK_EN_S) -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_PLL_8M_CLK_EN_S 19 -/** LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1; - * AUDIO PLL Clock Enable. - */ -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN (BIT(20)) -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_M (LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_S) -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_S 20 -/** LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1; - * SDIO PLL2 Clock Enable. - */ -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN (BIT(21)) -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_M (LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_S) -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_S 21 -/** LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1; - * SDIO PLL1 Clock Enable. - */ -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN (BIT(22)) -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_M (LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_S) -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_S 22 -/** LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1; - * SDIO PLL0 Clock Enable. - */ -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN (BIT(23)) -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_M (LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_S) -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_S 23 -/** LP_AONCLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1; - * FOSC 20M Clock Enable. - */ -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN (BIT(24)) -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_M (LP_AONCLKRST_HP_FOSC_20M_CLK_EN_V << LP_AONCLKRST_HP_FOSC_20M_CLK_EN_S) -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_FOSC_20M_CLK_EN_S 24 -/** LP_AONCLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1; - * XTAL 40M Clock Enalbe. - */ -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN (BIT(25)) -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_M (LP_AONCLKRST_HP_XTAL_40M_CLK_EN_V << LP_AONCLKRST_HP_XTAL_40M_CLK_EN_S) -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_XTAL_40M_CLK_EN_S 25 -/** LP_AONCLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1; - * CPLL 400M Clock Enable. - */ -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN (BIT(26)) -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_M (LP_AONCLKRST_HP_CPLL_400M_CLK_EN_V << LP_AONCLKRST_HP_CPLL_400M_CLK_EN_S) -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_CPLL_400M_CLK_EN_S 26 -/** LP_AONCLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1; - * SPLL 480M Clock Enable. - */ -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN (BIT(27)) -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_M (LP_AONCLKRST_HP_SPLL_480M_CLK_EN_V << LP_AONCLKRST_HP_SPLL_480M_CLK_EN_S) -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_SPLL_480M_CLK_EN_S 27 -/** LP_AONCLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1; - * MPLL 500M Clock Enable. - */ -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN (BIT(28)) -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_M (LP_AONCLKRST_HP_MPLL_500M_CLK_EN_V << LP_AONCLKRST_HP_MPLL_500M_CLK_EN_S) -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_HP_MPLL_500M_CLK_EN_S 28 - -/** LP_AONCLKRST_HP_USB_CLKRST_CTRL0_REG register - * HP USB Clock Reset Control Register. - */ -#define LP_AONCLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_AONCLKRST_BASE + 0x44) -/** LP_AONCLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0; - * unused. - */ -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE (BIT(0)) -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_M (LP_AONCLKRST_USB_OTG20_SLEEP_MODE_V << LP_AONCLKRST_USB_OTG20_SLEEP_MODE_S) -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_SLEEP_MODE_S 0 -/** LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; - * unused. - */ -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN (BIT(1)) -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_M (LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_S 1 -/** LP_AONCLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0; - * unused. - */ -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE (BIT(2)) -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_M (LP_AONCLKRST_USB_OTG11_SLEEP_MODE_V << LP_AONCLKRST_USB_OTG11_SLEEP_MODE_S) -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_V 0x00000001U -#define LP_AONCLKRST_USB_OTG11_SLEEP_MODE_S 2 -/** LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1; - * unused. - */ -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN (BIT(3)) -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_M (LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_S 3 -/** LP_AONCLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1; - * usb otg11 fs phy clock enable. - */ -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN (BIT(4)) -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_M (LP_AONCLKRST_USB_OTG11_48M_CLK_EN_V << LP_AONCLKRST_USB_OTG11_48M_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG11_48M_CLK_EN_S 4 -/** LP_AONCLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1; - * usb device fs phy clock enable. - */ -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN (BIT(5)) -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_M (LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_V << LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_S) -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_S 5 -/** LP_AONCLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9; - * usb 480m to 25m divide number. - */ -#define LP_AONCLKRST_USB_48M_DIV_NUM 0x000000FFU -#define LP_AONCLKRST_USB_48M_DIV_NUM_M (LP_AONCLKRST_USB_48M_DIV_NUM_V << LP_AONCLKRST_USB_48M_DIV_NUM_S) -#define LP_AONCLKRST_USB_48M_DIV_NUM_V 0x000000FFU -#define LP_AONCLKRST_USB_48M_DIV_NUM_S 6 -/** LP_AONCLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19; - * usb 500m to 25m divide number. - */ -#define LP_AONCLKRST_USB_25M_DIV_NUM 0x000000FFU -#define LP_AONCLKRST_USB_25M_DIV_NUM_M (LP_AONCLKRST_USB_25M_DIV_NUM_V << LP_AONCLKRST_USB_25M_DIV_NUM_S) -#define LP_AONCLKRST_USB_25M_DIV_NUM_V 0x000000FFU -#define LP_AONCLKRST_USB_25M_DIV_NUM_S 14 -/** LP_AONCLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39; - * usb 480m to 12m divide number. - */ -#define LP_AONCLKRST_USB_12M_DIV_NUM 0x000000FFU -#define LP_AONCLKRST_USB_12M_DIV_NUM_M (LP_AONCLKRST_USB_12M_DIV_NUM_V << LP_AONCLKRST_USB_12M_DIV_NUM_S) -#define LP_AONCLKRST_USB_12M_DIV_NUM_V 0x000000FFU -#define LP_AONCLKRST_USB_12M_DIV_NUM_S 22 - -/** LP_AONCLKRST_HP_USB_CLKRST_CTRL1_REG register - * HP USB Clock Reset Control Register. - */ -#define LP_AONCLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_AONCLKRST_BASE + 0x48) -/** LP_AONCLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0; - * usb otg20 adp reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP (BIT(0)) -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_M (LP_AONCLKRST_RST_EN_USB_OTG20_ADP_V << LP_AONCLKRST_RST_EN_USB_OTG20_ADP_S) -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG20_ADP_S 0 -/** LP_AONCLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0; - * usb otg20 phy reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY (BIT(1)) -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_M (LP_AONCLKRST_RST_EN_USB_OTG20_PHY_V << LP_AONCLKRST_RST_EN_USB_OTG20_PHY_S) -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG20_PHY_S 1 -/** LP_AONCLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0; - * usb otg20 reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG20 (BIT(2)) -#define LP_AONCLKRST_RST_EN_USB_OTG20_M (LP_AONCLKRST_RST_EN_USB_OTG20_V << LP_AONCLKRST_RST_EN_USB_OTG20_S) -#define LP_AONCLKRST_RST_EN_USB_OTG20_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG20_S 2 -/** LP_AONCLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0; - * usb org11 reset en - */ -#define LP_AONCLKRST_RST_EN_USB_OTG11 (BIT(3)) -#define LP_AONCLKRST_RST_EN_USB_OTG11_M (LP_AONCLKRST_RST_EN_USB_OTG11_V << LP_AONCLKRST_RST_EN_USB_OTG11_S) -#define LP_AONCLKRST_RST_EN_USB_OTG11_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_OTG11_S 3 -/** LP_AONCLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0; - * usb device reset en - */ -#define LP_AONCLKRST_RST_EN_USB_DEVICE (BIT(4)) -#define LP_AONCLKRST_RST_EN_USB_DEVICE_M (LP_AONCLKRST_RST_EN_USB_DEVICE_V << LP_AONCLKRST_RST_EN_USB_DEVICE_S) -#define LP_AONCLKRST_RST_EN_USB_DEVICE_V 0x00000001U -#define LP_AONCLKRST_RST_EN_USB_DEVICE_S 4 -/** LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0; - * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. - */ -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL 0x00000003U -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M (LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S) -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V 0x00000003U -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S 28 -/** LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1; - * usb otg20 hs phy refclk enable. - */ -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN (BIT(30)) -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_M (LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_S 30 -/** LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1; - * usb otg20 ulpi clock enable. - */ -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN (BIT(31)) -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_M (LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_S) -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_S 31 - -/** LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register - * need_des - */ -#define LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x4c) -/** LP_AONCLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0; - * hp sdmmc reset en - */ -#define LP_AONCLKRST_RST_EN_SDMMC (BIT(28)) -#define LP_AONCLKRST_RST_EN_SDMMC_M (LP_AONCLKRST_RST_EN_SDMMC_V << LP_AONCLKRST_RST_EN_SDMMC_S) -#define LP_AONCLKRST_RST_EN_SDMMC_V 0x00000001U -#define LP_AONCLKRST_RST_EN_SDMMC_S 28 -/** LP_AONCLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0; - * hp sdmmc force norst - */ -#define LP_AONCLKRST_FORCE_NORST_SDMMC (BIT(29)) -#define LP_AONCLKRST_FORCE_NORST_SDMMC_M (LP_AONCLKRST_FORCE_NORST_SDMMC_V << LP_AONCLKRST_FORCE_NORST_SDMMC_S) -#define LP_AONCLKRST_FORCE_NORST_SDMMC_V 0x00000001U -#define LP_AONCLKRST_FORCE_NORST_SDMMC_S 29 -/** LP_AONCLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0; - * hp emac reset en - */ -#define LP_AONCLKRST_RST_EN_EMAC (BIT(30)) -#define LP_AONCLKRST_RST_EN_EMAC_M (LP_AONCLKRST_RST_EN_EMAC_V << LP_AONCLKRST_RST_EN_EMAC_S) -#define LP_AONCLKRST_RST_EN_EMAC_V 0x00000001U -#define LP_AONCLKRST_RST_EN_EMAC_S 30 -/** LP_AONCLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0; - * hp emac force norst - */ -#define LP_AONCLKRST_FORCE_NORST_EMAC (BIT(31)) -#define LP_AONCLKRST_FORCE_NORST_EMAC_M (LP_AONCLKRST_FORCE_NORST_EMAC_V << LP_AONCLKRST_FORCE_NORST_EMAC_S) -#define LP_AONCLKRST_FORCE_NORST_EMAC_V 0x00000001U -#define LP_AONCLKRST_FORCE_NORST_EMAC_S 31 - -/** LP_AONCLKRST_DATE_REG register - * need_des - */ -#define LP_AONCLKRST_DATE_REG (DR_REG_LP_AONCLKRST_BASE + 0x3fc) -/** LP_AONCLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_AONCLKRST_CLK_EN (BIT(31)) -#define LP_AONCLKRST_CLK_EN_M (LP_AONCLKRST_CLK_EN_V << LP_AONCLKRST_CLK_EN_S) -#define LP_AONCLKRST_CLK_EN_V 0x00000001U -#define LP_AONCLKRST_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h b/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h deleted file mode 100644 index 6012eb38d7..0000000000 --- a/components/soc/esp32p4/include/soc/lp_aonclkrst_struct.h +++ /dev/null @@ -1,795 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of lp_clk_conf register - * need_des - */ -typedef union { - struct { - /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; - * need_des - */ - uint32_t slow_clk_sel:2; - /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; - * need_des - */ - uint32_t fast_clk_sel:2; - /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0; - * need_des - */ - uint32_t lp_peri_div_num:6; - /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t ana_sel_ref_pll8m:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_aonclkrst_lp_clk_conf_reg_t; - -/** Type of lp_clk_po_en register - * need_des - */ -typedef union { - struct { - /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t clk_core_efuse_oen:1; - /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t clk_lp_bus_oen:1; - /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t clk_aon_slow_oen:1; - /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t clk_aon_fast_oen:1; - /** clk_slow_oen : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t clk_slow_oen:1; - /** clk_fast_oen : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t clk_fast_oen:1; - /** clk_fosc_oen : R/W; bitpos: [6]; default: 0; - * need_des - */ - uint32_t clk_fosc_oen:1; - /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t clk_rc32k_oen:1; - /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0; - * need_des - */ - uint32_t clk_sxtal_oen:1; - /** clk_sosc_oen : R/W; bitpos: [9]; default: 0; - * 1'b1: probe sosc clk on - * 1'b0: probe sosc clk off - */ - uint32_t clk_sosc_oen:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} lp_aonclkrst_lp_clk_po_en_reg_t; - -/** Type of lp_clk_en register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_rtc_xtal_force_on:1; - /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t ck_en_lp_ram:1; - /** etm_event_tick_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t etm_event_tick_en:1; - /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t pll8m_clk_force_on:1; - /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t xtal_clk_force_on:1; - /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t fosc_clk_force_on:1; - }; - uint32_t val; -} lp_aonclkrst_lp_clk_en_reg_t; - -/** Type of lp_rst_en register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t rst_en_lp_huk:1; - /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t rst_en_lp_anaperi:1; - /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t rst_en_lp_wdt:1; - /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t rst_en_lp_timer:1; - /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t rst_en_lp_rtc:1; - /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t rst_en_lp_mailbox:1; - /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t rst_en_lp_aonefusereg:1; - /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t rst_en_lp_ram:1; - }; - uint32_t val; -} lp_aonclkrst_lp_rst_en_reg_t; - -/** Type of reset_cause register - * need_des - */ -typedef union { - struct { - /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0; - * 6'h1: POR reset - * 6'h9: PMU LP PERI power down reset - * 6'ha: PMU LP CPU reset - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: software reset - */ - uint32_t lpcore_reset_cause:6; - /** lpcore_reset_flag : RO; bitpos: [6]; default: 0; - * need_des - */ - uint32_t lpcore_reset_flag:1; - /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0; - * 6'h1: POR reset - * 6'h3: digital system software reset - * 6'h5: PMU HP system power down reset - * 6'h7: HP system reset from HP watchdog - * 6'h9: HP system reset from LP watchdog - * 6'hb: HP core reset from HP watchdog - * 6'hc: HP core software reset - * 6'hd: HP core reset from LP watchdog - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: efuse crc error reset - * 6'h16: HP usb jtag chip reset - * 6'h17: HP usb uart chip reset - * 6'h18: HP jtag reset - * 6'h1a: HP core lockup - */ - uint32_t hpcore0_reset_cause:6; - /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0; - * need_des - */ - uint32_t hpcore0_reset_flag:1; - /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0; - * 6'h1: POR reset - * 6'h3: digital system software reset - * 6'h5: PMU HP system power down reset - * 6'h7: HP system reset from HP watchdog - * 6'h9: HP system reset from LP watchdog - * 6'hb: HP core reset from HP watchdog - * 6'hc: HP core software reset - * 6'hd: HP core reset from LP watchdog - * 6'hf: brown out reset - * 6'h10: LP watchdog chip reset - * 6'h12: super watch dog reset - * 6'h13: glitch reset - * 6'h14: efuse crc error reset - * 6'h16: HP usb jtag chip reset - * 6'h17: HP usb uart chip reset - * 6'h18: HP jtag reset - * 6'h1a: HP core lockup - */ - uint32_t hpcore1_reset_cause:6; - /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t hpcore1_reset_flag:1; - uint32_t reserved_21:4; - /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1; - * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore - * pmu_lp_cpu_reset reset_cause - */ - uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1; - /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lpcore_reset_cause_clr:1; - /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lpcore_reset_flag_clr:1; - /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hpcore0_reset_cause_clr:1; - /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hpcore0_reset_flag_clr:1; - /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hpcore1_reset_cause_clr:1; - /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hpcore1_reset_flag_clr:1; - }; - uint32_t val; -} lp_aonclkrst_reset_cause_reg_t; - -/** Type of hpcpu_reset_ctrl0 register - * need_des - */ -typedef union { - struct { - /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0; - * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup - * reset feature - */ - uint32_t hpcore0_lockup_reset_en:1; - /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1; - * need_des - */ - uint32_t lp_wdt_hpcore0_reset_length:3; - /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0; - * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset - * hpcore0 feature - */ - uint32_t lp_wdt_hpcore0_reset_en:1; - /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0; - * need_des - */ - uint32_t hpcore0_stall_wait:7; - /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t hpcore0_stall_en:1; - /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0; - * need_des - */ - uint32_t hpcore0_sw_reset:1; - /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t hpcore0_ocd_halt_on_reset:1; - /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1; - * 1'b1: boot from HP TCM ROM: 0x4FC00000 - * 1'b0: boot from LP TCM RAM: 0x50108000 - */ - uint32_t hpcore0_stat_vector_sel:1; - /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0; - * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup - * reset feature - */ - uint32_t hpcore1_lockup_reset_en:1; - /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1; - * need_des - */ - uint32_t lp_wdt_hpcore1_reset_length:3; - /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0; - * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset - * hpcore1 feature - */ - uint32_t lp_wdt_hpcore1_reset_en:1; - /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0; - * need_des - */ - uint32_t hpcore1_stall_wait:7; - /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hpcore1_stall_en:1; - /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hpcore1_sw_reset:1; - /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hpcore1_ocd_halt_on_reset:1; - /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1; - * 1'b1: boot from HP TCM ROM: 0x4FC00000 - * 1'b0: boot from LP TCM RAM: 0x50108000 - */ - uint32_t hpcore1_stat_vector_sel:1; - }; - uint32_t val; -} lp_aonclkrst_hpcpu_reset_ctrl0_reg_t; - -/** Type of hpcpu_reset_ctrl1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0; - * HP core0 software stall when set to 8'h86 - */ - uint32_t hpcore0_sw_stall_code:8; - /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0; - * HP core1 software stall when set to 8'h86 - */ - uint32_t hpcore1_sw_stall_code:8; - }; - uint32_t val; -} lp_aonclkrst_hpcpu_reset_ctrl1_reg_t; - -/** Type of fosc_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400; - * need_des - */ - uint32_t fosc_dfreq:10; - }; - uint32_t val; -} lp_aonclkrst_fosc_cntl_reg_t; - -/** Type of rc32k_cntl register - * need_des - */ -typedef union { - struct { - /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650; - * need_des - */ - uint32_t rc32k_dfreq:32; - }; - uint32_t val; -} lp_aonclkrst_rc32k_cntl_reg_t; - -/** Type of sosc_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172; - * need_des - */ - uint32_t sosc_dfreq:10; - }; - uint32_t val; -} lp_aonclkrst_sosc_cntl_reg_t; - -/** Type of clk_to_hp register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; - * reserved - */ - uint32_t icg_hp_xtal32k:1; - /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; - * reserved - */ - uint32_t icg_hp_sosc:1; - /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; - * reserved - */ - uint32_t icg_hp_osc32k:1; - /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; - * reserved - */ - uint32_t icg_hp_fosc:1; - }; - uint32_t val; -} lp_aonclkrst_clk_to_hp_reg_t; - -/** Type of lpmem_force register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; - * reserved - */ - uint32_t lpmem_clk_force_on:1; - }; - uint32_t val; -} lp_aonclkrst_lpmem_force_reg_t; - -/** Type of xtal32k register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; - * need_des - */ - uint32_t dres_xtal32k:3; - /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; - * need_des - */ - uint32_t dgm_xtal32k:3; - /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t dbuf_xtal32k:1; - /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; - * need_des - */ - uint32_t dac_xtal32k:3; - }; - uint32_t val; -} lp_aonclkrst_xtal32k_reg_t; - -/** Type of mux_hpsys_reset_bypass register - * need_des - */ -typedef union { - struct { - /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ - uint32_t mux_hpsys_reset_bypass:32; - }; - uint32_t val; -} lp_aonclkrst_mux_hpsys_reset_bypass_reg_t; - -/** Type of hpsys_0_reset_bypass register - * need_des - */ -typedef union { - struct { - /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ - uint32_t hpsys_0_reset_bypass:32; - }; - uint32_t val; -} lp_aonclkrst_hpsys_0_reset_bypass_reg_t; - -/** Type of hpsys_apm_reset_bypass register - * need_des - */ -typedef union { - struct { - /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ - uint32_t hpsys_apm_reset_bypass:32; - }; - uint32_t val; -} lp_aonclkrst_hpsys_apm_reset_bypass_reg_t; - -/** Type of hp_clk_ctrl register - * HP Clock Control Register. - */ -typedef union { - struct { - /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0; - * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. - */ - uint32_t hp_root_clk_src_sel:2; - /** hp_root_clk_en : R/W; bitpos: [2]; default: 1; - * HP SoC Root Clock Enable. - */ - uint32_t hp_root_clk_en:1; - /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1; - * PARLIO TX Clock From Pad Enable. - */ - uint32_t hp_pad_parlio_tx_clk_en:1; - /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1; - * PARLIO RX Clock From Pad Enable. - */ - uint32_t hp_pad_parlio_rx_clk_en:1; - /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1; - * UART4 SLP Clock From Pad Enable. - */ - uint32_t hp_pad_uart4_slp_clk_en:1; - /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1; - * UART3 SLP Clock From Pad Enable. - */ - uint32_t hp_pad_uart3_slp_clk_en:1; - /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1; - * UART2 SLP Clock From Pad Enable. - */ - uint32_t hp_pad_uart2_slp_clk_en:1; - /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1; - * UART1 SLP Clock From Pad Enable. - */ - uint32_t hp_pad_uart1_slp_clk_en:1; - /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1; - * UART0 SLP Clock From Pad Enable. - */ - uint32_t hp_pad_uart0_slp_clk_en:1; - /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1; - * I2S2 MCLK Clock From Pad Enable. - */ - uint32_t hp_pad_i2s2_mclk_en:1; - /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1; - * I2S1 MCLK Clock From Pad Enable. - */ - uint32_t hp_pad_i2s1_mclk_en:1; - /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1; - * I2S0 MCLK Clock From Pad Enable. - */ - uint32_t hp_pad_i2s0_mclk_en:1; - /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1; - * EMAC RX Clock From Pad Enable. - */ - uint32_t hp_pad_emac_tx_clk_en:1; - /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1; - * EMAC TX Clock From Pad Enable. - */ - uint32_t hp_pad_emac_rx_clk_en:1; - /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1; - * EMAC TXRX Clock From Pad Enable. - */ - uint32_t hp_pad_emac_txrx_clk_en:1; - /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1; - * XTAL 32K Clock Enable. - */ - uint32_t hp_xtal_32k_clk_en:1; - /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1; - * RC 32K Clock Enable. - */ - uint32_t hp_rc_32k_clk_en:1; - /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1; - * SOSC 150K Clock Enable. - */ - uint32_t hp_sosc_150k_clk_en:1; - /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1; - * PLL 8M Clock Enable. - */ - uint32_t hp_pll_8m_clk_en:1; - /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1; - * AUDIO PLL Clock Enable. - */ - uint32_t hp_audio_pll_clk_en:1; - /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1; - * SDIO PLL2 Clock Enable. - */ - uint32_t hp_sdio_pll2_clk_en:1; - /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1; - * SDIO PLL1 Clock Enable. - */ - uint32_t hp_sdio_pll1_clk_en:1; - /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1; - * SDIO PLL0 Clock Enable. - */ - uint32_t hp_sdio_pll0_clk_en:1; - /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1; - * FOSC 20M Clock Enable. - */ - uint32_t hp_fosc_20m_clk_en:1; - /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1; - * XTAL 40M Clock Enalbe. - */ - uint32_t hp_xtal_40m_clk_en:1; - /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1; - * CPLL 400M Clock Enable. - */ - uint32_t hp_cpll_400m_clk_en:1; - /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1; - * SPLL 480M Clock Enable. - */ - uint32_t hp_spll_480m_clk_en:1; - /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1; - * MPLL 500M Clock Enable. - */ - uint32_t hp_mpll_500m_clk_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} lp_aonclkrst_hp_clk_ctrl_reg_t; - -/** Type of hp_usb_clkrst_ctrl0 register - * HP USB Clock Reset Control Register. - */ -typedef union { - struct { - /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0; - * unused. - */ - uint32_t usb_otg20_sleep_mode:1; - /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1; - * unused. - */ - uint32_t usb_otg20_bk_sys_clk_en:1; - /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0; - * unused. - */ - uint32_t usb_otg11_sleep_mode:1; - /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1; - * unused. - */ - uint32_t usb_otg11_bk_sys_clk_en:1; - /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1; - * usb otg11 fs phy clock enable. - */ - uint32_t usb_otg11_48m_clk_en:1; - /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1; - * usb device fs phy clock enable. - */ - uint32_t usb_device_48m_clk_en:1; - /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9; - * usb 480m to 25m divide number. - */ - uint32_t usb_48m_div_num:8; - /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19; - * usb 500m to 25m divide number. - */ - uint32_t usb_25m_div_num:8; - /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39; - * usb 480m to 12m divide number. - */ - uint32_t usb_12m_div_num:8; - uint32_t reserved_30:2; - }; - uint32_t val; -} lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t; - -/** Type of hp_usb_clkrst_ctrl1 register - * HP USB Clock Reset Control Register. - */ -typedef union { - struct { - /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0; - * usb otg20 adp reset en - */ - uint32_t rst_en_usb_otg20_adp:1; - /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0; - * usb otg20 phy reset en - */ - uint32_t rst_en_usb_otg20_phy:1; - /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0; - * usb otg20 reset en - */ - uint32_t rst_en_usb_otg20:1; - /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0; - * usb org11 reset en - */ - uint32_t rst_en_usb_otg11:1; - /** rst_en_usb_device : R/W; bitpos: [4]; default: 0; - * usb device reset en - */ - uint32_t rst_en_usb_device:1; - uint32_t reserved_5:23; - /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0; - * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. - */ - uint32_t usb_otg20_phyref_clk_src_sel:2; - /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1; - * usb otg20 hs phy refclk enable. - */ - uint32_t usb_otg20_phyref_clk_en:1; - /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1; - * usb otg20 ulpi clock enable. - */ - uint32_t usb_otg20_ulpi_clk_en:1; - }; - uint32_t val; -} lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t; - -/** Type of hp_sdmmc_emac_rst_ctrl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0; - * hp sdmmc reset en - */ - uint32_t rst_en_sdmmc:1; - /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0; - * hp sdmmc force norst - */ - uint32_t force_norst_sdmmc:1; - /** rst_en_emac : R/W; bitpos: [30]; default: 0; - * hp emac reset en - */ - uint32_t rst_en_emac:1; - /** force_norst_emac : R/W; bitpos: [31]; default: 0; - * hp emac force norst - */ - uint32_t force_norst_emac:1; - }; - uint32_t val; -} lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t; - -/** Type of date register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} lp_aonclkrst_date_reg_t; - - -typedef struct { - volatile lp_aonclkrst_lp_clk_conf_reg_t lp_clk_conf; - volatile lp_aonclkrst_lp_clk_po_en_reg_t lp_clk_po_en; - volatile lp_aonclkrst_lp_clk_en_reg_t lp_clk_en; - volatile lp_aonclkrst_lp_rst_en_reg_t lp_rst_en; - volatile lp_aonclkrst_reset_cause_reg_t reset_cause; - volatile lp_aonclkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0; - volatile lp_aonclkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1; - volatile lp_aonclkrst_fosc_cntl_reg_t fosc_cntl; - volatile lp_aonclkrst_rc32k_cntl_reg_t rc32k_cntl; - volatile lp_aonclkrst_sosc_cntl_reg_t sosc_cntl; - volatile lp_aonclkrst_clk_to_hp_reg_t clk_to_hp; - volatile lp_aonclkrst_lpmem_force_reg_t lpmem_force; - volatile lp_aonclkrst_xtal32k_reg_t xtal32k; - volatile lp_aonclkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass; - volatile lp_aonclkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass; - volatile lp_aonclkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass; - volatile lp_aonclkrst_hp_clk_ctrl_reg_t hp_clk_ctrl; - volatile lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0; - volatile lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1; - volatile lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl; - uint32_t reserved_050[235]; - volatile lp_aonclkrst_date_reg_t date; -} lp_aonclkrst_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_apm0_reg.h b/components/soc/esp32p4/include/soc/lp_apm0_reg.h deleted file mode 100644 index 495cc35ba2..0000000000 --- a/components/soc/esp32p4/include/soc/lp_apm0_reg.h +++ /dev/null @@ -1,506 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_APM0_REGION_FILTER_EN_REG register - * Region filter enable register - */ -#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) -/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; - * Region filter enable - */ -#define LP_APM0_REGION_FILTER_EN 0x0000000FU -#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) -#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU -#define LP_APM0_REGION_FILTER_EN_S 0 - -/** LP_APM0_REGION0_ADDR_START_REG register - * Region address register - */ -#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) -/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region0 - */ -#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU -#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) -#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU -#define LP_APM0_REGION0_ADDR_START_S 0 - -/** LP_APM0_REGION0_ADDR_END_REG register - * Region address register - */ -#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) -/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region0 - */ -#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU -#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) -#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU -#define LP_APM0_REGION0_ADDR_END_S 0 - -/** LP_APM0_REGION0_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) -/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM0_REGION0_R0_PMS_X (BIT(0)) -#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S) -#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U -#define LP_APM0_REGION0_R0_PMS_X_S 0 -/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM0_REGION0_R0_PMS_W (BIT(1)) -#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S) -#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U -#define LP_APM0_REGION0_R0_PMS_W_S 1 -/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM0_REGION0_R0_PMS_R (BIT(2)) -#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S) -#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U -#define LP_APM0_REGION0_R0_PMS_R_S 2 -/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM0_REGION0_R1_PMS_X (BIT(4)) -#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S) -#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U -#define LP_APM0_REGION0_R1_PMS_X_S 4 -/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM0_REGION0_R1_PMS_W (BIT(5)) -#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S) -#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U -#define LP_APM0_REGION0_R1_PMS_W_S 5 -/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM0_REGION0_R1_PMS_R (BIT(6)) -#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S) -#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U -#define LP_APM0_REGION0_R1_PMS_R_S 6 -/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM0_REGION0_R2_PMS_X (BIT(8)) -#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S) -#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U -#define LP_APM0_REGION0_R2_PMS_X_S 8 -/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM0_REGION0_R2_PMS_W (BIT(9)) -#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S) -#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U -#define LP_APM0_REGION0_R2_PMS_W_S 9 -/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM0_REGION0_R2_PMS_R (BIT(10)) -#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S) -#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U -#define LP_APM0_REGION0_R2_PMS_R_S 10 - -/** LP_APM0_REGION1_ADDR_START_REG register - * Region address register - */ -#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) -/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region1 - */ -#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU -#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) -#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU -#define LP_APM0_REGION1_ADDR_START_S 0 - -/** LP_APM0_REGION1_ADDR_END_REG register - * Region address register - */ -#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) -/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region1 - */ -#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU -#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) -#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU -#define LP_APM0_REGION1_ADDR_END_S 0 - -/** LP_APM0_REGION1_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) -/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM0_REGION1_R0_PMS_X (BIT(0)) -#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S) -#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U -#define LP_APM0_REGION1_R0_PMS_X_S 0 -/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM0_REGION1_R0_PMS_W (BIT(1)) -#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S) -#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U -#define LP_APM0_REGION1_R0_PMS_W_S 1 -/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM0_REGION1_R0_PMS_R (BIT(2)) -#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S) -#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U -#define LP_APM0_REGION1_R0_PMS_R_S 2 -/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM0_REGION1_R1_PMS_X (BIT(4)) -#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S) -#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U -#define LP_APM0_REGION1_R1_PMS_X_S 4 -/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM0_REGION1_R1_PMS_W (BIT(5)) -#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S) -#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U -#define LP_APM0_REGION1_R1_PMS_W_S 5 -/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM0_REGION1_R1_PMS_R (BIT(6)) -#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S) -#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U -#define LP_APM0_REGION1_R1_PMS_R_S 6 -/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM0_REGION1_R2_PMS_X (BIT(8)) -#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S) -#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U -#define LP_APM0_REGION1_R2_PMS_X_S 8 -/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM0_REGION1_R2_PMS_W (BIT(9)) -#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S) -#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U -#define LP_APM0_REGION1_R2_PMS_W_S 9 -/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM0_REGION1_R2_PMS_R (BIT(10)) -#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S) -#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U -#define LP_APM0_REGION1_R2_PMS_R_S 10 - -/** LP_APM0_REGION2_ADDR_START_REG register - * Region address register - */ -#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) -/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region2 - */ -#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU -#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) -#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU -#define LP_APM0_REGION2_ADDR_START_S 0 - -/** LP_APM0_REGION2_ADDR_END_REG register - * Region address register - */ -#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) -/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region2 - */ -#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU -#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) -#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU -#define LP_APM0_REGION2_ADDR_END_S 0 - -/** LP_APM0_REGION2_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) -/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM0_REGION2_R0_PMS_X (BIT(0)) -#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S) -#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U -#define LP_APM0_REGION2_R0_PMS_X_S 0 -/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM0_REGION2_R0_PMS_W (BIT(1)) -#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S) -#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U -#define LP_APM0_REGION2_R0_PMS_W_S 1 -/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM0_REGION2_R0_PMS_R (BIT(2)) -#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S) -#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U -#define LP_APM0_REGION2_R0_PMS_R_S 2 -/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM0_REGION2_R1_PMS_X (BIT(4)) -#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S) -#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U -#define LP_APM0_REGION2_R1_PMS_X_S 4 -/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM0_REGION2_R1_PMS_W (BIT(5)) -#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S) -#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U -#define LP_APM0_REGION2_R1_PMS_W_S 5 -/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM0_REGION2_R1_PMS_R (BIT(6)) -#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S) -#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U -#define LP_APM0_REGION2_R1_PMS_R_S 6 -/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM0_REGION2_R2_PMS_X (BIT(8)) -#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S) -#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U -#define LP_APM0_REGION2_R2_PMS_X_S 8 -/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM0_REGION2_R2_PMS_W (BIT(9)) -#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S) -#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U -#define LP_APM0_REGION2_R2_PMS_W_S 9 -/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM0_REGION2_R2_PMS_R (BIT(10)) -#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S) -#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U -#define LP_APM0_REGION2_R2_PMS_R_S 10 - -/** LP_APM0_REGION3_ADDR_START_REG register - * Region address register - */ -#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) -/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region3 - */ -#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU -#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) -#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU -#define LP_APM0_REGION3_ADDR_START_S 0 - -/** LP_APM0_REGION3_ADDR_END_REG register - * Region address register - */ -#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) -/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region3 - */ -#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU -#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) -#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU -#define LP_APM0_REGION3_ADDR_END_S 0 - -/** LP_APM0_REGION3_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) -/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM0_REGION3_R0_PMS_X (BIT(0)) -#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S) -#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U -#define LP_APM0_REGION3_R0_PMS_X_S 0 -/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM0_REGION3_R0_PMS_W (BIT(1)) -#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S) -#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U -#define LP_APM0_REGION3_R0_PMS_W_S 1 -/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM0_REGION3_R0_PMS_R (BIT(2)) -#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S) -#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U -#define LP_APM0_REGION3_R0_PMS_R_S 2 -/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM0_REGION3_R1_PMS_X (BIT(4)) -#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S) -#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U -#define LP_APM0_REGION3_R1_PMS_X_S 4 -/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM0_REGION3_R1_PMS_W (BIT(5)) -#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S) -#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U -#define LP_APM0_REGION3_R1_PMS_W_S 5 -/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM0_REGION3_R1_PMS_R (BIT(6)) -#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S) -#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U -#define LP_APM0_REGION3_R1_PMS_R_S 6 -/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM0_REGION3_R2_PMS_X (BIT(8)) -#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S) -#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U -#define LP_APM0_REGION3_R2_PMS_X_S 8 -/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM0_REGION3_R2_PMS_W (BIT(9)) -#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S) -#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U -#define LP_APM0_REGION3_R2_PMS_W_S 9 -/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM0_REGION3_R2_PMS_R (BIT(10)) -#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S) -#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U -#define LP_APM0_REGION3_R2_PMS_R_S 10 - -/** LP_APM0_FUNC_CTRL_REG register - * PMS function control register - */ -#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) -/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable - */ -#define LP_APM0_M0_PMS_FUNC_EN (BIT(0)) -#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S) -#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U -#define LP_APM0_M0_PMS_FUNC_EN_S 0 - -/** LP_APM0_M0_STATUS_REG register - * M0 status register - */ -#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) -/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Exception status - */ -#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U -#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) -#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U -#define LP_APM0_M0_EXCEPTION_STATUS_S 0 - -/** LP_APM0_M0_STATUS_CLR_REG register - * M0 status clear register - */ -#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) -/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Clear exception status - */ -#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0)) -#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S) -#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U -#define LP_APM0_M0_REGION_STATUS_CLR_S 0 - -/** LP_APM0_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register - */ -#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) -/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; - * Exception region - */ -#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU -#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) -#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU -#define LP_APM0_M0_EXCEPTION_REGION_S 0 -/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ -#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U -#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) -#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U -#define LP_APM0_M0_EXCEPTION_MODE_S 16 -/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ -#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU -#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) -#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU -#define LP_APM0_M0_EXCEPTION_ID_S 18 - -/** LP_APM0_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register - */ -#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) -/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ -#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU -#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) -#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU -#define LP_APM0_M0_EXCEPTION_ADDR_S 0 - -/** LP_APM0_INT_EN_REG register - * APM interrupt enable register - */ -#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) -/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * APM M0 interrupt enable - */ -#define LP_APM0_M0_APM_INT_EN (BIT(0)) -#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) -#define LP_APM0_M0_APM_INT_EN_V 0x00000001U -#define LP_APM0_M0_APM_INT_EN_S 0 - -/** LP_APM0_CLOCK_GATE_REG register - * clock gating register - */ -#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) -/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ -#define LP_APM0_CLK_EN (BIT(0)) -#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) -#define LP_APM0_CLK_EN_V 0x00000001U -#define LP_APM0_CLK_EN_S 0 - -/** LP_APM0_DATE_REG register - * Version register - */ -#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) -/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640; - * reg_date - */ -#define LP_APM0_DATE 0x0FFFFFFFU -#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) -#define LP_APM0_DATE_V 0x0FFFFFFFU -#define LP_APM0_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_apm0_struct.h b/components/soc/esp32p4/include/soc/lp_apm0_struct.h deleted file mode 100644 index 79939b7b37..0000000000 --- a/components/soc/esp32p4/include/soc/lp_apm0_struct.h +++ /dev/null @@ -1,499 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Region filter enable register */ -/** Type of region_filter_en register - * Region filter enable register - */ -typedef union { - struct { - /** region_filter_en : R/W; bitpos: [3:0]; default: 1; - * Region filter enable - */ - uint32_t region_filter_en:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} lp_apm0_region_filter_en_reg_t; - - -/** Group: Region address register */ -/** Type of region0_addr_start register - * Region address register - */ -typedef union { - struct { - /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region0 - */ - uint32_t region0_addr_start:32; - }; - uint32_t val; -} lp_apm0_region0_addr_start_reg_t; - -/** Type of region0_addr_end register - * Region address register - */ -typedef union { - struct { - /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region0 - */ - uint32_t region0_addr_end:32; - }; - uint32_t val; -} lp_apm0_region0_addr_end_reg_t; - -/** Type of region1_addr_start register - * Region address register - */ -typedef union { - struct { - /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region1 - */ - uint32_t region1_addr_start:32; - }; - uint32_t val; -} lp_apm0_region1_addr_start_reg_t; - -/** Type of region1_addr_end register - * Region address register - */ -typedef union { - struct { - /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region1 - */ - uint32_t region1_addr_end:32; - }; - uint32_t val; -} lp_apm0_region1_addr_end_reg_t; - -/** Type of region2_addr_start register - * Region address register - */ -typedef union { - struct { - /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region2 - */ - uint32_t region2_addr_start:32; - }; - uint32_t val; -} lp_apm0_region2_addr_start_reg_t; - -/** Type of region2_addr_end register - * Region address register - */ -typedef union { - struct { - /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region2 - */ - uint32_t region2_addr_end:32; - }; - uint32_t val; -} lp_apm0_region2_addr_end_reg_t; - -/** Type of region3_addr_start register - * Region address register - */ -typedef union { - struct { - /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region3 - */ - uint32_t region3_addr_start:32; - }; - uint32_t val; -} lp_apm0_region3_addr_start_reg_t; - -/** Type of region3_addr_end register - * Region address register - */ -typedef union { - struct { - /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region3 - */ - uint32_t region3_addr_end:32; - }; - uint32_t val; -} lp_apm0_region3_addr_end_reg_t; - - -/** Group: Region access authority attribute register */ -/** Type of region0_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region0_r0_pms_x:1; - /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region0_r0_pms_w:1; - /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region0_r0_pms_r:1; - uint32_t reserved_3:1; - /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region0_r1_pms_x:1; - /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region0_r1_pms_w:1; - /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region0_r1_pms_r:1; - uint32_t reserved_7:1; - /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region0_r2_pms_x:1; - /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region0_r2_pms_w:1; - /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region0_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm0_region0_pms_attr_reg_t; - -/** Type of region1_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region1_r0_pms_x:1; - /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region1_r0_pms_w:1; - /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region1_r0_pms_r:1; - uint32_t reserved_3:1; - /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region1_r1_pms_x:1; - /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region1_r1_pms_w:1; - /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region1_r1_pms_r:1; - uint32_t reserved_7:1; - /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region1_r2_pms_x:1; - /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region1_r2_pms_w:1; - /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region1_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm0_region1_pms_attr_reg_t; - -/** Type of region2_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region2_r0_pms_x:1; - /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region2_r0_pms_w:1; - /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region2_r0_pms_r:1; - uint32_t reserved_3:1; - /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region2_r1_pms_x:1; - /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region2_r1_pms_w:1; - /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region2_r1_pms_r:1; - uint32_t reserved_7:1; - /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region2_r2_pms_x:1; - /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region2_r2_pms_w:1; - /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region2_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm0_region2_pms_attr_reg_t; - -/** Type of region3_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region3_r0_pms_x:1; - /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region3_r0_pms_w:1; - /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region3_r0_pms_r:1; - uint32_t reserved_3:1; - /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region3_r1_pms_x:1; - /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region3_r1_pms_w:1; - /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region3_r1_pms_r:1; - uint32_t reserved_7:1; - /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region3_r2_pms_x:1; - /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region3_r2_pms_w:1; - /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region3_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm0_region3_pms_attr_reg_t; - - -/** Group: PMS function control register */ -/** Type of func_ctrl register - * PMS function control register - */ -typedef union { - struct { - /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable - */ - uint32_t m0_pms_func_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_apm0_func_ctrl_reg_t; - - -/** Group: M0 status register */ -/** Type of m0_status register - * M0 status register - */ -typedef union { - struct { - /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Exception status - */ - uint32_t m0_exception_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_apm0_m0_status_reg_t; - - -/** Group: M0 status clear register */ -/** Type of m0_status_clr register - * M0 status clear register - */ -typedef union { - struct { - /** m0_region_status_clr : WT; bitpos: [0]; default: 0; - * Clear exception status - */ - uint32_t m0_region_status_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_apm0_m0_status_clr_reg_t; - - -/** Group: M0 exception_info0 register */ -/** Type of m0_exception_info0 register - * M0 exception_info0 register - */ -typedef union { - struct { - /** m0_exception_region : RO; bitpos: [3:0]; default: 0; - * Exception region - */ - uint32_t m0_exception_region:4; - uint32_t reserved_4:12; - /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ - uint32_t m0_exception_mode:2; - /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ - uint32_t m0_exception_id:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} lp_apm0_m0_exception_info0_reg_t; - - -/** Group: M0 exception_info1 register */ -/** Type of m0_exception_info1 register - * M0 exception_info1 register - */ -typedef union { - struct { - /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ - uint32_t m0_exception_addr:32; - }; - uint32_t val; -} lp_apm0_m0_exception_info1_reg_t; - - -/** Group: APM interrupt enable register */ -/** Type of int_en register - * APM interrupt enable register - */ -typedef union { - struct { - /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * APM M0 interrupt enable - */ - uint32_t m0_apm_int_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_apm0_int_en_reg_t; - - -/** Group: clock gating register */ -/** Type of clock_gate register - * clock gating register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_apm0_clock_gate_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35672640; - * reg_date - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} lp_apm0_date_reg_t; - - -typedef struct lp_apm0_dev_t { - volatile lp_apm0_region_filter_en_reg_t region_filter_en; - volatile lp_apm0_region0_addr_start_reg_t region0_addr_start; - volatile lp_apm0_region0_addr_end_reg_t region0_addr_end; - volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr; - volatile lp_apm0_region1_addr_start_reg_t region1_addr_start; - volatile lp_apm0_region1_addr_end_reg_t region1_addr_end; - volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr; - volatile lp_apm0_region2_addr_start_reg_t region2_addr_start; - volatile lp_apm0_region2_addr_end_reg_t region2_addr_end; - volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr; - volatile lp_apm0_region3_addr_start_reg_t region3_addr_start; - volatile lp_apm0_region3_addr_end_reg_t region3_addr_end; - volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr; - uint32_t reserved_034[36]; - volatile lp_apm0_func_ctrl_reg_t func_ctrl; - volatile lp_apm0_m0_status_reg_t m0_status; - volatile lp_apm0_m0_status_clr_reg_t m0_status_clr; - volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0; - volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1; - volatile lp_apm0_int_en_reg_t int_en; - volatile lp_apm0_clock_gate_reg_t clock_gate; - uint32_t reserved_0e0[455]; - volatile lp_apm0_date_reg_t date; -} lp_apm0_dev_t; - -extern lp_apm0_dev_t LP_APM0; - -#ifndef __cplusplus -_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_apm_reg.h b/components/soc/esp32p4/include/soc/lp_apm_reg.h deleted file mode 100644 index 30b6038345..0000000000 --- a/components/soc/esp32p4/include/soc/lp_apm_reg.h +++ /dev/null @@ -1,582 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_APM_REGION_FILTER_EN_REG register - * Region filter enable register - */ -#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) -/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; - * Region filter enable - */ -#define LP_APM_REGION_FILTER_EN 0x0000000FU -#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) -#define LP_APM_REGION_FILTER_EN_V 0x0000000FU -#define LP_APM_REGION_FILTER_EN_S 0 - -/** LP_APM_REGION0_ADDR_START_REG register - * Region address register - */ -#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) -/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region0 - */ -#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU -#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) -#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU -#define LP_APM_REGION0_ADDR_START_S 0 - -/** LP_APM_REGION0_ADDR_END_REG register - * Region address register - */ -#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) -/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region0 - */ -#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU -#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) -#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU -#define LP_APM_REGION0_ADDR_END_S 0 - -/** LP_APM_REGION0_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) -/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM_REGION0_R0_PMS_X (BIT(0)) -#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) -#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U -#define LP_APM_REGION0_R0_PMS_X_S 0 -/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM_REGION0_R0_PMS_W (BIT(1)) -#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) -#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U -#define LP_APM_REGION0_R0_PMS_W_S 1 -/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM_REGION0_R0_PMS_R (BIT(2)) -#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) -#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U -#define LP_APM_REGION0_R0_PMS_R_S 2 -/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM_REGION0_R1_PMS_X (BIT(4)) -#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) -#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U -#define LP_APM_REGION0_R1_PMS_X_S 4 -/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM_REGION0_R1_PMS_W (BIT(5)) -#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) -#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U -#define LP_APM_REGION0_R1_PMS_W_S 5 -/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM_REGION0_R1_PMS_R (BIT(6)) -#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) -#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U -#define LP_APM_REGION0_R1_PMS_R_S 6 -/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM_REGION0_R2_PMS_X (BIT(8)) -#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) -#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U -#define LP_APM_REGION0_R2_PMS_X_S 8 -/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM_REGION0_R2_PMS_W (BIT(9)) -#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) -#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U -#define LP_APM_REGION0_R2_PMS_W_S 9 -/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM_REGION0_R2_PMS_R (BIT(10)) -#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) -#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U -#define LP_APM_REGION0_R2_PMS_R_S 10 - -/** LP_APM_REGION1_ADDR_START_REG register - * Region address register - */ -#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) -/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region1 - */ -#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU -#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) -#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU -#define LP_APM_REGION1_ADDR_START_S 0 - -/** LP_APM_REGION1_ADDR_END_REG register - * Region address register - */ -#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) -/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region1 - */ -#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU -#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) -#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU -#define LP_APM_REGION1_ADDR_END_S 0 - -/** LP_APM_REGION1_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) -/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM_REGION1_R0_PMS_X (BIT(0)) -#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) -#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U -#define LP_APM_REGION1_R0_PMS_X_S 0 -/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM_REGION1_R0_PMS_W (BIT(1)) -#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) -#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U -#define LP_APM_REGION1_R0_PMS_W_S 1 -/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM_REGION1_R0_PMS_R (BIT(2)) -#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) -#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U -#define LP_APM_REGION1_R0_PMS_R_S 2 -/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM_REGION1_R1_PMS_X (BIT(4)) -#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) -#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U -#define LP_APM_REGION1_R1_PMS_X_S 4 -/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM_REGION1_R1_PMS_W (BIT(5)) -#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) -#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U -#define LP_APM_REGION1_R1_PMS_W_S 5 -/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM_REGION1_R1_PMS_R (BIT(6)) -#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) -#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U -#define LP_APM_REGION1_R1_PMS_R_S 6 -/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM_REGION1_R2_PMS_X (BIT(8)) -#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) -#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U -#define LP_APM_REGION1_R2_PMS_X_S 8 -/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM_REGION1_R2_PMS_W (BIT(9)) -#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) -#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U -#define LP_APM_REGION1_R2_PMS_W_S 9 -/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM_REGION1_R2_PMS_R (BIT(10)) -#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) -#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U -#define LP_APM_REGION1_R2_PMS_R_S 10 - -/** LP_APM_REGION2_ADDR_START_REG register - * Region address register - */ -#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) -/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region2 - */ -#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU -#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) -#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU -#define LP_APM_REGION2_ADDR_START_S 0 - -/** LP_APM_REGION2_ADDR_END_REG register - * Region address register - */ -#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) -/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region2 - */ -#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU -#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) -#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU -#define LP_APM_REGION2_ADDR_END_S 0 - -/** LP_APM_REGION2_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) -/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM_REGION2_R0_PMS_X (BIT(0)) -#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S) -#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U -#define LP_APM_REGION2_R0_PMS_X_S 0 -/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM_REGION2_R0_PMS_W (BIT(1)) -#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S) -#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U -#define LP_APM_REGION2_R0_PMS_W_S 1 -/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM_REGION2_R0_PMS_R (BIT(2)) -#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S) -#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U -#define LP_APM_REGION2_R0_PMS_R_S 2 -/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM_REGION2_R1_PMS_X (BIT(4)) -#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S) -#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U -#define LP_APM_REGION2_R1_PMS_X_S 4 -/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM_REGION2_R1_PMS_W (BIT(5)) -#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S) -#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U -#define LP_APM_REGION2_R1_PMS_W_S 5 -/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM_REGION2_R1_PMS_R (BIT(6)) -#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S) -#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U -#define LP_APM_REGION2_R1_PMS_R_S 6 -/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM_REGION2_R2_PMS_X (BIT(8)) -#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S) -#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U -#define LP_APM_REGION2_R2_PMS_X_S 8 -/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM_REGION2_R2_PMS_W (BIT(9)) -#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S) -#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U -#define LP_APM_REGION2_R2_PMS_W_S 9 -/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM_REGION2_R2_PMS_R (BIT(10)) -#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S) -#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U -#define LP_APM_REGION2_R2_PMS_R_S 10 - -/** LP_APM_REGION3_ADDR_START_REG register - * Region address register - */ -#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) -/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Start address of region3 - */ -#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU -#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) -#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU -#define LP_APM_REGION3_ADDR_START_S 0 - -/** LP_APM_REGION3_ADDR_END_REG register - * Region address register - */ -#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) -/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region3 - */ -#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU -#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) -#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU -#define LP_APM_REGION3_ADDR_END_S 0 - -/** LP_APM_REGION3_PMS_ATTR_REG register - * Region access authority attribute register - */ -#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) -/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ -#define LP_APM_REGION3_R0_PMS_X (BIT(0)) -#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S) -#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U -#define LP_APM_REGION3_R0_PMS_X_S 0 -/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ -#define LP_APM_REGION3_R0_PMS_W (BIT(1)) -#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S) -#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U -#define LP_APM_REGION3_R0_PMS_W_S 1 -/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ -#define LP_APM_REGION3_R0_PMS_R (BIT(2)) -#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S) -#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U -#define LP_APM_REGION3_R0_PMS_R_S 2 -/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ -#define LP_APM_REGION3_R1_PMS_X (BIT(4)) -#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S) -#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U -#define LP_APM_REGION3_R1_PMS_X_S 4 -/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ -#define LP_APM_REGION3_R1_PMS_W (BIT(5)) -#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S) -#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U -#define LP_APM_REGION3_R1_PMS_W_S 5 -/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ -#define LP_APM_REGION3_R1_PMS_R (BIT(6)) -#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S) -#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U -#define LP_APM_REGION3_R1_PMS_R_S 6 -/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ -#define LP_APM_REGION3_R2_PMS_X (BIT(8)) -#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S) -#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U -#define LP_APM_REGION3_R2_PMS_X_S 8 -/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ -#define LP_APM_REGION3_R2_PMS_W (BIT(9)) -#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S) -#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U -#define LP_APM_REGION3_R2_PMS_W_S 9 -/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ -#define LP_APM_REGION3_R2_PMS_R (BIT(10)) -#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S) -#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U -#define LP_APM_REGION3_R2_PMS_R_S 10 - -/** LP_APM_FUNC_CTRL_REG register - * PMS function control register - */ -#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) -/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable - */ -#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) -#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) -#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U -#define LP_APM_M0_PMS_FUNC_EN_S 0 -/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable - */ -#define LP_APM_M1_PMS_FUNC_EN (BIT(1)) -#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S) -#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U -#define LP_APM_M1_PMS_FUNC_EN_S 1 - -/** LP_APM_M0_STATUS_REG register - * M0 status register - */ -#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) -/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Exception status - */ -#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U -#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) -#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U -#define LP_APM_M0_EXCEPTION_STATUS_S 0 - -/** LP_APM_M0_STATUS_CLR_REG register - * M0 status clear register - */ -#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) -/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Clear exception status - */ -#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) -#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) -#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U -#define LP_APM_M0_REGION_STATUS_CLR_S 0 - -/** LP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register - */ -#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) -/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; - * Exception region - */ -#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU -#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) -#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU -#define LP_APM_M0_EXCEPTION_REGION_S 0 -/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ -#define LP_APM_M0_EXCEPTION_MODE 0x00000003U -#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) -#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U -#define LP_APM_M0_EXCEPTION_MODE_S 16 -/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ -#define LP_APM_M0_EXCEPTION_ID 0x0000001FU -#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) -#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU -#define LP_APM_M0_EXCEPTION_ID_S 18 - -/** LP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register - */ -#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) -/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ -#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU -#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) -#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU -#define LP_APM_M0_EXCEPTION_ADDR_S 0 - -/** LP_APM_M1_STATUS_REG register - * M1 status register - */ -#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) -/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Exception status - */ -#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U -#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) -#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U -#define LP_APM_M1_EXCEPTION_STATUS_S 0 - -/** LP_APM_M1_STATUS_CLR_REG register - * M1 status clear register - */ -#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc) -/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Clear exception status - */ -#define LP_APM_M1_REGION_STATUS_CLR (BIT(0)) -#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S) -#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U -#define LP_APM_M1_REGION_STATUS_CLR_S 0 - -/** LP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register - */ -#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) -/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; - * Exception region - */ -#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU -#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) -#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU -#define LP_APM_M1_EXCEPTION_REGION_S 0 -/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ -#define LP_APM_M1_EXCEPTION_MODE 0x00000003U -#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S) -#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U -#define LP_APM_M1_EXCEPTION_MODE_S 16 -/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ -#define LP_APM_M1_EXCEPTION_ID 0x0000001FU -#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S) -#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU -#define LP_APM_M1_EXCEPTION_ID_S 18 - -/** LP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register - */ -#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4) -/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ -#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU -#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S) -#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU -#define LP_APM_M1_EXCEPTION_ADDR_S 0 - -/** LP_APM_INT_EN_REG register - * APM interrupt enable register - */ -#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) -/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * APM M0 interrupt enable - */ -#define LP_APM_M0_APM_INT_EN (BIT(0)) -#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) -#define LP_APM_M0_APM_INT_EN_V 0x00000001U -#define LP_APM_M0_APM_INT_EN_S 0 -/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * APM M1 interrupt enable - */ -#define LP_APM_M1_APM_INT_EN (BIT(1)) -#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) -#define LP_APM_M1_APM_INT_EN_V 0x00000001U -#define LP_APM_M1_APM_INT_EN_S 1 - -/** LP_APM_CLOCK_GATE_REG register - * clock gating register - */ -#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) -/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ -#define LP_APM_CLK_EN (BIT(0)) -#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) -#define LP_APM_CLK_EN_V 0x00000001U -#define LP_APM_CLK_EN_S 0 - -/** LP_APM_DATE_REG register - * Version register - */ -#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc) -/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640; - * reg_date - */ -#define LP_APM_DATE 0x0FFFFFFFU -#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) -#define LP_APM_DATE_V 0x0FFFFFFFU -#define LP_APM_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_apm_struct.h b/components/soc/esp32p4/include/soc/lp_apm_struct.h deleted file mode 100644 index 82587d5501..0000000000 --- a/components/soc/esp32p4/include/soc/lp_apm_struct.h +++ /dev/null @@ -1,583 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Region filter enable register */ -/** Type of region_filter_en register - * Region filter enable register - */ -typedef union { - struct { - /** region_filter_en : R/W; bitpos: [3:0]; default: 1; - * Region filter enable - */ - uint32_t region_filter_en:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} lp_apm_region_filter_en_reg_t; - - -/** Group: Region address register */ -/** Type of region0_addr_start register - * Region address register - */ -typedef union { - struct { - /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region0 - */ - uint32_t region0_addr_start:32; - }; - uint32_t val; -} lp_apm_region0_addr_start_reg_t; - -/** Type of region0_addr_end register - * Region address register - */ -typedef union { - struct { - /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region0 - */ - uint32_t region0_addr_end:32; - }; - uint32_t val; -} lp_apm_region0_addr_end_reg_t; - -/** Type of region1_addr_start register - * Region address register - */ -typedef union { - struct { - /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region1 - */ - uint32_t region1_addr_start:32; - }; - uint32_t val; -} lp_apm_region1_addr_start_reg_t; - -/** Type of region1_addr_end register - * Region address register - */ -typedef union { - struct { - /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region1 - */ - uint32_t region1_addr_end:32; - }; - uint32_t val; -} lp_apm_region1_addr_end_reg_t; - -/** Type of region2_addr_start register - * Region address register - */ -typedef union { - struct { - /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region2 - */ - uint32_t region2_addr_start:32; - }; - uint32_t val; -} lp_apm_region2_addr_start_reg_t; - -/** Type of region2_addr_end register - * Region address register - */ -typedef union { - struct { - /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region2 - */ - uint32_t region2_addr_end:32; - }; - uint32_t val; -} lp_apm_region2_addr_end_reg_t; - -/** Type of region3_addr_start register - * Region address register - */ -typedef union { - struct { - /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; - * Start address of region3 - */ - uint32_t region3_addr_start:32; - }; - uint32_t val; -} lp_apm_region3_addr_start_reg_t; - -/** Type of region3_addr_end register - * Region address register - */ -typedef union { - struct { - /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * End address of region3 - */ - uint32_t region3_addr_end:32; - }; - uint32_t val; -} lp_apm_region3_addr_end_reg_t; - - -/** Group: Region access authority attribute register */ -/** Type of region0_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region0_r0_pms_x:1; - /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region0_r0_pms_w:1; - /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region0_r0_pms_r:1; - uint32_t reserved_3:1; - /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region0_r1_pms_x:1; - /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region0_r1_pms_w:1; - /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region0_r1_pms_r:1; - uint32_t reserved_7:1; - /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region0_r2_pms_x:1; - /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region0_r2_pms_w:1; - /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region0_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm_region0_pms_attr_reg_t; - -/** Type of region1_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region1_r0_pms_x:1; - /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region1_r0_pms_w:1; - /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region1_r0_pms_r:1; - uint32_t reserved_3:1; - /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region1_r1_pms_x:1; - /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region1_r1_pms_w:1; - /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region1_r1_pms_r:1; - uint32_t reserved_7:1; - /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region1_r2_pms_x:1; - /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region1_r2_pms_w:1; - /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region1_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm_region1_pms_attr_reg_t; - -/** Type of region2_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region2_r0_pms_x:1; - /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region2_r0_pms_w:1; - /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region2_r0_pms_r:1; - uint32_t reserved_3:1; - /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region2_r1_pms_x:1; - /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region2_r1_pms_w:1; - /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region2_r1_pms_r:1; - uint32_t reserved_7:1; - /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region2_r2_pms_x:1; - /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region2_r2_pms_w:1; - /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region2_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm_region2_pms_attr_reg_t; - -/** Type of region3_pms_attr register - * Region access authority attribute register - */ -typedef union { - struct { - /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; - * Region execute authority in REE_MODE0 - */ - uint32_t region3_r0_pms_x:1; - /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; - * Region write authority in REE_MODE0 - */ - uint32_t region3_r0_pms_w:1; - /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; - * Region read authority in REE_MODE0 - */ - uint32_t region3_r0_pms_r:1; - uint32_t reserved_3:1; - /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; - * Region execute authority in REE_MODE1 - */ - uint32_t region3_r1_pms_x:1; - /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; - * Region write authority in REE_MODE1 - */ - uint32_t region3_r1_pms_w:1; - /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; - * Region read authority in REE_MODE1 - */ - uint32_t region3_r1_pms_r:1; - uint32_t reserved_7:1; - /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; - * Region execute authority in REE_MODE2 - */ - uint32_t region3_r2_pms_x:1; - /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; - * Region write authority in REE_MODE2 - */ - uint32_t region3_r2_pms_w:1; - /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; - * Region read authority in REE_MODE2 - */ - uint32_t region3_r2_pms_r:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} lp_apm_region3_pms_attr_reg_t; - - -/** Group: PMS function control register */ -/** Type of func_ctrl register - * PMS function control register - */ -typedef union { - struct { - /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable - */ - uint32_t m0_pms_func_en:1; - /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable - */ - uint32_t m1_pms_func_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_apm_func_ctrl_reg_t; - - -/** Group: M0 status register */ -/** Type of m0_status register - * M0 status register - */ -typedef union { - struct { - /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Exception status - */ - uint32_t m0_exception_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_apm_m0_status_reg_t; - - -/** Group: M0 status clear register */ -/** Type of m0_status_clr register - * M0 status clear register - */ -typedef union { - struct { - /** m0_region_status_clr : WT; bitpos: [0]; default: 0; - * Clear exception status - */ - uint32_t m0_region_status_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_apm_m0_status_clr_reg_t; - - -/** Group: M0 exception_info0 register */ -/** Type of m0_exception_info0 register - * M0 exception_info0 register - */ -typedef union { - struct { - /** m0_exception_region : RO; bitpos: [3:0]; default: 0; - * Exception region - */ - uint32_t m0_exception_region:4; - uint32_t reserved_4:12; - /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ - uint32_t m0_exception_mode:2; - /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ - uint32_t m0_exception_id:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} lp_apm_m0_exception_info0_reg_t; - - -/** Group: M0 exception_info1 register */ -/** Type of m0_exception_info1 register - * M0 exception_info1 register - */ -typedef union { - struct { - /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ - uint32_t m0_exception_addr:32; - }; - uint32_t val; -} lp_apm_m0_exception_info1_reg_t; - - -/** Group: M1 status register */ -/** Type of m1_status register - * M1 status register - */ -typedef union { - struct { - /** m1_exception_status : RO; bitpos: [1:0]; default: 0; - * Exception status - */ - uint32_t m1_exception_status:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_apm_m1_status_reg_t; - - -/** Group: M1 status clear register */ -/** Type of m1_status_clr register - * M1 status clear register - */ -typedef union { - struct { - /** m1_region_status_clr : WT; bitpos: [0]; default: 0; - * Clear exception status - */ - uint32_t m1_region_status_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_apm_m1_status_clr_reg_t; - - -/** Group: M1 exception_info0 register */ -/** Type of m1_exception_info0 register - * M1 exception_info0 register - */ -typedef union { - struct { - /** m1_exception_region : RO; bitpos: [3:0]; default: 0; - * Exception region - */ - uint32_t m1_exception_region:4; - uint32_t reserved_4:12; - /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Exception mode - */ - uint32_t m1_exception_mode:2; - /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Exception id information - */ - uint32_t m1_exception_id:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} lp_apm_m1_exception_info0_reg_t; - - -/** Group: M1 exception_info1 register */ -/** Type of m1_exception_info1 register - * M1 exception_info1 register - */ -typedef union { - struct { - /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Exception addr - */ - uint32_t m1_exception_addr:32; - }; - uint32_t val; -} lp_apm_m1_exception_info1_reg_t; - - -/** Group: APM interrupt enable register */ -/** Type of int_en register - * APM interrupt enable register - */ -typedef union { - struct { - /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * APM M0 interrupt enable - */ - uint32_t m0_apm_int_en:1; - /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * APM M1 interrupt enable - */ - uint32_t m1_apm_int_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_apm_int_en_reg_t; - - -/** Group: clock gating register */ -/** Type of clock_gate register - * clock gating register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_apm_clock_gate_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35672640; - * reg_date - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} lp_apm_date_reg_t; - - -typedef struct lp_apm_dev_t { - volatile lp_apm_region_filter_en_reg_t region_filter_en; - volatile lp_apm_region0_addr_start_reg_t region0_addr_start; - volatile lp_apm_region0_addr_end_reg_t region0_addr_end; - volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr; - volatile lp_apm_region1_addr_start_reg_t region1_addr_start; - volatile lp_apm_region1_addr_end_reg_t region1_addr_end; - volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr; - volatile lp_apm_region2_addr_start_reg_t region2_addr_start; - volatile lp_apm_region2_addr_end_reg_t region2_addr_end; - volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr; - volatile lp_apm_region3_addr_start_reg_t region3_addr_start; - volatile lp_apm_region3_addr_end_reg_t region3_addr_end; - volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr; - uint32_t reserved_034[36]; - volatile lp_apm_func_ctrl_reg_t func_ctrl; - volatile lp_apm_m0_status_reg_t m0_status; - volatile lp_apm_m0_status_clr_reg_t m0_status_clr; - volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0; - volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1; - volatile lp_apm_m1_status_reg_t m1_status; - volatile lp_apm_m1_status_clr_reg_t m1_status_clr; - volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0; - volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1; - volatile lp_apm_int_en_reg_t int_en; - volatile lp_apm_clock_gate_reg_t clock_gate; - uint32_t reserved_0f0[3]; - volatile lp_apm_date_reg_t date; -} lp_apm_dev_t; - -extern lp_apm_dev_t LP_APM; - -#ifndef __cplusplus -_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h index 6d7ef6a48c..de3f17820c 100644 --- a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h +++ b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,226 +22,495 @@ extern "C" { #define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) #define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U #define LP_CLKRST_SLOW_CLK_SEL_S 0 -/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1; +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; * need_des */ -#define LP_CLKRST_FAST_CLK_SEL (BIT(2)) +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U #define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) -#define LP_CLKRST_FAST_CLK_SEL_V 0x00000001U +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U #define LP_CLKRST_FAST_CLK_SEL_S 2 -/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0; +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0; * need_des */ -#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM 0x0000003FU #define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) -#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU -#define LP_CLKRST_LP_PERI_DIV_NUM_S 3 +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x0000003FU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 +/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_SEL_REF_PLL8M (BIT(10)) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_M (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_V 0x00000001U +#define LP_CLKRST_ANA_SEL_REF_PLL8M_S 10 /** LP_CLKRST_LP_CLK_PO_EN_REG register * need_des */ #define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) -/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; +/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0; * need_des */ -#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) -#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) -#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U -#define LP_CLKRST_AON_SLOW_OEN_S 0 -/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; +#define LP_CLKRST_CLK_CORE_EFUSE_OEN (BIT(0)) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S 0 +/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0; * need_des */ -#define LP_CLKRST_AON_FAST_OEN (BIT(1)) -#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) -#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U -#define LP_CLKRST_AON_FAST_OEN_S 1 -/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; +#define LP_CLKRST_CLK_LP_BUS_OEN (BIT(1)) +#define LP_CLKRST_CLK_LP_BUS_OEN_M (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S) +#define LP_CLKRST_CLK_LP_BUS_OEN_V 0x00000001U +#define LP_CLKRST_CLK_LP_BUS_OEN_S 1 +/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0; * need_des */ -#define LP_CLKRST_SOSC_OEN (BIT(2)) -#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) -#define LP_CLKRST_SOSC_OEN_V 0x00000001U -#define LP_CLKRST_SOSC_OEN_S 2 -/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; +#define LP_CLKRST_CLK_AON_SLOW_OEN (BIT(2)) +#define LP_CLKRST_CLK_AON_SLOW_OEN_M (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S) +#define LP_CLKRST_CLK_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_SLOW_OEN_S 2 +/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0; * need_des */ -#define LP_CLKRST_FOSC_OEN (BIT(3)) -#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) -#define LP_CLKRST_FOSC_OEN_V 0x00000001U -#define LP_CLKRST_FOSC_OEN_S 3 -/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; +#define LP_CLKRST_CLK_AON_FAST_OEN (BIT(3)) +#define LP_CLKRST_CLK_AON_FAST_OEN_M (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S) +#define LP_CLKRST_CLK_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_FAST_OEN_S 3 +/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0; * need_des */ -#define LP_CLKRST_OSC32K_OEN (BIT(4)) -#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) -#define LP_CLKRST_OSC32K_OEN_V 0x00000001U -#define LP_CLKRST_OSC32K_OEN_S 4 -/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; +#define LP_CLKRST_CLK_SLOW_OEN (BIT(4)) +#define LP_CLKRST_CLK_SLOW_OEN_M (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S) +#define LP_CLKRST_CLK_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SLOW_OEN_S 4 +/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0; * need_des */ -#define LP_CLKRST_XTAL32K_OEN (BIT(5)) -#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) -#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U -#define LP_CLKRST_XTAL32K_OEN_S 5 -/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; +#define LP_CLKRST_CLK_FAST_OEN (BIT(5)) +#define LP_CLKRST_CLK_FAST_OEN_M (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S) +#define LP_CLKRST_CLK_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FAST_OEN_S 5 +/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0; * need_des */ -#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) -#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) -#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U -#define LP_CLKRST_CORE_EFUSE_OEN_S 6 -/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; +#define LP_CLKRST_CLK_FOSC_OEN (BIT(6)) +#define LP_CLKRST_CLK_FOSC_OEN_M (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S) +#define LP_CLKRST_CLK_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FOSC_OEN_S 6 +/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0; * need_des */ -#define LP_CLKRST_SLOW_OEN (BIT(7)) -#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) -#define LP_CLKRST_SLOW_OEN_V 0x00000001U -#define LP_CLKRST_SLOW_OEN_S 7 -/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; +#define LP_CLKRST_CLK_RC32K_OEN (BIT(7)) +#define LP_CLKRST_CLK_RC32K_OEN_M (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S) +#define LP_CLKRST_CLK_RC32K_OEN_V 0x00000001U +#define LP_CLKRST_CLK_RC32K_OEN_S 7 +/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0; * need_des */ -#define LP_CLKRST_FAST_OEN (BIT(8)) -#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) -#define LP_CLKRST_FAST_OEN_V 0x00000001U -#define LP_CLKRST_FAST_OEN_S 8 -/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; - * need_des +#define LP_CLKRST_CLK_SXTAL_OEN (BIT(8)) +#define LP_CLKRST_CLK_SXTAL_OEN_M (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S) +#define LP_CLKRST_CLK_SXTAL_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SXTAL_OEN_S 8 +/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0; + * 1'b1: probe sosc clk on + * 1'b0: probe sosc clk off */ -#define LP_CLKRST_RNG_OEN (BIT(9)) -#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) -#define LP_CLKRST_RNG_OEN_V 0x00000001U -#define LP_CLKRST_RNG_OEN_S 9 -/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; - * need_des - */ -#define LP_CLKRST_LPBUS_OEN (BIT(10)) -#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) -#define LP_CLKRST_LPBUS_OEN_V 0x00000001U -#define LP_CLKRST_LPBUS_OEN_S 10 +#define LP_CLKRST_CLK_SOSC_OEN (BIT(9)) +#define LP_CLKRST_CLK_SOSC_OEN_M (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S) +#define LP_CLKRST_CLK_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SOSC_OEN_S 9 /** LP_CLKRST_LP_CLK_EN_REG register * need_des */ #define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) -/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; +/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0; * need_des */ -#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) -#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) -#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U -#define LP_CLKRST_FAST_ORI_GATE_S 31 +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON (BIT(26)) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S 26 +/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LP_CLKRST_CK_EN_LP_RAM (BIT(27)) +#define LP_CLKRST_CK_EN_LP_RAM_M (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S) +#define LP_CLKRST_CK_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_CK_EN_LP_RAM_S 27 +/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_ETM_EVENT_TICK_EN (BIT(28)) +#define LP_CLKRST_ETM_EVENT_TICK_EN_M (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S) +#define LP_CLKRST_ETM_EVENT_TICK_EN_V 0x00000001U +#define LP_CLKRST_ETM_EVENT_TICK_EN_S 28 +/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_PLL8M_CLK_FORCE_ON (BIT(29)) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S 29 +/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_XTAL_CLK_FORCE_ON (BIT(30)) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_M (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_XTAL_CLK_FORCE_ON_S 30 +/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FOSC_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_M (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_FOSC_CLK_FORCE_ON_S 31 /** LP_CLKRST_LP_RST_EN_REG register * need_des */ #define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) -/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; +/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0; * need_des */ -#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) -#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) -#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U -#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 -/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; +#define LP_CLKRST_RST_EN_LP_HUK (BIT(24)) +#define LP_CLKRST_RST_EN_LP_HUK_M (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S) +#define LP_CLKRST_RST_EN_LP_HUK_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_HUK_S 24 +/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0; * need_des */ -#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) -#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) -#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U -#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 -/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; +#define LP_CLKRST_RST_EN_LP_ANAPERI (BIT(25)) +#define LP_CLKRST_RST_EN_LP_ANAPERI_M (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S) +#define LP_CLKRST_RST_EN_LP_ANAPERI_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_ANAPERI_S 25 +/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0; * need_des */ -#define LP_CLKRST_WDT_RESET_EN (BIT(30)) -#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) -#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U -#define LP_CLKRST_WDT_RESET_EN_S 30 -/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; +#define LP_CLKRST_RST_EN_LP_WDT (BIT(26)) +#define LP_CLKRST_RST_EN_LP_WDT_M (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S) +#define LP_CLKRST_RST_EN_LP_WDT_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_WDT_S 26 +/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0; * need_des */ -#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) -#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) -#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U -#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 +#define LP_CLKRST_RST_EN_LP_TIMER (BIT(27)) +#define LP_CLKRST_RST_EN_LP_TIMER_M (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S) +#define LP_CLKRST_RST_EN_LP_TIMER_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_TIMER_S 27 +/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RTC (BIT(28)) +#define LP_CLKRST_RST_EN_LP_RTC_M (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S) +#define LP_CLKRST_RST_EN_LP_RTC_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RTC_S 28 +/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_MAILBOX (BIT(29)) +#define LP_CLKRST_RST_EN_LP_MAILBOX_M (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S) +#define LP_CLKRST_RST_EN_LP_MAILBOX_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_MAILBOX_S 29 +/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG (BIT(30)) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S 30 +/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RAM (BIT(31)) +#define LP_CLKRST_RST_EN_LP_RAM_M (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S) +#define LP_CLKRST_RST_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RAM_S 31 /** LP_CLKRST_RESET_CAUSE_REG register * need_des */ #define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) -/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; +/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0; + * 6'h1: POR reset + * 6'h9: PMU LP PERI power down reset + * 6'ha: PMU LP CPU reset + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: software reset + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_M (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_S 0 +/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0; * need_des */ -#define LP_CLKRST_RESET_CAUSE 0x0000001FU -#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) -#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU -#define LP_CLKRST_RESET_CAUSE_S 0 -/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; +#define LP_CLKRST_LPCORE_RESET_FLAG (BIT(6)) +#define LP_CLKRST_LPCORE_RESET_FLAG_M (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_S 6 +/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_M (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_S 7 +/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0; * need_des */ -#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) -#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) -#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U -#define LP_CLKRST_CORE0_RESET_FLAG_S 5 -/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; +#define LP_CLKRST_HPCORE0_RESET_FLAG (BIT(13)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_M (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_S 13 +/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_M (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_S 14 +/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0; * need_des */ -#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) -#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) -#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U -#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 -/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; +#define LP_CLKRST_HPCORE1_RESET_FLAG (BIT(20)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_M (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_S 20 +/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1; + * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore + * pmu_lp_cpu_reset reset_cause + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK (BIT(25)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S 25 +/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0; * need_des */ -#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) -#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) -#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U -#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 -/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR (BIT(26)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S 26 +/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0; * need_des */ -#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) -#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) -#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U -#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR (BIT(27)) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S 27 +/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR (BIT(28)) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S 28 +/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR (BIT(29)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S 29 +/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR (BIT(30)) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S 30 +/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S 31 -/** LP_CLKRST_CPU_RESET_REG register +/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register * need_des */ -#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) -/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; +#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(0)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 0 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1; * need_des */ -#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U -#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) -#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U -#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 -/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S 1 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0; + * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset + * hpcore0 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN (BIT(4)) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S 4 +/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0; * need_des */ -#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) -#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) -#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U -#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 -/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; +#define LP_CLKRST_HPCORE0_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_M (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S) +#define LP_CLKRST_HPCORE0_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_S 5 +/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0; * need_des */ -#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU -#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) -#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU -#define LP_CLKRST_CPU_STALL_WAIT_S 26 -/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; +#define LP_CLKRST_HPCORE0_STALL_EN (BIT(12)) +#define LP_CLKRST_HPCORE0_STALL_EN_M (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S) +#define LP_CLKRST_HPCORE0_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_STALL_EN_S 12 +/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0; * need_des */ -#define LP_CLKRST_CPU_STALL_EN (BIT(31)) -#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) -#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U -#define LP_CLKRST_CPU_STALL_EN_S 31 +#define LP_CLKRST_HPCORE0_SW_RESET (BIT(13)) +#define LP_CLKRST_HPCORE0_SW_RESET_M (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S) +#define LP_CLKRST_HPCORE0_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_SW_RESET_S 13 +/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET (BIT(14)) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S 14 +/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL (BIT(15)) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S 15 +/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0; + * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(16)) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S 16 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S 17 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0; + * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset + * hpcore1 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN (BIT(20)) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S 20 +/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_M (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S) +#define LP_CLKRST_HPCORE1_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_S 21 +/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_EN (BIT(28)) +#define LP_CLKRST_HPCORE1_STALL_EN_M (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S) +#define LP_CLKRST_HPCORE1_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_STALL_EN_S 28 +/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_SW_RESET (BIT(29)) +#define LP_CLKRST_HPCORE1_SW_RESET_M (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S) +#define LP_CLKRST_HPCORE1_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_SW_RESET_S 29 +/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET (BIT(30)) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S 30 +/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL (BIT(31)) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S 31 + +/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register + * need_des + */ +#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; + * HP core0 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE0_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S 16 +/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; + * HP core1 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE1_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S 24 /** LP_CLKRST_FOSC_CNTL_REG register * need_des */ -#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) -/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400; * need_des */ #define LP_CLKRST_FOSC_DFREQ 0x000003FFU @@ -252,42 +521,54 @@ extern "C" { /** LP_CLKRST_RC32K_CNTL_REG register * need_des */ -#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) -/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172; +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650; * need_des */ -#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ 0xFFFFFFFFU #define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) -#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU -#define LP_CLKRST_RC32K_DFREQ_S 22 +#define LP_CLKRST_RC32K_DFREQ_V 0xFFFFFFFFU +#define LP_CLKRST_RC32K_DFREQ_S 0 + +/** LP_CLKRST_SOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_SOSC_DFREQ 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_M (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S) +#define LP_CLKRST_SOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_S 22 /** LP_CLKRST_CLK_TO_HP_REG register * need_des */ -#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28) /** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; - * need_des + * reserved */ #define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) #define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) #define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U #define LP_CLKRST_ICG_HP_XTAL32K_S 28 /** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; - * need_des + * reserved */ #define LP_CLKRST_ICG_HP_SOSC (BIT(29)) #define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) #define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U #define LP_CLKRST_ICG_HP_SOSC_S 29 /** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; - * need_des + * reserved */ #define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) #define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) #define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U #define LP_CLKRST_ICG_HP_OSC32K_S 30 /** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; - * need_des + * reserved */ #define LP_CLKRST_ICG_HP_FOSC (BIT(31)) #define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) @@ -297,38 +578,19 @@ extern "C" { /** LP_CLKRST_LPMEM_FORCE_REG register * need_des */ -#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c) /** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; - * need_des + * reserved */ #define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) #define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) #define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U #define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 -/** LP_CLKRST_LPPERI_REG register - * need_des - */ -#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) -/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) -#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) -#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U -#define LP_CLKRST_LP_I2C_CLK_SEL_S 30 -/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) -#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) -#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U -#define LP_CLKRST_LP_UART_CLK_SEL_S 31 - /** LP_CLKRST_XTAL32K_REG register * need_des */ -#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30) /** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; * need_des */ @@ -358,17 +620,409 @@ extern "C" { #define LP_CLKRST_DAC_XTAL32K_V 0x00000007U #define LP_CLKRST_DAC_XTAL32K_S 29 +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34) +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S) +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38) +/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c) +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S 0 + +/** LP_CLKRST_HP_CLK_CTRL_REG register + * HP Clock Control Register. + */ +#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40) +/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0; + * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + */ +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S) +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S 0 +/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1; + * HP SoC Root Clock Enable. + */ +#define LP_CLKRST_HP_ROOT_CLK_EN (BIT(2)) +#define LP_CLKRST_HP_ROOT_CLK_EN_M (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S) +#define LP_CLKRST_HP_ROOT_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_ROOT_CLK_EN_S 2 +/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1; + * PARLIO TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN (BIT(3)) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S 3 +/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1; + * PARLIO RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN (BIT(4)) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S 4 +/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1; + * UART4 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN (BIT(5)) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S 5 +/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1; + * UART3 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN (BIT(6)) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S 6 +/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1; + * UART2 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN (BIT(7)) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S 7 +/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1; + * UART1 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN (BIT(8)) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S 8 +/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1; + * UART0 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN (BIT(9)) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S 9 +/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1; + * I2S2 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN (BIT(10)) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S 10 +/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1; + * I2S1 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN (BIT(11)) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S 11 +/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1; + * I2S0 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN (BIT(12)) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S 12 +/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1; + * EMAC RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN (BIT(13)) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S 13 +/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1; + * EMAC TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN (BIT(14)) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S 14 +/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1; + * EMAC TXRX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN (BIT(15)) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S 15 +/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1; + * XTAL 32K Clock Enable. + */ +#define LP_CLKRST_HP_XTAL_32K_CLK_EN (BIT(16)) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S 16 +/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1; + * RC 32K Clock Enable. + */ +#define LP_CLKRST_HP_RC_32K_CLK_EN (BIT(17)) +#define LP_CLKRST_HP_RC_32K_CLK_EN_M (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S) +#define LP_CLKRST_HP_RC_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_RC_32K_CLK_EN_S 17 +/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1; + * SOSC 150K Clock Enable. + */ +#define LP_CLKRST_HP_SOSC_150K_CLK_EN (BIT(18)) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S 18 +/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1; + * PLL 8M Clock Enable. + */ +#define LP_CLKRST_HP_PLL_8M_CLK_EN (BIT(19)) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_M (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PLL_8M_CLK_EN_S 19 +/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1; + * AUDIO PLL Clock Enable. + */ +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN (BIT(20)) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S 20 +/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1; + * SDIO PLL2 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN (BIT(21)) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S 21 +/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1; + * SDIO PLL1 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN (BIT(22)) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S 22 +/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1; + * SDIO PLL0 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN (BIT(23)) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S 23 +/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1; + * FOSC 20M Clock Enable. + */ +#define LP_CLKRST_HP_FOSC_20M_CLK_EN (BIT(24)) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S 24 +/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1; + * XTAL 40M Clock Enalbe. + */ +#define LP_CLKRST_HP_XTAL_40M_CLK_EN (BIT(25)) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S 25 +/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1; + * CPLL 400M Clock Enable. + */ +#define LP_CLKRST_HP_CPLL_400M_CLK_EN (BIT(26)) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S 26 +/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1; + * SPLL 480M Clock Enable. + */ +#define LP_CLKRST_HP_SPLL_480M_CLK_EN (BIT(27)) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S 27 +/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1; + * MPLL 500M Clock Enable. + */ +#define LP_CLKRST_HP_MPLL_500M_CLK_EN (BIT(28)) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S 28 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44) +/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG20_SLEEP_MODE (BIT(0)) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S 0 +/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN (BIT(1)) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S 1 +/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG11_SLEEP_MODE (BIT(2)) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S 2 +/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN (BIT(3)) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S 3 +/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * usb otg11 fs phy clock enable. + */ +#define LP_CLKRST_USB_OTG11_48M_CLK_EN (BIT(4)) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S 4 +/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * usb device fs phy clock enable. + */ +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN (BIT(5)) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S 5 +/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9; + * usb 480m to 25m divide number. + */ +#define LP_CLKRST_USB_48M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_M (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S) +#define LP_CLKRST_USB_48M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_S 6 +/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19; + * usb 500m to 25m divide number. + */ +#define LP_CLKRST_USB_25M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_M (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S) +#define LP_CLKRST_USB_25M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_S 14 +/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39; + * usb 480m to 12m divide number. + */ +#define LP_CLKRST_USB_12M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_M (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S) +#define LP_CLKRST_USB_12M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_S 22 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48) +/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0; + * usb otg20 adp reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_ADP (BIT(0)) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S 0 +/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0; + * usb otg20 phy reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_PHY (BIT(1)) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S 1 +/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0; + * usb otg20 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20 (BIT(2)) +#define LP_CLKRST_RST_EN_USB_OTG20_M (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S) +#define LP_CLKRST_RST_EN_USB_OTG20_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_S 2 +/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0; + * usb org11 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG11 (BIT(3)) +#define LP_CLKRST_RST_EN_USB_OTG11_M (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S) +#define LP_CLKRST_RST_EN_USB_OTG11_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG11_S 3 +/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0; + * usb device reset en + */ +#define LP_CLKRST_RST_EN_USB_DEVICE (BIT(4)) +#define LP_CLKRST_RST_EN_USB_DEVICE_M (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S) +#define LP_CLKRST_RST_EN_USB_DEVICE_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_DEVICE_S 4 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0; + * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S 28 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1; + * usb otg20 hs phy refclk enable. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN (BIT(30)) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S 30 +/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1; + * usb otg20 ulpi clock enable. + */ +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN (BIT(31)) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S 31 + +/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register + * need_des + */ +#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c) +/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0; + * hp sdmmc reset en + */ +#define LP_CLKRST_RST_EN_SDMMC (BIT(28)) +#define LP_CLKRST_RST_EN_SDMMC_M (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S) +#define LP_CLKRST_RST_EN_SDMMC_V 0x00000001U +#define LP_CLKRST_RST_EN_SDMMC_S 28 +/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0; + * hp sdmmc force norst + */ +#define LP_CLKRST_FORCE_NORST_SDMMC (BIT(29)) +#define LP_CLKRST_FORCE_NORST_SDMMC_M (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S) +#define LP_CLKRST_FORCE_NORST_SDMMC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_SDMMC_S 29 +/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0; + * hp emac reset en + */ +#define LP_CLKRST_RST_EN_EMAC (BIT(30)) +#define LP_CLKRST_RST_EN_EMAC_M (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S) +#define LP_CLKRST_RST_EN_EMAC_V 0x00000001U +#define LP_CLKRST_RST_EN_EMAC_S 30 +/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0; + * hp emac force norst + */ +#define LP_CLKRST_FORCE_NORST_EMAC (BIT(31)) +#define LP_CLKRST_FORCE_NORST_EMAC_M (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S) +#define LP_CLKRST_FORCE_NORST_EMAC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_EMAC_S 31 + /** LP_CLKRST_DATE_REG register * need_des */ #define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) -/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35676304; - * need_des - */ -#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU -#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) -#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU -#define LP_CLKRST_CLKRST_DATE_S 0 /** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; * need_des */ diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h index 453817997f..2ade245136 100644 --- a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h +++ b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,14 +20,18 @@ typedef union { * need_des */ uint32_t slow_clk_sel:2; - /** fast_clk_sel : R/W; bitpos: [2]; default: 1; + /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; * need_des */ - uint32_t fast_clk_sel:1; - /** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0; + uint32_t fast_clk_sel:2; + /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0; * need_des */ - uint32_t lp_peri_div_num:8; + uint32_t lp_peri_div_num:6; + /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_sel_ref_pll8m:1; uint32_t reserved_11:21; }; uint32_t val; @@ -38,51 +42,48 @@ typedef union { */ typedef union { struct { - /** aon_slow_oen : R/W; bitpos: [0]; default: 1; + /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0; * need_des */ - uint32_t aon_slow_oen:1; - /** aon_fast_oen : R/W; bitpos: [1]; default: 1; + uint32_t clk_core_efuse_oen:1; + /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0; * need_des */ - uint32_t aon_fast_oen:1; - /** sosc_oen : R/W; bitpos: [2]; default: 1; + uint32_t clk_lp_bus_oen:1; + /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0; * need_des */ - uint32_t sosc_oen:1; - /** fosc_oen : R/W; bitpos: [3]; default: 1; + uint32_t clk_aon_slow_oen:1; + /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0; * need_des */ - uint32_t fosc_oen:1; - /** osc32k_oen : R/W; bitpos: [4]; default: 1; + uint32_t clk_aon_fast_oen:1; + /** clk_slow_oen : R/W; bitpos: [4]; default: 0; * need_des */ - uint32_t osc32k_oen:1; - /** xtal32k_oen : R/W; bitpos: [5]; default: 1; + uint32_t clk_slow_oen:1; + /** clk_fast_oen : R/W; bitpos: [5]; default: 0; * need_des */ - uint32_t xtal32k_oen:1; - /** core_efuse_oen : R/W; bitpos: [6]; default: 1; + uint32_t clk_fast_oen:1; + /** clk_fosc_oen : R/W; bitpos: [6]; default: 0; * need_des */ - uint32_t core_efuse_oen:1; - /** slow_oen : R/W; bitpos: [7]; default: 1; + uint32_t clk_fosc_oen:1; + /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0; * need_des */ - uint32_t slow_oen:1; - /** fast_oen : R/W; bitpos: [8]; default: 1; + uint32_t clk_rc32k_oen:1; + /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0; * need_des */ - uint32_t fast_oen:1; - /** rng_oen : R/W; bitpos: [9]; default: 1; - * need_des + uint32_t clk_sxtal_oen:1; + /** clk_sosc_oen : R/W; bitpos: [9]; default: 0; + * 1'b1: probe sosc clk on + * 1'b0: probe sosc clk off */ - uint32_t rng_oen:1; - /** lpbus_oen : R/W; bitpos: [10]; default: 1; - * need_des - */ - uint32_t lpbus_oen:1; - uint32_t reserved_11:21; + uint32_t clk_sosc_oen:1; + uint32_t reserved_10:22; }; uint32_t val; } lp_clkrst_lp_clk_po_en_reg_t; @@ -92,11 +93,31 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:31; - /** fast_ori_gate : R/W; bitpos: [31]; default: 0; + uint32_t reserved_0:26; + /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0; * need_des */ - uint32_t fast_ori_gate:1; + uint32_t lp_rtc_xtal_force_on:1; + /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t ck_en_lp_ram:1; + /** etm_event_tick_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t etm_event_tick_en:1; + /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t pll8m_clk_force_on:1; + /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xtal_clk_force_on:1; + /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t fosc_clk_force_on:1; }; uint32_t val; } lp_clkrst_lp_clk_en_reg_t; @@ -106,23 +127,39 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:28; - /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + uint32_t reserved_0:24; + /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0; * need_des */ - uint32_t aon_efuse_core_reset_en:1; - /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + uint32_t rst_en_lp_huk:1; + /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0; * need_des */ - uint32_t lp_timer_reset_en:1; - /** wdt_reset_en : R/W; bitpos: [30]; default: 0; + uint32_t rst_en_lp_anaperi:1; + /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0; * need_des */ - uint32_t wdt_reset_en:1; - /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + uint32_t rst_en_lp_wdt:1; + /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0; * need_des */ - uint32_t ana_peri_reset_en:1; + uint32_t rst_en_lp_timer:1; + /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t rst_en_lp_rtc:1; + /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t rst_en_lp_mailbox:1; + /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t rst_en_lp_aonefusereg:1; + /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t rst_en_lp_ram:1; }; uint32_t val; } lp_clkrst_lp_rst_en_reg_t; @@ -132,56 +169,199 @@ typedef union { */ typedef union { struct { - /** reset_cause : RO; bitpos: [4:0]; default: 0; + /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0; + * 6'h1: POR reset + * 6'h9: PMU LP PERI power down reset + * 6'ha: PMU LP CPU reset + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: software reset + */ + uint32_t lpcore_reset_cause:6; + /** lpcore_reset_flag : RO; bitpos: [6]; default: 0; * need_des */ - uint32_t reset_cause:5; - /** core0_reset_flag : RO; bitpos: [5]; default: 1; + uint32_t lpcore_reset_flag:1; + /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ + uint32_t hpcore0_reset_cause:6; + /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0; * need_des */ - uint32_t core0_reset_flag:1; - uint32_t reserved_6:23; - /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + uint32_t hpcore0_reset_flag:1; + /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ + uint32_t hpcore1_reset_cause:6; + /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0; * need_des */ - uint32_t core0_reset_cause_clr:1; - /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; + uint32_t hpcore1_reset_flag:1; + uint32_t reserved_21:4; + /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1; + * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore + * pmu_lp_cpu_reset reset_cause + */ + uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1; + /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0; * need_des */ - uint32_t core0_reset_flag_set:1; - /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + uint32_t lpcore_reset_cause_clr:1; + /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0; * need_des */ - uint32_t core0_reset_flag_clr:1; + uint32_t lpcore_reset_flag_clr:1; + /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hpcore0_reset_cause_clr:1; + /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hpcore0_reset_flag_clr:1; + /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hpcore1_reset_cause_clr:1; + /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hpcore1_reset_flag_clr:1; }; uint32_t val; } lp_clkrst_reset_cause_reg_t; -/** Type of cpu_reset register +/** Type of hpcpu_reset_ctrl0 register * need_des */ typedef union { struct { - uint32_t reserved_0:22; - /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ + uint32_t hpcore0_lockup_reset_en:1; + /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1; * need_des */ - uint32_t rtc_wdt_cpu_reset_length:3; - /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + uint32_t lp_wdt_hpcore0_reset_length:3; + /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0; + * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset + * hpcore0 feature + */ + uint32_t lp_wdt_hpcore0_reset_en:1; + /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0; * need_des */ - uint32_t rtc_wdt_cpu_reset_en:1; - /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + uint32_t hpcore0_stall_wait:7; + /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0; * need_des */ - uint32_t cpu_stall_wait:5; - /** cpu_stall_en : R/W; bitpos: [31]; default: 0; + uint32_t hpcore0_stall_en:1; + /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0; * need_des */ - uint32_t cpu_stall_en:1; + uint32_t hpcore0_sw_reset:1; + /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t hpcore0_ocd_halt_on_reset:1; + /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ + uint32_t hpcore0_stat_vector_sel:1; + /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0; + * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup + * reset feature + */ + uint32_t hpcore1_lockup_reset_en:1; + /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1; + * need_des + */ + uint32_t lp_wdt_hpcore1_reset_length:3; + /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0; + * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset + * hpcore1 feature + */ + uint32_t lp_wdt_hpcore1_reset_en:1; + /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0; + * need_des + */ + uint32_t hpcore1_stall_wait:7; + /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hpcore1_stall_en:1; + /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hpcore1_sw_reset:1; + /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hpcore1_ocd_halt_on_reset:1; + /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ + uint32_t hpcore1_stat_vector_sel:1; }; uint32_t val; -} lp_clkrst_cpu_reset_reg_t; +} lp_clkrst_hpcpu_reset_ctrl0_reg_t; + +/** Type of hpcpu_reset_ctrl1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0; + * HP core0 software stall when set to 8'h86 + */ + uint32_t hpcore0_sw_stall_code:8; + /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0; + * HP core1 software stall when set to 8'h86 + */ + uint32_t hpcore1_sw_stall_code:8; + }; + uint32_t val; +} lp_clkrst_hpcpu_reset_ctrl1_reg_t; /** Type of fosc_cntl register * need_des @@ -189,7 +369,7 @@ typedef union { typedef union { struct { uint32_t reserved_0:22; - /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400; * need_des */ uint32_t fosc_dfreq:10; @@ -202,15 +382,28 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:22; - /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172; + /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650; * need_des */ - uint32_t rc32k_dfreq:10; + uint32_t rc32k_dfreq:32; }; uint32_t val; } lp_clkrst_rc32k_cntl_reg_t; +/** Type of sosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t sosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_sosc_cntl_reg_t; + /** Type of clk_to_hp register * need_des */ @@ -218,19 +411,19 @@ typedef union { struct { uint32_t reserved_0:28; /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; - * need_des + * reserved */ uint32_t icg_hp_xtal32k:1; /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; - * need_des + * reserved */ uint32_t icg_hp_sosc:1; /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; - * need_des + * reserved */ uint32_t icg_hp_osc32k:1; /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; - * need_des + * reserved */ uint32_t icg_hp_fosc:1; }; @@ -244,31 +437,13 @@ typedef union { struct { uint32_t reserved_0:31; /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; - * need_des + * reserved */ uint32_t lpmem_clk_force_on:1; }; uint32_t val; } lp_clkrst_lpmem_force_reg_t; -/** Type of lpperi register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_i2c_clk_sel:1; - /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_uart_clk_sel:1; - }; - uint32_t val; -} lp_clkrst_lpperi_reg_t; - /** Type of xtal32k register * need_des */ @@ -295,15 +470,287 @@ typedef union { uint32_t val; } lp_clkrst_xtal32k_reg_t; +/** Type of mux_hpsys_reset_bypass register + * need_des + */ +typedef union { + struct { + /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t mux_hpsys_reset_bypass:32; + }; + uint32_t val; +} lp_clkrst_mux_hpsys_reset_bypass_reg_t; + +/** Type of hpsys_0_reset_bypass register + * need_des + */ +typedef union { + struct { + /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t hpsys_0_reset_bypass:32; + }; + uint32_t val; +} lp_clkrst_hpsys_0_reset_bypass_reg_t; + +/** Type of hpsys_apm_reset_bypass register + * need_des + */ +typedef union { + struct { + /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t hpsys_apm_reset_bypass:32; + }; + uint32_t val; +} lp_clkrst_hpsys_apm_reset_bypass_reg_t; + +/** Type of hp_clk_ctrl register + * HP Clock Control Register. + */ +typedef union { + struct { + /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0; + * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + */ + uint32_t hp_root_clk_src_sel:2; + /** hp_root_clk_en : R/W; bitpos: [2]; default: 1; + * HP SoC Root Clock Enable. + */ + uint32_t hp_root_clk_en:1; + /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1; + * PARLIO TX Clock From Pad Enable. + */ + uint32_t hp_pad_parlio_tx_clk_en:1; + /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1; + * PARLIO RX Clock From Pad Enable. + */ + uint32_t hp_pad_parlio_rx_clk_en:1; + /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1; + * UART4 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart4_slp_clk_en:1; + /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1; + * UART3 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart3_slp_clk_en:1; + /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1; + * UART2 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart2_slp_clk_en:1; + /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1; + * UART1 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart1_slp_clk_en:1; + /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1; + * UART0 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart0_slp_clk_en:1; + /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1; + * I2S2 MCLK Clock From Pad Enable. + */ + uint32_t hp_pad_i2s2_mclk_en:1; + /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1; + * I2S1 MCLK Clock From Pad Enable. + */ + uint32_t hp_pad_i2s1_mclk_en:1; + /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1; + * I2S0 MCLK Clock From Pad Enable. + */ + uint32_t hp_pad_i2s0_mclk_en:1; + /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1; + * EMAC RX Clock From Pad Enable. + */ + uint32_t hp_pad_emac_tx_clk_en:1; + /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1; + * EMAC TX Clock From Pad Enable. + */ + uint32_t hp_pad_emac_rx_clk_en:1; + /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1; + * EMAC TXRX Clock From Pad Enable. + */ + uint32_t hp_pad_emac_txrx_clk_en:1; + /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1; + * XTAL 32K Clock Enable. + */ + uint32_t hp_xtal_32k_clk_en:1; + /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1; + * RC 32K Clock Enable. + */ + uint32_t hp_rc_32k_clk_en:1; + /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1; + * SOSC 150K Clock Enable. + */ + uint32_t hp_sosc_150k_clk_en:1; + /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1; + * PLL 8M Clock Enable. + */ + uint32_t hp_pll_8m_clk_en:1; + /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1; + * AUDIO PLL Clock Enable. + */ + uint32_t hp_audio_pll_clk_en:1; + /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1; + * SDIO PLL2 Clock Enable. + */ + uint32_t hp_sdio_pll2_clk_en:1; + /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1; + * SDIO PLL1 Clock Enable. + */ + uint32_t hp_sdio_pll1_clk_en:1; + /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1; + * SDIO PLL0 Clock Enable. + */ + uint32_t hp_sdio_pll0_clk_en:1; + /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1; + * FOSC 20M Clock Enable. + */ + uint32_t hp_fosc_20m_clk_en:1; + /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1; + * XTAL 40M Clock Enalbe. + */ + uint32_t hp_xtal_40m_clk_en:1; + /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1; + * CPLL 400M Clock Enable. + */ + uint32_t hp_cpll_400m_clk_en:1; + /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1; + * SPLL 480M Clock Enable. + */ + uint32_t hp_spll_480m_clk_en:1; + /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1; + * MPLL 500M Clock Enable. + */ + uint32_t hp_mpll_500m_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} lp_clkrst_hp_clk_ctrl_reg_t; + +/** Type of hp_usb_clkrst_ctrl0 register + * HP USB Clock Reset Control Register. + */ +typedef union { + struct { + /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0; + * unused. + */ + uint32_t usb_otg20_sleep_mode:1; + /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1; + * unused. + */ + uint32_t usb_otg20_bk_sys_clk_en:1; + /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0; + * unused. + */ + uint32_t usb_otg11_sleep_mode:1; + /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1; + * unused. + */ + uint32_t usb_otg11_bk_sys_clk_en:1; + /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1; + * usb otg11 fs phy clock enable. + */ + uint32_t usb_otg11_48m_clk_en:1; + /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1; + * usb device fs phy clock enable. + */ + uint32_t usb_device_48m_clk_en:1; + /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9; + * usb 480m to 25m divide number. + */ + uint32_t usb_48m_div_num:8; + /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19; + * usb 500m to 25m divide number. + */ + uint32_t usb_25m_div_num:8; + /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39; + * usb 480m to 12m divide number. + */ + uint32_t usb_12m_div_num:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_clkrst_hp_usb_clkrst_ctrl0_reg_t; + +/** Type of hp_usb_clkrst_ctrl1 register + * HP USB Clock Reset Control Register. + */ +typedef union { + struct { + /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0; + * usb otg20 adp reset en + */ + uint32_t rst_en_usb_otg20_adp:1; + /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0; + * usb otg20 phy reset en + */ + uint32_t rst_en_usb_otg20_phy:1; + /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0; + * usb otg20 reset en + */ + uint32_t rst_en_usb_otg20:1; + /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0; + * usb org11 reset en + */ + uint32_t rst_en_usb_otg11:1; + /** rst_en_usb_device : R/W; bitpos: [4]; default: 0; + * usb device reset en + */ + uint32_t rst_en_usb_device:1; + uint32_t reserved_5:23; + /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0; + * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + */ + uint32_t usb_otg20_phyref_clk_src_sel:2; + /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1; + * usb otg20 hs phy refclk enable. + */ + uint32_t usb_otg20_phyref_clk_en:1; + /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1; + * usb otg20 ulpi clock enable. + */ + uint32_t usb_otg20_ulpi_clk_en:1; + }; + uint32_t val; +} lp_clkrst_hp_usb_clkrst_ctrl1_reg_t; + +/** Type of hp_sdmmc_emac_rst_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0; + * hp sdmmc reset en + */ + uint32_t rst_en_sdmmc:1; + /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0; + * hp sdmmc force norst + */ + uint32_t force_norst_sdmmc:1; + /** rst_en_emac : R/W; bitpos: [30]; default: 0; + * hp emac reset en + */ + uint32_t rst_en_emac:1; + /** force_norst_emac : R/W; bitpos: [31]; default: 0; + * hp emac force norst + */ + uint32_t force_norst_emac:1; + }; + uint32_t val; +} lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t; + /** Type of date register * need_des */ typedef union { struct { - /** clkrst_date : R/W; bitpos: [30:0]; default: 35676304; - * need_des - */ - uint32_t clkrst_date:31; + uint32_t reserved_0:31; /** clk_en : R/W; bitpos: [31]; default: 0; * need_des */ @@ -313,24 +760,31 @@ typedef union { } lp_clkrst_date_reg_t; -typedef struct lp_clkrst_dev_t { +typedef struct { volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; volatile lp_clkrst_reset_cause_reg_t reset_cause; - volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0; + volatile lp_clkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1; volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_sosc_cntl_reg_t sosc_cntl; volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; volatile lp_clkrst_lpmem_force_reg_t lpmem_force; - volatile lp_clkrst_lpperi_reg_t lpperi; volatile lp_clkrst_xtal32k_reg_t xtal32k; - uint32_t reserved_030[243]; + volatile lp_clkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass; + volatile lp_clkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass; + volatile lp_clkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass; + volatile lp_clkrst_hp_clk_ctrl_reg_t hp_clk_ctrl; + volatile lp_clkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0; + volatile lp_clkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1; + volatile lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl; + uint32_t reserved_050[235]; volatile lp_clkrst_date_reg_t date; } lp_clkrst_dev_t; -extern lp_clkrst_dev_t LP_CLKRST; #ifndef __cplusplus _Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/lp_gpio_struct.h b/components/soc/esp32p4/include/soc/lp_gpio_struct.h index 78bcfcaff9..507cf47a8f 100644 --- a/components/soc/esp32p4/include/soc/lp_gpio_struct.h +++ b/components/soc/esp32p4/include/soc/lp_gpio_struct.h @@ -1449,7 +1449,7 @@ typedef union { } lp_gpio_func15_out_sel_cfg_reg_t; -typedef struct { +typedef struct lp_gpio_dev_t { volatile lp_gpio_clk_en_reg_t clk_en; volatile lp_gpio_ver_date_reg_t ver_date; volatile lp_gpio_out_reg_t out; @@ -1512,6 +1512,8 @@ typedef struct { volatile lp_gpio_func15_out_sel_cfg_reg_t func15_out_sel_cfg; } lp_gpio_dev_t; +extern lp_gpio_dev_t LP_GPIO; + #ifndef __cplusplus _Static_assert(sizeof(lp_gpio_dev_t) == 0x134, "Invalid size of lp_gpio_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/lp_io_reg.h b/components/soc/esp32p4/include/soc/lp_io_reg.h deleted file mode 100644 index 64b5f6c425..0000000000 --- a/components/soc/esp32p4/include/soc/lp_io_reg.h +++ /dev/null @@ -1,1263 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_IO_OUT_DATA_REG register - * need des - */ -#define LP_IO_OUT_DATA_REG (DR_REG_LP_IO_BASE + 0x0) -/** LP_IO_LP_GPIO_OUT_DATA : R/W/WTC; bitpos: [7:0]; default: 0; - * set lp gpio output data - */ -#define LP_IO_LP_GPIO_OUT_DATA 0x000000FFU -#define LP_IO_LP_GPIO_OUT_DATA_M (LP_IO_LP_GPIO_OUT_DATA_V << LP_IO_LP_GPIO_OUT_DATA_S) -#define LP_IO_LP_GPIO_OUT_DATA_V 0x000000FFU -#define LP_IO_LP_GPIO_OUT_DATA_S 0 - -/** LP_IO_OUT_DATA_W1TS_REG register - * need des - */ -#define LP_IO_OUT_DATA_W1TS_REG (DR_REG_LP_IO_BASE + 0x4) -/** LP_IO_LP_GPIO_OUT_DATA_W1TS : WT; bitpos: [7:0]; default: 0; - * set one time output data - */ -#define LP_IO_LP_GPIO_OUT_DATA_W1TS 0x000000FFU -#define LP_IO_LP_GPIO_OUT_DATA_W1TS_M (LP_IO_LP_GPIO_OUT_DATA_W1TS_V << LP_IO_LP_GPIO_OUT_DATA_W1TS_S) -#define LP_IO_LP_GPIO_OUT_DATA_W1TS_V 0x000000FFU -#define LP_IO_LP_GPIO_OUT_DATA_W1TS_S 0 - -/** LP_IO_OUT_DATA_W1TC_REG register - * need des - */ -#define LP_IO_OUT_DATA_W1TC_REG (DR_REG_LP_IO_BASE + 0x8) -/** LP_IO_LP_GPIO_OUT_DATA_W1TC : WT; bitpos: [7:0]; default: 0; - * clear one time output data - */ -#define LP_IO_LP_GPIO_OUT_DATA_W1TC 0x000000FFU -#define LP_IO_LP_GPIO_OUT_DATA_W1TC_M (LP_IO_LP_GPIO_OUT_DATA_W1TC_V << LP_IO_LP_GPIO_OUT_DATA_W1TC_S) -#define LP_IO_LP_GPIO_OUT_DATA_W1TC_V 0x000000FFU -#define LP_IO_LP_GPIO_OUT_DATA_W1TC_S 0 - -/** LP_IO_OUT_ENABLE_REG register - * need des - */ -#define LP_IO_OUT_ENABLE_REG (DR_REG_LP_IO_BASE + 0xc) -/** LP_IO_LP_GPIO_ENABLE : R/W/WTC; bitpos: [7:0]; default: 0; - * set lp gpio output data - */ -#define LP_IO_LP_GPIO_ENABLE 0x000000FFU -#define LP_IO_LP_GPIO_ENABLE_M (LP_IO_LP_GPIO_ENABLE_V << LP_IO_LP_GPIO_ENABLE_S) -#define LP_IO_LP_GPIO_ENABLE_V 0x000000FFU -#define LP_IO_LP_GPIO_ENABLE_S 0 - -/** LP_IO_OUT_ENABLE_W1TS_REG register - * need des - */ -#define LP_IO_OUT_ENABLE_W1TS_REG (DR_REG_LP_IO_BASE + 0x10) -/** LP_IO_LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0; - * set one time output data - */ -#define LP_IO_LP_GPIO_ENABLE_W1TS 0x000000FFU -#define LP_IO_LP_GPIO_ENABLE_W1TS_M (LP_IO_LP_GPIO_ENABLE_W1TS_V << LP_IO_LP_GPIO_ENABLE_W1TS_S) -#define LP_IO_LP_GPIO_ENABLE_W1TS_V 0x000000FFU -#define LP_IO_LP_GPIO_ENABLE_W1TS_S 0 - -/** LP_IO_OUT_ENABLE_W1TC_REG register - * need des - */ -#define LP_IO_OUT_ENABLE_W1TC_REG (DR_REG_LP_IO_BASE + 0x14) -/** LP_IO_LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0; - * clear one time output data - */ -#define LP_IO_LP_GPIO_ENABLE_W1TC 0x000000FFU -#define LP_IO_LP_GPIO_ENABLE_W1TC_M (LP_IO_LP_GPIO_ENABLE_W1TC_V << LP_IO_LP_GPIO_ENABLE_W1TC_S) -#define LP_IO_LP_GPIO_ENABLE_W1TC_V 0x000000FFU -#define LP_IO_LP_GPIO_ENABLE_W1TC_S 0 - -/** LP_IO_STATUS_REG register - * need des - */ -#define LP_IO_STATUS_REG (DR_REG_LP_IO_BASE + 0x18) -/** LP_IO_LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0; - * set lp gpio output data - */ -#define LP_IO_LP_GPIO_STATUS_INTERRUPT 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_INTERRUPT_M (LP_IO_LP_GPIO_STATUS_INTERRUPT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_S) -#define LP_IO_LP_GPIO_STATUS_INTERRUPT_V 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_INTERRUPT_S 0 - -/** LP_IO_STATUS_W1TS_REG register - * need des - */ -#define LP_IO_STATUS_W1TS_REG (DR_REG_LP_IO_BASE + 0x1c) -/** LP_IO_LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0; - * set one time output data - */ -#define LP_IO_LP_GPIO_STATUS_W1TS 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_W1TS_M (LP_IO_LP_GPIO_STATUS_W1TS_V << LP_IO_LP_GPIO_STATUS_W1TS_S) -#define LP_IO_LP_GPIO_STATUS_W1TS_V 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_W1TS_S 0 - -/** LP_IO_STATUS_W1TC_REG register - * need des - */ -#define LP_IO_STATUS_W1TC_REG (DR_REG_LP_IO_BASE + 0x20) -/** LP_IO_LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0; - * clear one time output data - */ -#define LP_IO_LP_GPIO_STATUS_W1TC 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_W1TC_M (LP_IO_LP_GPIO_STATUS_W1TC_V << LP_IO_LP_GPIO_STATUS_W1TC_S) -#define LP_IO_LP_GPIO_STATUS_W1TC_V 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_W1TC_S 0 - -/** LP_IO_IN_REG register - * need des - */ -#define LP_IO_IN_REG (DR_REG_LP_IO_BASE + 0x24) -/** LP_IO_LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO_IN_DATA_NEXT 0x000000FFU -#define LP_IO_LP_GPIO_IN_DATA_NEXT_M (LP_IO_LP_GPIO_IN_DATA_NEXT_V << LP_IO_LP_GPIO_IN_DATA_NEXT_S) -#define LP_IO_LP_GPIO_IN_DATA_NEXT_V 0x000000FFU -#define LP_IO_LP_GPIO_IN_DATA_NEXT_S 0 - -/** LP_IO_PIN0_REG register - * need des - */ -#define LP_IO_PIN0_REG (DR_REG_LP_IO_BASE + 0x28) -/** LP_IO_LP_GPIO0_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO0_SYNC_BYPASS_M (LP_IO_LP_GPIO0_SYNC_BYPASS_V << LP_IO_LP_GPIO0_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO0_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO0_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO0_PAD_DRIVER_M (LP_IO_LP_GPIO0_PAD_DRIVER_V << LP_IO_LP_GPIO0_PAD_DRIVER_S) -#define LP_IO_LP_GPIO0_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO0_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO0_INT_TYPE_M (LP_IO_LP_GPIO0_INT_TYPE_V << LP_IO_LP_GPIO0_INT_TYPE_S) -#define LP_IO_LP_GPIO0_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO0_INT_TYPE_S 7 -/** LP_IO_LP_GPIO0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_M (LP_IO_LP_GPIO0_WAKEUP_ENABLE_V << LP_IO_LP_GPIO0_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO0_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO0_FILTER_EN_M (LP_IO_LP_GPIO0_FILTER_EN_V << LP_IO_LP_GPIO0_FILTER_EN_S) -#define LP_IO_LP_GPIO0_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO0_FILTER_EN_S 11 - -/** LP_IO_PIN1_REG register - * need des - */ -#define LP_IO_PIN1_REG (DR_REG_LP_IO_BASE + 0x2c) -/** LP_IO_LP_GPIO1_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO1_SYNC_BYPASS_M (LP_IO_LP_GPIO1_SYNC_BYPASS_V << LP_IO_LP_GPIO1_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO1_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO1_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO1_PAD_DRIVER_M (LP_IO_LP_GPIO1_PAD_DRIVER_V << LP_IO_LP_GPIO1_PAD_DRIVER_S) -#define LP_IO_LP_GPIO1_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO1_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO1_INT_TYPE_M (LP_IO_LP_GPIO1_INT_TYPE_V << LP_IO_LP_GPIO1_INT_TYPE_S) -#define LP_IO_LP_GPIO1_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO1_INT_TYPE_S 7 -/** LP_IO_LP_GPIO1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_M (LP_IO_LP_GPIO1_WAKEUP_ENABLE_V << LP_IO_LP_GPIO1_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO1_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO1_FILTER_EN_M (LP_IO_LP_GPIO1_FILTER_EN_V << LP_IO_LP_GPIO1_FILTER_EN_S) -#define LP_IO_LP_GPIO1_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO1_FILTER_EN_S 11 - -/** LP_IO_PIN2_REG register - * need des - */ -#define LP_IO_PIN2_REG (DR_REG_LP_IO_BASE + 0x30) -/** LP_IO_LP_GPIO2_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO2_SYNC_BYPASS_M (LP_IO_LP_GPIO2_SYNC_BYPASS_V << LP_IO_LP_GPIO2_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO2_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO2_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO2_PAD_DRIVER_M (LP_IO_LP_GPIO2_PAD_DRIVER_V << LP_IO_LP_GPIO2_PAD_DRIVER_S) -#define LP_IO_LP_GPIO2_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO2_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO2_INT_TYPE_M (LP_IO_LP_GPIO2_INT_TYPE_V << LP_IO_LP_GPIO2_INT_TYPE_S) -#define LP_IO_LP_GPIO2_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO2_INT_TYPE_S 7 -/** LP_IO_LP_GPIO2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_M (LP_IO_LP_GPIO2_WAKEUP_ENABLE_V << LP_IO_LP_GPIO2_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO2_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO2_FILTER_EN_M (LP_IO_LP_GPIO2_FILTER_EN_V << LP_IO_LP_GPIO2_FILTER_EN_S) -#define LP_IO_LP_GPIO2_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO2_FILTER_EN_S 11 - -/** LP_IO_PIN3_REG register - * need des - */ -#define LP_IO_PIN3_REG (DR_REG_LP_IO_BASE + 0x34) -/** LP_IO_LP_GPIO3_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO3_SYNC_BYPASS_M (LP_IO_LP_GPIO3_SYNC_BYPASS_V << LP_IO_LP_GPIO3_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO3_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO3_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO3_PAD_DRIVER_M (LP_IO_LP_GPIO3_PAD_DRIVER_V << LP_IO_LP_GPIO3_PAD_DRIVER_S) -#define LP_IO_LP_GPIO3_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO3_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO3_INT_TYPE_M (LP_IO_LP_GPIO3_INT_TYPE_V << LP_IO_LP_GPIO3_INT_TYPE_S) -#define LP_IO_LP_GPIO3_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO3_INT_TYPE_S 7 -/** LP_IO_LP_GPIO3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_M (LP_IO_LP_GPIO3_WAKEUP_ENABLE_V << LP_IO_LP_GPIO3_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO3_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO3_FILTER_EN_M (LP_IO_LP_GPIO3_FILTER_EN_V << LP_IO_LP_GPIO3_FILTER_EN_S) -#define LP_IO_LP_GPIO3_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO3_FILTER_EN_S 11 - -/** LP_IO_PIN4_REG register - * need des - */ -#define LP_IO_PIN4_REG (DR_REG_LP_IO_BASE + 0x38) -/** LP_IO_LP_GPIO4_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO4_SYNC_BYPASS_M (LP_IO_LP_GPIO4_SYNC_BYPASS_V << LP_IO_LP_GPIO4_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO4_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO4_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO4_PAD_DRIVER_M (LP_IO_LP_GPIO4_PAD_DRIVER_V << LP_IO_LP_GPIO4_PAD_DRIVER_S) -#define LP_IO_LP_GPIO4_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO4_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO4_INT_TYPE_M (LP_IO_LP_GPIO4_INT_TYPE_V << LP_IO_LP_GPIO4_INT_TYPE_S) -#define LP_IO_LP_GPIO4_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO4_INT_TYPE_S 7 -/** LP_IO_LP_GPIO4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_M (LP_IO_LP_GPIO4_WAKEUP_ENABLE_V << LP_IO_LP_GPIO4_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO4_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO4_FILTER_EN_M (LP_IO_LP_GPIO4_FILTER_EN_V << LP_IO_LP_GPIO4_FILTER_EN_S) -#define LP_IO_LP_GPIO4_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO4_FILTER_EN_S 11 - -/** LP_IO_PIN5_REG register - * need des - */ -#define LP_IO_PIN5_REG (DR_REG_LP_IO_BASE + 0x3c) -/** LP_IO_LP_GPIO5_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO5_SYNC_BYPASS_M (LP_IO_LP_GPIO5_SYNC_BYPASS_V << LP_IO_LP_GPIO5_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO5_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO5_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO5_PAD_DRIVER_M (LP_IO_LP_GPIO5_PAD_DRIVER_V << LP_IO_LP_GPIO5_PAD_DRIVER_S) -#define LP_IO_LP_GPIO5_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO5_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO5_INT_TYPE_M (LP_IO_LP_GPIO5_INT_TYPE_V << LP_IO_LP_GPIO5_INT_TYPE_S) -#define LP_IO_LP_GPIO5_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO5_INT_TYPE_S 7 -/** LP_IO_LP_GPIO5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_M (LP_IO_LP_GPIO5_WAKEUP_ENABLE_V << LP_IO_LP_GPIO5_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO5_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO5_FILTER_EN_M (LP_IO_LP_GPIO5_FILTER_EN_V << LP_IO_LP_GPIO5_FILTER_EN_S) -#define LP_IO_LP_GPIO5_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO5_FILTER_EN_S 11 - -/** LP_IO_PIN6_REG register - * need des - */ -#define LP_IO_PIN6_REG (DR_REG_LP_IO_BASE + 0x40) -/** LP_IO_LP_GPIO6_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO6_SYNC_BYPASS_M (LP_IO_LP_GPIO6_SYNC_BYPASS_V << LP_IO_LP_GPIO6_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO6_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO6_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO6_PAD_DRIVER_M (LP_IO_LP_GPIO6_PAD_DRIVER_V << LP_IO_LP_GPIO6_PAD_DRIVER_S) -#define LP_IO_LP_GPIO6_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO6_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO6_INT_TYPE_M (LP_IO_LP_GPIO6_INT_TYPE_V << LP_IO_LP_GPIO6_INT_TYPE_S) -#define LP_IO_LP_GPIO6_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO6_INT_TYPE_S 7 -/** LP_IO_LP_GPIO6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_M (LP_IO_LP_GPIO6_WAKEUP_ENABLE_V << LP_IO_LP_GPIO6_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO6_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO6_FILTER_EN_M (LP_IO_LP_GPIO6_FILTER_EN_V << LP_IO_LP_GPIO6_FILTER_EN_S) -#define LP_IO_LP_GPIO6_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO6_FILTER_EN_S 11 - -/** LP_IO_PIN7_REG register - * need des - */ -#define LP_IO_PIN7_REG (DR_REG_LP_IO_BASE + 0x44) -/** LP_IO_LP_GPIO7_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_SYNC_BYPASS 0x00000003U -#define LP_IO_LP_GPIO7_SYNC_BYPASS_M (LP_IO_LP_GPIO7_SYNC_BYPASS_V << LP_IO_LP_GPIO7_SYNC_BYPASS_S) -#define LP_IO_LP_GPIO7_SYNC_BYPASS_V 0x00000003U -#define LP_IO_LP_GPIO7_SYNC_BYPASS_S 0 -/** LP_IO_LP_GPIO7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_PAD_DRIVER (BIT(2)) -#define LP_IO_LP_GPIO7_PAD_DRIVER_M (LP_IO_LP_GPIO7_PAD_DRIVER_V << LP_IO_LP_GPIO7_PAD_DRIVER_S) -#define LP_IO_LP_GPIO7_PAD_DRIVER_V 0x00000001U -#define LP_IO_LP_GPIO7_PAD_DRIVER_S 2 -/** LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR (BIT(3)) -#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S) -#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S 3 -/** LP_IO_LP_GPIO7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_INT_TYPE 0x00000007U -#define LP_IO_LP_GPIO7_INT_TYPE_M (LP_IO_LP_GPIO7_INT_TYPE_V << LP_IO_LP_GPIO7_INT_TYPE_S) -#define LP_IO_LP_GPIO7_INT_TYPE_V 0x00000007U -#define LP_IO_LP_GPIO7_INT_TYPE_S 7 -/** LP_IO_LP_GPIO7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_WAKEUP_ENABLE (BIT(10)) -#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_M (LP_IO_LP_GPIO7_WAKEUP_ENABLE_V << LP_IO_LP_GPIO7_WAKEUP_ENABLE_S) -#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_V 0x00000001U -#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_S 10 -/** LP_IO_LP_GPIO7_FILTER_EN : R/W; bitpos: [11]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_FILTER_EN (BIT(11)) -#define LP_IO_LP_GPIO7_FILTER_EN_M (LP_IO_LP_GPIO7_FILTER_EN_V << LP_IO_LP_GPIO7_FILTER_EN_S) -#define LP_IO_LP_GPIO7_FILTER_EN_V 0x00000001U -#define LP_IO_LP_GPIO7_FILTER_EN_S 11 - -/** LP_IO_GPIO0_REG register - * need des - */ -#define LP_IO_GPIO0_REG (DR_REG_LP_IO_BASE + 0x48) -/** LP_IO_LP_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO0_MCU_OE_M (LP_IO_LP_GPIO0_MCU_OE_V << LP_IO_LP_GPIO0_MCU_OE_S) -#define LP_IO_LP_GPIO0_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO0_MCU_OE_S 0 -/** LP_IO_LP_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO0_SLP_SEL_M (LP_IO_LP_GPIO0_SLP_SEL_V << LP_IO_LP_GPIO0_SLP_SEL_S) -#define LP_IO_LP_GPIO0_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO0_SLP_SEL_S 1 -/** LP_IO_LP_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO0_MCU_WPD_M (LP_IO_LP_GPIO0_MCU_WPD_V << LP_IO_LP_GPIO0_MCU_WPD_S) -#define LP_IO_LP_GPIO0_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO0_MCU_WPD_S 2 -/** LP_IO_LP_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO0_MCU_WPU_M (LP_IO_LP_GPIO0_MCU_WPU_V << LP_IO_LP_GPIO0_MCU_WPU_S) -#define LP_IO_LP_GPIO0_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO0_MCU_WPU_S 3 -/** LP_IO_LP_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO0_MCU_IE_M (LP_IO_LP_GPIO0_MCU_IE_V << LP_IO_LP_GPIO0_MCU_IE_S) -#define LP_IO_LP_GPIO0_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO0_MCU_IE_S 4 -/** LP_IO_LP_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO0_MCU_DRV_M (LP_IO_LP_GPIO0_MCU_DRV_V << LP_IO_LP_GPIO0_MCU_DRV_S) -#define LP_IO_LP_GPIO0_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO0_MCU_DRV_S 5 -/** LP_IO_LP_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO0_FUN_WPD_M (LP_IO_LP_GPIO0_FUN_WPD_V << LP_IO_LP_GPIO0_FUN_WPD_S) -#define LP_IO_LP_GPIO0_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO0_FUN_WPD_S 7 -/** LP_IO_LP_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO0_FUN_WPU_M (LP_IO_LP_GPIO0_FUN_WPU_V << LP_IO_LP_GPIO0_FUN_WPU_S) -#define LP_IO_LP_GPIO0_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO0_FUN_WPU_S 8 -/** LP_IO_LP_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO0_FUN_IE_M (LP_IO_LP_GPIO0_FUN_IE_V << LP_IO_LP_GPIO0_FUN_IE_S) -#define LP_IO_LP_GPIO0_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO0_FUN_IE_S 9 -/** LP_IO_LP_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO0_FUN_DRV_M (LP_IO_LP_GPIO0_FUN_DRV_V << LP_IO_LP_GPIO0_FUN_DRV_S) -#define LP_IO_LP_GPIO0_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO0_FUN_DRV_S 10 -/** LP_IO_LP_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO0_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO0_MCU_SEL_M (LP_IO_LP_GPIO0_MCU_SEL_V << LP_IO_LP_GPIO0_MCU_SEL_S) -#define LP_IO_LP_GPIO0_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO0_MCU_SEL_S 12 - -/** LP_IO_GPIO1_REG register - * need des - */ -#define LP_IO_GPIO1_REG (DR_REG_LP_IO_BASE + 0x4c) -/** LP_IO_LP_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO1_MCU_OE_M (LP_IO_LP_GPIO1_MCU_OE_V << LP_IO_LP_GPIO1_MCU_OE_S) -#define LP_IO_LP_GPIO1_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO1_MCU_OE_S 0 -/** LP_IO_LP_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO1_SLP_SEL_M (LP_IO_LP_GPIO1_SLP_SEL_V << LP_IO_LP_GPIO1_SLP_SEL_S) -#define LP_IO_LP_GPIO1_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO1_SLP_SEL_S 1 -/** LP_IO_LP_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO1_MCU_WPD_M (LP_IO_LP_GPIO1_MCU_WPD_V << LP_IO_LP_GPIO1_MCU_WPD_S) -#define LP_IO_LP_GPIO1_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO1_MCU_WPD_S 2 -/** LP_IO_LP_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO1_MCU_WPU_M (LP_IO_LP_GPIO1_MCU_WPU_V << LP_IO_LP_GPIO1_MCU_WPU_S) -#define LP_IO_LP_GPIO1_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO1_MCU_WPU_S 3 -/** LP_IO_LP_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO1_MCU_IE_M (LP_IO_LP_GPIO1_MCU_IE_V << LP_IO_LP_GPIO1_MCU_IE_S) -#define LP_IO_LP_GPIO1_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO1_MCU_IE_S 4 -/** LP_IO_LP_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO1_MCU_DRV_M (LP_IO_LP_GPIO1_MCU_DRV_V << LP_IO_LP_GPIO1_MCU_DRV_S) -#define LP_IO_LP_GPIO1_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO1_MCU_DRV_S 5 -/** LP_IO_LP_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO1_FUN_WPD_M (LP_IO_LP_GPIO1_FUN_WPD_V << LP_IO_LP_GPIO1_FUN_WPD_S) -#define LP_IO_LP_GPIO1_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO1_FUN_WPD_S 7 -/** LP_IO_LP_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO1_FUN_WPU_M (LP_IO_LP_GPIO1_FUN_WPU_V << LP_IO_LP_GPIO1_FUN_WPU_S) -#define LP_IO_LP_GPIO1_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO1_FUN_WPU_S 8 -/** LP_IO_LP_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO1_FUN_IE_M (LP_IO_LP_GPIO1_FUN_IE_V << LP_IO_LP_GPIO1_FUN_IE_S) -#define LP_IO_LP_GPIO1_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO1_FUN_IE_S 9 -/** LP_IO_LP_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO1_FUN_DRV_M (LP_IO_LP_GPIO1_FUN_DRV_V << LP_IO_LP_GPIO1_FUN_DRV_S) -#define LP_IO_LP_GPIO1_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO1_FUN_DRV_S 10 -/** LP_IO_LP_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO1_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO1_MCU_SEL_M (LP_IO_LP_GPIO1_MCU_SEL_V << LP_IO_LP_GPIO1_MCU_SEL_S) -#define LP_IO_LP_GPIO1_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO1_MCU_SEL_S 12 - -/** LP_IO_GPIO2_REG register - * need des - */ -#define LP_IO_GPIO2_REG (DR_REG_LP_IO_BASE + 0x50) -/** LP_IO_LP_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO2_MCU_OE_M (LP_IO_LP_GPIO2_MCU_OE_V << LP_IO_LP_GPIO2_MCU_OE_S) -#define LP_IO_LP_GPIO2_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO2_MCU_OE_S 0 -/** LP_IO_LP_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO2_SLP_SEL_M (LP_IO_LP_GPIO2_SLP_SEL_V << LP_IO_LP_GPIO2_SLP_SEL_S) -#define LP_IO_LP_GPIO2_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO2_SLP_SEL_S 1 -/** LP_IO_LP_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO2_MCU_WPD_M (LP_IO_LP_GPIO2_MCU_WPD_V << LP_IO_LP_GPIO2_MCU_WPD_S) -#define LP_IO_LP_GPIO2_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO2_MCU_WPD_S 2 -/** LP_IO_LP_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO2_MCU_WPU_M (LP_IO_LP_GPIO2_MCU_WPU_V << LP_IO_LP_GPIO2_MCU_WPU_S) -#define LP_IO_LP_GPIO2_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO2_MCU_WPU_S 3 -/** LP_IO_LP_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO2_MCU_IE_M (LP_IO_LP_GPIO2_MCU_IE_V << LP_IO_LP_GPIO2_MCU_IE_S) -#define LP_IO_LP_GPIO2_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO2_MCU_IE_S 4 -/** LP_IO_LP_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO2_MCU_DRV_M (LP_IO_LP_GPIO2_MCU_DRV_V << LP_IO_LP_GPIO2_MCU_DRV_S) -#define LP_IO_LP_GPIO2_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO2_MCU_DRV_S 5 -/** LP_IO_LP_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO2_FUN_WPD_M (LP_IO_LP_GPIO2_FUN_WPD_V << LP_IO_LP_GPIO2_FUN_WPD_S) -#define LP_IO_LP_GPIO2_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO2_FUN_WPD_S 7 -/** LP_IO_LP_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO2_FUN_WPU_M (LP_IO_LP_GPIO2_FUN_WPU_V << LP_IO_LP_GPIO2_FUN_WPU_S) -#define LP_IO_LP_GPIO2_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO2_FUN_WPU_S 8 -/** LP_IO_LP_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO2_FUN_IE_M (LP_IO_LP_GPIO2_FUN_IE_V << LP_IO_LP_GPIO2_FUN_IE_S) -#define LP_IO_LP_GPIO2_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO2_FUN_IE_S 9 -/** LP_IO_LP_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO2_FUN_DRV_M (LP_IO_LP_GPIO2_FUN_DRV_V << LP_IO_LP_GPIO2_FUN_DRV_S) -#define LP_IO_LP_GPIO2_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO2_FUN_DRV_S 10 -/** LP_IO_LP_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO2_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO2_MCU_SEL_M (LP_IO_LP_GPIO2_MCU_SEL_V << LP_IO_LP_GPIO2_MCU_SEL_S) -#define LP_IO_LP_GPIO2_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO2_MCU_SEL_S 12 - -/** LP_IO_GPIO3_REG register - * need des - */ -#define LP_IO_GPIO3_REG (DR_REG_LP_IO_BASE + 0x54) -/** LP_IO_LP_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO3_MCU_OE_M (LP_IO_LP_GPIO3_MCU_OE_V << LP_IO_LP_GPIO3_MCU_OE_S) -#define LP_IO_LP_GPIO3_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO3_MCU_OE_S 0 -/** LP_IO_LP_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO3_SLP_SEL_M (LP_IO_LP_GPIO3_SLP_SEL_V << LP_IO_LP_GPIO3_SLP_SEL_S) -#define LP_IO_LP_GPIO3_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO3_SLP_SEL_S 1 -/** LP_IO_LP_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO3_MCU_WPD_M (LP_IO_LP_GPIO3_MCU_WPD_V << LP_IO_LP_GPIO3_MCU_WPD_S) -#define LP_IO_LP_GPIO3_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO3_MCU_WPD_S 2 -/** LP_IO_LP_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO3_MCU_WPU_M (LP_IO_LP_GPIO3_MCU_WPU_V << LP_IO_LP_GPIO3_MCU_WPU_S) -#define LP_IO_LP_GPIO3_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO3_MCU_WPU_S 3 -/** LP_IO_LP_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO3_MCU_IE_M (LP_IO_LP_GPIO3_MCU_IE_V << LP_IO_LP_GPIO3_MCU_IE_S) -#define LP_IO_LP_GPIO3_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO3_MCU_IE_S 4 -/** LP_IO_LP_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO3_MCU_DRV_M (LP_IO_LP_GPIO3_MCU_DRV_V << LP_IO_LP_GPIO3_MCU_DRV_S) -#define LP_IO_LP_GPIO3_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO3_MCU_DRV_S 5 -/** LP_IO_LP_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO3_FUN_WPD_M (LP_IO_LP_GPIO3_FUN_WPD_V << LP_IO_LP_GPIO3_FUN_WPD_S) -#define LP_IO_LP_GPIO3_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO3_FUN_WPD_S 7 -/** LP_IO_LP_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO3_FUN_WPU_M (LP_IO_LP_GPIO3_FUN_WPU_V << LP_IO_LP_GPIO3_FUN_WPU_S) -#define LP_IO_LP_GPIO3_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO3_FUN_WPU_S 8 -/** LP_IO_LP_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO3_FUN_IE_M (LP_IO_LP_GPIO3_FUN_IE_V << LP_IO_LP_GPIO3_FUN_IE_S) -#define LP_IO_LP_GPIO3_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO3_FUN_IE_S 9 -/** LP_IO_LP_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO3_FUN_DRV_M (LP_IO_LP_GPIO3_FUN_DRV_V << LP_IO_LP_GPIO3_FUN_DRV_S) -#define LP_IO_LP_GPIO3_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO3_FUN_DRV_S 10 -/** LP_IO_LP_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO3_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO3_MCU_SEL_M (LP_IO_LP_GPIO3_MCU_SEL_V << LP_IO_LP_GPIO3_MCU_SEL_S) -#define LP_IO_LP_GPIO3_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO3_MCU_SEL_S 12 - -/** LP_IO_GPIO4_REG register - * need des - */ -#define LP_IO_GPIO4_REG (DR_REG_LP_IO_BASE + 0x58) -/** LP_IO_LP_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO4_MCU_OE_M (LP_IO_LP_GPIO4_MCU_OE_V << LP_IO_LP_GPIO4_MCU_OE_S) -#define LP_IO_LP_GPIO4_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO4_MCU_OE_S 0 -/** LP_IO_LP_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO4_SLP_SEL_M (LP_IO_LP_GPIO4_SLP_SEL_V << LP_IO_LP_GPIO4_SLP_SEL_S) -#define LP_IO_LP_GPIO4_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO4_SLP_SEL_S 1 -/** LP_IO_LP_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO4_MCU_WPD_M (LP_IO_LP_GPIO4_MCU_WPD_V << LP_IO_LP_GPIO4_MCU_WPD_S) -#define LP_IO_LP_GPIO4_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO4_MCU_WPD_S 2 -/** LP_IO_LP_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO4_MCU_WPU_M (LP_IO_LP_GPIO4_MCU_WPU_V << LP_IO_LP_GPIO4_MCU_WPU_S) -#define LP_IO_LP_GPIO4_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO4_MCU_WPU_S 3 -/** LP_IO_LP_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO4_MCU_IE_M (LP_IO_LP_GPIO4_MCU_IE_V << LP_IO_LP_GPIO4_MCU_IE_S) -#define LP_IO_LP_GPIO4_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO4_MCU_IE_S 4 -/** LP_IO_LP_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO4_MCU_DRV_M (LP_IO_LP_GPIO4_MCU_DRV_V << LP_IO_LP_GPIO4_MCU_DRV_S) -#define LP_IO_LP_GPIO4_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO4_MCU_DRV_S 5 -/** LP_IO_LP_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO4_FUN_WPD_M (LP_IO_LP_GPIO4_FUN_WPD_V << LP_IO_LP_GPIO4_FUN_WPD_S) -#define LP_IO_LP_GPIO4_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO4_FUN_WPD_S 7 -/** LP_IO_LP_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO4_FUN_WPU_M (LP_IO_LP_GPIO4_FUN_WPU_V << LP_IO_LP_GPIO4_FUN_WPU_S) -#define LP_IO_LP_GPIO4_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO4_FUN_WPU_S 8 -/** LP_IO_LP_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO4_FUN_IE_M (LP_IO_LP_GPIO4_FUN_IE_V << LP_IO_LP_GPIO4_FUN_IE_S) -#define LP_IO_LP_GPIO4_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO4_FUN_IE_S 9 -/** LP_IO_LP_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO4_FUN_DRV_M (LP_IO_LP_GPIO4_FUN_DRV_V << LP_IO_LP_GPIO4_FUN_DRV_S) -#define LP_IO_LP_GPIO4_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO4_FUN_DRV_S 10 -/** LP_IO_LP_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO4_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO4_MCU_SEL_M (LP_IO_LP_GPIO4_MCU_SEL_V << LP_IO_LP_GPIO4_MCU_SEL_S) -#define LP_IO_LP_GPIO4_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO4_MCU_SEL_S 12 - -/** LP_IO_GPIO5_REG register - * need des - */ -#define LP_IO_GPIO5_REG (DR_REG_LP_IO_BASE + 0x5c) -/** LP_IO_LP_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO5_MCU_OE_M (LP_IO_LP_GPIO5_MCU_OE_V << LP_IO_LP_GPIO5_MCU_OE_S) -#define LP_IO_LP_GPIO5_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO5_MCU_OE_S 0 -/** LP_IO_LP_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO5_SLP_SEL_M (LP_IO_LP_GPIO5_SLP_SEL_V << LP_IO_LP_GPIO5_SLP_SEL_S) -#define LP_IO_LP_GPIO5_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO5_SLP_SEL_S 1 -/** LP_IO_LP_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO5_MCU_WPD_M (LP_IO_LP_GPIO5_MCU_WPD_V << LP_IO_LP_GPIO5_MCU_WPD_S) -#define LP_IO_LP_GPIO5_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO5_MCU_WPD_S 2 -/** LP_IO_LP_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO5_MCU_WPU_M (LP_IO_LP_GPIO5_MCU_WPU_V << LP_IO_LP_GPIO5_MCU_WPU_S) -#define LP_IO_LP_GPIO5_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO5_MCU_WPU_S 3 -/** LP_IO_LP_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO5_MCU_IE_M (LP_IO_LP_GPIO5_MCU_IE_V << LP_IO_LP_GPIO5_MCU_IE_S) -#define LP_IO_LP_GPIO5_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO5_MCU_IE_S 4 -/** LP_IO_LP_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO5_MCU_DRV_M (LP_IO_LP_GPIO5_MCU_DRV_V << LP_IO_LP_GPIO5_MCU_DRV_S) -#define LP_IO_LP_GPIO5_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO5_MCU_DRV_S 5 -/** LP_IO_LP_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO5_FUN_WPD_M (LP_IO_LP_GPIO5_FUN_WPD_V << LP_IO_LP_GPIO5_FUN_WPD_S) -#define LP_IO_LP_GPIO5_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO5_FUN_WPD_S 7 -/** LP_IO_LP_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO5_FUN_WPU_M (LP_IO_LP_GPIO5_FUN_WPU_V << LP_IO_LP_GPIO5_FUN_WPU_S) -#define LP_IO_LP_GPIO5_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO5_FUN_WPU_S 8 -/** LP_IO_LP_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO5_FUN_IE_M (LP_IO_LP_GPIO5_FUN_IE_V << LP_IO_LP_GPIO5_FUN_IE_S) -#define LP_IO_LP_GPIO5_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO5_FUN_IE_S 9 -/** LP_IO_LP_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO5_FUN_DRV_M (LP_IO_LP_GPIO5_FUN_DRV_V << LP_IO_LP_GPIO5_FUN_DRV_S) -#define LP_IO_LP_GPIO5_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO5_FUN_DRV_S 10 -/** LP_IO_LP_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO5_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO5_MCU_SEL_M (LP_IO_LP_GPIO5_MCU_SEL_V << LP_IO_LP_GPIO5_MCU_SEL_S) -#define LP_IO_LP_GPIO5_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO5_MCU_SEL_S 12 - -/** LP_IO_GPIO6_REG register - * need des - */ -#define LP_IO_GPIO6_REG (DR_REG_LP_IO_BASE + 0x60) -/** LP_IO_LP_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO6_MCU_OE_M (LP_IO_LP_GPIO6_MCU_OE_V << LP_IO_LP_GPIO6_MCU_OE_S) -#define LP_IO_LP_GPIO6_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO6_MCU_OE_S 0 -/** LP_IO_LP_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO6_SLP_SEL_M (LP_IO_LP_GPIO6_SLP_SEL_V << LP_IO_LP_GPIO6_SLP_SEL_S) -#define LP_IO_LP_GPIO6_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO6_SLP_SEL_S 1 -/** LP_IO_LP_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO6_MCU_WPD_M (LP_IO_LP_GPIO6_MCU_WPD_V << LP_IO_LP_GPIO6_MCU_WPD_S) -#define LP_IO_LP_GPIO6_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO6_MCU_WPD_S 2 -/** LP_IO_LP_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO6_MCU_WPU_M (LP_IO_LP_GPIO6_MCU_WPU_V << LP_IO_LP_GPIO6_MCU_WPU_S) -#define LP_IO_LP_GPIO6_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO6_MCU_WPU_S 3 -/** LP_IO_LP_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO6_MCU_IE_M (LP_IO_LP_GPIO6_MCU_IE_V << LP_IO_LP_GPIO6_MCU_IE_S) -#define LP_IO_LP_GPIO6_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO6_MCU_IE_S 4 -/** LP_IO_LP_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO6_MCU_DRV_M (LP_IO_LP_GPIO6_MCU_DRV_V << LP_IO_LP_GPIO6_MCU_DRV_S) -#define LP_IO_LP_GPIO6_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO6_MCU_DRV_S 5 -/** LP_IO_LP_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO6_FUN_WPD_M (LP_IO_LP_GPIO6_FUN_WPD_V << LP_IO_LP_GPIO6_FUN_WPD_S) -#define LP_IO_LP_GPIO6_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO6_FUN_WPD_S 7 -/** LP_IO_LP_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO6_FUN_WPU_M (LP_IO_LP_GPIO6_FUN_WPU_V << LP_IO_LP_GPIO6_FUN_WPU_S) -#define LP_IO_LP_GPIO6_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO6_FUN_WPU_S 8 -/** LP_IO_LP_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO6_FUN_IE_M (LP_IO_LP_GPIO6_FUN_IE_V << LP_IO_LP_GPIO6_FUN_IE_S) -#define LP_IO_LP_GPIO6_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO6_FUN_IE_S 9 -/** LP_IO_LP_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO6_FUN_DRV_M (LP_IO_LP_GPIO6_FUN_DRV_V << LP_IO_LP_GPIO6_FUN_DRV_S) -#define LP_IO_LP_GPIO6_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO6_FUN_DRV_S 10 -/** LP_IO_LP_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO6_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO6_MCU_SEL_M (LP_IO_LP_GPIO6_MCU_SEL_V << LP_IO_LP_GPIO6_MCU_SEL_S) -#define LP_IO_LP_GPIO6_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO6_MCU_SEL_S 12 - -/** LP_IO_GPIO7_REG register - * need des - */ -#define LP_IO_GPIO7_REG (DR_REG_LP_IO_BASE + 0x64) -/** LP_IO_LP_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_MCU_OE (BIT(0)) -#define LP_IO_LP_GPIO7_MCU_OE_M (LP_IO_LP_GPIO7_MCU_OE_V << LP_IO_LP_GPIO7_MCU_OE_S) -#define LP_IO_LP_GPIO7_MCU_OE_V 0x00000001U -#define LP_IO_LP_GPIO7_MCU_OE_S 0 -/** LP_IO_LP_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_SLP_SEL (BIT(1)) -#define LP_IO_LP_GPIO7_SLP_SEL_M (LP_IO_LP_GPIO7_SLP_SEL_V << LP_IO_LP_GPIO7_SLP_SEL_S) -#define LP_IO_LP_GPIO7_SLP_SEL_V 0x00000001U -#define LP_IO_LP_GPIO7_SLP_SEL_S 1 -/** LP_IO_LP_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_MCU_WPD (BIT(2)) -#define LP_IO_LP_GPIO7_MCU_WPD_M (LP_IO_LP_GPIO7_MCU_WPD_V << LP_IO_LP_GPIO7_MCU_WPD_S) -#define LP_IO_LP_GPIO7_MCU_WPD_V 0x00000001U -#define LP_IO_LP_GPIO7_MCU_WPD_S 2 -/** LP_IO_LP_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_MCU_WPU (BIT(3)) -#define LP_IO_LP_GPIO7_MCU_WPU_M (LP_IO_LP_GPIO7_MCU_WPU_V << LP_IO_LP_GPIO7_MCU_WPU_S) -#define LP_IO_LP_GPIO7_MCU_WPU_V 0x00000001U -#define LP_IO_LP_GPIO7_MCU_WPU_S 3 -/** LP_IO_LP_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_MCU_IE (BIT(4)) -#define LP_IO_LP_GPIO7_MCU_IE_M (LP_IO_LP_GPIO7_MCU_IE_V << LP_IO_LP_GPIO7_MCU_IE_S) -#define LP_IO_LP_GPIO7_MCU_IE_V 0x00000001U -#define LP_IO_LP_GPIO7_MCU_IE_S 4 -/** LP_IO_LP_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_MCU_DRV 0x00000003U -#define LP_IO_LP_GPIO7_MCU_DRV_M (LP_IO_LP_GPIO7_MCU_DRV_V << LP_IO_LP_GPIO7_MCU_DRV_S) -#define LP_IO_LP_GPIO7_MCU_DRV_V 0x00000003U -#define LP_IO_LP_GPIO7_MCU_DRV_S 5 -/** LP_IO_LP_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_FUN_WPD (BIT(7)) -#define LP_IO_LP_GPIO7_FUN_WPD_M (LP_IO_LP_GPIO7_FUN_WPD_V << LP_IO_LP_GPIO7_FUN_WPD_S) -#define LP_IO_LP_GPIO7_FUN_WPD_V 0x00000001U -#define LP_IO_LP_GPIO7_FUN_WPD_S 7 -/** LP_IO_LP_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_FUN_WPU (BIT(8)) -#define LP_IO_LP_GPIO7_FUN_WPU_M (LP_IO_LP_GPIO7_FUN_WPU_V << LP_IO_LP_GPIO7_FUN_WPU_S) -#define LP_IO_LP_GPIO7_FUN_WPU_V 0x00000001U -#define LP_IO_LP_GPIO7_FUN_WPU_S 8 -/** LP_IO_LP_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_FUN_IE (BIT(9)) -#define LP_IO_LP_GPIO7_FUN_IE_M (LP_IO_LP_GPIO7_FUN_IE_V << LP_IO_LP_GPIO7_FUN_IE_S) -#define LP_IO_LP_GPIO7_FUN_IE_V 0x00000001U -#define LP_IO_LP_GPIO7_FUN_IE_S 9 -/** LP_IO_LP_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_FUN_DRV 0x00000003U -#define LP_IO_LP_GPIO7_FUN_DRV_M (LP_IO_LP_GPIO7_FUN_DRV_V << LP_IO_LP_GPIO7_FUN_DRV_S) -#define LP_IO_LP_GPIO7_FUN_DRV_V 0x00000003U -#define LP_IO_LP_GPIO7_FUN_DRV_S 10 -/** LP_IO_LP_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO7_MCU_SEL 0x00000007U -#define LP_IO_LP_GPIO7_MCU_SEL_M (LP_IO_LP_GPIO7_MCU_SEL_V << LP_IO_LP_GPIO7_MCU_SEL_S) -#define LP_IO_LP_GPIO7_MCU_SEL_V 0x00000007U -#define LP_IO_LP_GPIO7_MCU_SEL_S 12 - -/** LP_IO_STATUS_INTERRUPT_REG register - * need des - */ -#define LP_IO_STATUS_INTERRUPT_REG (DR_REG_LP_IO_BASE + 0x68) -/** LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0; - * need des - */ -#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_M (LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S) -#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x000000FFU -#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S 0 - -/** LP_IO_DEBUG_SEL0_REG register - * need des - */ -#define LP_IO_DEBUG_SEL0_REG (DR_REG_LP_IO_BASE + 0x6c) -/** LP_IO_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; - * need des - */ -#define LP_IO_LP_DEBUG_SEL0 0x0000007FU -#define LP_IO_LP_DEBUG_SEL0_M (LP_IO_LP_DEBUG_SEL0_V << LP_IO_LP_DEBUG_SEL0_S) -#define LP_IO_LP_DEBUG_SEL0_V 0x0000007FU -#define LP_IO_LP_DEBUG_SEL0_S 0 -/** LP_IO_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; - * need des - */ -#define LP_IO_LP_DEBUG_SEL1 0x0000007FU -#define LP_IO_LP_DEBUG_SEL1_M (LP_IO_LP_DEBUG_SEL1_V << LP_IO_LP_DEBUG_SEL1_S) -#define LP_IO_LP_DEBUG_SEL1_V 0x0000007FU -#define LP_IO_LP_DEBUG_SEL1_S 7 -/** LP_IO_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; - * need des - */ -#define LP_IO_LP_DEBUG_SEL2 0x0000007FU -#define LP_IO_LP_DEBUG_SEL2_M (LP_IO_LP_DEBUG_SEL2_V << LP_IO_LP_DEBUG_SEL2_S) -#define LP_IO_LP_DEBUG_SEL2_V 0x0000007FU -#define LP_IO_LP_DEBUG_SEL2_S 14 -/** LP_IO_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; - * need des - */ -#define LP_IO_LP_DEBUG_SEL3 0x0000007FU -#define LP_IO_LP_DEBUG_SEL3_M (LP_IO_LP_DEBUG_SEL3_V << LP_IO_LP_DEBUG_SEL3_S) -#define LP_IO_LP_DEBUG_SEL3_V 0x0000007FU -#define LP_IO_LP_DEBUG_SEL3_S 21 - -/** LP_IO_DEBUG_SEL1_REG register - * need des - */ -#define LP_IO_DEBUG_SEL1_REG (DR_REG_LP_IO_BASE + 0x70) -/** LP_IO_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; - * need des - */ -#define LP_IO_LP_DEBUG_SEL4 0x0000007FU -#define LP_IO_LP_DEBUG_SEL4_M (LP_IO_LP_DEBUG_SEL4_V << LP_IO_LP_DEBUG_SEL4_S) -#define LP_IO_LP_DEBUG_SEL4_V 0x0000007FU -#define LP_IO_LP_DEBUG_SEL4_S 0 - -/** LP_IO_LPI2C_REG register - * need des - */ -#define LP_IO_LPI2C_REG (DR_REG_LP_IO_BASE + 0x74) -/** LP_IO_LP_I2C_SDA_IE : R/W; bitpos: [30]; default: 1; - * need des - */ -#define LP_IO_LP_I2C_SDA_IE (BIT(30)) -#define LP_IO_LP_I2C_SDA_IE_M (LP_IO_LP_I2C_SDA_IE_V << LP_IO_LP_I2C_SDA_IE_S) -#define LP_IO_LP_I2C_SDA_IE_V 0x00000001U -#define LP_IO_LP_I2C_SDA_IE_S 30 -/** LP_IO_LP_I2C_SCL_IE : R/W; bitpos: [31]; default: 1; - * need des - */ -#define LP_IO_LP_I2C_SCL_IE (BIT(31)) -#define LP_IO_LP_I2C_SCL_IE_M (LP_IO_LP_I2C_SCL_IE_V << LP_IO_LP_I2C_SCL_IE_S) -#define LP_IO_LP_I2C_SCL_IE_V 0x00000001U -#define LP_IO_LP_I2C_SCL_IE_S 31 - -/** LP_IO_DATE_REG register - * need des - */ -#define LP_IO_DATE_REG (DR_REG_LP_IO_BASE + 0x3fc) -/** LP_IO_LP_IO_DATE : R/W; bitpos: [30:0]; default: 35660032; - * need des - */ -#define LP_IO_LP_IO_DATE 0x7FFFFFFFU -#define LP_IO_LP_IO_DATE_M (LP_IO_LP_IO_DATE_V << LP_IO_LP_IO_DATE_S) -#define LP_IO_LP_IO_DATE_V 0x7FFFFFFFU -#define LP_IO_LP_IO_DATE_S 0 -/** LP_IO_CLK_EN : R/W; bitpos: [31]; default: 0; - * need des - */ -#define LP_IO_CLK_EN (BIT(31)) -#define LP_IO_CLK_EN_M (LP_IO_CLK_EN_V << LP_IO_CLK_EN_S) -#define LP_IO_CLK_EN_V 0x00000001U -#define LP_IO_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_io_struct.h b/components/soc/esp32p4/include/soc/lp_io_struct.h deleted file mode 100644 index 97404851bb..0000000000 --- a/components/soc/esp32p4/include/soc/lp_io_struct.h +++ /dev/null @@ -1,362 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of out_data register - * need des - */ -typedef union { - struct { - /** out_data : R/W/WTC; bitpos: [7:0]; default: 0; - * set lp gpio output data - */ - uint32_t out_data:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_out_data_reg_t; - -/** Type of out_data_w1ts register - * need des - */ -typedef union { - struct { - /** out_data_w1ts : WT; bitpos: [7:0]; default: 0; - * set one time output data - */ - uint32_t out_data_w1ts:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_out_data_w1ts_reg_t; - -/** Type of out_data_w1tc register - * need des - */ -typedef union { - struct { - /** out_data_w1tc : WT; bitpos: [7:0]; default: 0; - * clear one time output data - */ - uint32_t out_data_w1tc:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_out_data_w1tc_reg_t; - -/** Type of out_enable register - * need des - */ -typedef union { - struct { - /** enable : R/W/WTC; bitpos: [7:0]; default: 0; - * set lp gpio output data - */ - uint32_t enable:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_out_enable_reg_t; - -/** Type of out_enable_w1ts register - * need des - */ -typedef union { - struct { - /** enable_w1ts : WT; bitpos: [7:0]; default: 0; - * set one time output data - */ - uint32_t enable_w1ts:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_out_enable_w1ts_reg_t; - -/** Type of out_enable_w1tc register - * need des - */ -typedef union { - struct { - /** enable_w1tc : WT; bitpos: [7:0]; default: 0; - * clear one time output data - */ - uint32_t enable_w1tc:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_out_enable_w1tc_reg_t; - -/** Type of status register - * need des - */ -typedef union { - struct { - /** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0; - * set lp gpio output data - */ - uint32_t status_interrupt:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_status_reg_t; - -/** Type of status_w1ts register - * need des - */ -typedef union { - struct { - /** status_w1ts : WT; bitpos: [7:0]; default: 0; - * set one time output data - */ - uint32_t status_w1ts:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_status_w1ts_reg_t; - -/** Type of status_w1tc register - * need des - */ -typedef union { - struct { - /** status_w1tc : WT; bitpos: [7:0]; default: 0; - * clear one time output data - */ - uint32_t status_w1tc:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_status_w1tc_reg_t; - -/** Type of in register - * need des - */ -typedef union { - struct { - /** in_data_next : RO; bitpos: [7:0]; default: 0; - * need des - */ - uint32_t in_data_next:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_in_reg_t; - -/** Type of pin register - * need des - */ -typedef union { - struct { - /** sync_bypass : R/W; bitpos: [1:0]; default: 0; - * need des - */ - uint32_t sync_bypass:2; - /** pad_driver : R/W; bitpos: [2]; default: 0; - * need des - */ - uint32_t pad_driver:1; - /** edge_wakeup_clr : WT; bitpos: [3]; default: 0; - * need des - */ - uint32_t edge_wakeup_clr:1; - uint32_t reserved_4:3; - /** int_type : R/W; bitpos: [9:7]; default: 0; - * need des - */ - uint32_t int_type:3; - /** wakeup_enable : R/W; bitpos: [10]; default: 0; - * need des - */ - uint32_t wakeup_enable:1; - /** filter_en : R/W; bitpos: [11]; default: 0; - * need des - */ - uint32_t filter_en:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} lp_io_pin_reg_t; - -/** Type of gpio register - * need des - */ -typedef union { - struct { - /** mcu_oe : R/W; bitpos: [0]; default: 0; - * need des - */ - uint32_t mcu_oe:1; - /** slp_sel : R/W; bitpos: [1]; default: 0; - * need des - */ - uint32_t slp_sel:1; - /** mcu_wpd : R/W; bitpos: [2]; default: 0; - * need des - */ - uint32_t mcu_wpd:1; - /** mcu_wpu : R/W; bitpos: [3]; default: 0; - * need des - */ - uint32_t mcu_wpu:1; - /** mcu_ie : R/W; bitpos: [4]; default: 0; - * need des - */ - uint32_t mcu_ie:1; - /** mcu_drv : R/W; bitpos: [6:5]; default: 0; - * need des - */ - uint32_t mcu_drv:2; - /** fun_wpd : R/W; bitpos: [7]; default: 0; - * need des - */ - uint32_t fun_wpd:1; - /** fun_wpu : R/W; bitpos: [8]; default: 0; - * need des - */ - uint32_t fun_wpu:1; - /** fun_ie : R/W; bitpos: [9]; default: 0; - * need des - */ - uint32_t fun_ie:1; - /** fun_drv : R/W; bitpos: [11:10]; default: 0; - * need des - */ - uint32_t fun_drv:2; - /** mcu_sel : R/W; bitpos: [14:12]; default: 0; - * need des - */ - uint32_t mcu_sel:3; - uint32_t reserved_15:17; - }; - uint32_t val; -} lp_io_gpio_reg_t; - -/** Type of status_interrupt register - * need des - */ -typedef union { - struct { - /** status_interrupt_next : RO; bitpos: [7:0]; default: 0; - * need des - */ - uint32_t status_interrupt_next:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_io_status_interrupt_reg_t; - -/** Type of debug_sel0 register - * need des - */ -typedef union { - struct { - /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; - * need des - */ - uint32_t debug_sel0:7; - /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; - * need des - */ - uint32_t debug_sel1:7; - /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; - * need des - */ - uint32_t debug_sel2:7; - /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; - * need des - */ - uint32_t debug_sel3:7; - uint32_t reserved_28:4; - }; - uint32_t val; -} lp_io_debug_sel0_reg_t; - -/** Type of debug_sel1 register - * need des - */ -typedef union { - struct { - /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; - * need des - */ - uint32_t debug_sel4:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} lp_io_debug_sel1_reg_t; - -/** Type of lpi2c register - * need des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1; - * need des - */ - uint32_t lp_i2c_sda_ie:1; - /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1; - * need des - */ - uint32_t lp_i2c_scl_ie:1; - }; - uint32_t val; -} lp_io_lpi2c_reg_t; - -/** Type of date register - * need des - */ -typedef union { - struct { - /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032; - * need des - */ - uint32_t lp_io_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} lp_io_date_reg_t; - - -typedef struct lp_io_dev_t { - volatile lp_io_out_data_reg_t out_data; - volatile lp_io_out_data_w1ts_reg_t out_data_w1ts; - volatile lp_io_out_data_w1tc_reg_t out_data_w1tc; - volatile lp_io_out_enable_reg_t out_enable; - volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts; - volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc; - volatile lp_io_status_reg_t status; - volatile lp_io_status_w1ts_reg_t status_w1ts; - volatile lp_io_status_w1tc_reg_t status_w1tc; - volatile lp_io_in_reg_t in; - volatile lp_io_pin_reg_t pin[8]; - volatile lp_io_gpio_reg_t gpio[8]; - volatile lp_io_status_interrupt_reg_t status_interrupt; - volatile lp_io_debug_sel0_reg_t debug_sel0; - volatile lp_io_debug_sel1_reg_t debug_sel1; - volatile lp_io_lpi2c_reg_t lpi2c; - uint32_t reserved_078[225]; - volatile lp_io_date_reg_t date; -} lp_io_dev_t; - -extern lp_io_dev_t LP_IO; - -#ifndef __cplusplus -_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_iomux_struct.h b/components/soc/esp32p4/include/soc/lp_iomux_struct.h index 5d19cd4a0e..c389b7e4fa 100644 --- a/components/soc/esp32p4/include/soc/lp_iomux_struct.h +++ b/components/soc/esp32p4/include/soc/lp_iomux_struct.h @@ -926,7 +926,7 @@ typedef union { } lp_iomux_lp_pad_hys_reg_t; -typedef struct { +typedef struct lp_iomux_dev_t { volatile lp_iomux_clk_en_reg_t clk_en; volatile lp_iomux_ver_date_reg_t ver_date; volatile lp_iomux_pad0_reg_t pad0; diff --git a/components/soc/esp32p4/include/soc/lp_sys_reg.h b/components/soc/esp32p4/include/soc/lp_sys_reg.h deleted file mode 100644 index 5df8429220..0000000000 --- a/components/soc/esp32p4/include/soc/lp_sys_reg.h +++ /dev/null @@ -1,1349 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_SYSTEM_REG_LP_SYS_VER_DATE_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_SYS_VER_DATE_REG (DR_REG_LP_SYS_BASE + 0x0) -/** LP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165961; - * need_des - */ -#define LP_SYSTEM_REG_VER_DATE 0xFFFFFFFFU -#define LP_SYSTEM_REG_VER_DATE_M (LP_SYSTEM_REG_VER_DATE_V << LP_SYSTEM_REG_VER_DATE_S) -#define LP_SYSTEM_REG_VER_DATE_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_VER_DATE_S 0 - -/** LP_SYSTEM_REG_CLK_SEL_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_CLK_SEL_CTRL_REG (DR_REG_LP_SYS_BASE + 0x4) -/** LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK (BIT(16)) -#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_M (LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V << LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S) -#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V 0x00000001U -#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S 16 -/** LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL : R/W; bitpos: [17]; default: 0; - * reserved - */ -#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL (BIT(17)) -#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_M (LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V << LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S) -#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V 0x00000001U -#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S 17 - -/** LP_SYSTEM_REG_SYS_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_SYS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x8) -/** LP_SYSTEM_REG_LP_CORE_DISABLE : R/W; bitpos: [0]; default: 0; - * lp cpu disable - */ -#define LP_SYSTEM_REG_LP_CORE_DISABLE (BIT(0)) -#define LP_SYSTEM_REG_LP_CORE_DISABLE_M (LP_SYSTEM_REG_LP_CORE_DISABLE_V << LP_SYSTEM_REG_LP_CORE_DISABLE_S) -#define LP_SYSTEM_REG_LP_CORE_DISABLE_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_DISABLE_S 0 -/** LP_SYSTEM_REG_SYS_SW_RST : WT; bitpos: [1]; default: 0; - * digital system software reset bit - */ -#define LP_SYSTEM_REG_SYS_SW_RST (BIT(1)) -#define LP_SYSTEM_REG_SYS_SW_RST_M (LP_SYSTEM_REG_SYS_SW_RST_V << LP_SYSTEM_REG_SYS_SW_RST_S) -#define LP_SYSTEM_REG_SYS_SW_RST_V 0x00000001U -#define LP_SYSTEM_REG_SYS_SW_RST_S 1 -/** LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [2]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT (BIT(2)) -#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_M (LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V << LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S) -#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V 0x00000001U -#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S 2 -/** LP_SYSTEM_REG_DIG_FIB : R/W; bitpos: [10:3]; default: 255; - * need_des - */ -#define LP_SYSTEM_REG_DIG_FIB 0x000000FFU -#define LP_SYSTEM_REG_DIG_FIB_M (LP_SYSTEM_REG_DIG_FIB_V << LP_SYSTEM_REG_DIG_FIB_S) -#define LP_SYSTEM_REG_DIG_FIB_V 0x000000FFU -#define LP_SYSTEM_REG_DIG_FIB_S 3 -/** LP_SYSTEM_REG_IO_MUX_RESET_DISABLE : R/W; bitpos: [11]; default: 0; - * reset disable bit for LP IOMUX - */ -#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE (BIT(11)) -#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_M (LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V << LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S) -#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V 0x00000001U -#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S 11 -/** LP_SYSTEM_REG_ANA_FIB : RO; bitpos: [20:14]; default: 127; - * need_des - */ -#define LP_SYSTEM_REG_ANA_FIB 0x0000007FU -#define LP_SYSTEM_REG_ANA_FIB_M (LP_SYSTEM_REG_ANA_FIB_V << LP_SYSTEM_REG_ANA_FIB_S) -#define LP_SYSTEM_REG_ANA_FIB_V 0x0000007FU -#define LP_SYSTEM_REG_ANA_FIB_S 14 -/** LP_SYSTEM_REG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255; - * need_des - */ -#define LP_SYSTEM_REG_LP_FIB_SEL 0x000000FFU -#define LP_SYSTEM_REG_LP_FIB_SEL_M (LP_SYSTEM_REG_LP_FIB_SEL_V << LP_SYSTEM_REG_LP_FIB_SEL_S) -#define LP_SYSTEM_REG_LP_FIB_SEL_V 0x000000FFU -#define LP_SYSTEM_REG_LP_FIB_SEL_S 21 -/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [29]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR (BIT(29)) -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_M (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S) -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S 29 -/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG (BIT(30)) -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_M (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S) -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S 30 -/** LP_SYSTEM_REG_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0; - * 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from - * hp_core1 - */ -#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL (BIT(31)) -#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_M (LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V << LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S) -#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V 0x00000001U -#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S 31 - -/** LP_SYSTEM_REG_LP_CLK_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0xc) -/** LP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * need_des - */ -#define LP_SYSTEM_REG_CLK_EN (BIT(0)) -#define LP_SYSTEM_REG_CLK_EN_M (LP_SYSTEM_REG_CLK_EN_V << LP_SYSTEM_REG_CLK_EN_S) -#define LP_SYSTEM_REG_CLK_EN_V 0x00000001U -#define LP_SYSTEM_REG_CLK_EN_S 0 -/** LP_SYSTEM_REG_LP_FOSC_HP_CKEN : R/W; bitpos: [14]; default: 1; - * reserved - */ -#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN (BIT(14)) -#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_M (LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V << LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S) -#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V 0x00000001U -#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S 14 - -/** LP_SYSTEM_REG_LP_RST_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_RST_CTRL_REG (DR_REG_LP_SYS_BASE + 0x10) -/** LP_SYSTEM_REG_ANA_RST_BYPASS : R/W; bitpos: [0]; default: 1; - * analog source reset bypass : wdt,brown out,super wdt,glitch - */ -#define LP_SYSTEM_REG_ANA_RST_BYPASS (BIT(0)) -#define LP_SYSTEM_REG_ANA_RST_BYPASS_M (LP_SYSTEM_REG_ANA_RST_BYPASS_V << LP_SYSTEM_REG_ANA_RST_BYPASS_S) -#define LP_SYSTEM_REG_ANA_RST_BYPASS_V 0x00000001U -#define LP_SYSTEM_REG_ANA_RST_BYPASS_S 0 -/** LP_SYSTEM_REG_SYS_RST_BYPASS : R/W; bitpos: [1]; default: 1; - * system source reset bypass : software reset,hp wdt,lp wdt,efuse - */ -#define LP_SYSTEM_REG_SYS_RST_BYPASS (BIT(1)) -#define LP_SYSTEM_REG_SYS_RST_BYPASS_M (LP_SYSTEM_REG_SYS_RST_BYPASS_V << LP_SYSTEM_REG_SYS_RST_BYPASS_S) -#define LP_SYSTEM_REG_SYS_RST_BYPASS_V 0x00000001U -#define LP_SYSTEM_REG_SYS_RST_BYPASS_S 1 -/** LP_SYSTEM_REG_EFUSE_FORCE_NORST : R/W; bitpos: [2]; default: 0; - * efuse force no reset control - */ -#define LP_SYSTEM_REG_EFUSE_FORCE_NORST (BIT(2)) -#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_M (LP_SYSTEM_REG_EFUSE_FORCE_NORST_V << LP_SYSTEM_REG_EFUSE_FORCE_NORST_S) -#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_V 0x00000001U -#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_S 2 - -/** LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG (DR_REG_LP_SYS_BASE + 0x18) -/** LP_SYSTEM_REG_LP_CPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 1343225856; - * need_des - */ -#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_M (LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V << LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S) -#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S 0 - -/** LP_SYSTEM_REG_EXT_WAKEUP1_REG register - * need_des - */ -#define LP_SYSTEM_REG_EXT_WAKEUP1_REG (DR_REG_LP_SYS_BASE + 0x1c) -/** LP_SYSTEM_REG_EXT_WAKEUP1_SEL : R/W; bitpos: [15:0]; default: 0; - * Bitmap to select RTC pads for ext wakeup1 - */ -#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL 0x0000FFFFU -#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_M (LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V << LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S) -#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V 0x0000FFFFU -#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S 0 -/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR : WT; bitpos: [16]; default: 0; - * clear ext wakeup1 status - */ -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR (BIT(16)) -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_M (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S) -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V 0x00000001U -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S 16 - -/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG register - * need_des - */ -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG (DR_REG_LP_SYS_BASE + 0x20) -/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS : RO; bitpos: [15:0]; default: 0; - * ext wakeup1 status - */ -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS 0x0000FFFFU -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_M (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S) -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V 0x0000FFFFU -#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S 0 - -/** LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG (DR_REG_LP_SYS_BASE + 0x24) -/** LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON (BIT(5)) -#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_M (LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S) -#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V 0x00000001U -#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S 5 -/** LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON (BIT(7)) -#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_M (LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S) -#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V 0x00000001U -#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S 7 - -/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG register - * need_des - */ -#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG (DR_REG_LP_SYS_BASE + 0x28) -/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP 0xFFFFFFFFU -#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_M (LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V << LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S) -#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S 0 - -/** LP_SYSTEM_REG_LP_STORE0_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE0_REG (DR_REG_LP_SYS_BASE + 0x2c) -/** LP_SYSTEM_REG_LP_SCRATCH0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH0 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH0_M (LP_SYSTEM_REG_LP_SCRATCH0_V << LP_SYSTEM_REG_LP_SCRATCH0_S) -#define LP_SYSTEM_REG_LP_SCRATCH0_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH0_S 0 - -/** LP_SYSTEM_REG_LP_STORE1_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE1_REG (DR_REG_LP_SYS_BASE + 0x30) -/** LP_SYSTEM_REG_LP_SCRATCH1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH1 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH1_M (LP_SYSTEM_REG_LP_SCRATCH1_V << LP_SYSTEM_REG_LP_SCRATCH1_S) -#define LP_SYSTEM_REG_LP_SCRATCH1_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH1_S 0 - -/** LP_SYSTEM_REG_LP_STORE2_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE2_REG (DR_REG_LP_SYS_BASE + 0x34) -/** LP_SYSTEM_REG_LP_SCRATCH2 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH2 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH2_M (LP_SYSTEM_REG_LP_SCRATCH2_V << LP_SYSTEM_REG_LP_SCRATCH2_S) -#define LP_SYSTEM_REG_LP_SCRATCH2_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH2_S 0 - -/** LP_SYSTEM_REG_LP_STORE3_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE3_REG (DR_REG_LP_SYS_BASE + 0x38) -/** LP_SYSTEM_REG_LP_SCRATCH3 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH3 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH3_M (LP_SYSTEM_REG_LP_SCRATCH3_V << LP_SYSTEM_REG_LP_SCRATCH3_S) -#define LP_SYSTEM_REG_LP_SCRATCH3_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH3_S 0 - -/** LP_SYSTEM_REG_LP_STORE4_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE4_REG (DR_REG_LP_SYS_BASE + 0x3c) -/** LP_SYSTEM_REG_LP_SCRATCH4 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH4 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH4_M (LP_SYSTEM_REG_LP_SCRATCH4_V << LP_SYSTEM_REG_LP_SCRATCH4_S) -#define LP_SYSTEM_REG_LP_SCRATCH4_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH4_S 0 - -/** LP_SYSTEM_REG_LP_STORE5_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE5_REG (DR_REG_LP_SYS_BASE + 0x40) -/** LP_SYSTEM_REG_LP_SCRATCH5 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH5 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH5_M (LP_SYSTEM_REG_LP_SCRATCH5_V << LP_SYSTEM_REG_LP_SCRATCH5_S) -#define LP_SYSTEM_REG_LP_SCRATCH5_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH5_S 0 - -/** LP_SYSTEM_REG_LP_STORE6_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE6_REG (DR_REG_LP_SYS_BASE + 0x44) -/** LP_SYSTEM_REG_LP_SCRATCH6 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH6 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH6_M (LP_SYSTEM_REG_LP_SCRATCH6_V << LP_SYSTEM_REG_LP_SCRATCH6_S) -#define LP_SYSTEM_REG_LP_SCRATCH6_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH6_S 0 - -/** LP_SYSTEM_REG_LP_STORE7_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE7_REG (DR_REG_LP_SYS_BASE + 0x48) -/** LP_SYSTEM_REG_LP_SCRATCH7 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH7 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH7_M (LP_SYSTEM_REG_LP_SCRATCH7_V << LP_SYSTEM_REG_LP_SCRATCH7_S) -#define LP_SYSTEM_REG_LP_SCRATCH7_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH7_S 0 - -/** LP_SYSTEM_REG_LP_STORE8_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE8_REG (DR_REG_LP_SYS_BASE + 0x4c) -/** LP_SYSTEM_REG_LP_SCRATCH8 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH8 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH8_M (LP_SYSTEM_REG_LP_SCRATCH8_V << LP_SYSTEM_REG_LP_SCRATCH8_S) -#define LP_SYSTEM_REG_LP_SCRATCH8_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH8_S 0 - -/** LP_SYSTEM_REG_LP_STORE9_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE9_REG (DR_REG_LP_SYS_BASE + 0x50) -/** LP_SYSTEM_REG_LP_SCRATCH9 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH9 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH9_M (LP_SYSTEM_REG_LP_SCRATCH9_V << LP_SYSTEM_REG_LP_SCRATCH9_S) -#define LP_SYSTEM_REG_LP_SCRATCH9_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH9_S 0 - -/** LP_SYSTEM_REG_LP_STORE10_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE10_REG (DR_REG_LP_SYS_BASE + 0x54) -/** LP_SYSTEM_REG_LP_SCRATCH10 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH10 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH10_M (LP_SYSTEM_REG_LP_SCRATCH10_V << LP_SYSTEM_REG_LP_SCRATCH10_S) -#define LP_SYSTEM_REG_LP_SCRATCH10_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH10_S 0 - -/** LP_SYSTEM_REG_LP_STORE11_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE11_REG (DR_REG_LP_SYS_BASE + 0x58) -/** LP_SYSTEM_REG_LP_SCRATCH11 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH11 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH11_M (LP_SYSTEM_REG_LP_SCRATCH11_V << LP_SYSTEM_REG_LP_SCRATCH11_S) -#define LP_SYSTEM_REG_LP_SCRATCH11_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH11_S 0 - -/** LP_SYSTEM_REG_LP_STORE12_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE12_REG (DR_REG_LP_SYS_BASE + 0x5c) -/** LP_SYSTEM_REG_LP_SCRATCH12 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH12 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH12_M (LP_SYSTEM_REG_LP_SCRATCH12_V << LP_SYSTEM_REG_LP_SCRATCH12_S) -#define LP_SYSTEM_REG_LP_SCRATCH12_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH12_S 0 - -/** LP_SYSTEM_REG_LP_STORE13_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE13_REG (DR_REG_LP_SYS_BASE + 0x60) -/** LP_SYSTEM_REG_LP_SCRATCH13 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH13 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH13_M (LP_SYSTEM_REG_LP_SCRATCH13_V << LP_SYSTEM_REG_LP_SCRATCH13_S) -#define LP_SYSTEM_REG_LP_SCRATCH13_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH13_S 0 - -/** LP_SYSTEM_REG_LP_STORE14_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE14_REG (DR_REG_LP_SYS_BASE + 0x64) -/** LP_SYSTEM_REG_LP_SCRATCH14 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH14 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH14_M (LP_SYSTEM_REG_LP_SCRATCH14_V << LP_SYSTEM_REG_LP_SCRATCH14_S) -#define LP_SYSTEM_REG_LP_SCRATCH14_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH14_S 0 - -/** LP_SYSTEM_REG_LP_STORE15_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_STORE15_REG (DR_REG_LP_SYS_BASE + 0x68) -/** LP_SYSTEM_REG_LP_SCRATCH15 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_SCRATCH15 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH15_M (LP_SYSTEM_REG_LP_SCRATCH15_V << LP_SYSTEM_REG_LP_SCRATCH15_S) -#define LP_SYSTEM_REG_LP_SCRATCH15_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_SCRATCH15_S 0 - -/** LP_SYSTEM_REG_LP_PROBEA_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_PROBEA_CTRL_REG (DR_REG_LP_SYS_BASE + 0x6c) -/** LP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_A_MOD_SEL 0x0000FFFFU -#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_M (LP_SYSTEM_REG_PROBE_A_MOD_SEL_V << LP_SYSTEM_REG_PROBE_A_MOD_SEL_S) -#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_V 0x0000FFFFU -#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_S 0 -/** LP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_A_TOP_SEL 0x000000FFU -#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_M (LP_SYSTEM_REG_PROBE_A_TOP_SEL_V << LP_SYSTEM_REG_PROBE_A_TOP_SEL_S) -#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_V 0x000000FFU -#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_S 16 -/** LP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_L_SEL 0x00000003U -#define LP_SYSTEM_REG_PROBE_L_SEL_M (LP_SYSTEM_REG_PROBE_L_SEL_V << LP_SYSTEM_REG_PROBE_L_SEL_S) -#define LP_SYSTEM_REG_PROBE_L_SEL_V 0x00000003U -#define LP_SYSTEM_REG_PROBE_L_SEL_S 24 -/** LP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_H_SEL 0x00000003U -#define LP_SYSTEM_REG_PROBE_H_SEL_M (LP_SYSTEM_REG_PROBE_H_SEL_V << LP_SYSTEM_REG_PROBE_H_SEL_S) -#define LP_SYSTEM_REG_PROBE_H_SEL_V 0x00000003U -#define LP_SYSTEM_REG_PROBE_H_SEL_S 26 -/** LP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_GLOBAL_EN (BIT(28)) -#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_M (LP_SYSTEM_REG_PROBE_GLOBAL_EN_V << LP_SYSTEM_REG_PROBE_GLOBAL_EN_S) -#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_V 0x00000001U -#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_S 28 - -/** LP_SYSTEM_REG_LP_PROBEB_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_PROBEB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x70) -/** LP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_B_MOD_SEL 0x0000FFFFU -#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_M (LP_SYSTEM_REG_PROBE_B_MOD_SEL_V << LP_SYSTEM_REG_PROBE_B_MOD_SEL_S) -#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_V 0x0000FFFFU -#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_S 0 -/** LP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_B_TOP_SEL 0x000000FFU -#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_M (LP_SYSTEM_REG_PROBE_B_TOP_SEL_V << LP_SYSTEM_REG_PROBE_B_TOP_SEL_S) -#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_V 0x000000FFU -#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_S 16 -/** LP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_B_EN (BIT(24)) -#define LP_SYSTEM_REG_PROBE_B_EN_M (LP_SYSTEM_REG_PROBE_B_EN_V << LP_SYSTEM_REG_PROBE_B_EN_S) -#define LP_SYSTEM_REG_PROBE_B_EN_V 0x00000001U -#define LP_SYSTEM_REG_PROBE_B_EN_S 24 - -/** LP_SYSTEM_REG_LP_PROBE_OUT_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_PROBE_OUT_REG (DR_REG_LP_SYS_BASE + 0x74) -/** LP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PROBE_TOP_OUT 0xFFFFFFFFU -#define LP_SYSTEM_REG_PROBE_TOP_OUT_M (LP_SYSTEM_REG_PROBE_TOP_OUT_V << LP_SYSTEM_REG_PROBE_TOP_OUT_S) -#define LP_SYSTEM_REG_PROBE_TOP_OUT_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_PROBE_TOP_OUT_S 0 - -/** LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG register - * need_des - */ -#define LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG (DR_REG_LP_SYS_BASE + 0x9c) -/** LP_SYSTEM_REG_F2S_APB_POSTW_EN : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define LP_SYSTEM_REG_F2S_APB_POSTW_EN (BIT(0)) -#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_M (LP_SYSTEM_REG_F2S_APB_POSTW_EN_V << LP_SYSTEM_REG_F2S_APB_POSTW_EN_S) -#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_V 0x00000001U -#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_S 0 - -/** LP_SYSTEM_REG_USB_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_USB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x100) -/** LP_SYSTEM_REG_SW_HW_USB_PHY_SEL : R/W; bitpos: [0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL (BIT(0)) -#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_M (LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S) -#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V 0x00000001U -#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S 0 -/** LP_SYSTEM_REG_SW_USB_PHY_SEL : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_SW_USB_PHY_SEL (BIT(1)) -#define LP_SYSTEM_REG_SW_USB_PHY_SEL_M (LP_SYSTEM_REG_SW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_USB_PHY_SEL_S) -#define LP_SYSTEM_REG_SW_USB_PHY_SEL_V 0x00000001U -#define LP_SYSTEM_REG_SW_USB_PHY_SEL_S 1 -/** LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR : WT; bitpos: [2]; default: 0; - * clear usb wakeup to PMU. - */ -#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR (BIT(2)) -#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_M (LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V << LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S) -#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V 0x00000001U -#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S 2 -/** LP_SYSTEM_REG_USBOTG20_IN_SUSPEND : R/W; bitpos: [3]; default: 0; - * indicate usb otg2.0 is in suspend state. - */ -#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND (BIT(3)) -#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_M (LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V << LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S) -#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V 0x00000001U -#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S 3 - -/** LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG register - * need_des - */ -#define LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG (DR_REG_LP_SYS_BASE + 0x10c) -/** LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP : R/W; bitpos: [7:0]; default: 255; - * Set 1 to power up pad group - */ -#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP 0x000000FFU -#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_M (LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V << LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S) -#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V 0x000000FFU -#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S 0 - -/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x110) -/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN (BIT(0)) -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S) -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V 0x00000001U -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S 0 -/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT (BIT(1)) -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S) -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V 0x00000001U -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S 1 - -/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x114) -/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S) -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S 0 - -/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x118) -/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S) -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S 0 - -/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x11c) -/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN (BIT(0)) -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S) -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V 0x00000001U -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S 0 -/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT (BIT(1)) -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S) -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V 0x00000001U -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S 1 - -/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x120) -/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S) -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S 0 - -/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x124) -/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S) -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S 0 - -/** LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0x130) -/** LP_SYSTEM_REG_CPU_CLK_EN : R/W; bitpos: [0]; default: 1; - * clock gate enable for hp cpu root 400M clk - */ -#define LP_SYSTEM_REG_CPU_CLK_EN (BIT(0)) -#define LP_SYSTEM_REG_CPU_CLK_EN_M (LP_SYSTEM_REG_CPU_CLK_EN_V << LP_SYSTEM_REG_CPU_CLK_EN_S) -#define LP_SYSTEM_REG_CPU_CLK_EN_V 0x00000001U -#define LP_SYSTEM_REG_CPU_CLK_EN_S 0 -/** LP_SYSTEM_REG_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; - * clock gate enable for hp sys root 480M clk - */ -#define LP_SYSTEM_REG_SYS_CLK_EN (BIT(1)) -#define LP_SYSTEM_REG_SYS_CLK_EN_M (LP_SYSTEM_REG_SYS_CLK_EN_V << LP_SYSTEM_REG_SYS_CLK_EN_S) -#define LP_SYSTEM_REG_SYS_CLK_EN_V 0x00000001U -#define LP_SYSTEM_REG_SYS_CLK_EN_S 1 - -/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x138) -/** LP_SYSTEM_REG_PMU_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW 0xFFFFFFFFU -#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_M (LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V << LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S) -#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S 0 - -/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x13c) -/** LP_SYSTEM_REG_PMU_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ -#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH 0xFFFFFFFFU -#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_M (LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V << LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S) -#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S 0 - -/** LP_SYSTEM_REG_PAD_COMP0_REG register - * need_des - */ -#define LP_SYSTEM_REG_PAD_COMP0_REG (DR_REG_LP_SYS_BASE + 0x148) -/** LP_SYSTEM_REG_DREF_COMP0 : R/W; bitpos: [2:0]; default: 0; - * pad comp dref - */ -#define LP_SYSTEM_REG_DREF_COMP0 0x00000007U -#define LP_SYSTEM_REG_DREF_COMP0_M (LP_SYSTEM_REG_DREF_COMP0_V << LP_SYSTEM_REG_DREF_COMP0_S) -#define LP_SYSTEM_REG_DREF_COMP0_V 0x00000007U -#define LP_SYSTEM_REG_DREF_COMP0_S 0 -/** LP_SYSTEM_REG_MODE_COMP0 : R/W; bitpos: [3]; default: 0; - * pad comp mode - */ -#define LP_SYSTEM_REG_MODE_COMP0 (BIT(3)) -#define LP_SYSTEM_REG_MODE_COMP0_M (LP_SYSTEM_REG_MODE_COMP0_V << LP_SYSTEM_REG_MODE_COMP0_S) -#define LP_SYSTEM_REG_MODE_COMP0_V 0x00000001U -#define LP_SYSTEM_REG_MODE_COMP0_S 3 -/** LP_SYSTEM_REG_XPD_COMP0 : R/W; bitpos: [4]; default: 0; - * pad comp xpd - */ -#define LP_SYSTEM_REG_XPD_COMP0 (BIT(4)) -#define LP_SYSTEM_REG_XPD_COMP0_M (LP_SYSTEM_REG_XPD_COMP0_V << LP_SYSTEM_REG_XPD_COMP0_S) -#define LP_SYSTEM_REG_XPD_COMP0_V 0x00000001U -#define LP_SYSTEM_REG_XPD_COMP0_S 4 - -/** LP_SYSTEM_REG_PAD_COMP1_REG register - * need_des - */ -#define LP_SYSTEM_REG_PAD_COMP1_REG (DR_REG_LP_SYS_BASE + 0x14c) -/** LP_SYSTEM_REG_DREF_COMP1 : R/W; bitpos: [2:0]; default: 0; - * pad comp dref - */ -#define LP_SYSTEM_REG_DREF_COMP1 0x00000007U -#define LP_SYSTEM_REG_DREF_COMP1_M (LP_SYSTEM_REG_DREF_COMP1_V << LP_SYSTEM_REG_DREF_COMP1_S) -#define LP_SYSTEM_REG_DREF_COMP1_V 0x00000007U -#define LP_SYSTEM_REG_DREF_COMP1_S 0 -/** LP_SYSTEM_REG_MODE_COMP1 : R/W; bitpos: [3]; default: 0; - * pad comp mode - */ -#define LP_SYSTEM_REG_MODE_COMP1 (BIT(3)) -#define LP_SYSTEM_REG_MODE_COMP1_M (LP_SYSTEM_REG_MODE_COMP1_V << LP_SYSTEM_REG_MODE_COMP1_S) -#define LP_SYSTEM_REG_MODE_COMP1_V 0x00000001U -#define LP_SYSTEM_REG_MODE_COMP1_S 3 -/** LP_SYSTEM_REG_XPD_COMP1 : R/W; bitpos: [4]; default: 0; - * pad comp xpd - */ -#define LP_SYSTEM_REG_XPD_COMP1 (BIT(4)) -#define LP_SYSTEM_REG_XPD_COMP1_M (LP_SYSTEM_REG_XPD_COMP1_V << LP_SYSTEM_REG_XPD_COMP1_S) -#define LP_SYSTEM_REG_XPD_COMP1_V 0x00000001U -#define LP_SYSTEM_REG_XPD_COMP1_S 4 - -/** LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG register - * need_des - */ -#define LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG (DR_REG_LP_SYS_BASE + 0x154) -/** LP_SYSTEM_REG_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10; - * need_des - */ -#define LP_SYSTEM_REG_BURST_LIMIT_AON 0x0000001FU -#define LP_SYSTEM_REG_BURST_LIMIT_AON_M (LP_SYSTEM_REG_BURST_LIMIT_AON_V << LP_SYSTEM_REG_BURST_LIMIT_AON_S) -#define LP_SYSTEM_REG_BURST_LIMIT_AON_V 0x0000001FU -#define LP_SYSTEM_REG_BURST_LIMIT_AON_S 0 -/** LP_SYSTEM_REG_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10; - * need_des - */ -#define LP_SYSTEM_REG_READ_INTERVAL_AON 0x0000007FU -#define LP_SYSTEM_REG_READ_INTERVAL_AON_M (LP_SYSTEM_REG_READ_INTERVAL_AON_V << LP_SYSTEM_REG_READ_INTERVAL_AON_S) -#define LP_SYSTEM_REG_READ_INTERVAL_AON_V 0x0000007FU -#define LP_SYSTEM_REG_READ_INTERVAL_AON_S 5 -/** LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [21:12]; default: 100; - * need_des - */ -#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON 0x000003FFU -#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_M (LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S) -#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V 0x000003FFU -#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S 12 -/** LP_SYSTEM_REG_LINK_TOUT_THRES_AON : R/W; bitpos: [31:22]; default: 100; - * need_des - */ -#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON 0x000003FFU -#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_M (LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S) -#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V 0x000003FFU -#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S 22 - -/** LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG register - * need_des - */ -#define LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG (DR_REG_LP_SYS_BASE + 0x158) -/** LP_SYSTEM_REG_AON_BYPASS : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_AON_BYPASS (BIT(31)) -#define LP_SYSTEM_REG_AON_BYPASS_M (LP_SYSTEM_REG_AON_BYPASS_V << LP_SYSTEM_REG_AON_BYPASS_S) -#define LP_SYSTEM_REG_AON_BYPASS_V 0x00000001U -#define LP_SYSTEM_REG_AON_BYPASS_S 31 - -/** LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG register - * need_des - */ -#define LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG (DR_REG_LP_SYS_BASE + 0x15c) -/** LP_SYSTEM_REG_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LINK_ADDR_AON 0xFFFFFFFFU -#define LP_SYSTEM_REG_LINK_ADDR_AON_M (LP_SYSTEM_REG_LINK_ADDR_AON_V << LP_SYSTEM_REG_LINK_ADDR_AON_S) -#define LP_SYSTEM_REG_LINK_ADDR_AON_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LINK_ADDR_AON_S 0 - -/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG register - * need_des - */ -#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG (DR_REG_LP_SYS_BASE + 0x164) -/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 0xFFFFFFFFU -#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_M (LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V << LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S) -#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S 0 - -/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x168) -/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_M (LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S 0 - -/** LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x16c) -/** LP_SYSTEM_REG_LP_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0; - * master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: - * regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha - * tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_ID 0x0000001FU -#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_M (LP_SYSTEM_REG_LP_ADDRHOLE_ID_V << LP_SYSTEM_REG_LP_ADDRHOLE_ID_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_V 0x0000001FU -#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_S 0 -/** LP_SYSTEM_REG_LP_ADDRHOLE_WR : RO; bitpos: [5]; default: 0; - * 1:write trans, 0: read trans. - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_WR (BIT(5)) -#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_M (LP_SYSTEM_REG_LP_ADDRHOLE_WR_V << LP_SYSTEM_REG_LP_ADDRHOLE_WR_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_V 0x00000001U -#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_S 5 -/** LP_SYSTEM_REG_LP_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0; - * 1: illegal address access, 0: access without permission - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE (BIT(6)) -#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_M (LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V 0x00000001U -#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S 6 - -/** LP_SYSTEM_REG_INT_RAW_REG register - * raw interrupt register - */ -#define LP_SYSTEM_REG_INT_RAW_REG (DR_REG_LP_SYS_BASE + 0x170) -/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp - * matrix default slave) - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW (BIT(0)) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V 0x00000001U -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S 0 -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW (BIT(1)) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V 0x00000001U -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S 1 -/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * the raw interrupt status of lp core ahb bus timeout - */ -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW (BIT(2)) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S 2 -/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; - * the raw interrupt status of lp core ibus timeout - */ -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW (BIT(3)) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S 3 -/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; - * the raw interrupt status of lp core dbus timeout - */ -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW (BIT(4)) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S 4 -/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; - * the raw interrupt status of etm task ulp - */ -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW (BIT(5)) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V 0x00000001U -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S 5 -/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; - * the raw interrupt status of slow_clk_tick - */ -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW (BIT(6)) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V 0x00000001U -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S 6 - -/** LP_SYSTEM_REG_INT_ST_REG register - * masked interrupt register - */ -#define LP_SYSTEM_REG_INT_ST_REG (DR_REG_LP_SYS_BASE + 0x174) -/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST : RO; bitpos: [0]; default: 0; - * the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp - * matrix default slave) - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST (BIT(0)) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V 0x00000001U -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S 0 -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0; - * the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST (BIT(1)) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V 0x00000001U -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S 1 -/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0; - * the masked interrupt status of lp core ahb bus timeout - */ -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST (BIT(2)) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S 2 -/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0; - * the masked interrupt status of lp core ibus timeout - */ -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST (BIT(3)) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S 3 -/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0; - * the masked interrupt status of lp core dbus timeout - */ -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST (BIT(4)) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S 4 -/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST : RO; bitpos: [5]; default: 0; - * the masked interrupt status of etm task ulp - */ -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST (BIT(5)) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V 0x00000001U -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S 5 -/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST : RO; bitpos: [6]; default: 0; - * the masked interrupt status of slow_clk_tick - */ -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST (BIT(6)) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V 0x00000001U -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S 6 - -/** LP_SYSTEM_REG_INT_ENA_REG register - * masked interrupt register - */ -#define LP_SYSTEM_REG_INT_ENA_REG (DR_REG_LP_SYS_BASE + 0x178) -/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable lp addrhole int - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA (BIT(0)) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V 0x00000001U -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S 0 -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable idbus addrhole int - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA (BIT(1)) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V 0x00000001U -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S 1 -/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable lp_core_ahb_timeout int - */ -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA (BIT(2)) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S 2 -/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable lp_core_ibus_timeout int - */ -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA (BIT(3)) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S 3 -/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable lp_core_dbus_timeout int - */ -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA (BIT(4)) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S 4 -/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable etm task ulp int - */ -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA (BIT(5)) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V 0x00000001U -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S 5 -/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable slow_clk_tick int - */ -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA (BIT(6)) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V 0x00000001U -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S 6 - -/** LP_SYSTEM_REG_INT_CLR_REG register - * interrupt clear register - */ -#define LP_SYSTEM_REG_INT_CLR_REG (DR_REG_LP_SYS_BASE + 0x17c) -/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR : WT; bitpos: [0]; default: 0; - * write 1 to clear lp addrhole int - */ -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR (BIT(0)) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S) -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V 0x00000001U -#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S 0 -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0; - * write 1 to clear idbus addrhole int - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR (BIT(1)) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V 0x00000001U -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S 1 -/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear lp_core_ahb_timeout int - */ -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR (BIT(2)) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S 2 -/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear lp_core_ibus_timeout int - */ -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR (BIT(3)) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S 3 -/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear lp_core_dbus_timeout int - */ -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR (BIT(4)) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S 4 -/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear etm tasl ulp int - */ -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR (BIT(5)) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S) -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V 0x00000001U -#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S 5 -/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear slow_clk_tick int - */ -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR (BIT(6)) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S) -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V 0x00000001U -#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S 6 - -/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180) -/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; - * need_des - */ -#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL 0xFFFFFFFFU -#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_M (LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S) -#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S 0 - -/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184) -/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; - * need_des - */ -#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_M (LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S) -#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S 0 - -/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x188) -/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112; - * need_des - */ -#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL 0xFFFFFFFFU -#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_M (LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S) -#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S 0 - -/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x18c) -/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112; - * need_des - */ -#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_M (LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S) -#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S 0 - -/** LP_SYSTEM_REG_LP_CPU_DBG_PC_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CPU_DBG_PC_REG (DR_REG_LP_SYS_BASE + 0x190) -/** LP_SYSTEM_REG_LP_CPU_DBG_PC : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_CPU_DBG_PC 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_CPU_DBG_PC_M (LP_SYSTEM_REG_LP_CPU_DBG_PC_V << LP_SYSTEM_REG_LP_CPU_DBG_PC_S) -#define LP_SYSTEM_REG_LP_CPU_DBG_PC_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_CPU_DBG_PC_S 0 - -/** LP_SYSTEM_REG_LP_CPU_EXC_PC_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CPU_EXC_PC_REG (DR_REG_LP_SYS_BASE + 0x194) -/** LP_SYSTEM_REG_LP_CPU_EXC_PC : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_LP_CPU_EXC_PC 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_CPU_EXC_PC_M (LP_SYSTEM_REG_LP_CPU_EXC_PC_V << LP_SYSTEM_REG_LP_CPU_EXC_PC_S) -#define LP_SYSTEM_REG_LP_CPU_EXC_PC_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_LP_CPU_EXC_PC_S 0 - -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG register - * need_des - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x198) -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR 0xFFFFFFFFU -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S 0 - -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG register - * need_des - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x19c) -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID 0x0000001FU -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V 0x0000001FU -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S 0 -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR : RO; bitpos: [5]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR (BIT(5)) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V 0x00000001U -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S 5 -/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0; - * need_des - */ -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE (BIT(6)) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S) -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V 0x00000001U -#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S 6 - -/** LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG register - * need_des - */ -#define LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1a0) -/** LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL : R/W; bitpos: [15:8]; default: 255; - * [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn - * [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn - * [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn - * [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn - * [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst - * [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst - * [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn - * [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn - */ -#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL 0x000000FFU -#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_M (LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S) -#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V 0x000000FFU -#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S 8 -/** LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL : R/W; bitpos: [31:24]; default: 255; - * [31] 1'b1: po_rstn bypass sys_sw_rstn - * [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn - * [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn - * [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn - * [27] 1'b1: po_rstn bypass usb_jtag_chip_rst - * [26] 1'b1: po_rstn bypass usb_uart_chip_rst - * [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn - * [24] 1'b1: po_rstn bypass efuse_err_rstn - */ -#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL 0x000000FFU -#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_M (LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S) -#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V 0x000000FFU -#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S 24 - -/** LP_SYSTEM_REG_RNG_DATA_REG register - * rng data register - */ -#define LP_SYSTEM_REG_RNG_DATA_REG (DR_REG_LP_SYS_BASE + 0x1a4) -/** LP_SYSTEM_REG_RND_DATA : RO; bitpos: [31:0]; default: 0; - * result of rng output - */ -#define LP_SYSTEM_REG_RND_DATA 0xFFFFFFFFU -#define LP_SYSTEM_REG_RND_DATA_M (LP_SYSTEM_REG_RND_DATA_V << LP_SYSTEM_REG_RND_DATA_S) -#define LP_SYSTEM_REG_RND_DATA_V 0xFFFFFFFFU -#define LP_SYSTEM_REG_RND_DATA_S 0 - -/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b0) -/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1; - * set this field to 1 to enable lp core ahb timeout handle - */ -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN (BIT(0)) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S 0 -/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535; - * This field used to set lp core ahb bus timeout threshold - */ -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES 0x0000FFFFU -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S) -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V 0x0000FFFFU -#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S 1 -/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN : R/W; bitpos: [17]; default: 1; - * set this field to 1 to enable lp2hp ahb timeout handle - */ -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN (BIT(17)) -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_M (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S) -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V 0x00000001U -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S 17 -/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES : R/W; bitpos: [22:18]; default: 31; - * This field used to set lp2hp ahb bus timeout threshold - */ -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES 0x0000001FU -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S) -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V 0x0000001FU -#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S 18 - -/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b4) -/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1; - * set this field to 1 to enable lp core ibus timeout handle - */ -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN (BIT(0)) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S 0 -/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535; - * This field used to set lp core ibus timeout threshold - */ -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES 0x0000FFFFU -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S) -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V 0x0000FFFFU -#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S 1 - -/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b8) -/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1; - * set this field to 1 to enable lp core dbus timeout handle - */ -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN (BIT(0)) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V 0x00000001U -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S 0 -/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535; - * This field used to set lp core dbus timeout threshold - */ -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES 0x0000FFFFU -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S) -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V 0x0000FFFFU -#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S 1 - -/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG register - * need_des - */ -#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG (DR_REG_LP_SYS_BASE + 0x1bc) -/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0; - * Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to - * disable ahb err resp. - */ -#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS 0x00000007U -#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_M (LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V << LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S) -#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V 0x00000007U -#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S 0 - -/** LP_SYSTEM_REG_RNG_CFG_REG register - * rng cfg register - */ -#define LP_SYSTEM_REG_RNG_CFG_REG (DR_REG_LP_SYS_BASE + 0x1c0) -/** LP_SYSTEM_REG_RNG_TIMER_EN : R/W; bitpos: [0]; default: 1; - * enable rng timer - */ -#define LP_SYSTEM_REG_RNG_TIMER_EN (BIT(0)) -#define LP_SYSTEM_REG_RNG_TIMER_EN_M (LP_SYSTEM_REG_RNG_TIMER_EN_V << LP_SYSTEM_REG_RNG_TIMER_EN_S) -#define LP_SYSTEM_REG_RNG_TIMER_EN_V 0x00000001U -#define LP_SYSTEM_REG_RNG_TIMER_EN_S 0 -/** LP_SYSTEM_REG_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 1; - * configure ng timer pscale - */ -#define LP_SYSTEM_REG_RNG_TIMER_PSCALE 0x000000FFU -#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_M (LP_SYSTEM_REG_RNG_TIMER_PSCALE_V << LP_SYSTEM_REG_RNG_TIMER_PSCALE_S) -#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_V 0x000000FFU -#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_S 1 -/** LP_SYSTEM_REG_RNG_SAR_ENABLE : R/W; bitpos: [9]; default: 0; - * enable rng_saradc - */ -#define LP_SYSTEM_REG_RNG_SAR_ENABLE (BIT(9)) -#define LP_SYSTEM_REG_RNG_SAR_ENABLE_M (LP_SYSTEM_REG_RNG_SAR_ENABLE_V << LP_SYSTEM_REG_RNG_SAR_ENABLE_S) -#define LP_SYSTEM_REG_RNG_SAR_ENABLE_V 0x00000001U -#define LP_SYSTEM_REG_RNG_SAR_ENABLE_S 9 -/** LP_SYSTEM_REG_RNG_SAR_DATA : RO; bitpos: [28:16]; default: 0; - * debug rng sar sample cnt - */ -#define LP_SYSTEM_REG_RNG_SAR_DATA 0x00001FFFU -#define LP_SYSTEM_REG_RNG_SAR_DATA_M (LP_SYSTEM_REG_RNG_SAR_DATA_V << LP_SYSTEM_REG_RNG_SAR_DATA_S) -#define LP_SYSTEM_REG_RNG_SAR_DATA_V 0x00001FFFU -#define LP_SYSTEM_REG_RNG_SAR_DATA_S 16 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_sys_struct.h b/components/soc/esp32p4/include/soc/lp_sys_struct.h deleted file mode 100644 index f54c249eec..0000000000 --- a/components/soc/esp32p4/include/soc/lp_sys_struct.h +++ /dev/null @@ -1,1333 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of lp_sys_ver_date register - * need_des - */ -typedef union { - struct { - /** ver_date : R/W; bitpos: [31:0]; default: 539165961; - * need_des - */ - uint32_t ver_date:32; - }; - uint32_t val; -} lp_system_reg_lp_sys_ver_date_reg_t; - -/** Type of clk_sel_ctrl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** ena_sw_sel_sys_clk : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t ena_sw_sel_sys_clk:1; - /** sw_sys_clk_src_sel : R/W; bitpos: [17]; default: 0; - * reserved - */ - uint32_t sw_sys_clk_src_sel:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} lp_system_reg_clk_sel_ctrl_reg_t; - -/** Type of sys_ctrl register - * need_des - */ -typedef union { - struct { - /** lp_core_disable : R/W; bitpos: [0]; default: 0; - * lp cpu disable - */ - uint32_t lp_core_disable:1; - /** sys_sw_rst : WT; bitpos: [1]; default: 0; - * digital system software reset bit - */ - uint32_t sys_sw_rst:1; - /** force_download_boot : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t force_download_boot:1; - /** dig_fib : R/W; bitpos: [10:3]; default: 255; - * need_des - */ - uint32_t dig_fib:8; - /** io_mux_reset_disable : R/W; bitpos: [11]; default: 0; - * reset disable bit for LP IOMUX - */ - uint32_t io_mux_reset_disable:1; - uint32_t reserved_12:2; - /** ana_fib : RO; bitpos: [20:14]; default: 127; - * need_des - */ - uint32_t ana_fib:7; - /** lp_fib_sel : R/W; bitpos: [28:21]; default: 255; - * need_des - */ - uint32_t lp_fib_sel:8; - /** lp_core_etm_wakeup_flag_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_core_etm_wakeup_flag_clr:1; - /** lp_core_etm_wakeup_flag : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_core_etm_wakeup_flag:1; - /** systimer_stall_sel : R/W; bitpos: [31]; default: 0; - * 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from - * hp_core1 - */ - uint32_t systimer_stall_sel:1; - }; - uint32_t val; -} lp_system_reg_sys_ctrl_reg_t; - -/** Type of lp_clk_ctrl register - * need_des - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * need_des - */ - uint32_t clk_en:1; - uint32_t reserved_1:13; - /** lp_fosc_hp_cken : R/W; bitpos: [14]; default: 1; - * reserved - */ - uint32_t lp_fosc_hp_cken:1; - uint32_t reserved_15:17; - }; - uint32_t val; -} lp_system_reg_lp_clk_ctrl_reg_t; - -/** Type of lp_rst_ctrl register - * need_des - */ -typedef union { - struct { - /** ana_rst_bypass : R/W; bitpos: [0]; default: 1; - * analog source reset bypass : wdt,brown out,super wdt,glitch - */ - uint32_t ana_rst_bypass:1; - /** sys_rst_bypass : R/W; bitpos: [1]; default: 1; - * system source reset bypass : software reset,hp wdt,lp wdt,efuse - */ - uint32_t sys_rst_bypass:1; - /** efuse_force_norst : R/W; bitpos: [2]; default: 0; - * efuse force no reset control - */ - uint32_t efuse_force_norst:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} lp_system_reg_lp_rst_ctrl_reg_t; - -/** Type of lp_core_boot_addr register - * need_des - */ -typedef union { - struct { - /** lp_cpu_boot_addr : R/W; bitpos: [31:0]; default: 1343225856; - * need_des - */ - uint32_t lp_cpu_boot_addr:32; - }; - uint32_t val; -} lp_system_reg_lp_core_boot_addr_reg_t; - -/** Type of ext_wakeup1 register - * need_des - */ -typedef union { - struct { - /** ext_wakeup1_sel : R/W; bitpos: [15:0]; default: 0; - * Bitmap to select RTC pads for ext wakeup1 - */ - uint32_t ext_wakeup1_sel:16; - /** ext_wakeup1_status_clr : WT; bitpos: [16]; default: 0; - * clear ext wakeup1 status - */ - uint32_t ext_wakeup1_status_clr:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} lp_system_reg_ext_wakeup1_reg_t; - -/** Type of ext_wakeup1_status register - * need_des - */ -typedef union { - struct { - /** ext_wakeup1_status : RO; bitpos: [15:0]; default: 0; - * ext wakeup1 status - */ - uint32_t ext_wakeup1_status:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} lp_system_reg_ext_wakeup1_status_reg_t; - -/** Type of lp_tcm_pwr_ctrl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** lp_tcm_rom_clk_force_on : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t lp_tcm_rom_clk_force_on:1; - uint32_t reserved_6:1; - /** lp_tcm_ram_clk_force_on : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t lp_tcm_ram_clk_force_on:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_system_reg_lp_tcm_pwr_ctrl_reg_t; - -/** Type of boot_addr_hp_lp_reg register - * need_des - */ -typedef union { - struct { - /** boot_addr_hp_lp : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t boot_addr_hp_lp:32; - }; - uint32_t val; -} lp_system_reg_boot_addr_hp_lp_reg_reg_t; - -/** Type of lp_store0 register - * need_des - */ -typedef union { - struct { - /** lp_scratch0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch0:32; - }; - uint32_t val; -} lp_system_reg_lp_store0_reg_t; - -/** Type of lp_store1 register - * need_des - */ -typedef union { - struct { - /** lp_scratch1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch1:32; - }; - uint32_t val; -} lp_system_reg_lp_store1_reg_t; - -/** Type of lp_store2 register - * need_des - */ -typedef union { - struct { - /** lp_scratch2 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch2:32; - }; - uint32_t val; -} lp_system_reg_lp_store2_reg_t; - -/** Type of lp_store3 register - * need_des - */ -typedef union { - struct { - /** lp_scratch3 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch3:32; - }; - uint32_t val; -} lp_system_reg_lp_store3_reg_t; - -/** Type of lp_store4 register - * need_des - */ -typedef union { - struct { - /** lp_scratch4 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch4:32; - }; - uint32_t val; -} lp_system_reg_lp_store4_reg_t; - -/** Type of lp_store5 register - * need_des - */ -typedef union { - struct { - /** lp_scratch5 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch5:32; - }; - uint32_t val; -} lp_system_reg_lp_store5_reg_t; - -/** Type of lp_store6 register - * need_des - */ -typedef union { - struct { - /** lp_scratch6 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch6:32; - }; - uint32_t val; -} lp_system_reg_lp_store6_reg_t; - -/** Type of lp_store7 register - * need_des - */ -typedef union { - struct { - /** lp_scratch7 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch7:32; - }; - uint32_t val; -} lp_system_reg_lp_store7_reg_t; - -/** Type of lp_store8 register - * need_des - */ -typedef union { - struct { - /** lp_scratch8 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch8:32; - }; - uint32_t val; -} lp_system_reg_lp_store8_reg_t; - -/** Type of lp_store9 register - * need_des - */ -typedef union { - struct { - /** lp_scratch9 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch9:32; - }; - uint32_t val; -} lp_system_reg_lp_store9_reg_t; - -/** Type of lp_store10 register - * need_des - */ -typedef union { - struct { - /** lp_scratch10 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch10:32; - }; - uint32_t val; -} lp_system_reg_lp_store10_reg_t; - -/** Type of lp_store11 register - * need_des - */ -typedef union { - struct { - /** lp_scratch11 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch11:32; - }; - uint32_t val; -} lp_system_reg_lp_store11_reg_t; - -/** Type of lp_store12 register - * need_des - */ -typedef union { - struct { - /** lp_scratch12 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch12:32; - }; - uint32_t val; -} lp_system_reg_lp_store12_reg_t; - -/** Type of lp_store13 register - * need_des - */ -typedef union { - struct { - /** lp_scratch13 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch13:32; - }; - uint32_t val; -} lp_system_reg_lp_store13_reg_t; - -/** Type of lp_store14 register - * need_des - */ -typedef union { - struct { - /** lp_scratch14 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch14:32; - }; - uint32_t val; -} lp_system_reg_lp_store14_reg_t; - -/** Type of lp_store15 register - * need_des - */ -typedef union { - struct { - /** lp_scratch15 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_scratch15:32; - }; - uint32_t val; -} lp_system_reg_lp_store15_reg_t; - -/** Type of lp_probea_ctrl register - * need_des - */ -typedef union { - struct { - /** probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t probe_a_mod_sel:16; - /** probe_a_top_sel : R/W; bitpos: [23:16]; default: 0; - * need_des - */ - uint32_t probe_a_top_sel:8; - /** probe_l_sel : R/W; bitpos: [25:24]; default: 0; - * need_des - */ - uint32_t probe_l_sel:2; - /** probe_h_sel : R/W; bitpos: [27:26]; default: 0; - * need_des - */ - uint32_t probe_h_sel:2; - /** probe_global_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t probe_global_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} lp_system_reg_lp_probea_ctrl_reg_t; - -/** Type of lp_probeb_ctrl register - * need_des - */ -typedef union { - struct { - /** probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t probe_b_mod_sel:16; - /** probe_b_top_sel : R/W; bitpos: [23:16]; default: 0; - * need_des - */ - uint32_t probe_b_top_sel:8; - /** probe_b_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t probe_b_en:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} lp_system_reg_lp_probeb_ctrl_reg_t; - -/** Type of lp_probe_out register - * need_des - */ -typedef union { - struct { - /** probe_top_out : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t probe_top_out:32; - }; - uint32_t val; -} lp_system_reg_lp_probe_out_reg_t; - -/** Type of f2s_apb_brg_cntl register - * need_des - */ -typedef union { - struct { - /** f2s_apb_postw_en : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t f2s_apb_postw_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_system_reg_f2s_apb_brg_cntl_reg_t; - -/** Type of usb_ctrl register - * need_des - */ -typedef union { - struct { - /** sw_hw_usb_phy_sel : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t sw_hw_usb_phy_sel:1; - /** sw_usb_phy_sel : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t sw_usb_phy_sel:1; - /** usbotg20_wakeup_clr : WT; bitpos: [2]; default: 0; - * clear usb wakeup to PMU. - */ - uint32_t usbotg20_wakeup_clr:1; - /** usbotg20_in_suspend : R/W; bitpos: [3]; default: 0; - * indicate usb otg2.0 is in suspend state. - */ - uint32_t usbotg20_in_suspend:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} lp_system_reg_usb_ctrl_reg_t; - -/** Type of ana_xpd_pad_group register - * need_des - */ -typedef union { - struct { - /** ana_reg_xpd_pad_group : R/W; bitpos: [7:0]; default: 255; - * Set 1 to power up pad group - */ - uint32_t ana_reg_xpd_pad_group:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_system_reg_ana_xpd_pad_group_reg_t; - -/** Type of lp_tcm_ram_rdn_eco_cs register - * need_des - */ -typedef union { - struct { - /** lp_tcm_ram_rdn_eco_en : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_tcm_ram_rdn_eco_en:1; - /** lp_tcm_ram_rdn_eco_result : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_tcm_ram_rdn_eco_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t; - -/** Type of lp_tcm_ram_rdn_eco_low register - * need_des - */ -typedef union { - struct { - /** lp_tcm_ram_rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_tcm_ram_rdn_eco_low:32; - }; - uint32_t val; -} lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t; - -/** Type of lp_tcm_ram_rdn_eco_high register - * need_des - */ -typedef union { - struct { - /** lp_tcm_ram_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t lp_tcm_ram_rdn_eco_high:32; - }; - uint32_t val; -} lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t; - -/** Type of lp_tcm_rom_rdn_eco_cs register - * need_des - */ -typedef union { - struct { - /** lp_tcm_rom_rdn_eco_en : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_tcm_rom_rdn_eco_en:1; - /** lp_tcm_rom_rdn_eco_result : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_tcm_rom_rdn_eco_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t; - -/** Type of lp_tcm_rom_rdn_eco_low register - * need_des - */ -typedef union { - struct { - /** lp_tcm_rom_rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_tcm_rom_rdn_eco_low:32; - }; - uint32_t val; -} lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t; - -/** Type of lp_tcm_rom_rdn_eco_high register - * need_des - */ -typedef union { - struct { - /** lp_tcm_rom_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t lp_tcm_rom_rdn_eco_high:32; - }; - uint32_t val; -} lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t; - -/** Type of hp_root_clk_ctrl register - * need_des - */ -typedef union { - struct { - /** cpu_clk_en : R/W; bitpos: [0]; default: 1; - * clock gate enable for hp cpu root 400M clk - */ - uint32_t cpu_clk_en:1; - /** sys_clk_en : R/W; bitpos: [1]; default: 1; - * clock gate enable for hp sys root 480M clk - */ - uint32_t sys_clk_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_system_reg_hp_root_clk_ctrl_reg_t; - -/** Type of lp_pmu_rdn_eco_low register - * need_des - */ -typedef union { - struct { - /** pmu_rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t pmu_rdn_eco_low:32; - }; - uint32_t val; -} lp_system_reg_lp_pmu_rdn_eco_low_reg_t; - -/** Type of lp_pmu_rdn_eco_high register - * need_des - */ -typedef union { - struct { - /** pmu_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t pmu_rdn_eco_high:32; - }; - uint32_t val; -} lp_system_reg_lp_pmu_rdn_eco_high_reg_t; - -/** Type of pad_comp0 register - * need_des - */ -typedef union { - struct { - /** dref_comp0 : R/W; bitpos: [2:0]; default: 0; - * pad comp dref - */ - uint32_t dref_comp0:3; - /** mode_comp0 : R/W; bitpos: [3]; default: 0; - * pad comp mode - */ - uint32_t mode_comp0:1; - /** xpd_comp0 : R/W; bitpos: [4]; default: 0; - * pad comp xpd - */ - uint32_t xpd_comp0:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} lp_system_reg_pad_comp0_reg_t; - -/** Type of pad_comp1 register - * need_des - */ -typedef union { - struct { - /** dref_comp1 : R/W; bitpos: [2:0]; default: 0; - * pad comp dref - */ - uint32_t dref_comp1:3; - /** mode_comp1 : R/W; bitpos: [3]; default: 0; - * pad comp mode - */ - uint32_t mode_comp1:1; - /** xpd_comp1 : R/W; bitpos: [4]; default: 0; - * pad comp xpd - */ - uint32_t xpd_comp1:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} lp_system_reg_pad_comp1_reg_t; - -/** Type of backup_dma_cfg0 register - * need_des - */ -typedef union { - struct { - /** burst_limit_aon : R/W; bitpos: [4:0]; default: 10; - * need_des - */ - uint32_t burst_limit_aon:5; - /** read_interval_aon : R/W; bitpos: [11:5]; default: 10; - * need_des - */ - uint32_t read_interval_aon:7; - /** link_backup_tout_thres_aon : R/W; bitpos: [21:12]; default: 100; - * need_des - */ - uint32_t link_backup_tout_thres_aon:10; - /** link_tout_thres_aon : R/W; bitpos: [31:22]; default: 100; - * need_des - */ - uint32_t link_tout_thres_aon:10; - }; - uint32_t val; -} lp_system_reg_backup_dma_cfg0_reg_t; - -/** Type of backup_dma_cfg1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** aon_bypass : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t aon_bypass:1; - }; - uint32_t val; -} lp_system_reg_backup_dma_cfg1_reg_t; - -/** Type of backup_dma_cfg2 register - * need_des - */ -typedef union { - struct { - /** link_addr_aon : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t link_addr_aon:32; - }; - uint32_t val; -} lp_system_reg_backup_dma_cfg2_reg_t; - -/** Type of boot_addr_hp_core1 register - * need_des - */ -typedef union { - struct { - /** boot_addr_hp_core1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t boot_addr_hp_core1:32; - }; - uint32_t val; -} lp_system_reg_boot_addr_hp_core1_reg_t; - -/** Type of hp_mem_aux_ctrl register - * need_des - */ -typedef union { - struct { - /** hp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; - * need_des - */ - uint32_t hp_mem_aux_ctrl:32; - }; - uint32_t val; -} lp_system_reg_hp_mem_aux_ctrl_reg_t; - -/** Type of lp_mem_aux_ctrl register - * need_des - */ -typedef union { - struct { - /** lp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; - * need_des - */ - uint32_t lp_mem_aux_ctrl:32; - }; - uint32_t val; -} lp_system_reg_lp_mem_aux_ctrl_reg_t; - -/** Type of hp_rom_aux_ctrl register - * need_des - */ -typedef union { - struct { - /** hp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112; - * need_des - */ - uint32_t hp_rom_aux_ctrl:32; - }; - uint32_t val; -} lp_system_reg_hp_rom_aux_ctrl_reg_t; - -/** Type of lp_rom_aux_ctrl register - * need_des - */ -typedef union { - struct { - /** lp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112; - * need_des - */ - uint32_t lp_rom_aux_ctrl:32; - }; - uint32_t val; -} lp_system_reg_lp_rom_aux_ctrl_reg_t; - -/** Type of hp_por_rst_bypass_ctrl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_po_cnnt_rstn_bypass_ctrl : R/W; bitpos: [15:8]; default: 255; - * [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn - * [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn - * [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn - * [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn - * [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst - * [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst - * [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn - * [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn - */ - uint32_t hp_po_cnnt_rstn_bypass_ctrl:8; - uint32_t reserved_16:8; - /** hp_po_rstn_bypass_ctrl : R/W; bitpos: [31:24]; default: 255; - * [31] 1'b1: po_rstn bypass sys_sw_rstn - * [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn - * [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn - * [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn - * [27] 1'b1: po_rstn bypass usb_jtag_chip_rst - * [26] 1'b1: po_rstn bypass usb_uart_chip_rst - * [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn - * [24] 1'b1: po_rstn bypass efuse_err_rstn - */ - uint32_t hp_po_rstn_bypass_ctrl:8; - }; - uint32_t val; -} lp_system_reg_hp_por_rst_bypass_ctrl_reg_t; - -/** Type of lp_core_ahb_timeout register - * need_des - */ -typedef union { - struct { - /** lp_core_ahb_timeout_en : R/W; bitpos: [0]; default: 1; - * set this field to 1 to enable lp core ahb timeout handle - */ - uint32_t lp_core_ahb_timeout_en:1; - /** lp_core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535; - * This field used to set lp core ahb bus timeout threshold - */ - uint32_t lp_core_ahb_timeout_thres:16; - /** lp2hp_ahb_timeout_en : R/W; bitpos: [17]; default: 1; - * set this field to 1 to enable lp2hp ahb timeout handle - */ - uint32_t lp2hp_ahb_timeout_en:1; - /** lp2hp_ahb_timeout_thres : R/W; bitpos: [22:18]; default: 31; - * This field used to set lp2hp ahb bus timeout threshold - */ - uint32_t lp2hp_ahb_timeout_thres:5; - uint32_t reserved_23:9; - }; - uint32_t val; -} lp_system_reg_lp_core_ahb_timeout_reg_t; - -/** Type of lp_core_ibus_timeout register - * need_des - */ -typedef union { - struct { - /** lp_core_ibus_timeout_en : R/W; bitpos: [0]; default: 1; - * set this field to 1 to enable lp core ibus timeout handle - */ - uint32_t lp_core_ibus_timeout_en:1; - /** lp_core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535; - * This field used to set lp core ibus timeout threshold - */ - uint32_t lp_core_ibus_timeout_thres:16; - uint32_t reserved_17:15; - }; - uint32_t val; -} lp_system_reg_lp_core_ibus_timeout_reg_t; - -/** Type of lp_core_dbus_timeout register - * need_des - */ -typedef union { - struct { - /** lp_core_dbus_timeout_en : R/W; bitpos: [0]; default: 1; - * set this field to 1 to enable lp core dbus timeout handle - */ - uint32_t lp_core_dbus_timeout_en:1; - /** lp_core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535; - * This field used to set lp core dbus timeout threshold - */ - uint32_t lp_core_dbus_timeout_thres:16; - uint32_t reserved_17:15; - }; - uint32_t val; -} lp_system_reg_lp_core_dbus_timeout_reg_t; - - -/** Group: status_register */ -/** Type of lp_addrhole_addr register - * need_des - */ -typedef union { - struct { - /** lp_addrhole_addr : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_addrhole_addr:32; - }; - uint32_t val; -} lp_system_reg_lp_addrhole_addr_reg_t; - -/** Type of lp_addrhole_info register - * need_des - */ -typedef union { - struct { - /** lp_addrhole_id : RO; bitpos: [4:0]; default: 0; - * master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: - * regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha - * tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. - */ - uint32_t lp_addrhole_id:5; - /** lp_addrhole_wr : RO; bitpos: [5]; default: 0; - * 1:write trans, 0: read trans. - */ - uint32_t lp_addrhole_wr:1; - /** lp_addrhole_secure : RO; bitpos: [6]; default: 0; - * 1: illegal address access, 0: access without permission - */ - uint32_t lp_addrhole_secure:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} lp_system_reg_lp_addrhole_info_reg_t; - -/** Type of lp_cpu_dbg_pc register - * need_des - */ -typedef union { - struct { - /** lp_cpu_dbg_pc : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_dbg_pc:32; - }; - uint32_t val; -} lp_system_reg_lp_cpu_dbg_pc_reg_t; - -/** Type of lp_cpu_exc_pc register - * need_des - */ -typedef union { - struct { - /** lp_cpu_exc_pc : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_pc:32; - }; - uint32_t val; -} lp_system_reg_lp_cpu_exc_pc_reg_t; - -/** Type of idbus_addrhole_addr register - * need_des - */ -typedef union { - struct { - /** idbus_addrhole_addr : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t idbus_addrhole_addr:32; - }; - uint32_t val; -} lp_system_reg_idbus_addrhole_addr_reg_t; - -/** Type of idbus_addrhole_info register - * need_des - */ -typedef union { - struct { - /** idbus_addrhole_id : RO; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t idbus_addrhole_id:5; - /** idbus_addrhole_wr : RO; bitpos: [5]; default: 0; - * need_des - */ - uint32_t idbus_addrhole_wr:1; - /** idbus_addrhole_secure : RO; bitpos: [6]; default: 0; - * need_des - */ - uint32_t idbus_addrhole_secure:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} lp_system_reg_idbus_addrhole_info_reg_t; - -/** Type of rng_data register - * rng data register - */ -typedef union { - struct { - /** rnd_data : RO; bitpos: [31:0]; default: 0; - * result of rng output - */ - uint32_t rnd_data:32; - }; - uint32_t val; -} lp_system_reg_rng_data_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * raw interrupt register - */ -typedef union { - struct { - /** lp_addrhole_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp - * matrix default slave) - */ - uint32_t lp_addrhole_int_raw:1; - /** idbus_addrhole_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) - */ - uint32_t idbus_addrhole_int_raw:1; - /** lp_core_ahb_timeout_int_raw : R/SS/WTC; bitpos: [2]; default: 0; - * the raw interrupt status of lp core ahb bus timeout - */ - uint32_t lp_core_ahb_timeout_int_raw:1; - /** lp_core_ibus_timeout_int_raw : R/SS/WTC; bitpos: [3]; default: 0; - * the raw interrupt status of lp core ibus timeout - */ - uint32_t lp_core_ibus_timeout_int_raw:1; - /** lp_core_dbus_timeout_int_raw : R/SS/WTC; bitpos: [4]; default: 0; - * the raw interrupt status of lp core dbus timeout - */ - uint32_t lp_core_dbus_timeout_int_raw:1; - /** etm_task_ulp_int_raw : R/SS/WTC; bitpos: [5]; default: 0; - * the raw interrupt status of etm task ulp - */ - uint32_t etm_task_ulp_int_raw:1; - /** slow_clk_tick_int_raw : R/SS/WTC; bitpos: [6]; default: 0; - * the raw interrupt status of slow_clk_tick - */ - uint32_t slow_clk_tick_int_raw:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} lp_system_reg_int_raw_reg_t; - -/** Type of int_st register - * masked interrupt register - */ -typedef union { - struct { - /** lp_addrhole_int_st : RO; bitpos: [0]; default: 0; - * the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp - * matrix default slave) - */ - uint32_t lp_addrhole_int_st:1; - /** idbus_addrhole_int_st : RO; bitpos: [1]; default: 0; - * the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) - */ - uint32_t idbus_addrhole_int_st:1; - /** lp_core_ahb_timeout_int_st : RO; bitpos: [2]; default: 0; - * the masked interrupt status of lp core ahb bus timeout - */ - uint32_t lp_core_ahb_timeout_int_st:1; - /** lp_core_ibus_timeout_int_st : RO; bitpos: [3]; default: 0; - * the masked interrupt status of lp core ibus timeout - */ - uint32_t lp_core_ibus_timeout_int_st:1; - /** lp_core_dbus_timeout_int_st : RO; bitpos: [4]; default: 0; - * the masked interrupt status of lp core dbus timeout - */ - uint32_t lp_core_dbus_timeout_int_st:1; - /** etm_task_ulp_int_st : RO; bitpos: [5]; default: 0; - * the masked interrupt status of etm task ulp - */ - uint32_t etm_task_ulp_int_st:1; - /** slow_clk_tick_int_st : RO; bitpos: [6]; default: 0; - * the masked interrupt status of slow_clk_tick - */ - uint32_t slow_clk_tick_int_st:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} lp_system_reg_int_st_reg_t; - -/** Type of int_ena register - * masked interrupt register - */ -typedef union { - struct { - /** lp_addrhole_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable lp addrhole int - */ - uint32_t lp_addrhole_int_ena:1; - /** idbus_addrhole_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable idbus addrhole int - */ - uint32_t idbus_addrhole_int_ena:1; - /** lp_core_ahb_timeout_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable lp_core_ahb_timeout int - */ - uint32_t lp_core_ahb_timeout_int_ena:1; - /** lp_core_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable lp_core_ibus_timeout int - */ - uint32_t lp_core_ibus_timeout_int_ena:1; - /** lp_core_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable lp_core_dbus_timeout int - */ - uint32_t lp_core_dbus_timeout_int_ena:1; - /** etm_task_ulp_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable etm task ulp int - */ - uint32_t etm_task_ulp_int_ena:1; - /** slow_clk_tick_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable slow_clk_tick int - */ - uint32_t slow_clk_tick_int_ena:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} lp_system_reg_int_ena_reg_t; - -/** Type of int_clr register - * interrupt clear register - */ -typedef union { - struct { - /** lp_addrhole_int_clr : WT; bitpos: [0]; default: 0; - * write 1 to clear lp addrhole int - */ - uint32_t lp_addrhole_int_clr:1; - /** idbus_addrhole_int_clr : WT; bitpos: [1]; default: 0; - * write 1 to clear idbus addrhole int - */ - uint32_t idbus_addrhole_int_clr:1; - /** lp_core_ahb_timeout_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear lp_core_ahb_timeout int - */ - uint32_t lp_core_ahb_timeout_int_clr:1; - /** lp_core_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear lp_core_ibus_timeout int - */ - uint32_t lp_core_ibus_timeout_int_clr:1; - /** lp_core_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear lp_core_dbus_timeout int - */ - uint32_t lp_core_dbus_timeout_int_clr:1; - /** etm_task_ulp_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear etm tasl ulp int - */ - uint32_t etm_task_ulp_int_clr:1; - /** slow_clk_tick_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear slow_clk_tick int - */ - uint32_t slow_clk_tick_int_clr:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} lp_system_reg_int_clr_reg_t; - - -/** Group: control registers */ -/** Type of lp_core_err_resp_dis register - * need_des - */ -typedef union { - struct { - /** lp_core_err_resp_dis : R/W; bitpos: [2:0]; default: 0; - * Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to - * disable ahb err resp. - */ - uint32_t lp_core_err_resp_dis:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} lp_system_reg_lp_core_err_resp_dis_reg_t; - -/** Type of rng_cfg register - * rng cfg register - */ -typedef union { - struct { - /** rng_timer_en : R/W; bitpos: [0]; default: 1; - * enable rng timer - */ - uint32_t rng_timer_en:1; - /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 1; - * configure ng timer pscale - */ - uint32_t rng_timer_pscale:8; - /** rng_sar_enable : R/W; bitpos: [9]; default: 0; - * enable rng_saradc - */ - uint32_t rng_sar_enable:1; - uint32_t reserved_10:6; - /** rng_sar_data : RO; bitpos: [28:16]; default: 0; - * debug rng sar sample cnt - */ - uint32_t rng_sar_data:13; - uint32_t reserved_29:3; - }; - uint32_t val; -} lp_system_reg_rng_cfg_reg_t; - - -typedef struct { - volatile lp_system_reg_lp_sys_ver_date_reg_t lp_sys_ver_date; - volatile lp_system_reg_clk_sel_ctrl_reg_t clk_sel_ctrl; - volatile lp_system_reg_sys_ctrl_reg_t sys_ctrl; - volatile lp_system_reg_lp_clk_ctrl_reg_t lp_clk_ctrl; - volatile lp_system_reg_lp_rst_ctrl_reg_t lp_rst_ctrl; - uint32_t reserved_014; - volatile lp_system_reg_lp_core_boot_addr_reg_t lp_core_boot_addr; - volatile lp_system_reg_ext_wakeup1_reg_t ext_wakeup1; - volatile lp_system_reg_ext_wakeup1_status_reg_t ext_wakeup1_status; - volatile lp_system_reg_lp_tcm_pwr_ctrl_reg_t lp_tcm_pwr_ctrl; - volatile lp_system_reg_boot_addr_hp_lp_reg_reg_t boot_addr_hp_lp_reg; - volatile lp_system_reg_lp_store0_reg_t lp_store0; - volatile lp_system_reg_lp_store1_reg_t lp_store1; - volatile lp_system_reg_lp_store2_reg_t lp_store2; - volatile lp_system_reg_lp_store3_reg_t lp_store3; - volatile lp_system_reg_lp_store4_reg_t lp_store4; - volatile lp_system_reg_lp_store5_reg_t lp_store5; - volatile lp_system_reg_lp_store6_reg_t lp_store6; - volatile lp_system_reg_lp_store7_reg_t lp_store7; - volatile lp_system_reg_lp_store8_reg_t lp_store8; - volatile lp_system_reg_lp_store9_reg_t lp_store9; - volatile lp_system_reg_lp_store10_reg_t lp_store10; - volatile lp_system_reg_lp_store11_reg_t lp_store11; - volatile lp_system_reg_lp_store12_reg_t lp_store12; - volatile lp_system_reg_lp_store13_reg_t lp_store13; - volatile lp_system_reg_lp_store14_reg_t lp_store14; - volatile lp_system_reg_lp_store15_reg_t lp_store15; - volatile lp_system_reg_lp_probea_ctrl_reg_t lp_probea_ctrl; - volatile lp_system_reg_lp_probeb_ctrl_reg_t lp_probeb_ctrl; - volatile lp_system_reg_lp_probe_out_reg_t lp_probe_out; - uint32_t reserved_078[9]; - volatile lp_system_reg_f2s_apb_brg_cntl_reg_t f2s_apb_brg_cntl; - uint32_t reserved_0a0[24]; - volatile lp_system_reg_usb_ctrl_reg_t usb_ctrl; - uint32_t reserved_104[2]; - volatile lp_system_reg_ana_xpd_pad_group_reg_t ana_xpd_pad_group; - volatile lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t lp_tcm_ram_rdn_eco_cs; - volatile lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t lp_tcm_ram_rdn_eco_low; - volatile lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t lp_tcm_ram_rdn_eco_high; - volatile lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t lp_tcm_rom_rdn_eco_cs; - volatile lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t lp_tcm_rom_rdn_eco_low; - volatile lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t lp_tcm_rom_rdn_eco_high; - uint32_t reserved_128[2]; - volatile lp_system_reg_hp_root_clk_ctrl_reg_t hp_root_clk_ctrl; - uint32_t reserved_134; - volatile lp_system_reg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low; - volatile lp_system_reg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high; - uint32_t reserved_140[2]; - volatile lp_system_reg_pad_comp0_reg_t pad_comp0; - volatile lp_system_reg_pad_comp1_reg_t pad_comp1; - uint32_t reserved_150; - volatile lp_system_reg_backup_dma_cfg0_reg_t backup_dma_cfg0; - volatile lp_system_reg_backup_dma_cfg1_reg_t backup_dma_cfg1; - volatile lp_system_reg_backup_dma_cfg2_reg_t backup_dma_cfg2; - uint32_t reserved_160; - volatile lp_system_reg_boot_addr_hp_core1_reg_t boot_addr_hp_core1; - volatile lp_system_reg_lp_addrhole_addr_reg_t lp_addrhole_addr; - volatile lp_system_reg_lp_addrhole_info_reg_t lp_addrhole_info; - volatile lp_system_reg_int_raw_reg_t int_raw; - volatile lp_system_reg_int_st_reg_t int_st; - volatile lp_system_reg_int_ena_reg_t int_ena; - volatile lp_system_reg_int_clr_reg_t int_clr; - volatile lp_system_reg_hp_mem_aux_ctrl_reg_t hp_mem_aux_ctrl; - volatile lp_system_reg_lp_mem_aux_ctrl_reg_t lp_mem_aux_ctrl; - volatile lp_system_reg_hp_rom_aux_ctrl_reg_t hp_rom_aux_ctrl; - volatile lp_system_reg_lp_rom_aux_ctrl_reg_t lp_rom_aux_ctrl; - volatile lp_system_reg_lp_cpu_dbg_pc_reg_t lp_cpu_dbg_pc; - volatile lp_system_reg_lp_cpu_exc_pc_reg_t lp_cpu_exc_pc; - volatile lp_system_reg_idbus_addrhole_addr_reg_t idbus_addrhole_addr; - volatile lp_system_reg_idbus_addrhole_info_reg_t idbus_addrhole_info; - volatile lp_system_reg_hp_por_rst_bypass_ctrl_reg_t hp_por_rst_bypass_ctrl; - volatile lp_system_reg_rng_data_reg_t rng_data; - uint32_t reserved_1a8[2]; - volatile lp_system_reg_lp_core_ahb_timeout_reg_t lp_core_ahb_timeout; - volatile lp_system_reg_lp_core_ibus_timeout_reg_t lp_core_ibus_timeout; - volatile lp_system_reg_lp_core_dbus_timeout_reg_t lp_core_dbus_timeout; - volatile lp_system_reg_lp_core_err_resp_dis_reg_t lp_core_err_resp_dis; - volatile lp_system_reg_rng_cfg_reg_t rng_cfg; -} lp_system_reg_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(lp_system_reg_dev_t) == 0x1c4, "Invalid size of lp_system_reg_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_tee_reg.h b/components/soc/esp32p4/include/soc/lp_tee_reg.h deleted file mode 100644 index 932c959d04..0000000000 --- a/components/soc/esp32p4/include/soc/lp_tee_reg.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_TEE_M0_MODE_CTRL_REG register - * Tee mode control register - */ -#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) -/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; - * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define LP_TEE_M0_MODE 0x00000003U -#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) -#define LP_TEE_M0_MODE_V 0x00000003U -#define LP_TEE_M0_MODE_S 0 - -/** LP_TEE_CLOCK_GATE_REG register - * Clock gating register - */ -#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4) -/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ -#define LP_TEE_CLK_EN (BIT(0)) -#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) -#define LP_TEE_CLK_EN_V 0x00000001U -#define LP_TEE_CLK_EN_S 0 - -/** LP_TEE_FORCE_ACC_HP_REG register - * need_des - */ -#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) -/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; - * need_des - */ -#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) -#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) -#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U -#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 - -/** LP_TEE_DATE_REG register - * Version register - */ -#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) -/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688; - * reg_tee_date - */ -#define LP_TEE_DATE_REG 0x0FFFFFFFU -#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S) -#define LP_TEE_DATE_REG_V 0x0FFFFFFFU -#define LP_TEE_DATE_REG_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_tee_struct.h b/components/soc/esp32p4/include/soc/lp_tee_struct.h deleted file mode 100644 index b769f963c6..0000000000 --- a/components/soc/esp32p4/include/soc/lp_tee_struct.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Tee mode control register */ -/** Type of m0_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m0_mode : R/W; bitpos: [1:0]; default: 3; - * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m0_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} lp_tee_m0_mode_ctrl_reg_t; - - -/** Group: clock gating register */ -/** Type of clock_gate register - * Clock gating register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_tee_clock_gate_reg_t; - - -/** Group: configure_register */ -/** Type of force_acc_hp register - * need_des - */ -typedef union { - struct { - /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_acc_hpmem_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} lp_tee_force_acc_hp_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version register - */ -typedef union { - struct { - /** date_reg : R/W; bitpos: [27:0]; default: 35672688; - * reg_tee_date - */ - uint32_t date_reg:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} lp_tee_date_reg_t; - - -typedef struct lp_tee_dev_t { - volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl; - volatile lp_tee_clock_gate_reg_t clock_gate; - uint32_t reserved_008[34]; - volatile lp_tee_force_acc_hp_reg_t force_acc_hp; - uint32_t reserved_094[26]; - volatile lp_tee_date_reg_t date; -} lp_tee_dev_t; - -extern lp_tee_dev_t LP_TEE; - -#ifndef __cplusplus -_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/mem_monitor_reg.h b/components/soc/esp32p4/include/soc/mem_monitor_reg.h deleted file mode 100644 index 3aec488661..0000000000 --- a/components/soc/esp32p4/include/soc/mem_monitor_reg.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_MEM_MONITOR_REG_H_ -#define _SOC_MEM_MONITOR_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" - -#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) -/* MEM_MONITOR_LOG_DMA_1_ENA : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ -/*description: enable dma_1 log.*/ -#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FF -#define MEM_MONITOR_LOG_DMA_1_ENA_M ((MEM_MONITOR_LOG_DMA_1_ENA_V)<<(MEM_MONITOR_LOG_DMA_1_ENA_S)) -#define MEM_MONITOR_LOG_DMA_1_ENA_V 0xFF -#define MEM_MONITOR_LOG_DMA_1_ENA_S 24 -/* MEM_MONITOR_LOG_DMA_0_ENA : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: enable dma_0 log.*/ -#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FF -#define MEM_MONITOR_LOG_DMA_0_ENA_M ((MEM_MONITOR_LOG_DMA_0_ENA_V)<<(MEM_MONITOR_LOG_DMA_0_ENA_S)) -#define MEM_MONITOR_LOG_DMA_0_ENA_V 0xFF -#define MEM_MONITOR_LOG_DMA_0_ENA_S 16 -/* MEM_MONITOR_LOG_CORE_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ -/*description: enable core log.*/ -#define MEM_MONITOR_LOG_CORE_ENA 0x000000FF -#define MEM_MONITOR_LOG_CORE_ENA_M ((MEM_MONITOR_LOG_CORE_ENA_V)<<(MEM_MONITOR_LOG_CORE_ENA_S)) -#define MEM_MONITOR_LOG_CORE_ENA_V 0xFF -#define MEM_MONITOR_LOG_CORE_ENA_S 8 -/* MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END.*/ -#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4)) -#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (BIT(4)) -#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x1 -#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4 -/* MEM_MONITOR_LOG_MODE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYT -E monitor.*/ -#define MEM_MONITOR_LOG_MODE 0x0000000F -#define MEM_MONITOR_LOG_MODE_M ((MEM_MONITOR_LOG_MODE_V)<<(MEM_MONITOR_LOG_MODE_S)) -#define MEM_MONITOR_LOG_MODE_V 0xF -#define MEM_MONITOR_LOG_MODE_S 0 - -#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4) -/* MEM_MONITOR_LOG_DMA_3_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ -/*description: enable dma_3 log.*/ -#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FF -#define MEM_MONITOR_LOG_DMA_3_ENA_M ((MEM_MONITOR_LOG_DMA_3_ENA_V)<<(MEM_MONITOR_LOG_DMA_3_ENA_S)) -#define MEM_MONITOR_LOG_DMA_3_ENA_V 0xFF -#define MEM_MONITOR_LOG_DMA_3_ENA_S 8 -/* MEM_MONITOR_LOG_DMA_2_ENA : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: enable dma_2 log.*/ -#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FF -#define MEM_MONITOR_LOG_DMA_2_ENA_M ((MEM_MONITOR_LOG_DMA_2_ENA_V)<<(MEM_MONITOR_LOG_DMA_2_ENA_S)) -#define MEM_MONITOR_LOG_DMA_2_ENA_V 0xFF -#define MEM_MONITOR_LOG_DMA_2_ENA_S 0 - -#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8) -/* MEM_MONITOR_LOG_CHECK_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The special check data, when write this special data, it will trigger logging..*/ -#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFF -#define MEM_MONITOR_LOG_CHECK_DATA_M ((MEM_MONITOR_LOG_CHECK_DATA_V)<<(MEM_MONITOR_LOG_CHECK_DATA_S)) -#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFF -#define MEM_MONITOR_LOG_CHECK_DATA_S 0 - -#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xC) -/* MEM_MONITOR_LOG_DATA_MASK : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BI -T1 mask second byte, and so on..*/ -#define MEM_MONITOR_LOG_DATA_MASK 0x0000000F -#define MEM_MONITOR_LOG_DATA_MASK_M ((MEM_MONITOR_LOG_DATA_MASK_V)<<(MEM_MONITOR_LOG_DATA_MASK_S)) -#define MEM_MONITOR_LOG_DATA_MASK_V 0xF -#define MEM_MONITOR_LOG_DATA_MASK_S 0 - -#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10) -/* MEM_MONITOR_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: the min address of log range.*/ -#define MEM_MONITOR_LOG_MIN 0xFFFFFFFF -#define MEM_MONITOR_LOG_MIN_M ((MEM_MONITOR_LOG_MIN_V)<<(MEM_MONITOR_LOG_MIN_S)) -#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFF -#define MEM_MONITOR_LOG_MIN_S 0 - -#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14) -/* MEM_MONITOR_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: the max address of log range.*/ -#define MEM_MONITOR_LOG_MAX 0xFFFFFFFF -#define MEM_MONITOR_LOG_MAX_M ((MEM_MONITOR_LOG_MAX_V)<<(MEM_MONITOR_LOG_MAX_S)) -#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFF -#define MEM_MONITOR_LOG_MAX_S 0 - -#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x18) -/* MEM_MONITOR_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: the start address of writing logging message.*/ -#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFF -#define MEM_MONITOR_LOG_MEM_START_M ((MEM_MONITOR_LOG_MEM_START_V)<<(MEM_MONITOR_LOG_MEM_START_S)) -#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFF -#define MEM_MONITOR_LOG_MEM_START_S 0 - -#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x1C) -/* MEM_MONITOR_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: the end address of writing logging message.*/ -#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFF -#define MEM_MONITOR_LOG_MEM_END_M ((MEM_MONITOR_LOG_MEM_END_V)<<(MEM_MONITOR_LOG_MEM_END_S)) -#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFF -#define MEM_MONITOR_LOG_MEM_END_S 0 - -#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x20) -/* MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: means next writing address.*/ -#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFF -#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M ((MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V)<<(MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)) -#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFF -#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0 - -#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x24) -/* MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_ME -M_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START.*/ -#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) -#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (BIT(0)) -#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x1 -#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 - -#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x28) -/* MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG.*/ -#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) -#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (BIT(1)) -#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x1 -#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 -/* MEM_MONITOR_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1 means memory write loop at least one time at the range of MEM_START and MEM_EN -D.*/ -#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) -#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (BIT(0)) -#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x1 -#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 - -#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2C) -/* MEM_MONITOR_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to force on the clk of mem_monitor register.*/ -#define MEM_MONITOR_CLK_EN (BIT(0)) -#define MEM_MONITOR_CLK_EN_M (BIT(0)) -#define MEM_MONITOR_CLK_EN_V 0x1 -#define MEM_MONITOR_CLK_EN_S 0 - -#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3FC) -/* MEM_MONITOR_DATE : R/W ;bitpos:[27:0] ;default: 28'h2302220 ; */ -/*description: version register.*/ -#define MEM_MONITOR_DATE 0x0FFFFFFF -#define MEM_MONITOR_DATE_M ((MEM_MONITOR_DATE_V)<<(MEM_MONITOR_DATE_S)) -#define MEM_MONITOR_DATE_V 0xFFFFFFF -#define MEM_MONITOR_DATE_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_MEM_MONITOR_REG_H_ */ diff --git a/components/soc/esp32p4/include/soc/mem_monitor_struct.h b/components/soc/esp32p4/include/soc/mem_monitor_struct.h deleted file mode 100644 index 463f58aa4e..0000000000 --- a/components/soc/esp32p4/include/soc/mem_monitor_struct.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_MEM_MONITOR_STRUCT_H_ -#define _SOC_MEM_MONITOR_STRUCT_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc/soc.h" - -typedef volatile struct { - union { - struct { - uint32_t reg_log_mode : 4; /*Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE monitor */ - uint32_t reg_log_mem_loop_enable : 1; /*Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END*/ - uint32_t reserved5 : 3; /*reseved*/ - uint32_t reg_log_core_ena : 8; /*enable core log*/ - uint32_t reg_log_dma_0_ena : 8; /*enable dma_0 log*/ - uint32_t reg_log_dma_1_ena : 8; /*enable dma_1 log*/ - }; - uint32_t val; - } log_setting; - union { - struct { - uint32_t reg_log_dma_2_ena : 8; /*enable dma_2 log*/ - uint32_t reg_log_dma_3_ena : 8; /*enable dma_3 log*/ - uint32_t reserved16 : 16; /*reseved*/ - }; - uint32_t val; - } log_setting1; - uint32_t log_check_data; - union { - struct { - uint32_t reg_log_data_mask : 4; /*byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on.*/ - uint32_t reserved4 : 28; /*reseved*/ - }; - uint32_t val; - } log_data_mask; - uint32_t log_min; - uint32_t log_max; - uint32_t log_mem_start; - uint32_t log_mem_end; - uint32_t log_mem_current_addr; - union { - struct { - uint32_t reg_log_mem_addr_update : 1; /*Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START */ - uint32_t reserved1 : 31; /*reseved*/ - }; - uint32_t val; - } log_mem_addr_update; - union { - struct { - uint32_t reg_log_mem_full_flag : 1; /*1 means memory write loop at least one time at the range of MEM_START and MEM_END*/ - uint32_t reg_clr_log_mem_full_flag : 1; /*Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG*/ - uint32_t reserved2 : 30; /*reseved*/ - }; - uint32_t val; - } log_mem_full_flag; - union { - struct { - uint32_t reg_clk_en : 1; /*Set 1 to force on the clk of mem_monitor register */ - uint32_t reserved1 : 31; /*reseved*/ - }; - uint32_t val; - } clock_gate; - uint32_t reserved_30; - uint32_t reserved_34; - uint32_t reserved_38; - uint32_t reserved_3c; - uint32_t reserved_40; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - union { - struct { - uint32_t reg_mem_monitor_date : 28; /*version register*/ - uint32_t reserved28 : 4; /*reseved*/ - }; - uint32_t val; - } date; -} mem_monitor_dev_t; -extern mem_monitor_dev_t MEM_MONITOR; -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_MEM_MONITOR_STRUCT_H_ */ diff --git a/components/soc/esp32p4/include/soc/mmu.h b/components/soc/esp32p4/include/soc/mmu.h index f0eb7f00f4..94937c2117 100644 --- a/components/soc/esp32p4/include/soc/mmu.h +++ b/components/soc/esp32p4/include/soc/mmu.h @@ -13,21 +13,8 @@ extern "C" { #endif -/* Defined for flash mmap */ -#define SOC_MMU_REGIONS_COUNT 1 -#define SOC_MMU_PAGES_PER_REGION 1024 -#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) -#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) -#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) -#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) -#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL -#define SOC_MMU_ADDR_MASK (MMU_VALID - 1) -#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash -#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE -#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW -#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START -#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) -#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW +//To delete this file +//TODO: IDF-7686 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/otp_debug_reg.h b/components/soc/esp32p4/include/soc/otp_debug_reg.h deleted file mode 100644 index 521f116aa0..0000000000 --- a/components/soc/esp32p4/include/soc/otp_debug_reg.h +++ /dev/null @@ -1,1600 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** OTP_DEBUG_WR_DIS_REG register - * Otp debuger block0 data register1. - */ -#define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0) -/** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Otp block0 write disable data. - */ -#define OTP_DEBUG_BLOCK0_WR_DIS 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_WR_DIS_M (OTP_DEBUG_BLOCK0_WR_DIS_V << OTP_DEBUG_BLOCK0_WR_DIS_S) -#define OTP_DEBUG_BLOCK0_WR_DIS_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_WR_DIS_S 0 - -/** OTP_DEBUG_BLK0_BACKUP1_W1_REG register - * Otp debuger block0 data register2. - */ -#define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4) -/** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word1 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP1_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W1_M (OTP_DEBUG_BLOCK0_BACKUP1_W1_V << OTP_DEBUG_BLOCK0_BACKUP1_W1_S) -#define OTP_DEBUG_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W1_S 0 - -/** OTP_DEBUG_BLK0_BACKUP1_W2_REG register - * Otp debuger block0 data register3. - */ -#define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8) -/** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word2 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP1_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W2_M (OTP_DEBUG_BLOCK0_BACKUP1_W2_V << OTP_DEBUG_BLOCK0_BACKUP1_W2_S) -#define OTP_DEBUG_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W2_S 0 - -/** OTP_DEBUG_BLK0_BACKUP1_W3_REG register - * Otp debuger block0 data register4. - */ -#define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc) -/** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word3 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP1_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W3_M (OTP_DEBUG_BLOCK0_BACKUP1_W3_V << OTP_DEBUG_BLOCK0_BACKUP1_W3_S) -#define OTP_DEBUG_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W3_S 0 - -/** OTP_DEBUG_BLK0_BACKUP1_W4_REG register - * Otp debuger block0 data register5. - */ -#define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10) -/** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word4 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP1_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W4_M (OTP_DEBUG_BLOCK0_BACKUP1_W4_V << OTP_DEBUG_BLOCK0_BACKUP1_W4_S) -#define OTP_DEBUG_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W4_S 0 - -/** OTP_DEBUG_BLK0_BACKUP1_W5_REG register - * Otp debuger block0 data register6. - */ -#define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14) -/** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word5 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP1_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W5_M (OTP_DEBUG_BLOCK0_BACKUP1_W5_V << OTP_DEBUG_BLOCK0_BACKUP1_W5_S) -#define OTP_DEBUG_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP1_W5_S 0 - -/** OTP_DEBUG_BLK0_BACKUP2_W1_REG register - * Otp debuger block0 data register7. - */ -#define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18) -/** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word1 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP2_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W1_M (OTP_DEBUG_BLOCK0_BACKUP2_W1_V << OTP_DEBUG_BLOCK0_BACKUP2_W1_S) -#define OTP_DEBUG_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W1_S 0 - -/** OTP_DEBUG_BLK0_BACKUP2_W2_REG register - * Otp debuger block0 data register8. - */ -#define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c) -/** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word2 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP2_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W2_M (OTP_DEBUG_BLOCK0_BACKUP2_W2_V << OTP_DEBUG_BLOCK0_BACKUP2_W2_S) -#define OTP_DEBUG_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W2_S 0 - -/** OTP_DEBUG_BLK0_BACKUP2_W3_REG register - * Otp debuger block0 data register9. - */ -#define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20) -/** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word3 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP2_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W3_M (OTP_DEBUG_BLOCK0_BACKUP2_W3_V << OTP_DEBUG_BLOCK0_BACKUP2_W3_S) -#define OTP_DEBUG_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W3_S 0 - -/** OTP_DEBUG_BLK0_BACKUP2_W4_REG register - * Otp debuger block0 data register10. - */ -#define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24) -/** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word4 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP2_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W4_M (OTP_DEBUG_BLOCK0_BACKUP2_W4_V << OTP_DEBUG_BLOCK0_BACKUP2_W4_S) -#define OTP_DEBUG_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W4_S 0 - -/** OTP_DEBUG_BLK0_BACKUP2_W5_REG register - * Otp debuger block0 data register11. - */ -#define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28) -/** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word5 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP2_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W5_M (OTP_DEBUG_BLOCK0_BACKUP2_W5_V << OTP_DEBUG_BLOCK0_BACKUP2_W5_S) -#define OTP_DEBUG_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP2_W5_S 0 - -/** OTP_DEBUG_BLK0_BACKUP3_W1_REG register - * Otp debuger block0 data register12. - */ -#define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c) -/** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word1 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP3_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W1_M (OTP_DEBUG_BLOCK0_BACKUP3_W1_V << OTP_DEBUG_BLOCK0_BACKUP3_W1_S) -#define OTP_DEBUG_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W1_S 0 - -/** OTP_DEBUG_BLK0_BACKUP3_W2_REG register - * Otp debuger block0 data register13. - */ -#define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30) -/** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word2 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP3_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W2_M (OTP_DEBUG_BLOCK0_BACKUP3_W2_V << OTP_DEBUG_BLOCK0_BACKUP3_W2_S) -#define OTP_DEBUG_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W2_S 0 - -/** OTP_DEBUG_BLK0_BACKUP3_W3_REG register - * Otp debuger block0 data register14. - */ -#define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34) -/** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word3 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP3_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W3_M (OTP_DEBUG_BLOCK0_BACKUP3_W3_V << OTP_DEBUG_BLOCK0_BACKUP3_W3_S) -#define OTP_DEBUG_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W3_S 0 - -/** OTP_DEBUG_BLK0_BACKUP3_W4_REG register - * Otp debuger block0 data register15. - */ -#define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38) -/** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word4 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP3_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W4_M (OTP_DEBUG_BLOCK0_BACKUP3_W4_V << OTP_DEBUG_BLOCK0_BACKUP3_W4_S) -#define OTP_DEBUG_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W4_S 0 - -/** OTP_DEBUG_BLK0_BACKUP3_W5_REG register - * Otp debuger block0 data register16. - */ -#define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c) -/** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word5 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP3_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W5_M (OTP_DEBUG_BLOCK0_BACKUP3_W5_V << OTP_DEBUG_BLOCK0_BACKUP3_W5_S) -#define OTP_DEBUG_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP3_W5_S 0 - -/** OTP_DEBUG_BLK0_BACKUP4_W1_REG register - * Otp debuger block0 data register17. - */ -#define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40) -/** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word1 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP4_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W1_M (OTP_DEBUG_BLOCK0_BACKUP4_W1_V << OTP_DEBUG_BLOCK0_BACKUP4_W1_S) -#define OTP_DEBUG_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W1_S 0 - -/** OTP_DEBUG_BLK0_BACKUP4_W2_REG register - * Otp debuger block0 data register18. - */ -#define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44) -/** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word2 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP4_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W2_M (OTP_DEBUG_BLOCK0_BACKUP4_W2_V << OTP_DEBUG_BLOCK0_BACKUP4_W2_S) -#define OTP_DEBUG_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W2_S 0 - -/** OTP_DEBUG_BLK0_BACKUP4_W3_REG register - * Otp debuger block0 data register19. - */ -#define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48) -/** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word3 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP4_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W3_M (OTP_DEBUG_BLOCK0_BACKUP4_W3_V << OTP_DEBUG_BLOCK0_BACKUP4_W3_S) -#define OTP_DEBUG_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W3_S 0 - -/** OTP_DEBUG_BLK0_BACKUP4_W4_REG register - * Otp debuger block0 data register20. - */ -#define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c) -/** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word4 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP4_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W4_M (OTP_DEBUG_BLOCK0_BACKUP4_W4_V << OTP_DEBUG_BLOCK0_BACKUP4_W4_S) -#define OTP_DEBUG_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W4_S 0 - -/** OTP_DEBUG_BLK0_BACKUP4_W5_REG register - * Otp debuger block0 data register21. - */ -#define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50) -/** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word5 data. - */ -#define OTP_DEBUG_BLOCK0_BACKUP4_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W5_M (OTP_DEBUG_BLOCK0_BACKUP4_W5_V << OTP_DEBUG_BLOCK0_BACKUP4_W5_S) -#define OTP_DEBUG_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK0_BACKUP4_W5_S 0 - -/** OTP_DEBUG_BLK1_W1_REG register - * Otp debuger block1 data register1. - */ -#define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54) -/** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word1 data. - */ -#define OTP_DEBUG_BLOCK1_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W1_M (OTP_DEBUG_BLOCK1_W1_V << OTP_DEBUG_BLOCK1_W1_S) -#define OTP_DEBUG_BLOCK1_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W1_S 0 - -/** OTP_DEBUG_BLK1_W2_REG register - * Otp debuger block1 data register2. - */ -#define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58) -/** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word2 data. - */ -#define OTP_DEBUG_BLOCK1_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W2_M (OTP_DEBUG_BLOCK1_W2_V << OTP_DEBUG_BLOCK1_W2_S) -#define OTP_DEBUG_BLOCK1_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W2_S 0 - -/** OTP_DEBUG_BLK1_W3_REG register - * Otp debuger block1 data register3. - */ -#define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c) -/** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word3 data. - */ -#define OTP_DEBUG_BLOCK1_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W3_M (OTP_DEBUG_BLOCK1_W3_V << OTP_DEBUG_BLOCK1_W3_S) -#define OTP_DEBUG_BLOCK1_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W3_S 0 - -/** OTP_DEBUG_BLK1_W4_REG register - * Otp debuger block1 data register4. - */ -#define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60) -/** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word4 data. - */ -#define OTP_DEBUG_BLOCK1_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W4_M (OTP_DEBUG_BLOCK1_W4_V << OTP_DEBUG_BLOCK1_W4_S) -#define OTP_DEBUG_BLOCK1_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W4_S 0 - -/** OTP_DEBUG_BLK1_W5_REG register - * Otp debuger block1 data register5. - */ -#define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64) -/** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word5 data. - */ -#define OTP_DEBUG_BLOCK1_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W5_M (OTP_DEBUG_BLOCK1_W5_V << OTP_DEBUG_BLOCK1_W5_S) -#define OTP_DEBUG_BLOCK1_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W5_S 0 - -/** OTP_DEBUG_BLK1_W6_REG register - * Otp debuger block1 data register6. - */ -#define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68) -/** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word6 data. - */ -#define OTP_DEBUG_BLOCK1_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W6_M (OTP_DEBUG_BLOCK1_W6_V << OTP_DEBUG_BLOCK1_W6_S) -#define OTP_DEBUG_BLOCK1_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W6_S 0 - -/** OTP_DEBUG_BLK1_W7_REG register - * Otp debuger block1 data register7. - */ -#define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c) -/** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word7 data. - */ -#define OTP_DEBUG_BLOCK1_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W7_M (OTP_DEBUG_BLOCK1_W7_V << OTP_DEBUG_BLOCK1_W7_S) -#define OTP_DEBUG_BLOCK1_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W7_S 0 - -/** OTP_DEBUG_BLK1_W8_REG register - * Otp debuger block1 data register8. - */ -#define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70) -/** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word8 data. - */ -#define OTP_DEBUG_BLOCK1_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W8_M (OTP_DEBUG_BLOCK1_W8_V << OTP_DEBUG_BLOCK1_W8_S) -#define OTP_DEBUG_BLOCK1_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W8_S 0 - -/** OTP_DEBUG_BLK1_W9_REG register - * Otp debuger block1 data register9. - */ -#define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74) -/** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word9 data. - */ -#define OTP_DEBUG_BLOCK1_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W9_M (OTP_DEBUG_BLOCK1_W9_V << OTP_DEBUG_BLOCK1_W9_S) -#define OTP_DEBUG_BLOCK1_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK1_W9_S 0 - -/** OTP_DEBUG_BLK2_W1_REG register - * Otp debuger block2 data register1. - */ -#define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78) -/** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word1 data. - */ -#define OTP_DEBUG_BLOCK2_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W1_M (OTP_DEBUG_BLOCK2_W1_V << OTP_DEBUG_BLOCK2_W1_S) -#define OTP_DEBUG_BLOCK2_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W1_S 0 - -/** OTP_DEBUG_BLK2_W2_REG register - * Otp debuger block2 data register2. - */ -#define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c) -/** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word2 data. - */ -#define OTP_DEBUG_BLOCK2_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W2_M (OTP_DEBUG_BLOCK2_W2_V << OTP_DEBUG_BLOCK2_W2_S) -#define OTP_DEBUG_BLOCK2_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W2_S 0 - -/** OTP_DEBUG_BLK2_W3_REG register - * Otp debuger block2 data register3. - */ -#define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80) -/** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word3 data. - */ -#define OTP_DEBUG_BLOCK2_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W3_M (OTP_DEBUG_BLOCK2_W3_V << OTP_DEBUG_BLOCK2_W3_S) -#define OTP_DEBUG_BLOCK2_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W3_S 0 - -/** OTP_DEBUG_BLK2_W4_REG register - * Otp debuger block2 data register4. - */ -#define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84) -/** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word4 data. - */ -#define OTP_DEBUG_BLOCK2_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W4_M (OTP_DEBUG_BLOCK2_W4_V << OTP_DEBUG_BLOCK2_W4_S) -#define OTP_DEBUG_BLOCK2_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W4_S 0 - -/** OTP_DEBUG_BLK2_W5_REG register - * Otp debuger block2 data register5. - */ -#define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88) -/** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word5 data. - */ -#define OTP_DEBUG_BLOCK2_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W5_M (OTP_DEBUG_BLOCK2_W5_V << OTP_DEBUG_BLOCK2_W5_S) -#define OTP_DEBUG_BLOCK2_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W5_S 0 - -/** OTP_DEBUG_BLK2_W6_REG register - * Otp debuger block2 data register6. - */ -#define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c) -/** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word6 data. - */ -#define OTP_DEBUG_BLOCK2_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W6_M (OTP_DEBUG_BLOCK2_W6_V << OTP_DEBUG_BLOCK2_W6_S) -#define OTP_DEBUG_BLOCK2_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W6_S 0 - -/** OTP_DEBUG_BLK2_W7_REG register - * Otp debuger block2 data register7. - */ -#define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90) -/** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word7 data. - */ -#define OTP_DEBUG_BLOCK2_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W7_M (OTP_DEBUG_BLOCK2_W7_V << OTP_DEBUG_BLOCK2_W7_S) -#define OTP_DEBUG_BLOCK2_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W7_S 0 - -/** OTP_DEBUG_BLK2_W8_REG register - * Otp debuger block2 data register8. - */ -#define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94) -/** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word8 data. - */ -#define OTP_DEBUG_BLOCK2_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W8_M (OTP_DEBUG_BLOCK2_W8_V << OTP_DEBUG_BLOCK2_W8_S) -#define OTP_DEBUG_BLOCK2_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W8_S 0 - -/** OTP_DEBUG_BLK2_W9_REG register - * Otp debuger block2 data register9. - */ -#define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98) -/** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word9 data. - */ -#define OTP_DEBUG_BLOCK2_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W9_M (OTP_DEBUG_BLOCK2_W9_V << OTP_DEBUG_BLOCK2_W9_S) -#define OTP_DEBUG_BLOCK2_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W9_S 0 - -/** OTP_DEBUG_BLK2_W10_REG register - * Otp debuger block2 data register10. - */ -#define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c) -/** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word10 data. - */ -#define OTP_DEBUG_BLOCK2_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W10_M (OTP_DEBUG_BLOCK2_W10_V << OTP_DEBUG_BLOCK2_W10_S) -#define OTP_DEBUG_BLOCK2_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W10_S 0 - -/** OTP_DEBUG_BLK2_W11_REG register - * Otp debuger block2 data register11. - */ -#define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0) -/** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word11 data. - */ -#define OTP_DEBUG_BLOCK2_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W11_M (OTP_DEBUG_BLOCK2_W11_V << OTP_DEBUG_BLOCK2_W11_S) -#define OTP_DEBUG_BLOCK2_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK2_W11_S 0 - -/** OTP_DEBUG_BLK3_W1_REG register - * Otp debuger block3 data register1. - */ -#define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4) -/** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word1 data. - */ -#define OTP_DEBUG_BLOCK3_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W1_M (OTP_DEBUG_BLOCK3_W1_V << OTP_DEBUG_BLOCK3_W1_S) -#define OTP_DEBUG_BLOCK3_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W1_S 0 - -/** OTP_DEBUG_BLK3_W2_REG register - * Otp debuger block3 data register2. - */ -#define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8) -/** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word2 data. - */ -#define OTP_DEBUG_BLOCK3_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W2_M (OTP_DEBUG_BLOCK3_W2_V << OTP_DEBUG_BLOCK3_W2_S) -#define OTP_DEBUG_BLOCK3_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W2_S 0 - -/** OTP_DEBUG_BLK3_W3_REG register - * Otp debuger block3 data register3. - */ -#define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac) -/** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word3 data. - */ -#define OTP_DEBUG_BLOCK3_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W3_M (OTP_DEBUG_BLOCK3_W3_V << OTP_DEBUG_BLOCK3_W3_S) -#define OTP_DEBUG_BLOCK3_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W3_S 0 - -/** OTP_DEBUG_BLK3_W4_REG register - * Otp debuger block3 data register4. - */ -#define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0) -/** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word4 data. - */ -#define OTP_DEBUG_BLOCK3_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W4_M (OTP_DEBUG_BLOCK3_W4_V << OTP_DEBUG_BLOCK3_W4_S) -#define OTP_DEBUG_BLOCK3_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W4_S 0 - -/** OTP_DEBUG_BLK3_W5_REG register - * Otp debuger block3 data register5. - */ -#define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4) -/** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word5 data. - */ -#define OTP_DEBUG_BLOCK3_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W5_M (OTP_DEBUG_BLOCK3_W5_V << OTP_DEBUG_BLOCK3_W5_S) -#define OTP_DEBUG_BLOCK3_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W5_S 0 - -/** OTP_DEBUG_BLK3_W6_REG register - * Otp debuger block3 data register6. - */ -#define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8) -/** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word6 data. - */ -#define OTP_DEBUG_BLOCK3_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W6_M (OTP_DEBUG_BLOCK3_W6_V << OTP_DEBUG_BLOCK3_W6_S) -#define OTP_DEBUG_BLOCK3_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W6_S 0 - -/** OTP_DEBUG_BLK3_W7_REG register - * Otp debuger block3 data register7. - */ -#define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc) -/** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word7 data. - */ -#define OTP_DEBUG_BLOCK3_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W7_M (OTP_DEBUG_BLOCK3_W7_V << OTP_DEBUG_BLOCK3_W7_S) -#define OTP_DEBUG_BLOCK3_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W7_S 0 - -/** OTP_DEBUG_BLK3_W8_REG register - * Otp debuger block3 data register8. - */ -#define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0) -/** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word8 data. - */ -#define OTP_DEBUG_BLOCK3_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W8_M (OTP_DEBUG_BLOCK3_W8_V << OTP_DEBUG_BLOCK3_W8_S) -#define OTP_DEBUG_BLOCK3_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W8_S 0 - -/** OTP_DEBUG_BLK3_W9_REG register - * Otp debuger block3 data register9. - */ -#define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4) -/** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word9 data. - */ -#define OTP_DEBUG_BLOCK3_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W9_M (OTP_DEBUG_BLOCK3_W9_V << OTP_DEBUG_BLOCK3_W9_S) -#define OTP_DEBUG_BLOCK3_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W9_S 0 - -/** OTP_DEBUG_BLK3_W10_REG register - * Otp debuger block3 data register10. - */ -#define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8) -/** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word10 data. - */ -#define OTP_DEBUG_BLOCK3_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W10_M (OTP_DEBUG_BLOCK3_W10_V << OTP_DEBUG_BLOCK3_W10_S) -#define OTP_DEBUG_BLOCK3_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W10_S 0 - -/** OTP_DEBUG_BLK3_W11_REG register - * Otp debuger block3 data register11. - */ -#define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc) -/** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word11 data. - */ -#define OTP_DEBUG_BLOCK3_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W11_M (OTP_DEBUG_BLOCK3_W11_V << OTP_DEBUG_BLOCK3_W11_S) -#define OTP_DEBUG_BLOCK3_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK3_W11_S 0 - -/** OTP_DEBUG_BLK4_W1_REG register - * Otp debuger block4 data register1. - */ -#define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0) -/** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word1 data. - */ -#define OTP_DEBUG_BLOCK4_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W1_M (OTP_DEBUG_BLOCK4_W1_V << OTP_DEBUG_BLOCK4_W1_S) -#define OTP_DEBUG_BLOCK4_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W1_S 0 - -/** OTP_DEBUG_BLK4_W2_REG register - * Otp debuger block4 data register2. - */ -#define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4) -/** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word2 data. - */ -#define OTP_DEBUG_BLOCK4_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W2_M (OTP_DEBUG_BLOCK4_W2_V << OTP_DEBUG_BLOCK4_W2_S) -#define OTP_DEBUG_BLOCK4_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W2_S 0 - -/** OTP_DEBUG_BLK4_W3_REG register - * Otp debuger block4 data register3. - */ -#define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8) -/** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word3 data. - */ -#define OTP_DEBUG_BLOCK4_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W3_M (OTP_DEBUG_BLOCK4_W3_V << OTP_DEBUG_BLOCK4_W3_S) -#define OTP_DEBUG_BLOCK4_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W3_S 0 - -/** OTP_DEBUG_BLK4_W4_REG register - * Otp debuger block4 data register4. - */ -#define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc) -/** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word4 data. - */ -#define OTP_DEBUG_BLOCK4_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W4_M (OTP_DEBUG_BLOCK4_W4_V << OTP_DEBUG_BLOCK4_W4_S) -#define OTP_DEBUG_BLOCK4_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W4_S 0 - -/** OTP_DEBUG_BLK4_W5_REG register - * Otp debuger block4 data register5. - */ -#define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0) -/** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word5 data. - */ -#define OTP_DEBUG_BLOCK4_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W5_M (OTP_DEBUG_BLOCK4_W5_V << OTP_DEBUG_BLOCK4_W5_S) -#define OTP_DEBUG_BLOCK4_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W5_S 0 - -/** OTP_DEBUG_BLK4_W6_REG register - * Otp debuger block4 data register6. - */ -#define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4) -/** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word6 data. - */ -#define OTP_DEBUG_BLOCK4_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W6_M (OTP_DEBUG_BLOCK4_W6_V << OTP_DEBUG_BLOCK4_W6_S) -#define OTP_DEBUG_BLOCK4_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W6_S 0 - -/** OTP_DEBUG_BLK4_W7_REG register - * Otp debuger block4 data register7. - */ -#define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8) -/** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word7 data. - */ -#define OTP_DEBUG_BLOCK4_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W7_M (OTP_DEBUG_BLOCK4_W7_V << OTP_DEBUG_BLOCK4_W7_S) -#define OTP_DEBUG_BLOCK4_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W7_S 0 - -/** OTP_DEBUG_BLK4_W8_REG register - * Otp debuger block4 data register8. - */ -#define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec) -/** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word8 data. - */ -#define OTP_DEBUG_BLOCK4_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W8_M (OTP_DEBUG_BLOCK4_W8_V << OTP_DEBUG_BLOCK4_W8_S) -#define OTP_DEBUG_BLOCK4_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W8_S 0 - -/** OTP_DEBUG_BLK4_W9_REG register - * Otp debuger block4 data register9. - */ -#define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0) -/** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word9 data. - */ -#define OTP_DEBUG_BLOCK4_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W9_M (OTP_DEBUG_BLOCK4_W9_V << OTP_DEBUG_BLOCK4_W9_S) -#define OTP_DEBUG_BLOCK4_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W9_S 0 - -/** OTP_DEBUG_BLK4_W10_REG register - * Otp debuger block4 data registe10. - */ -#define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4) -/** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word10 data. - */ -#define OTP_DEBUG_BLOCK4_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W10_M (OTP_DEBUG_BLOCK4_W10_V << OTP_DEBUG_BLOCK4_W10_S) -#define OTP_DEBUG_BLOCK4_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W10_S 0 - -/** OTP_DEBUG_BLK4_W11_REG register - * Otp debuger block4 data register11. - */ -#define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8) -/** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word11 data. - */ -#define OTP_DEBUG_BLOCK4_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W11_M (OTP_DEBUG_BLOCK4_W11_V << OTP_DEBUG_BLOCK4_W11_S) -#define OTP_DEBUG_BLOCK4_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK4_W11_S 0 - -/** OTP_DEBUG_BLK5_W1_REG register - * Otp debuger block5 data register1. - */ -#define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc) -/** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word1 data. - */ -#define OTP_DEBUG_BLOCK5_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W1_M (OTP_DEBUG_BLOCK5_W1_V << OTP_DEBUG_BLOCK5_W1_S) -#define OTP_DEBUG_BLOCK5_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W1_S 0 - -/** OTP_DEBUG_BLK5_W2_REG register - * Otp debuger block5 data register2. - */ -#define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100) -/** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word2 data. - */ -#define OTP_DEBUG_BLOCK5_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W2_M (OTP_DEBUG_BLOCK5_W2_V << OTP_DEBUG_BLOCK5_W2_S) -#define OTP_DEBUG_BLOCK5_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W2_S 0 - -/** OTP_DEBUG_BLK5_W3_REG register - * Otp debuger block5 data register3. - */ -#define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104) -/** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word3 data. - */ -#define OTP_DEBUG_BLOCK5_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W3_M (OTP_DEBUG_BLOCK5_W3_V << OTP_DEBUG_BLOCK5_W3_S) -#define OTP_DEBUG_BLOCK5_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W3_S 0 - -/** OTP_DEBUG_BLK5_W4_REG register - * Otp debuger block5 data register4. - */ -#define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108) -/** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word4 data. - */ -#define OTP_DEBUG_BLOCK5_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W4_M (OTP_DEBUG_BLOCK5_W4_V << OTP_DEBUG_BLOCK5_W4_S) -#define OTP_DEBUG_BLOCK5_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W4_S 0 - -/** OTP_DEBUG_BLK5_W5_REG register - * Otp debuger block5 data register5. - */ -#define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c) -/** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word5 data. - */ -#define OTP_DEBUG_BLOCK5_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W5_M (OTP_DEBUG_BLOCK5_W5_V << OTP_DEBUG_BLOCK5_W5_S) -#define OTP_DEBUG_BLOCK5_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W5_S 0 - -/** OTP_DEBUG_BLK5_W6_REG register - * Otp debuger block5 data register6. - */ -#define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110) -/** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word6 data. - */ -#define OTP_DEBUG_BLOCK5_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W6_M (OTP_DEBUG_BLOCK5_W6_V << OTP_DEBUG_BLOCK5_W6_S) -#define OTP_DEBUG_BLOCK5_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W6_S 0 - -/** OTP_DEBUG_BLK5_W7_REG register - * Otp debuger block5 data register7. - */ -#define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114) -/** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word7 data. - */ -#define OTP_DEBUG_BLOCK5_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W7_M (OTP_DEBUG_BLOCK5_W7_V << OTP_DEBUG_BLOCK5_W7_S) -#define OTP_DEBUG_BLOCK5_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W7_S 0 - -/** OTP_DEBUG_BLK5_W8_REG register - * Otp debuger block5 data register8. - */ -#define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118) -/** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word8 data. - */ -#define OTP_DEBUG_BLOCK5_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W8_M (OTP_DEBUG_BLOCK5_W8_V << OTP_DEBUG_BLOCK5_W8_S) -#define OTP_DEBUG_BLOCK5_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W8_S 0 - -/** OTP_DEBUG_BLK5_W9_REG register - * Otp debuger block5 data register9. - */ -#define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c) -/** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word9 data. - */ -#define OTP_DEBUG_BLOCK5_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W9_M (OTP_DEBUG_BLOCK5_W9_V << OTP_DEBUG_BLOCK5_W9_S) -#define OTP_DEBUG_BLOCK5_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W9_S 0 - -/** OTP_DEBUG_BLK5_W10_REG register - * Otp debuger block5 data register10. - */ -#define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120) -/** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word10 data. - */ -#define OTP_DEBUG_BLOCK5_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W10_M (OTP_DEBUG_BLOCK5_W10_V << OTP_DEBUG_BLOCK5_W10_S) -#define OTP_DEBUG_BLOCK5_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W10_S 0 - -/** OTP_DEBUG_BLK5_W11_REG register - * Otp debuger block5 data register11. - */ -#define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124) -/** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word11 data. - */ -#define OTP_DEBUG_BLOCK5_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W11_M (OTP_DEBUG_BLOCK5_W11_V << OTP_DEBUG_BLOCK5_W11_S) -#define OTP_DEBUG_BLOCK5_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK5_W11_S 0 - -/** OTP_DEBUG_BLK6_W1_REG register - * Otp debuger block6 data register1. - */ -#define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128) -/** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word1 data. - */ -#define OTP_DEBUG_BLOCK6_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W1_M (OTP_DEBUG_BLOCK6_W1_V << OTP_DEBUG_BLOCK6_W1_S) -#define OTP_DEBUG_BLOCK6_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W1_S 0 - -/** OTP_DEBUG_BLK6_W2_REG register - * Otp debuger block6 data register2. - */ -#define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c) -/** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word2 data. - */ -#define OTP_DEBUG_BLOCK6_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W2_M (OTP_DEBUG_BLOCK6_W2_V << OTP_DEBUG_BLOCK6_W2_S) -#define OTP_DEBUG_BLOCK6_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W2_S 0 - -/** OTP_DEBUG_BLK6_W3_REG register - * Otp debuger block6 data register3. - */ -#define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130) -/** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word3 data. - */ -#define OTP_DEBUG_BLOCK6_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W3_M (OTP_DEBUG_BLOCK6_W3_V << OTP_DEBUG_BLOCK6_W3_S) -#define OTP_DEBUG_BLOCK6_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W3_S 0 - -/** OTP_DEBUG_BLK6_W4_REG register - * Otp debuger block6 data register4. - */ -#define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134) -/** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word4 data. - */ -#define OTP_DEBUG_BLOCK6_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W4_M (OTP_DEBUG_BLOCK6_W4_V << OTP_DEBUG_BLOCK6_W4_S) -#define OTP_DEBUG_BLOCK6_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W4_S 0 - -/** OTP_DEBUG_BLK6_W5_REG register - * Otp debuger block6 data register5. - */ -#define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138) -/** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word5 data. - */ -#define OTP_DEBUG_BLOCK6_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W5_M (OTP_DEBUG_BLOCK6_W5_V << OTP_DEBUG_BLOCK6_W5_S) -#define OTP_DEBUG_BLOCK6_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W5_S 0 - -/** OTP_DEBUG_BLK6_W6_REG register - * Otp debuger block6 data register6. - */ -#define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c) -/** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word6 data. - */ -#define OTP_DEBUG_BLOCK6_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W6_M (OTP_DEBUG_BLOCK6_W6_V << OTP_DEBUG_BLOCK6_W6_S) -#define OTP_DEBUG_BLOCK6_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W6_S 0 - -/** OTP_DEBUG_BLK6_W7_REG register - * Otp debuger block6 data register7. - */ -#define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140) -/** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word7 data. - */ -#define OTP_DEBUG_BLOCK6_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W7_M (OTP_DEBUG_BLOCK6_W7_V << OTP_DEBUG_BLOCK6_W7_S) -#define OTP_DEBUG_BLOCK6_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W7_S 0 - -/** OTP_DEBUG_BLK6_W8_REG register - * Otp debuger block6 data register8. - */ -#define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144) -/** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word8 data. - */ -#define OTP_DEBUG_BLOCK6_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W8_M (OTP_DEBUG_BLOCK6_W8_V << OTP_DEBUG_BLOCK6_W8_S) -#define OTP_DEBUG_BLOCK6_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W8_S 0 - -/** OTP_DEBUG_BLK6_W9_REG register - * Otp debuger block6 data register9. - */ -#define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148) -/** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word9 data. - */ -#define OTP_DEBUG_BLOCK6_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W9_M (OTP_DEBUG_BLOCK6_W9_V << OTP_DEBUG_BLOCK6_W9_S) -#define OTP_DEBUG_BLOCK6_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W9_S 0 - -/** OTP_DEBUG_BLK6_W10_REG register - * Otp debuger block6 data register10. - */ -#define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c) -/** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word10 data. - */ -#define OTP_DEBUG_BLOCK6_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W10_M (OTP_DEBUG_BLOCK6_W10_V << OTP_DEBUG_BLOCK6_W10_S) -#define OTP_DEBUG_BLOCK6_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W10_S 0 - -/** OTP_DEBUG_BLK6_W11_REG register - * Otp debuger block6 data register11. - */ -#define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150) -/** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word11 data. - */ -#define OTP_DEBUG_BLOCK6_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W11_M (OTP_DEBUG_BLOCK6_W11_V << OTP_DEBUG_BLOCK6_W11_S) -#define OTP_DEBUG_BLOCK6_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK6_W11_S 0 - -/** OTP_DEBUG_BLK7_W1_REG register - * Otp debuger block7 data register1. - */ -#define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154) -/** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word1 data. - */ -#define OTP_DEBUG_BLOCK7_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W1_M (OTP_DEBUG_BLOCK7_W1_V << OTP_DEBUG_BLOCK7_W1_S) -#define OTP_DEBUG_BLOCK7_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W1_S 0 - -/** OTP_DEBUG_BLK7_W2_REG register - * Otp debuger block7 data register2. - */ -#define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158) -/** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word2 data. - */ -#define OTP_DEBUG_BLOCK7_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W2_M (OTP_DEBUG_BLOCK7_W2_V << OTP_DEBUG_BLOCK7_W2_S) -#define OTP_DEBUG_BLOCK7_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W2_S 0 - -/** OTP_DEBUG_BLK7_W3_REG register - * Otp debuger block7 data register3. - */ -#define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c) -/** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word3 data. - */ -#define OTP_DEBUG_BLOCK7_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W3_M (OTP_DEBUG_BLOCK7_W3_V << OTP_DEBUG_BLOCK7_W3_S) -#define OTP_DEBUG_BLOCK7_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W3_S 0 - -/** OTP_DEBUG_BLK7_W4_REG register - * Otp debuger block7 data register4. - */ -#define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160) -/** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word4 data. - */ -#define OTP_DEBUG_BLOCK7_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W4_M (OTP_DEBUG_BLOCK7_W4_V << OTP_DEBUG_BLOCK7_W4_S) -#define OTP_DEBUG_BLOCK7_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W4_S 0 - -/** OTP_DEBUG_BLK7_W5_REG register - * Otp debuger block7 data register5. - */ -#define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164) -/** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word5 data. - */ -#define OTP_DEBUG_BLOCK7_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W5_M (OTP_DEBUG_BLOCK7_W5_V << OTP_DEBUG_BLOCK7_W5_S) -#define OTP_DEBUG_BLOCK7_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W5_S 0 - -/** OTP_DEBUG_BLK7_W6_REG register - * Otp debuger block7 data register6. - */ -#define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168) -/** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word6 data. - */ -#define OTP_DEBUG_BLOCK7_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W6_M (OTP_DEBUG_BLOCK7_W6_V << OTP_DEBUG_BLOCK7_W6_S) -#define OTP_DEBUG_BLOCK7_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W6_S 0 - -/** OTP_DEBUG_BLK7_W7_REG register - * Otp debuger block7 data register7. - */ -#define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c) -/** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word7 data. - */ -#define OTP_DEBUG_BLOCK7_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W7_M (OTP_DEBUG_BLOCK7_W7_V << OTP_DEBUG_BLOCK7_W7_S) -#define OTP_DEBUG_BLOCK7_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W7_S 0 - -/** OTP_DEBUG_BLK7_W8_REG register - * Otp debuger block7 data register8. - */ -#define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170) -/** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word8 data. - */ -#define OTP_DEBUG_BLOCK7_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W8_M (OTP_DEBUG_BLOCK7_W8_V << OTP_DEBUG_BLOCK7_W8_S) -#define OTP_DEBUG_BLOCK7_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W8_S 0 - -/** OTP_DEBUG_BLK7_W9_REG register - * Otp debuger block7 data register9. - */ -#define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174) -/** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word9 data. - */ -#define OTP_DEBUG_BLOCK7_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W9_M (OTP_DEBUG_BLOCK7_W9_V << OTP_DEBUG_BLOCK7_W9_S) -#define OTP_DEBUG_BLOCK7_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W9_S 0 - -/** OTP_DEBUG_BLK7_W10_REG register - * Otp debuger block7 data register10. - */ -#define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178) -/** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word10 data. - */ -#define OTP_DEBUG_BLOCK7_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W10_M (OTP_DEBUG_BLOCK7_W10_V << OTP_DEBUG_BLOCK7_W10_S) -#define OTP_DEBUG_BLOCK7_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W10_S 0 - -/** OTP_DEBUG_BLK7_W11_REG register - * Otp debuger block7 data register11. - */ -#define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c) -/** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word11 data. - */ -#define OTP_DEBUG_BLOCK7_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W11_M (OTP_DEBUG_BLOCK7_W11_V << OTP_DEBUG_BLOCK7_W11_S) -#define OTP_DEBUG_BLOCK7_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK7_W11_S 0 - -/** OTP_DEBUG_BLK8_W1_REG register - * Otp debuger block8 data register1. - */ -#define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180) -/** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word1 data. - */ -#define OTP_DEBUG_BLOCK8_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W1_M (OTP_DEBUG_BLOCK8_W1_V << OTP_DEBUG_BLOCK8_W1_S) -#define OTP_DEBUG_BLOCK8_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W1_S 0 - -/** OTP_DEBUG_BLK8_W2_REG register - * Otp debuger block8 data register2. - */ -#define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184) -/** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word2 data. - */ -#define OTP_DEBUG_BLOCK8_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W2_M (OTP_DEBUG_BLOCK8_W2_V << OTP_DEBUG_BLOCK8_W2_S) -#define OTP_DEBUG_BLOCK8_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W2_S 0 - -/** OTP_DEBUG_BLK8_W3_REG register - * Otp debuger block8 data register3. - */ -#define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188) -/** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word3 data. - */ -#define OTP_DEBUG_BLOCK8_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W3_M (OTP_DEBUG_BLOCK8_W3_V << OTP_DEBUG_BLOCK8_W3_S) -#define OTP_DEBUG_BLOCK8_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W3_S 0 - -/** OTP_DEBUG_BLK8_W4_REG register - * Otp debuger block8 data register4. - */ -#define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c) -/** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word4 data. - */ -#define OTP_DEBUG_BLOCK8_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W4_M (OTP_DEBUG_BLOCK8_W4_V << OTP_DEBUG_BLOCK8_W4_S) -#define OTP_DEBUG_BLOCK8_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W4_S 0 - -/** OTP_DEBUG_BLK8_W5_REG register - * Otp debuger block8 data register5. - */ -#define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190) -/** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word5 data. - */ -#define OTP_DEBUG_BLOCK8_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W5_M (OTP_DEBUG_BLOCK8_W5_V << OTP_DEBUG_BLOCK8_W5_S) -#define OTP_DEBUG_BLOCK8_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W5_S 0 - -/** OTP_DEBUG_BLK8_W6_REG register - * Otp debuger block8 data register6. - */ -#define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194) -/** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word6 data. - */ -#define OTP_DEBUG_BLOCK8_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W6_M (OTP_DEBUG_BLOCK8_W6_V << OTP_DEBUG_BLOCK8_W6_S) -#define OTP_DEBUG_BLOCK8_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W6_S 0 - -/** OTP_DEBUG_BLK8_W7_REG register - * Otp debuger block8 data register7. - */ -#define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198) -/** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word7 data. - */ -#define OTP_DEBUG_BLOCK8_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W7_M (OTP_DEBUG_BLOCK8_W7_V << OTP_DEBUG_BLOCK8_W7_S) -#define OTP_DEBUG_BLOCK8_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W7_S 0 - -/** OTP_DEBUG_BLK8_W8_REG register - * Otp debuger block8 data register8. - */ -#define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c) -/** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word8 data. - */ -#define OTP_DEBUG_BLOCK8_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W8_M (OTP_DEBUG_BLOCK8_W8_V << OTP_DEBUG_BLOCK8_W8_S) -#define OTP_DEBUG_BLOCK8_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W8_S 0 - -/** OTP_DEBUG_BLK8_W9_REG register - * Otp debuger block8 data register9. - */ -#define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0) -/** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word9 data. - */ -#define OTP_DEBUG_BLOCK8_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W9_M (OTP_DEBUG_BLOCK8_W9_V << OTP_DEBUG_BLOCK8_W9_S) -#define OTP_DEBUG_BLOCK8_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W9_S 0 - -/** OTP_DEBUG_BLK8_W10_REG register - * Otp debuger block8 data register10. - */ -#define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4) -/** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word10 data. - */ -#define OTP_DEBUG_BLOCK8_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W10_M (OTP_DEBUG_BLOCK8_W10_V << OTP_DEBUG_BLOCK8_W10_S) -#define OTP_DEBUG_BLOCK8_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W10_S 0 - -/** OTP_DEBUG_BLK8_W11_REG register - * Otp debuger block8 data register11. - */ -#define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8) -/** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word11 data. - */ -#define OTP_DEBUG_BLOCK8_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W11_M (OTP_DEBUG_BLOCK8_W11_V << OTP_DEBUG_BLOCK8_W11_S) -#define OTP_DEBUG_BLOCK8_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK8_W11_S 0 - -/** OTP_DEBUG_BLK9_W1_REG register - * Otp debuger block9 data register1. - */ -#define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac) -/** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word1 data. - */ -#define OTP_DEBUG_BLOCK9_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W1_M (OTP_DEBUG_BLOCK9_W1_V << OTP_DEBUG_BLOCK9_W1_S) -#define OTP_DEBUG_BLOCK9_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W1_S 0 - -/** OTP_DEBUG_BLK9_W2_REG register - * Otp debuger block9 data register2. - */ -#define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0) -/** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word2 data. - */ -#define OTP_DEBUG_BLOCK9_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W2_M (OTP_DEBUG_BLOCK9_W2_V << OTP_DEBUG_BLOCK9_W2_S) -#define OTP_DEBUG_BLOCK9_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W2_S 0 - -/** OTP_DEBUG_BLK9_W3_REG register - * Otp debuger block9 data register3. - */ -#define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4) -/** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word3 data. - */ -#define OTP_DEBUG_BLOCK9_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W3_M (OTP_DEBUG_BLOCK9_W3_V << OTP_DEBUG_BLOCK9_W3_S) -#define OTP_DEBUG_BLOCK9_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W3_S 0 - -/** OTP_DEBUG_BLK9_W4_REG register - * Otp debuger block9 data register4. - */ -#define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8) -/** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word4 data. - */ -#define OTP_DEBUG_BLOCK9_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W4_M (OTP_DEBUG_BLOCK9_W4_V << OTP_DEBUG_BLOCK9_W4_S) -#define OTP_DEBUG_BLOCK9_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W4_S 0 - -/** OTP_DEBUG_BLK9_W5_REG register - * Otp debuger block9 data register5. - */ -#define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc) -/** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word5 data. - */ -#define OTP_DEBUG_BLOCK9_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W5_M (OTP_DEBUG_BLOCK9_W5_V << OTP_DEBUG_BLOCK9_W5_S) -#define OTP_DEBUG_BLOCK9_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W5_S 0 - -/** OTP_DEBUG_BLK9_W6_REG register - * Otp debuger block9 data register6. - */ -#define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0) -/** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word6 data. - */ -#define OTP_DEBUG_BLOCK9_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W6_M (OTP_DEBUG_BLOCK9_W6_V << OTP_DEBUG_BLOCK9_W6_S) -#define OTP_DEBUG_BLOCK9_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W6_S 0 - -/** OTP_DEBUG_BLK9_W7_REG register - * Otp debuger block9 data register7. - */ -#define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4) -/** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word7 data. - */ -#define OTP_DEBUG_BLOCK9_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W7_M (OTP_DEBUG_BLOCK9_W7_V << OTP_DEBUG_BLOCK9_W7_S) -#define OTP_DEBUG_BLOCK9_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W7_S 0 - -/** OTP_DEBUG_BLK9_W8_REG register - * Otp debuger block9 data register8. - */ -#define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8) -/** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word8 data. - */ -#define OTP_DEBUG_BLOCK9_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W8_M (OTP_DEBUG_BLOCK9_W8_V << OTP_DEBUG_BLOCK9_W8_S) -#define OTP_DEBUG_BLOCK9_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W8_S 0 - -/** OTP_DEBUG_BLK9_W9_REG register - * Otp debuger block9 data register9. - */ -#define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc) -/** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word9 data. - */ -#define OTP_DEBUG_BLOCK9_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W9_M (OTP_DEBUG_BLOCK9_W9_V << OTP_DEBUG_BLOCK9_W9_S) -#define OTP_DEBUG_BLOCK9_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W9_S 0 - -/** OTP_DEBUG_BLK9_W10_REG register - * Otp debuger block9 data register10. - */ -#define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0) -/** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word10 data. - */ -#define OTP_DEBUG_BLOCK9_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W10_M (OTP_DEBUG_BLOCK9_W10_V << OTP_DEBUG_BLOCK9_W10_S) -#define OTP_DEBUG_BLOCK9_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W10_S 0 - -/** OTP_DEBUG_BLK9_W11_REG register - * Otp debuger block9 data register11. - */ -#define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4) -/** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word11 data. - */ -#define OTP_DEBUG_BLOCK9_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W11_M (OTP_DEBUG_BLOCK9_W11_V << OTP_DEBUG_BLOCK9_W11_S) -#define OTP_DEBUG_BLOCK9_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK9_W11_S 0 - -/** OTP_DEBUG_BLK10_W1_REG register - * Otp debuger block10 data register1. - */ -#define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8) -/** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word1 data. - */ -#define OTP_DEBUG_BLOCK10_W1 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W1_M (OTP_DEBUG_BLOCK10_W1_V << OTP_DEBUG_BLOCK10_W1_S) -#define OTP_DEBUG_BLOCK10_W1_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W1_S 0 - -/** OTP_DEBUG_BLK10_W2_REG register - * Otp debuger block10 data register2. - */ -#define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc) -/** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word2 data. - */ -#define OTP_DEBUG_BLOCK10_W2 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W2_M (OTP_DEBUG_BLOCK10_W2_V << OTP_DEBUG_BLOCK10_W2_S) -#define OTP_DEBUG_BLOCK10_W2_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W2_S 0 - -/** OTP_DEBUG_BLK10_W3_REG register - * Otp debuger block10 data register3. - */ -#define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0) -/** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word3 data. - */ -#define OTP_DEBUG_BLOCK10_W3 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W3_M (OTP_DEBUG_BLOCK10_W3_V << OTP_DEBUG_BLOCK10_W3_S) -#define OTP_DEBUG_BLOCK10_W3_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W3_S 0 - -/** OTP_DEBUG_BLK10_W4_REG register - * Otp debuger block10 data register4. - */ -#define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4) -/** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word4 data. - */ -#define OTP_DEBUG_BLOCK10_W4 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W4_M (OTP_DEBUG_BLOCK10_W4_V << OTP_DEBUG_BLOCK10_W4_S) -#define OTP_DEBUG_BLOCK10_W4_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W4_S 0 - -/** OTP_DEBUG_BLK10_W5_REG register - * Otp debuger block10 data register5. - */ -#define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8) -/** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word5 data. - */ -#define OTP_DEBUG_BLOCK10_W5 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W5_M (OTP_DEBUG_BLOCK10_W5_V << OTP_DEBUG_BLOCK10_W5_S) -#define OTP_DEBUG_BLOCK10_W5_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W5_S 0 - -/** OTP_DEBUG_BLK10_W6_REG register - * Otp debuger block10 data register6. - */ -#define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec) -/** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word6 data. - */ -#define OTP_DEBUG_BLOCK10_W6 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W6_M (OTP_DEBUG_BLOCK10_W6_V << OTP_DEBUG_BLOCK10_W6_S) -#define OTP_DEBUG_BLOCK10_W6_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W6_S 0 - -/** OTP_DEBUG_BLK10_W7_REG register - * Otp debuger block10 data register7. - */ -#define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0) -/** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word7 data. - */ -#define OTP_DEBUG_BLOCK10_W7 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W7_M (OTP_DEBUG_BLOCK10_W7_V << OTP_DEBUG_BLOCK10_W7_S) -#define OTP_DEBUG_BLOCK10_W7_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W7_S 0 - -/** OTP_DEBUG_BLK10_W8_REG register - * Otp debuger block10 data register8. - */ -#define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4) -/** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word8 data. - */ -#define OTP_DEBUG_BLOCK10_W8 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W8_M (OTP_DEBUG_BLOCK10_W8_V << OTP_DEBUG_BLOCK10_W8_S) -#define OTP_DEBUG_BLOCK10_W8_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W8_S 0 - -/** OTP_DEBUG_BLK10_W9_REG register - * Otp debuger block10 data register9. - */ -#define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8) -/** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word9 data. - */ -#define OTP_DEBUG_BLOCK10_W9 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W9_M (OTP_DEBUG_BLOCK10_W9_V << OTP_DEBUG_BLOCK10_W9_S) -#define OTP_DEBUG_BLOCK10_W9_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W9_S 0 - -/** OTP_DEBUG_BLK10_W10_REG register - * Otp debuger block10 data register10. - */ -#define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc) -/** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word10 data. - */ -#define OTP_DEBUG_BLOCK19_W10 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK19_W10_M (OTP_DEBUG_BLOCK19_W10_V << OTP_DEBUG_BLOCK19_W10_S) -#define OTP_DEBUG_BLOCK19_W10_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK19_W10_S 0 - -/** OTP_DEBUG_BLK10_W11_REG register - * Otp debuger block10 data register11. - */ -#define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200) -/** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ -#define OTP_DEBUG_BLOCK10_W11 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W11_M (OTP_DEBUG_BLOCK10_W11_V << OTP_DEBUG_BLOCK10_W11_S) -#define OTP_DEBUG_BLOCK10_W11_V 0xFFFFFFFFU -#define OTP_DEBUG_BLOCK10_W11_S 0 - -/** OTP_DEBUG_CLK_REG register - * Otp debuger clk_en configuration register. - */ -#define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204) -/** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0; - * Force clock on for this register file. - */ -#define OTP_DEBUG_CLK_EN (BIT(0)) -#define OTP_DEBUG_CLK_EN_M (OTP_DEBUG_CLK_EN_V << OTP_DEBUG_CLK_EN_S) -#define OTP_DEBUG_CLK_EN_V 0x00000001U -#define OTP_DEBUG_CLK_EN_S 0 - -/** OTP_DEBUG_APB2OTP_EN_REG register - * Otp_debuger apb2otp enable configuration register. - */ -#define OTP_DEBUG_APB2OTP_EN_REG (DR_REG_OTP_DEBUG_BASE + 0x208) -/** OTP_DEBUG_APB2OTP_EN : R/W; bitpos: [0]; default: 0; - * Debug mode enable signal. - */ -#define OTP_DEBUG_APB2OTP_EN (BIT(0)) -#define OTP_DEBUG_APB2OTP_EN_M (OTP_DEBUG_APB2OTP_EN_V << OTP_DEBUG_APB2OTP_EN_S) -#define OTP_DEBUG_APB2OTP_EN_V 0x00000001U -#define OTP_DEBUG_APB2OTP_EN_S 0 - -/** OTP_DEBUG_DATE_REG register - * eFuse version register. - */ -#define OTP_DEBUG_DATE_REG (DR_REG_OTP_DEBUG_BASE + 0x20c) -/** OTP_DEBUG_DATE : R/W; bitpos: [27:0]; default: 539037736; - * Stores otp_debug version. - */ -#define OTP_DEBUG_DATE 0x0FFFFFFFU -#define OTP_DEBUG_DATE_M (OTP_DEBUG_DATE_V << OTP_DEBUG_DATE_S) -#define OTP_DEBUG_DATE_V 0x0FFFFFFFU -#define OTP_DEBUG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/otp_debug_struct.h b/components/soc/esp32p4/include/soc/otp_debug_struct.h deleted file mode 100644 index 8166a857cb..0000000000 --- a/components/soc/esp32p4/include/soc/otp_debug_struct.h +++ /dev/null @@ -1,2137 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: OTP_DEBUG Block0 Write Disable Data */ -/** Type of wr_dis register - * Otp debuger block0 data register1. - */ -typedef union { - struct { - /** block0_wr_dis : RO; bitpos: [31:0]; default: 0; - * Otp block0 write disable data. - */ - uint32_t block0_wr_dis:32; - }; - uint32_t val; -} otp_debug_wr_dis_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup1 Word1 Data */ -/** Type of blk0_backup1_w1 register - * Otp debuger block0 data register2. - */ -typedef union { - struct { - /** block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word1 data. - */ - uint32_t block0_backup1_w1:32; - }; - uint32_t val; -} otp_debug_blk0_backup1_w1_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup1 Word2 Data */ -/** Type of blk0_backup1_w2 register - * Otp debuger block0 data register3. - */ -typedef union { - struct { - /** block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word2 data. - */ - uint32_t block0_backup1_w2:32; - }; - uint32_t val; -} otp_debug_blk0_backup1_w2_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup1 Word3 Data */ -/** Type of blk0_backup1_w3 register - * Otp debuger block0 data register4. - */ -typedef union { - struct { - /** block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word3 data. - */ - uint32_t block0_backup1_w3:32; - }; - uint32_t val; -} otp_debug_blk0_backup1_w3_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup1 Word4 Data */ -/** Type of blk0_backup1_w4 register - * Otp debuger block0 data register5. - */ -typedef union { - struct { - /** block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word4 data. - */ - uint32_t block0_backup1_w4:32; - }; - uint32_t val; -} otp_debug_blk0_backup1_w4_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup1 Word5 Data */ -/** Type of blk0_backup1_w5 register - * Otp debuger block0 data register6. - */ -typedef union { - struct { - /** block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word5 data. - */ - uint32_t block0_backup1_w5:32; - }; - uint32_t val; -} otp_debug_blk0_backup1_w5_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup2 Word1 Data */ -/** Type of blk0_backup2_w1 register - * Otp debuger block0 data register7. - */ -typedef union { - struct { - /** block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word1 data. - */ - uint32_t block0_backup2_w1:32; - }; - uint32_t val; -} otp_debug_blk0_backup2_w1_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup2 Word2 Data */ -/** Type of blk0_backup2_w2 register - * Otp debuger block0 data register8. - */ -typedef union { - struct { - /** block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word2 data. - */ - uint32_t block0_backup2_w2:32; - }; - uint32_t val; -} otp_debug_blk0_backup2_w2_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup2 Word3 Data */ -/** Type of blk0_backup2_w3 register - * Otp debuger block0 data register9. - */ -typedef union { - struct { - /** block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word3 data. - */ - uint32_t block0_backup2_w3:32; - }; - uint32_t val; -} otp_debug_blk0_backup2_w3_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup2 Word4 Data */ -/** Type of blk0_backup2_w4 register - * Otp debuger block0 data register10. - */ -typedef union { - struct { - /** block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word4 data. - */ - uint32_t block0_backup2_w4:32; - }; - uint32_t val; -} otp_debug_blk0_backup2_w4_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup2 Word5 Data */ -/** Type of blk0_backup2_w5 register - * Otp debuger block0 data register11. - */ -typedef union { - struct { - /** block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word5 data. - */ - uint32_t block0_backup2_w5:32; - }; - uint32_t val; -} otp_debug_blk0_backup2_w5_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup3 Word1 Data */ -/** Type of blk0_backup3_w1 register - * Otp debuger block0 data register12. - */ -typedef union { - struct { - /** block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word1 data. - */ - uint32_t block0_backup3_w1:32; - }; - uint32_t val; -} otp_debug_blk0_backup3_w1_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup3 Word2 Data */ -/** Type of blk0_backup3_w2 register - * Otp debuger block0 data register13. - */ -typedef union { - struct { - /** block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word2 data. - */ - uint32_t block0_backup3_w2:32; - }; - uint32_t val; -} otp_debug_blk0_backup3_w2_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup3 Word3 Data */ -/** Type of blk0_backup3_w3 register - * Otp debuger block0 data register14. - */ -typedef union { - struct { - /** block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word3 data. - */ - uint32_t block0_backup3_w3:32; - }; - uint32_t val; -} otp_debug_blk0_backup3_w3_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup3 Word4 Data */ -/** Type of blk0_backup3_w4 register - * Otp debuger block0 data register15. - */ -typedef union { - struct { - /** block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word4 data. - */ - uint32_t block0_backup3_w4:32; - }; - uint32_t val; -} otp_debug_blk0_backup3_w4_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup3 Word5 Data */ -/** Type of blk0_backup3_w5 register - * Otp debuger block0 data register16. - */ -typedef union { - struct { - /** block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word5 data. - */ - uint32_t block0_backup3_w5:32; - }; - uint32_t val; -} otp_debug_blk0_backup3_w5_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup4 Word1 Data */ -/** Type of blk0_backup4_w1 register - * Otp debuger block0 data register17. - */ -typedef union { - struct { - /** block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word1 data. - */ - uint32_t block0_backup4_w1:32; - }; - uint32_t val; -} otp_debug_blk0_backup4_w1_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup4 Word2 Data */ -/** Type of blk0_backup4_w2 register - * Otp debuger block0 data register18. - */ -typedef union { - struct { - /** block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word2 data. - */ - uint32_t block0_backup4_w2:32; - }; - uint32_t val; -} otp_debug_blk0_backup4_w2_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup4 Word3 Data */ -/** Type of blk0_backup4_w3 register - * Otp debuger block0 data register19. - */ -typedef union { - struct { - /** block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word3 data. - */ - uint32_t block0_backup4_w3:32; - }; - uint32_t val; -} otp_debug_blk0_backup4_w3_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup4 Word4 Data */ -/** Type of blk0_backup4_w4 register - * Otp debuger block0 data register20. - */ -typedef union { - struct { - /** block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word4 data. - */ - uint32_t block0_backup4_w4:32; - }; - uint32_t val; -} otp_debug_blk0_backup4_w4_reg_t; - - -/** Group: OTP_DEBUG Block0 Backup4 Word5 Data */ -/** Type of blk0_backup4_w5 register - * Otp debuger block0 data register21. - */ -typedef union { - struct { - /** block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word5 data. - */ - uint32_t block0_backup4_w5:32; - }; - uint32_t val; -} otp_debug_blk0_backup4_w5_reg_t; - - -/** Group: OTP_DEBUG Block1 Word1 Data */ -/** Type of blk1_w1 register - * Otp debuger block1 data register1. - */ -typedef union { - struct { - /** block1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word1 data. - */ - uint32_t block1_w1:32; - }; - uint32_t val; -} otp_debug_blk1_w1_reg_t; - - -/** Group: OTP_DEBUG Block1 Word2 Data */ -/** Type of blk1_w2 register - * Otp debuger block1 data register2. - */ -typedef union { - struct { - /** block1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word2 data. - */ - uint32_t block1_w2:32; - }; - uint32_t val; -} otp_debug_blk1_w2_reg_t; - - -/** Group: OTP_DEBUG Block1 Word3 Data */ -/** Type of blk1_w3 register - * Otp debuger block1 data register3. - */ -typedef union { - struct { - /** block1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word3 data. - */ - uint32_t block1_w3:32; - }; - uint32_t val; -} otp_debug_blk1_w3_reg_t; - - -/** Group: OTP_DEBUG Block1 Word4 Data */ -/** Type of blk1_w4 register - * Otp debuger block1 data register4. - */ -typedef union { - struct { - /** block1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word4 data. - */ - uint32_t block1_w4:32; - }; - uint32_t val; -} otp_debug_blk1_w4_reg_t; - - -/** Group: OTP_DEBUG Block1 Word5 Data */ -/** Type of blk1_w5 register - * Otp debuger block1 data register5. - */ -typedef union { - struct { - /** block1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word5 data. - */ - uint32_t block1_w5:32; - }; - uint32_t val; -} otp_debug_blk1_w5_reg_t; - - -/** Group: OTP_DEBUG Block1 Word6 Data */ -/** Type of blk1_w6 register - * Otp debuger block1 data register6. - */ -typedef union { - struct { - /** block1_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word6 data. - */ - uint32_t block1_w6:32; - }; - uint32_t val; -} otp_debug_blk1_w6_reg_t; - - -/** Group: OTP_DEBUG Block1 Word7 Data */ -/** Type of blk1_w7 register - * Otp debuger block1 data register7. - */ -typedef union { - struct { - /** block1_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word7 data. - */ - uint32_t block1_w7:32; - }; - uint32_t val; -} otp_debug_blk1_w7_reg_t; - - -/** Group: OTP_DEBUG Block1 Word8 Data */ -/** Type of blk1_w8 register - * Otp debuger block1 data register8. - */ -typedef union { - struct { - /** block1_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word8 data. - */ - uint32_t block1_w8:32; - }; - uint32_t val; -} otp_debug_blk1_w8_reg_t; - - -/** Group: OTP_DEBUG Block1 Word9 Data */ -/** Type of blk1_w9 register - * Otp debuger block1 data register9. - */ -typedef union { - struct { - /** block1_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word9 data. - */ - uint32_t block1_w9:32; - }; - uint32_t val; -} otp_debug_blk1_w9_reg_t; - - -/** Group: OTP_DEBUG Block2 Word1 Data */ -/** Type of blk2_w1 register - * Otp debuger block2 data register1. - */ -typedef union { - struct { - /** block2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word1 data. - */ - uint32_t block2_w1:32; - }; - uint32_t val; -} otp_debug_blk2_w1_reg_t; - - -/** Group: OTP_DEBUG Block2 Word2 Data */ -/** Type of blk2_w2 register - * Otp debuger block2 data register2. - */ -typedef union { - struct { - /** block2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word2 data. - */ - uint32_t block2_w2:32; - }; - uint32_t val; -} otp_debug_blk2_w2_reg_t; - - -/** Group: OTP_DEBUG Block2 Word3 Data */ -/** Type of blk2_w3 register - * Otp debuger block2 data register3. - */ -typedef union { - struct { - /** block2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word3 data. - */ - uint32_t block2_w3:32; - }; - uint32_t val; -} otp_debug_blk2_w3_reg_t; - - -/** Group: OTP_DEBUG Block2 Word4 Data */ -/** Type of blk2_w4 register - * Otp debuger block2 data register4. - */ -typedef union { - struct { - /** block2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word4 data. - */ - uint32_t block2_w4:32; - }; - uint32_t val; -} otp_debug_blk2_w4_reg_t; - - -/** Group: OTP_DEBUG Block2 Word5 Data */ -/** Type of blk2_w5 register - * Otp debuger block2 data register5. - */ -typedef union { - struct { - /** block2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word5 data. - */ - uint32_t block2_w5:32; - }; - uint32_t val; -} otp_debug_blk2_w5_reg_t; - - -/** Group: OTP_DEBUG Block2 Word6 Data */ -/** Type of blk2_w6 register - * Otp debuger block2 data register6. - */ -typedef union { - struct { - /** block2_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word6 data. - */ - uint32_t block2_w6:32; - }; - uint32_t val; -} otp_debug_blk2_w6_reg_t; - - -/** Group: OTP_DEBUG Block2 Word7 Data */ -/** Type of blk2_w7 register - * Otp debuger block2 data register7. - */ -typedef union { - struct { - /** block2_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word7 data. - */ - uint32_t block2_w7:32; - }; - uint32_t val; -} otp_debug_blk2_w7_reg_t; - - -/** Group: OTP_DEBUG Block2 Word8 Data */ -/** Type of blk2_w8 register - * Otp debuger block2 data register8. - */ -typedef union { - struct { - /** block2_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word8 data. - */ - uint32_t block2_w8:32; - }; - uint32_t val; -} otp_debug_blk2_w8_reg_t; - - -/** Group: OTP_DEBUG Block2 Word9 Data */ -/** Type of blk2_w9 register - * Otp debuger block2 data register9. - */ -typedef union { - struct { - /** block2_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word9 data. - */ - uint32_t block2_w9:32; - }; - uint32_t val; -} otp_debug_blk2_w9_reg_t; - - -/** Group: OTP_DEBUG Block2 Word10 Data */ -/** Type of blk2_w10 register - * Otp debuger block2 data register10. - */ -typedef union { - struct { - /** block2_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word10 data. - */ - uint32_t block2_w10:32; - }; - uint32_t val; -} otp_debug_blk2_w10_reg_t; - - -/** Group: OTP_DEBUG Block2 Word11 Data */ -/** Type of blk2_w11 register - * Otp debuger block2 data register11. - */ -typedef union { - struct { - /** block2_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word11 data. - */ - uint32_t block2_w11:32; - }; - uint32_t val; -} otp_debug_blk2_w11_reg_t; - -/** Type of blk10_w11 register - * Otp debuger block10 data register11. - */ -typedef union { - struct { - /** block10_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ - uint32_t block10_w11:32; - }; - uint32_t val; -} otp_debug_blk10_w11_reg_t; - - -/** Group: OTP_DEBUG Block3 Word1 Data */ -/** Type of blk3_w1 register - * Otp debuger block3 data register1. - */ -typedef union { - struct { - /** block3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word1 data. - */ - uint32_t block3_w1:32; - }; - uint32_t val; -} otp_debug_blk3_w1_reg_t; - - -/** Group: OTP_DEBUG Block3 Word2 Data */ -/** Type of blk3_w2 register - * Otp debuger block3 data register2. - */ -typedef union { - struct { - /** block3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word2 data. - */ - uint32_t block3_w2:32; - }; - uint32_t val; -} otp_debug_blk3_w2_reg_t; - - -/** Group: OTP_DEBUG Block3 Word3 Data */ -/** Type of blk3_w3 register - * Otp debuger block3 data register3. - */ -typedef union { - struct { - /** block3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word3 data. - */ - uint32_t block3_w3:32; - }; - uint32_t val; -} otp_debug_blk3_w3_reg_t; - - -/** Group: OTP_DEBUG Block3 Word4 Data */ -/** Type of blk3_w4 register - * Otp debuger block3 data register4. - */ -typedef union { - struct { - /** block3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word4 data. - */ - uint32_t block3_w4:32; - }; - uint32_t val; -} otp_debug_blk3_w4_reg_t; - - -/** Group: OTP_DEBUG Block3 Word5 Data */ -/** Type of blk3_w5 register - * Otp debuger block3 data register5. - */ -typedef union { - struct { - /** block3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word5 data. - */ - uint32_t block3_w5:32; - }; - uint32_t val; -} otp_debug_blk3_w5_reg_t; - - -/** Group: OTP_DEBUG Block3 Word6 Data */ -/** Type of blk3_w6 register - * Otp debuger block3 data register6. - */ -typedef union { - struct { - /** block3_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word6 data. - */ - uint32_t block3_w6:32; - }; - uint32_t val; -} otp_debug_blk3_w6_reg_t; - - -/** Group: OTP_DEBUG Block3 Word7 Data */ -/** Type of blk3_w7 register - * Otp debuger block3 data register7. - */ -typedef union { - struct { - /** block3_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word7 data. - */ - uint32_t block3_w7:32; - }; - uint32_t val; -} otp_debug_blk3_w7_reg_t; - - -/** Group: OTP_DEBUG Block3 Word8 Data */ -/** Type of blk3_w8 register - * Otp debuger block3 data register8. - */ -typedef union { - struct { - /** block3_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word8 data. - */ - uint32_t block3_w8:32; - }; - uint32_t val; -} otp_debug_blk3_w8_reg_t; - - -/** Group: OTP_DEBUG Block3 Word9 Data */ -/** Type of blk3_w9 register - * Otp debuger block3 data register9. - */ -typedef union { - struct { - /** block3_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word9 data. - */ - uint32_t block3_w9:32; - }; - uint32_t val; -} otp_debug_blk3_w9_reg_t; - - -/** Group: OTP_DEBUG Block3 Word10 Data */ -/** Type of blk3_w10 register - * Otp debuger block3 data register10. - */ -typedef union { - struct { - /** block3_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word10 data. - */ - uint32_t block3_w10:32; - }; - uint32_t val; -} otp_debug_blk3_w10_reg_t; - - -/** Group: OTP_DEBUG Block3 Word11 Data */ -/** Type of blk3_w11 register - * Otp debuger block3 data register11. - */ -typedef union { - struct { - /** block3_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word11 data. - */ - uint32_t block3_w11:32; - }; - uint32_t val; -} otp_debug_blk3_w11_reg_t; - - -/** Group: OTP_DEBUG Block4 Word1 Data */ -/** Type of blk4_w1 register - * Otp debuger block4 data register1. - */ -typedef union { - struct { - /** block4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word1 data. - */ - uint32_t block4_w1:32; - }; - uint32_t val; -} otp_debug_blk4_w1_reg_t; - - -/** Group: OTP_DEBUG Block4 Word2 Data */ -/** Type of blk4_w2 register - * Otp debuger block4 data register2. - */ -typedef union { - struct { - /** block4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word2 data. - */ - uint32_t block4_w2:32; - }; - uint32_t val; -} otp_debug_blk4_w2_reg_t; - - -/** Group: OTP_DEBUG Block4 Word3 Data */ -/** Type of blk4_w3 register - * Otp debuger block4 data register3. - */ -typedef union { - struct { - /** block4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word3 data. - */ - uint32_t block4_w3:32; - }; - uint32_t val; -} otp_debug_blk4_w3_reg_t; - - -/** Group: OTP_DEBUG Block4 Word4 Data */ -/** Type of blk4_w4 register - * Otp debuger block4 data register4. - */ -typedef union { - struct { - /** block4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word4 data. - */ - uint32_t block4_w4:32; - }; - uint32_t val; -} otp_debug_blk4_w4_reg_t; - - -/** Group: OTP_DEBUG Block4 Word5 Data */ -/** Type of blk4_w5 register - * Otp debuger block4 data register5. - */ -typedef union { - struct { - /** block4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word5 data. - */ - uint32_t block4_w5:32; - }; - uint32_t val; -} otp_debug_blk4_w5_reg_t; - - -/** Group: OTP_DEBUG Block4 Word6 Data */ -/** Type of blk4_w6 register - * Otp debuger block4 data register6. - */ -typedef union { - struct { - /** block4_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word6 data. - */ - uint32_t block4_w6:32; - }; - uint32_t val; -} otp_debug_blk4_w6_reg_t; - - -/** Group: OTP_DEBUG Block4 Word7 Data */ -/** Type of blk4_w7 register - * Otp debuger block4 data register7. - */ -typedef union { - struct { - /** block4_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word7 data. - */ - uint32_t block4_w7:32; - }; - uint32_t val; -} otp_debug_blk4_w7_reg_t; - - -/** Group: OTP_DEBUG Block4 Word8 Data */ -/** Type of blk4_w8 register - * Otp debuger block4 data register8. - */ -typedef union { - struct { - /** block4_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word8 data. - */ - uint32_t block4_w8:32; - }; - uint32_t val; -} otp_debug_blk4_w8_reg_t; - - -/** Group: OTP_DEBUG Block4 Word9 Data */ -/** Type of blk4_w9 register - * Otp debuger block4 data register9. - */ -typedef union { - struct { - /** block4_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word9 data. - */ - uint32_t block4_w9:32; - }; - uint32_t val; -} otp_debug_blk4_w9_reg_t; - - -/** Group: OTP_DEBUG Block4 Word10 Data */ -/** Type of blk4_w10 register - * Otp debuger block4 data registe10. - */ -typedef union { - struct { - /** block4_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word10 data. - */ - uint32_t block4_w10:32; - }; - uint32_t val; -} otp_debug_blk4_w10_reg_t; - - -/** Group: OTP_DEBUG Block4 Word11 Data */ -/** Type of blk4_w11 register - * Otp debuger block4 data register11. - */ -typedef union { - struct { - /** block4_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word11 data. - */ - uint32_t block4_w11:32; - }; - uint32_t val; -} otp_debug_blk4_w11_reg_t; - - -/** Group: OTP_DEBUG Block5 Word1 Data */ -/** Type of blk5_w1 register - * Otp debuger block5 data register1. - */ -typedef union { - struct { - /** block5_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word1 data. - */ - uint32_t block5_w1:32; - }; - uint32_t val; -} otp_debug_blk5_w1_reg_t; - - -/** Group: OTP_DEBUG Block5 Word2 Data */ -/** Type of blk5_w2 register - * Otp debuger block5 data register2. - */ -typedef union { - struct { - /** block5_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word2 data. - */ - uint32_t block5_w2:32; - }; - uint32_t val; -} otp_debug_blk5_w2_reg_t; - - -/** Group: OTP_DEBUG Block5 Word3 Data */ -/** Type of blk5_w3 register - * Otp debuger block5 data register3. - */ -typedef union { - struct { - /** block5_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word3 data. - */ - uint32_t block5_w3:32; - }; - uint32_t val; -} otp_debug_blk5_w3_reg_t; - - -/** Group: OTP_DEBUG Block5 Word4 Data */ -/** Type of blk5_w4 register - * Otp debuger block5 data register4. - */ -typedef union { - struct { - /** block5_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word4 data. - */ - uint32_t block5_w4:32; - }; - uint32_t val; -} otp_debug_blk5_w4_reg_t; - - -/** Group: OTP_DEBUG Block5 Word5 Data */ -/** Type of blk5_w5 register - * Otp debuger block5 data register5. - */ -typedef union { - struct { - /** block5_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word5 data. - */ - uint32_t block5_w5:32; - }; - uint32_t val; -} otp_debug_blk5_w5_reg_t; - - -/** Group: OTP_DEBUG Block5 Word6 Data */ -/** Type of blk5_w6 register - * Otp debuger block5 data register6. - */ -typedef union { - struct { - /** block5_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word6 data. - */ - uint32_t block5_w6:32; - }; - uint32_t val; -} otp_debug_blk5_w6_reg_t; - - -/** Group: OTP_DEBUG Block5 Word7 Data */ -/** Type of blk5_w7 register - * Otp debuger block5 data register7. - */ -typedef union { - struct { - /** block5_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word7 data. - */ - uint32_t block5_w7:32; - }; - uint32_t val; -} otp_debug_blk5_w7_reg_t; - - -/** Group: OTP_DEBUG Block5 Word8 Data */ -/** Type of blk5_w8 register - * Otp debuger block5 data register8. - */ -typedef union { - struct { - /** block5_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word8 data. - */ - uint32_t block5_w8:32; - }; - uint32_t val; -} otp_debug_blk5_w8_reg_t; - - -/** Group: OTP_DEBUG Block5 Word9 Data */ -/** Type of blk5_w9 register - * Otp debuger block5 data register9. - */ -typedef union { - struct { - /** block5_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word9 data. - */ - uint32_t block5_w9:32; - }; - uint32_t val; -} otp_debug_blk5_w9_reg_t; - - -/** Group: OTP_DEBUG Block5 Word10 Data */ -/** Type of blk5_w10 register - * Otp debuger block5 data register10. - */ -typedef union { - struct { - /** block5_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word10 data. - */ - uint32_t block5_w10:32; - }; - uint32_t val; -} otp_debug_blk5_w10_reg_t; - - -/** Group: OTP_DEBUG Block5 Word11 Data */ -/** Type of blk5_w11 register - * Otp debuger block5 data register11. - */ -typedef union { - struct { - /** block5_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word11 data. - */ - uint32_t block5_w11:32; - }; - uint32_t val; -} otp_debug_blk5_w11_reg_t; - - -/** Group: OTP_DEBUG Block6 Word1 Data */ -/** Type of blk6_w1 register - * Otp debuger block6 data register1. - */ -typedef union { - struct { - /** block6_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word1 data. - */ - uint32_t block6_w1:32; - }; - uint32_t val; -} otp_debug_blk6_w1_reg_t; - - -/** Group: OTP_DEBUG Block6 Word2 Data */ -/** Type of blk6_w2 register - * Otp debuger block6 data register2. - */ -typedef union { - struct { - /** block6_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word2 data. - */ - uint32_t block6_w2:32; - }; - uint32_t val; -} otp_debug_blk6_w2_reg_t; - - -/** Group: OTP_DEBUG Block6 Word3 Data */ -/** Type of blk6_w3 register - * Otp debuger block6 data register3. - */ -typedef union { - struct { - /** block6_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word3 data. - */ - uint32_t block6_w3:32; - }; - uint32_t val; -} otp_debug_blk6_w3_reg_t; - - -/** Group: OTP_DEBUG Block6 Word4 Data */ -/** Type of blk6_w4 register - * Otp debuger block6 data register4. - */ -typedef union { - struct { - /** block6_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word4 data. - */ - uint32_t block6_w4:32; - }; - uint32_t val; -} otp_debug_blk6_w4_reg_t; - - -/** Group: OTP_DEBUG Block6 Word5 Data */ -/** Type of blk6_w5 register - * Otp debuger block6 data register5. - */ -typedef union { - struct { - /** block6_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word5 data. - */ - uint32_t block6_w5:32; - }; - uint32_t val; -} otp_debug_blk6_w5_reg_t; - - -/** Group: OTP_DEBUG Block6 Word6 Data */ -/** Type of blk6_w6 register - * Otp debuger block6 data register6. - */ -typedef union { - struct { - /** block6_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word6 data. - */ - uint32_t block6_w6:32; - }; - uint32_t val; -} otp_debug_blk6_w6_reg_t; - - -/** Group: OTP_DEBUG Block6 Word7 Data */ -/** Type of blk6_w7 register - * Otp debuger block6 data register7. - */ -typedef union { - struct { - /** block6_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word7 data. - */ - uint32_t block6_w7:32; - }; - uint32_t val; -} otp_debug_blk6_w7_reg_t; - - -/** Group: OTP_DEBUG Block6 Word8 Data */ -/** Type of blk6_w8 register - * Otp debuger block6 data register8. - */ -typedef union { - struct { - /** block6_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word8 data. - */ - uint32_t block6_w8:32; - }; - uint32_t val; -} otp_debug_blk6_w8_reg_t; - - -/** Group: OTP_DEBUG Block6 Word9 Data */ -/** Type of blk6_w9 register - * Otp debuger block6 data register9. - */ -typedef union { - struct { - /** block6_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word9 data. - */ - uint32_t block6_w9:32; - }; - uint32_t val; -} otp_debug_blk6_w9_reg_t; - - -/** Group: OTP_DEBUG Block6 Word10 Data */ -/** Type of blk6_w10 register - * Otp debuger block6 data register10. - */ -typedef union { - struct { - /** block6_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word10 data. - */ - uint32_t block6_w10:32; - }; - uint32_t val; -} otp_debug_blk6_w10_reg_t; - - -/** Group: OTP_DEBUG Block6 Word11 Data */ -/** Type of blk6_w11 register - * Otp debuger block6 data register11. - */ -typedef union { - struct { - /** block6_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word11 data. - */ - uint32_t block6_w11:32; - }; - uint32_t val; -} otp_debug_blk6_w11_reg_t; - - -/** Group: OTP_DEBUG Block7 Word1 Data */ -/** Type of blk7_w1 register - * Otp debuger block7 data register1. - */ -typedef union { - struct { - /** block7_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word1 data. - */ - uint32_t block7_w1:32; - }; - uint32_t val; -} otp_debug_blk7_w1_reg_t; - - -/** Group: OTP_DEBUG Block7 Word2 Data */ -/** Type of blk7_w2 register - * Otp debuger block7 data register2. - */ -typedef union { - struct { - /** block7_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word2 data. - */ - uint32_t block7_w2:32; - }; - uint32_t val; -} otp_debug_blk7_w2_reg_t; - - -/** Group: OTP_DEBUG Block7 Word3 Data */ -/** Type of blk7_w3 register - * Otp debuger block7 data register3. - */ -typedef union { - struct { - /** block7_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word3 data. - */ - uint32_t block7_w3:32; - }; - uint32_t val; -} otp_debug_blk7_w3_reg_t; - - -/** Group: OTP_DEBUG Block7 Word4 Data */ -/** Type of blk7_w4 register - * Otp debuger block7 data register4. - */ -typedef union { - struct { - /** block7_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word4 data. - */ - uint32_t block7_w4:32; - }; - uint32_t val; -} otp_debug_blk7_w4_reg_t; - - -/** Group: OTP_DEBUG Block7 Word5 Data */ -/** Type of blk7_w5 register - * Otp debuger block7 data register5. - */ -typedef union { - struct { - /** block7_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word5 data. - */ - uint32_t block7_w5:32; - }; - uint32_t val; -} otp_debug_blk7_w5_reg_t; - - -/** Group: OTP_DEBUG Block7 Word6 Data */ -/** Type of blk7_w6 register - * Otp debuger block7 data register6. - */ -typedef union { - struct { - /** block7_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word6 data. - */ - uint32_t block7_w6:32; - }; - uint32_t val; -} otp_debug_blk7_w6_reg_t; - - -/** Group: OTP_DEBUG Block7 Word7 Data */ -/** Type of blk7_w7 register - * Otp debuger block7 data register7. - */ -typedef union { - struct { - /** block7_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word7 data. - */ - uint32_t block7_w7:32; - }; - uint32_t val; -} otp_debug_blk7_w7_reg_t; - - -/** Group: OTP_DEBUG Block7 Word8 Data */ -/** Type of blk7_w8 register - * Otp debuger block7 data register8. - */ -typedef union { - struct { - /** block7_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word8 data. - */ - uint32_t block7_w8:32; - }; - uint32_t val; -} otp_debug_blk7_w8_reg_t; - - -/** Group: OTP_DEBUG Block7 Word9 Data */ -/** Type of blk7_w9 register - * Otp debuger block7 data register9. - */ -typedef union { - struct { - /** block7_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word9 data. - */ - uint32_t block7_w9:32; - }; - uint32_t val; -} otp_debug_blk7_w9_reg_t; - - -/** Group: OTP_DEBUG Block7 Word10 Data */ -/** Type of blk7_w10 register - * Otp debuger block7 data register10. - */ -typedef union { - struct { - /** block7_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word10 data. - */ - uint32_t block7_w10:32; - }; - uint32_t val; -} otp_debug_blk7_w10_reg_t; - - -/** Group: OTP_DEBUG Block7 Word11 Data */ -/** Type of blk7_w11 register - * Otp debuger block7 data register11. - */ -typedef union { - struct { - /** block7_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word11 data. - */ - uint32_t block7_w11:32; - }; - uint32_t val; -} otp_debug_blk7_w11_reg_t; - - -/** Group: OTP_DEBUG Block8 Word1 Data */ -/** Type of blk8_w1 register - * Otp debuger block8 data register1. - */ -typedef union { - struct { - /** block8_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word1 data. - */ - uint32_t block8_w1:32; - }; - uint32_t val; -} otp_debug_blk8_w1_reg_t; - - -/** Group: OTP_DEBUG Block8 Word2 Data */ -/** Type of blk8_w2 register - * Otp debuger block8 data register2. - */ -typedef union { - struct { - /** block8_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word2 data. - */ - uint32_t block8_w2:32; - }; - uint32_t val; -} otp_debug_blk8_w2_reg_t; - - -/** Group: OTP_DEBUG Block8 Word3 Data */ -/** Type of blk8_w3 register - * Otp debuger block8 data register3. - */ -typedef union { - struct { - /** block8_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word3 data. - */ - uint32_t block8_w3:32; - }; - uint32_t val; -} otp_debug_blk8_w3_reg_t; - - -/** Group: OTP_DEBUG Block8 Word4 Data */ -/** Type of blk8_w4 register - * Otp debuger block8 data register4. - */ -typedef union { - struct { - /** block8_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word4 data. - */ - uint32_t block8_w4:32; - }; - uint32_t val; -} otp_debug_blk8_w4_reg_t; - - -/** Group: OTP_DEBUG Block8 Word5 Data */ -/** Type of blk8_w5 register - * Otp debuger block8 data register5. - */ -typedef union { - struct { - /** block8_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word5 data. - */ - uint32_t block8_w5:32; - }; - uint32_t val; -} otp_debug_blk8_w5_reg_t; - - -/** Group: OTP_DEBUG Block8 Word6 Data */ -/** Type of blk8_w6 register - * Otp debuger block8 data register6. - */ -typedef union { - struct { - /** block8_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word6 data. - */ - uint32_t block8_w6:32; - }; - uint32_t val; -} otp_debug_blk8_w6_reg_t; - - -/** Group: OTP_DEBUG Block8 Word7 Data */ -/** Type of blk8_w7 register - * Otp debuger block8 data register7. - */ -typedef union { - struct { - /** block8_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word7 data. - */ - uint32_t block8_w7:32; - }; - uint32_t val; -} otp_debug_blk8_w7_reg_t; - - -/** Group: OTP_DEBUG Block8 Word8 Data */ -/** Type of blk8_w8 register - * Otp debuger block8 data register8. - */ -typedef union { - struct { - /** block8_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word8 data. - */ - uint32_t block8_w8:32; - }; - uint32_t val; -} otp_debug_blk8_w8_reg_t; - - -/** Group: OTP_DEBUG Block8 Word9 Data */ -/** Type of blk8_w9 register - * Otp debuger block8 data register9. - */ -typedef union { - struct { - /** block8_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word9 data. - */ - uint32_t block8_w9:32; - }; - uint32_t val; -} otp_debug_blk8_w9_reg_t; - - -/** Group: OTP_DEBUG Block8 Word10 Data */ -/** Type of blk8_w10 register - * Otp debuger block8 data register10. - */ -typedef union { - struct { - /** block8_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word10 data. - */ - uint32_t block8_w10:32; - }; - uint32_t val; -} otp_debug_blk8_w10_reg_t; - - -/** Group: OTP_DEBUG Block8 Word11 Data */ -/** Type of blk8_w11 register - * Otp debuger block8 data register11. - */ -typedef union { - struct { - /** block8_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word11 data. - */ - uint32_t block8_w11:32; - }; - uint32_t val; -} otp_debug_blk8_w11_reg_t; - - -/** Group: OTP_DEBUG Block9 Word1 Data */ -/** Type of blk9_w1 register - * Otp debuger block9 data register1. - */ -typedef union { - struct { - /** block9_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word1 data. - */ - uint32_t block9_w1:32; - }; - uint32_t val; -} otp_debug_blk9_w1_reg_t; - - -/** Group: OTP_DEBUG Block9 Word2 Data */ -/** Type of blk9_w2 register - * Otp debuger block9 data register2. - */ -typedef union { - struct { - /** block9_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word2 data. - */ - uint32_t block9_w2:32; - }; - uint32_t val; -} otp_debug_blk9_w2_reg_t; - - -/** Group: OTP_DEBUG Block9 Word3 Data */ -/** Type of blk9_w3 register - * Otp debuger block9 data register3. - */ -typedef union { - struct { - /** block9_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word3 data. - */ - uint32_t block9_w3:32; - }; - uint32_t val; -} otp_debug_blk9_w3_reg_t; - - -/** Group: OTP_DEBUG Block9 Word4 Data */ -/** Type of blk9_w4 register - * Otp debuger block9 data register4. - */ -typedef union { - struct { - /** block9_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word4 data. - */ - uint32_t block9_w4:32; - }; - uint32_t val; -} otp_debug_blk9_w4_reg_t; - - -/** Group: OTP_DEBUG Block9 Word5 Data */ -/** Type of blk9_w5 register - * Otp debuger block9 data register5. - */ -typedef union { - struct { - /** block9_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word5 data. - */ - uint32_t block9_w5:32; - }; - uint32_t val; -} otp_debug_blk9_w5_reg_t; - - -/** Group: OTP_DEBUG Block9 Word6 Data */ -/** Type of blk9_w6 register - * Otp debuger block9 data register6. - */ -typedef union { - struct { - /** block9_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word6 data. - */ - uint32_t block9_w6:32; - }; - uint32_t val; -} otp_debug_blk9_w6_reg_t; - - -/** Group: OTP_DEBUG Block9 Word7 Data */ -/** Type of blk9_w7 register - * Otp debuger block9 data register7. - */ -typedef union { - struct { - /** block9_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word7 data. - */ - uint32_t block9_w7:32; - }; - uint32_t val; -} otp_debug_blk9_w7_reg_t; - - -/** Group: OTP_DEBUG Block9 Word8 Data */ -/** Type of blk9_w8 register - * Otp debuger block9 data register8. - */ -typedef union { - struct { - /** block9_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word8 data. - */ - uint32_t block9_w8:32; - }; - uint32_t val; -} otp_debug_blk9_w8_reg_t; - - -/** Group: OTP_DEBUG Block9 Word9 Data */ -/** Type of blk9_w9 register - * Otp debuger block9 data register9. - */ -typedef union { - struct { - /** block9_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word9 data. - */ - uint32_t block9_w9:32; - }; - uint32_t val; -} otp_debug_blk9_w9_reg_t; - - -/** Group: OTP_DEBUG Block9 Word10 Data */ -/** Type of blk9_w10 register - * Otp debuger block9 data register10. - */ -typedef union { - struct { - /** block9_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word10 data. - */ - uint32_t block9_w10:32; - }; - uint32_t val; -} otp_debug_blk9_w10_reg_t; - - -/** Group: OTP_DEBUG Block9 Word11 Data */ -/** Type of blk9_w11 register - * Otp debuger block9 data register11. - */ -typedef union { - struct { - /** block9_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word11 data. - */ - uint32_t block9_w11:32; - }; - uint32_t val; -} otp_debug_blk9_w11_reg_t; - - -/** Group: OTP_DEBUG Block10 Word1 Data */ -/** Type of blk10_w1 register - * Otp debuger block10 data register1. - */ -typedef union { - struct { - /** block10_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word1 data. - */ - uint32_t block10_w1:32; - }; - uint32_t val; -} otp_debug_blk10_w1_reg_t; - - -/** Group: OTP_DEBUG Block10 Word2 Data */ -/** Type of blk10_w2 register - * Otp debuger block10 data register2. - */ -typedef union { - struct { - /** block10_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word2 data. - */ - uint32_t block10_w2:32; - }; - uint32_t val; -} otp_debug_blk10_w2_reg_t; - - -/** Group: OTP_DEBUG Block10 Word3 Data */ -/** Type of blk10_w3 register - * Otp debuger block10 data register3. - */ -typedef union { - struct { - /** block10_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word3 data. - */ - uint32_t block10_w3:32; - }; - uint32_t val; -} otp_debug_blk10_w3_reg_t; - - -/** Group: OTP_DEBUG Block10 Word4 Data */ -/** Type of blk10_w4 register - * Otp debuger block10 data register4. - */ -typedef union { - struct { - /** block10_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word4 data. - */ - uint32_t block10_w4:32; - }; - uint32_t val; -} otp_debug_blk10_w4_reg_t; - - -/** Group: OTP_DEBUG Block10 Word5 Data */ -/** Type of blk10_w5 register - * Otp debuger block10 data register5. - */ -typedef union { - struct { - /** block10_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word5 data. - */ - uint32_t block10_w5:32; - }; - uint32_t val; -} otp_debug_blk10_w5_reg_t; - - -/** Group: OTP_DEBUG Block10 Word6 Data */ -/** Type of blk10_w6 register - * Otp debuger block10 data register6. - */ -typedef union { - struct { - /** block10_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word6 data. - */ - uint32_t block10_w6:32; - }; - uint32_t val; -} otp_debug_blk10_w6_reg_t; - - -/** Group: OTP_DEBUG Block10 Word7 Data */ -/** Type of blk10_w7 register - * Otp debuger block10 data register7. - */ -typedef union { - struct { - /** block10_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word7 data. - */ - uint32_t block10_w7:32; - }; - uint32_t val; -} otp_debug_blk10_w7_reg_t; - - -/** Group: OTP_DEBUG Block10 Word8 Data */ -/** Type of blk10_w8 register - * Otp debuger block10 data register8. - */ -typedef union { - struct { - /** block10_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word8 data. - */ - uint32_t block10_w8:32; - }; - uint32_t val; -} otp_debug_blk10_w8_reg_t; - - -/** Group: OTP_DEBUG Block10 Word9 Data */ -/** Type of blk10_w9 register - * Otp debuger block10 data register9. - */ -typedef union { - struct { - /** block10_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word9 data. - */ - uint32_t block10_w9:32; - }; - uint32_t val; -} otp_debug_blk10_w9_reg_t; - - -/** Group: OTP_DEBUG Block10 Word10 Data */ -/** Type of blk10_w10 register - * Otp debuger block10 data register10. - */ -typedef union { - struct { - /** block19_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word10 data. - */ - uint32_t block19_w10:32; - }; - uint32_t val; -} otp_debug_blk10_w10_reg_t; - - -/** Group: OTP_DEBUG Clock_en Configuration Register */ -/** Type of clk register - * Otp debuger clk_en configuration register. - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Force clock on for this register file. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} otp_debug_clk_reg_t; - - -/** Group: OTP_DEBUG Apb2otp Enable Singal */ -/** Type of apb2otp_en register - * Otp_debuger apb2otp enable configuration register. - */ -typedef union { - struct { - /** apb2otp_en : R/W; bitpos: [0]; default: 0; - * Debug mode enable signal. - */ - uint32_t apb2otp_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} otp_debug_apb2otp_en_reg_t; - - -/** Group: OTP_DEBUG Version Register */ -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 539037736; - * Stores otp_debug version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} otp_debug_date_reg_t; - - -typedef struct otp_debug_dev_t { - volatile otp_debug_wr_dis_reg_t wr_dis; - volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1; - volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2; - volatile otp_debug_blk0_backup1_w3_reg_t blk0_backup1_w3; - volatile otp_debug_blk0_backup1_w4_reg_t blk0_backup1_w4; - volatile otp_debug_blk0_backup1_w5_reg_t blk0_backup1_w5; - volatile otp_debug_blk0_backup2_w1_reg_t blk0_backup2_w1; - volatile otp_debug_blk0_backup2_w2_reg_t blk0_backup2_w2; - volatile otp_debug_blk0_backup2_w3_reg_t blk0_backup2_w3; - volatile otp_debug_blk0_backup2_w4_reg_t blk0_backup2_w4; - volatile otp_debug_blk0_backup2_w5_reg_t blk0_backup2_w5; - volatile otp_debug_blk0_backup3_w1_reg_t blk0_backup3_w1; - volatile otp_debug_blk0_backup3_w2_reg_t blk0_backup3_w2; - volatile otp_debug_blk0_backup3_w3_reg_t blk0_backup3_w3; - volatile otp_debug_blk0_backup3_w4_reg_t blk0_backup3_w4; - volatile otp_debug_blk0_backup3_w5_reg_t blk0_backup3_w5; - volatile otp_debug_blk0_backup4_w1_reg_t blk0_backup4_w1; - volatile otp_debug_blk0_backup4_w2_reg_t blk0_backup4_w2; - volatile otp_debug_blk0_backup4_w3_reg_t blk0_backup4_w3; - volatile otp_debug_blk0_backup4_w4_reg_t blk0_backup4_w4; - volatile otp_debug_blk0_backup4_w5_reg_t blk0_backup4_w5; - volatile otp_debug_blk1_w1_reg_t blk1_w1; - volatile otp_debug_blk1_w2_reg_t blk1_w2; - volatile otp_debug_blk1_w3_reg_t blk1_w3; - volatile otp_debug_blk1_w4_reg_t blk1_w4; - volatile otp_debug_blk1_w5_reg_t blk1_w5; - volatile otp_debug_blk1_w6_reg_t blk1_w6; - volatile otp_debug_blk1_w7_reg_t blk1_w7; - volatile otp_debug_blk1_w8_reg_t blk1_w8; - volatile otp_debug_blk1_w9_reg_t blk1_w9; - volatile otp_debug_blk2_w1_reg_t blk2_w1; - volatile otp_debug_blk2_w2_reg_t blk2_w2; - volatile otp_debug_blk2_w3_reg_t blk2_w3; - volatile otp_debug_blk2_w4_reg_t blk2_w4; - volatile otp_debug_blk2_w5_reg_t blk2_w5; - volatile otp_debug_blk2_w6_reg_t blk2_w6; - volatile otp_debug_blk2_w7_reg_t blk2_w7; - volatile otp_debug_blk2_w8_reg_t blk2_w8; - volatile otp_debug_blk2_w9_reg_t blk2_w9; - volatile otp_debug_blk2_w10_reg_t blk2_w10; - volatile otp_debug_blk2_w11_reg_t blk2_w11; - volatile otp_debug_blk3_w1_reg_t blk3_w1; - volatile otp_debug_blk3_w2_reg_t blk3_w2; - volatile otp_debug_blk3_w3_reg_t blk3_w3; - volatile otp_debug_blk3_w4_reg_t blk3_w4; - volatile otp_debug_blk3_w5_reg_t blk3_w5; - volatile otp_debug_blk3_w6_reg_t blk3_w6; - volatile otp_debug_blk3_w7_reg_t blk3_w7; - volatile otp_debug_blk3_w8_reg_t blk3_w8; - volatile otp_debug_blk3_w9_reg_t blk3_w9; - volatile otp_debug_blk3_w10_reg_t blk3_w10; - volatile otp_debug_blk3_w11_reg_t blk3_w11; - volatile otp_debug_blk4_w1_reg_t blk4_w1; - volatile otp_debug_blk4_w2_reg_t blk4_w2; - volatile otp_debug_blk4_w3_reg_t blk4_w3; - volatile otp_debug_blk4_w4_reg_t blk4_w4; - volatile otp_debug_blk4_w5_reg_t blk4_w5; - volatile otp_debug_blk4_w6_reg_t blk4_w6; - volatile otp_debug_blk4_w7_reg_t blk4_w7; - volatile otp_debug_blk4_w8_reg_t blk4_w8; - volatile otp_debug_blk4_w9_reg_t blk4_w9; - volatile otp_debug_blk4_w10_reg_t blk4_w10; - volatile otp_debug_blk4_w11_reg_t blk4_w11; - volatile otp_debug_blk5_w1_reg_t blk5_w1; - volatile otp_debug_blk5_w2_reg_t blk5_w2; - volatile otp_debug_blk5_w3_reg_t blk5_w3; - volatile otp_debug_blk5_w4_reg_t blk5_w4; - volatile otp_debug_blk5_w5_reg_t blk5_w5; - volatile otp_debug_blk5_w6_reg_t blk5_w6; - volatile otp_debug_blk5_w7_reg_t blk5_w7; - volatile otp_debug_blk5_w8_reg_t blk5_w8; - volatile otp_debug_blk5_w9_reg_t blk5_w9; - volatile otp_debug_blk5_w10_reg_t blk5_w10; - volatile otp_debug_blk5_w11_reg_t blk5_w11; - volatile otp_debug_blk6_w1_reg_t blk6_w1; - volatile otp_debug_blk6_w2_reg_t blk6_w2; - volatile otp_debug_blk6_w3_reg_t blk6_w3; - volatile otp_debug_blk6_w4_reg_t blk6_w4; - volatile otp_debug_blk6_w5_reg_t blk6_w5; - volatile otp_debug_blk6_w6_reg_t blk6_w6; - volatile otp_debug_blk6_w7_reg_t blk6_w7; - volatile otp_debug_blk6_w8_reg_t blk6_w8; - volatile otp_debug_blk6_w9_reg_t blk6_w9; - volatile otp_debug_blk6_w10_reg_t blk6_w10; - volatile otp_debug_blk6_w11_reg_t blk6_w11; - volatile otp_debug_blk7_w1_reg_t blk7_w1; - volatile otp_debug_blk7_w2_reg_t blk7_w2; - volatile otp_debug_blk7_w3_reg_t blk7_w3; - volatile otp_debug_blk7_w4_reg_t blk7_w4; - volatile otp_debug_blk7_w5_reg_t blk7_w5; - volatile otp_debug_blk7_w6_reg_t blk7_w6; - volatile otp_debug_blk7_w7_reg_t blk7_w7; - volatile otp_debug_blk7_w8_reg_t blk7_w8; - volatile otp_debug_blk7_w9_reg_t blk7_w9; - volatile otp_debug_blk7_w10_reg_t blk7_w10; - volatile otp_debug_blk7_w11_reg_t blk7_w11; - volatile otp_debug_blk8_w1_reg_t blk8_w1; - volatile otp_debug_blk8_w2_reg_t blk8_w2; - volatile otp_debug_blk8_w3_reg_t blk8_w3; - volatile otp_debug_blk8_w4_reg_t blk8_w4; - volatile otp_debug_blk8_w5_reg_t blk8_w5; - volatile otp_debug_blk8_w6_reg_t blk8_w6; - volatile otp_debug_blk8_w7_reg_t blk8_w7; - volatile otp_debug_blk8_w8_reg_t blk8_w8; - volatile otp_debug_blk8_w9_reg_t blk8_w9; - volatile otp_debug_blk8_w10_reg_t blk8_w10; - volatile otp_debug_blk8_w11_reg_t blk8_w11; - volatile otp_debug_blk9_w1_reg_t blk9_w1; - volatile otp_debug_blk9_w2_reg_t blk9_w2; - volatile otp_debug_blk9_w3_reg_t blk9_w3; - volatile otp_debug_blk9_w4_reg_t blk9_w4; - volatile otp_debug_blk9_w5_reg_t blk9_w5; - volatile otp_debug_blk9_w6_reg_t blk9_w6; - volatile otp_debug_blk9_w7_reg_t blk9_w7; - volatile otp_debug_blk9_w8_reg_t blk9_w8; - volatile otp_debug_blk9_w9_reg_t blk9_w9; - volatile otp_debug_blk9_w10_reg_t blk9_w10; - volatile otp_debug_blk9_w11_reg_t blk9_w11; - volatile otp_debug_blk10_w1_reg_t blk10_w1; - volatile otp_debug_blk10_w2_reg_t blk10_w2; - volatile otp_debug_blk10_w3_reg_t blk10_w3; - volatile otp_debug_blk10_w4_reg_t blk10_w4; - volatile otp_debug_blk10_w5_reg_t blk10_w5; - volatile otp_debug_blk10_w6_reg_t blk10_w6; - volatile otp_debug_blk10_w7_reg_t blk10_w7; - volatile otp_debug_blk10_w8_reg_t blk10_w8; - volatile otp_debug_blk10_w9_reg_t blk10_w9; - volatile otp_debug_blk10_w10_reg_t blk10_w10; - volatile otp_debug_blk10_w11_reg_t blk10_w11; - volatile otp_debug_clk_reg_t clk; - volatile otp_debug_apb2otp_en_reg_t apb2otp_en; - volatile otp_debug_date_reg_t date; -} otp_debug_dev_t; - -extern otp_debug_dev_t OTP_DEBUG; - -#ifndef __cplusplus -_Static_assert(sizeof(otp_debug_dev_t) == 0x210, "Invalid size of otp_debug_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/parl_io_struct.h b/components/soc/esp32p4/include/soc/parl_io_struct.h index 97c911c737..7c1693b9bc 100644 --- a/components/soc/esp32p4/include/soc/parl_io_struct.h +++ b/components/soc/esp32p4/include/soc/parl_io_struct.h @@ -472,7 +472,7 @@ typedef union { } parl_io_version_reg_t; -typedef struct { +typedef struct parl_io_dev_t { volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg; volatile parl_io_rx_data_cfg_reg_t rx_data_cfg; volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg; diff --git a/components/soc/esp32p4/include/soc/pcr_reg.h b/components/soc/esp32p4/include/soc/pcr_reg.h deleted file mode 100644 index 7209befa4a..0000000000 --- a/components/soc/esp32p4/include/soc/pcr_reg.h +++ /dev/null @@ -1,2065 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** PCR_UART0_CONF_REG register - * UART0 configuration register - */ -#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) -/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable uart0 apb clock - */ -#define PCR_UART0_CLK_EN (BIT(0)) -#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) -#define PCR_UART0_CLK_EN_V 0x00000001U -#define PCR_UART0_CLK_EN_S 0 -/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module - */ -#define PCR_UART0_RST_EN (BIT(1)) -#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) -#define PCR_UART0_RST_EN_V 0x00000001U -#define PCR_UART0_RST_EN_S 1 - -/** PCR_UART0_SCLK_CONF_REG register - * UART0_SCLK configuration register - */ -#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) -/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the uart0 function clock. - */ -#define PCR_UART0_SCLK_DIV_A 0x0000003FU -#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) -#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU -#define PCR_UART0_SCLK_DIV_A_S 0 -/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the uart0 function clock. - */ -#define PCR_UART0_SCLK_DIV_B 0x0000003FU -#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) -#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU -#define PCR_UART0_SCLK_DIV_B_S 6 -/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; - * The integral part of the frequency divider factor of the uart0 function clock. - */ -#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU -#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) -#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU -#define PCR_UART0_SCLK_DIV_NUM_S 12 -/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; - * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: - * FOSC, 3(default): XTAL. - */ -#define PCR_UART0_SCLK_SEL 0x00000003U -#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) -#define PCR_UART0_SCLK_SEL_V 0x00000003U -#define PCR_UART0_SCLK_SEL_S 20 -/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable uart0 function clock - */ -#define PCR_UART0_SCLK_EN (BIT(22)) -#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) -#define PCR_UART0_SCLK_EN_V 0x00000001U -#define PCR_UART0_SCLK_EN_S 22 - -/** PCR_UART0_PD_CTRL_REG register - * UART0 power control register - */ -#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) -/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power down UART0 memory. - */ -#define PCR_UART0_MEM_FORCE_PU (BIT(1)) -#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) -#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U -#define PCR_UART0_MEM_FORCE_PU_S 1 -/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power up UART0 memory. - */ -#define PCR_UART0_MEM_FORCE_PD (BIT(2)) -#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) -#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U -#define PCR_UART0_MEM_FORCE_PD_S 2 - -/** PCR_UART1_CONF_REG register - * UART1 configuration register - */ -#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) -/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable uart1 apb clock - */ -#define PCR_UART1_CLK_EN (BIT(0)) -#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) -#define PCR_UART1_CLK_EN_V 0x00000001U -#define PCR_UART1_CLK_EN_S 0 -/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module - */ -#define PCR_UART1_RST_EN (BIT(1)) -#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) -#define PCR_UART1_RST_EN_V 0x00000001U -#define PCR_UART1_RST_EN_S 1 - -/** PCR_UART1_SCLK_CONF_REG register - * UART1_SCLK configuration register - */ -#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) -/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the uart1 function clock. - */ -#define PCR_UART1_SCLK_DIV_A 0x0000003FU -#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) -#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU -#define PCR_UART1_SCLK_DIV_A_S 0 -/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the uart1 function clock. - */ -#define PCR_UART1_SCLK_DIV_B 0x0000003FU -#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) -#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU -#define PCR_UART1_SCLK_DIV_B_S 6 -/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; - * The integral part of the frequency divider factor of the uart1 function clock. - */ -#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU -#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) -#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU -#define PCR_UART1_SCLK_DIV_NUM_S 12 -/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; - * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: - * FOSC, 3(default): XTAL. - */ -#define PCR_UART1_SCLK_SEL 0x00000003U -#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) -#define PCR_UART1_SCLK_SEL_V 0x00000003U -#define PCR_UART1_SCLK_SEL_S 20 -/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable uart0 function clock - */ -#define PCR_UART1_SCLK_EN (BIT(22)) -#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) -#define PCR_UART1_SCLK_EN_V 0x00000001U -#define PCR_UART1_SCLK_EN_S 22 - -/** PCR_UART1_PD_CTRL_REG register - * UART1 power control register - */ -#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) -/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power down UART1 memory. - */ -#define PCR_UART1_MEM_FORCE_PU (BIT(1)) -#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) -#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U -#define PCR_UART1_MEM_FORCE_PU_S 1 -/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power up UART1 memory. - */ -#define PCR_UART1_MEM_FORCE_PD (BIT(2)) -#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) -#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U -#define PCR_UART1_MEM_FORCE_PD_S 2 - -/** PCR_MSPI_CONF_REG register - * MSPI configuration register - */ -#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) -/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable mspi clock, include mspi pll clock - */ -#define PCR_MSPI_CLK_EN (BIT(0)) -#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) -#define PCR_MSPI_CLK_EN_V 0x00000001U -#define PCR_MSPI_CLK_EN_S 0 -/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module - */ -#define PCR_MSPI_RST_EN (BIT(1)) -#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) -#define PCR_MSPI_RST_EN_V 0x00000001U -#define PCR_MSPI_RST_EN_S 1 -/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable mspi pll clock - */ -#define PCR_MSPI_PLL_CLK_EN (BIT(2)) -#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) -#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U -#define PCR_MSPI_PLL_CLK_EN_S 2 - -/** PCR_MSPI_CLK_CONF_REG register - * MSPI_CLK configuration register - */ -#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) -/** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a - * low-speed clock-source such as XTAL/FOSC. - */ -#define PCR_MSPI_FAST_LS_DIV_NUM 0x000000FFU -#define PCR_MSPI_FAST_LS_DIV_NUM_M (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S) -#define PCR_MSPI_FAST_LS_DIV_NUM_V 0x000000FFU -#define PCR_MSPI_FAST_LS_DIV_NUM_S 0 -/** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; - * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a - * high-speed clock-source such as SPLL. - */ -#define PCR_MSPI_FAST_HS_DIV_NUM 0x000000FFU -#define PCR_MSPI_FAST_HS_DIV_NUM_M (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S) -#define PCR_MSPI_FAST_HS_DIV_NUM_V 0x000000FFU -#define PCR_MSPI_FAST_HS_DIV_NUM_S 8 - -/** PCR_I2C_CONF_REG register - * I2C configuration register - */ -#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) -/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable i2c apb clock - */ -#define PCR_I2C_CLK_EN (BIT(0)) -#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) -#define PCR_I2C_CLK_EN_V 0x00000001U -#define PCR_I2C_CLK_EN_S 0 -/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module - */ -#define PCR_I2C_RST_EN (BIT(1)) -#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) -#define PCR_I2C_RST_EN_V 0x00000001U -#define PCR_I2C_RST_EN_S 1 - -/** PCR_I2C_SCLK_CONF_REG register - * I2C_SCLK configuration register - */ -#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) -/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the i2c function clock. - */ -#define PCR_I2C_SCLK_DIV_A 0x0000003FU -#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) -#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU -#define PCR_I2C_SCLK_DIV_A_S 0 -/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the i2c function clock. - */ -#define PCR_I2C_SCLK_DIV_B 0x0000003FU -#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) -#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU -#define PCR_I2C_SCLK_DIV_B_S 6 -/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; - * The integral part of the frequency divider factor of the i2c function clock. - */ -#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU -#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) -#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU -#define PCR_I2C_SCLK_DIV_NUM_S 12 -/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ -#define PCR_I2C_SCLK_SEL (BIT(20)) -#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) -#define PCR_I2C_SCLK_SEL_V 0x00000001U -#define PCR_I2C_SCLK_SEL_S 20 -/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable i2c function clock - */ -#define PCR_I2C_SCLK_EN (BIT(22)) -#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) -#define PCR_I2C_SCLK_EN_V 0x00000001U -#define PCR_I2C_SCLK_EN_S 22 - -/** PCR_UHCI_CONF_REG register - * UHCI configuration register - */ -#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28) -/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable uhci clock - */ -#define PCR_UHCI_CLK_EN (BIT(0)) -#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) -#define PCR_UHCI_CLK_EN_V 0x00000001U -#define PCR_UHCI_CLK_EN_S 0 -/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uhci module - */ -#define PCR_UHCI_RST_EN (BIT(1)) -#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) -#define PCR_UHCI_RST_EN_V 0x00000001U -#define PCR_UHCI_RST_EN_S 1 - -/** PCR_RMT_CONF_REG register - * RMT configuration register - */ -#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c) -/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable rmt apb clock - */ -#define PCR_RMT_CLK_EN (BIT(0)) -#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) -#define PCR_RMT_CLK_EN_V 0x00000001U -#define PCR_RMT_CLK_EN_S 0 -/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rmt module - */ -#define PCR_RMT_RST_EN (BIT(1)) -#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) -#define PCR_RMT_RST_EN_V 0x00000001U -#define PCR_RMT_RST_EN_S 1 - -/** PCR_RMT_SCLK_CONF_REG register - * RMT_SCLK configuration register - */ -#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30) -/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the rmt function clock. - */ -#define PCR_RMT_SCLK_DIV_A 0x0000003FU -#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) -#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU -#define PCR_RMT_SCLK_DIV_A_S 0 -/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the rmt function clock. - */ -#define PCR_RMT_SCLK_DIV_B 0x0000003FU -#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) -#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU -#define PCR_RMT_SCLK_DIV_B_S 6 -/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor of the rmt function clock. - */ -#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU -#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) -#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU -#define PCR_RMT_SCLK_DIV_NUM_S 12 -/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; - * set this field to select clock-source. 0: do not select anyone clock, 1(default): - * 80MHz, 2: FOSC, 3: XTAL. - */ -#define PCR_RMT_SCLK_SEL 0x00000003U -#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) -#define PCR_RMT_SCLK_SEL_V 0x00000003U -#define PCR_RMT_SCLK_SEL_S 20 -/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable rmt function clock - */ -#define PCR_RMT_SCLK_EN (BIT(22)) -#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) -#define PCR_RMT_SCLK_EN_V 0x00000001U -#define PCR_RMT_SCLK_EN_S 22 - -/** PCR_LEDC_CONF_REG register - * LEDC configuration register - */ -#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34) -/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ledc apb clock - */ -#define PCR_LEDC_CLK_EN (BIT(0)) -#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) -#define PCR_LEDC_CLK_EN_V 0x00000001U -#define PCR_LEDC_CLK_EN_S 0 -/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module - */ -#define PCR_LEDC_RST_EN (BIT(1)) -#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) -#define PCR_LEDC_RST_EN_V 0x00000001U -#define PCR_LEDC_RST_EN_S 1 - -/** PCR_LEDC_SCLK_CONF_REG register - * LEDC_SCLK configuration register - */ -#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) -/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): do not select anyone clock, 1: - * 80MHz, 2: FOSC, 3: XTAL. - */ -#define PCR_LEDC_SCLK_SEL 0x00000003U -#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) -#define PCR_LEDC_SCLK_SEL_V 0x00000003U -#define PCR_LEDC_SCLK_SEL_S 20 -/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable ledc function clock - */ -#define PCR_LEDC_SCLK_EN (BIT(22)) -#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) -#define PCR_LEDC_SCLK_EN_V 0x00000001U -#define PCR_LEDC_SCLK_EN_S 22 - -/** PCR_TIMERGROUP0_CONF_REG register - * TIMERGROUP0 configuration register - */ -#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c) -/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable timer_group0 apb clock - */ -#define PCR_TG0_CLK_EN (BIT(0)) -#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) -#define PCR_TG0_CLK_EN_V 0x00000001U -#define PCR_TG0_CLK_EN_S 0 -/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module - */ -#define PCR_TG0_RST_EN (BIT(1)) -#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) -#define PCR_TG0_RST_EN_V 0x00000001U -#define PCR_TG0_RST_EN_S 1 - -/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register - * TIMERGROUP0_TIMER_CLK configuration register - */ -#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40) -/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: - * reserved. - */ -#define PCR_TG0_TIMER_CLK_SEL 0x00000003U -#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) -#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U -#define PCR_TG0_TIMER_CLK_SEL_S 20 -/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group0 timer clock - */ -#define PCR_TG0_TIMER_CLK_EN (BIT(22)) -#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) -#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U -#define PCR_TG0_TIMER_CLK_EN_S 22 - -/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register - * TIMERGROUP0_WDT_CLK configuration register - */ -#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) -/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: - * reserved. - */ -#define PCR_TG0_WDT_CLK_SEL 0x00000003U -#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) -#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U -#define PCR_TG0_WDT_CLK_SEL_S 20 -/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group0 wdt clock - */ -#define PCR_TG0_WDT_CLK_EN (BIT(22)) -#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) -#define PCR_TG0_WDT_CLK_EN_V 0x00000001U -#define PCR_TG0_WDT_CLK_EN_S 22 - -/** PCR_TIMERGROUP1_CONF_REG register - * TIMERGROUP1 configuration register - */ -#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48) -/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable timer_group1 apb clock - */ -#define PCR_TG1_CLK_EN (BIT(0)) -#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) -#define PCR_TG1_CLK_EN_V 0x00000001U -#define PCR_TG1_CLK_EN_S 0 -/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module - */ -#define PCR_TG1_RST_EN (BIT(1)) -#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) -#define PCR_TG1_RST_EN_V 0x00000001U -#define PCR_TG1_RST_EN_S 1 - -/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register - * TIMERGROUP1_TIMER_CLK configuration register - */ -#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) -/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: - * reserved. - */ -#define PCR_TG1_TIMER_CLK_SEL 0x00000003U -#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) -#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U -#define PCR_TG1_TIMER_CLK_SEL_S 20 -/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group1 timer clock - */ -#define PCR_TG1_TIMER_CLK_EN (BIT(22)) -#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) -#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U -#define PCR_TG1_TIMER_CLK_EN_S 22 - -/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register - * TIMERGROUP1_WDT_CLK configuration register - */ -#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) -/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: - * reserved. - */ -#define PCR_TG1_WDT_CLK_SEL 0x00000003U -#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) -#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U -#define PCR_TG1_WDT_CLK_SEL_S 20 -/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group0 wdt clock - */ -#define PCR_TG1_WDT_CLK_EN (BIT(22)) -#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) -#define PCR_TG1_WDT_CLK_EN_V 0x00000001U -#define PCR_TG1_WDT_CLK_EN_S 22 - -/** PCR_SYSTIMER_CONF_REG register - * SYSTIMER configuration register - */ -#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54) -/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable systimer apb clock - */ -#define PCR_SYSTIMER_CLK_EN (BIT(0)) -#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) -#define PCR_SYSTIMER_CLK_EN_V 0x00000001U -#define PCR_SYSTIMER_CLK_EN_S 0 -/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module - */ -#define PCR_SYSTIMER_RST_EN (BIT(1)) -#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) -#define PCR_SYSTIMER_RST_EN_V 0x00000001U -#define PCR_SYSTIMER_RST_EN_S 1 - -/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register - * SYSTIMER_FUNC_CLK configuration register - */ -#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) -/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ -#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) -#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) -#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U -#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 -/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable systimer function clock - */ -#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) -#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) -#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U -#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 - -/** PCR_TWAI0_CONF_REG register - * TWAI0 configuration register - */ -#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c) -/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable twai0 apb clock - */ -#define PCR_TWAI0_CLK_EN (BIT(0)) -#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) -#define PCR_TWAI0_CLK_EN_V 0x00000001U -#define PCR_TWAI0_CLK_EN_S 0 -/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai0 module - */ -#define PCR_TWAI0_RST_EN (BIT(1)) -#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) -#define PCR_TWAI0_RST_EN_V 0x00000001U -#define PCR_TWAI0_RST_EN_S 1 - -/** PCR_TWAI0_FUNC_CLK_CONF_REG register - * TWAI0_FUNC_CLK configuration register - */ -#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) -/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ -#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) -#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) -#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U -#define PCR_TWAI0_FUNC_CLK_SEL_S 20 -/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable twai0 function clock - */ -#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) -#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) -#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U -#define PCR_TWAI0_FUNC_CLK_EN_S 22 - -/** PCR_TWAI1_CONF_REG register - * TWAI1 configuration register - */ -#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64) -/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable twai1 apb clock - */ -#define PCR_TWAI1_CLK_EN (BIT(0)) -#define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) -#define PCR_TWAI1_CLK_EN_V 0x00000001U -#define PCR_TWAI1_CLK_EN_S 0 -/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai1 module - */ -#define PCR_TWAI1_RST_EN (BIT(1)) -#define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) -#define PCR_TWAI1_RST_EN_V 0x00000001U -#define PCR_TWAI1_RST_EN_S 1 - -/** PCR_TWAI1_FUNC_CLK_CONF_REG register - * TWAI1_FUNC_CLK configuration register - */ -#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) -/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ -#define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) -#define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) -#define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001U -#define PCR_TWAI1_FUNC_CLK_SEL_S 20 -/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable twai1 function clock - */ -#define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) -#define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) -#define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001U -#define PCR_TWAI1_FUNC_CLK_EN_S 22 - -/** PCR_I2S_CONF_REG register - * I2S configuration register - */ -#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) -/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable i2s apb clock - */ -#define PCR_I2S_CLK_EN (BIT(0)) -#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) -#define PCR_I2S_CLK_EN_V 0x00000001U -#define PCR_I2S_CLK_EN_S 0 -/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module - */ -#define PCR_I2S_RST_EN (BIT(1)) -#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) -#define PCR_I2S_RST_EN_V 0x00000001U -#define PCR_I2S_RST_EN_S 1 - -/** PCR_I2S_TX_CLKM_CONF_REG register - * I2S_TX_CLKM configuration register - */ -#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) -/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; - * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be - * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= - * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * - * (n+1)-div] + y * (n+1)-div. - */ -#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU -#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) -#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU -#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 -/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: - * I2S_MCLK_in. - */ -#define PCR_I2S_TX_CLKM_SEL 0x00000003U -#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) -#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U -#define PCR_I2S_TX_CLKM_SEL_S 20 -/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable i2s_tx function clock - */ -#define PCR_I2S_TX_CLKM_EN (BIT(22)) -#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) -#define PCR_I2S_TX_CLKM_EN_V 0x00000001U -#define PCR_I2S_TX_CLKM_EN_S 22 - -/** PCR_I2S_TX_CLKM_DIV_CONF_REG register - * I2S_TX_CLKM_DIV configuration register - */ -#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) -/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of - * I2S_TX_CLKM_DIV_Z is (a-b). - */ -#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU -#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) -#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU -#define PCR_I2S_TX_CLKM_DIV_Z_S 0 -/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of - * I2S_TX_CLKM_DIV_Y is (a%(a-b)). - */ -#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU -#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) -#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU -#define PCR_I2S_TX_CLKM_DIV_Y_S 9 -/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value - * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. - */ -#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU -#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) -#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU -#define PCR_I2S_TX_CLKM_DIV_X_S 18 -/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of - * I2S_TX_CLKM_DIV_YN1 is 1. - */ -#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) -#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) -#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U -#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 - -/** PCR_I2S_RX_CLKM_CONF_REG register - * I2S_RX_CLKM configuration register - */ -#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) -/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; - * Integral I2S clock divider value - */ -#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU -#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) -#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU -#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 -/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. - */ -#define PCR_I2S_RX_CLKM_SEL 0x00000003U -#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) -#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U -#define PCR_I2S_RX_CLKM_SEL_S 20 -/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable i2s_rx function clock - */ -#define PCR_I2S_RX_CLKM_EN (BIT(22)) -#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) -#define PCR_I2S_RX_CLKM_EN_V 0x00000001U -#define PCR_I2S_RX_CLKM_EN_S 22 -/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; - * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx - */ -#define PCR_I2S_MCLK_SEL (BIT(23)) -#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) -#define PCR_I2S_MCLK_SEL_V 0x00000001U -#define PCR_I2S_MCLK_SEL_S 23 - -/** PCR_I2S_RX_CLKM_DIV_CONF_REG register - * I2S_RX_CLKM_DIV configuration register - */ -#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) -/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of - * I2S_RX_CLKM_DIV_Z is (a-b). - */ -#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU -#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) -#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU -#define PCR_I2S_RX_CLKM_DIV_Z_S 0 -/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of - * I2S_RX_CLKM_DIV_Y is (a%(a-b)). - */ -#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU -#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) -#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU -#define PCR_I2S_RX_CLKM_DIV_Y_S 9 -/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value - * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. - */ -#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU -#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) -#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU -#define PCR_I2S_RX_CLKM_DIV_X_S 18 -/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of - * I2S_RX_CLKM_DIV_YN1 is 1. - */ -#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) -#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) -#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U -#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 - -/** PCR_SARADC_CONF_REG register - * SARADC configuration register - */ -#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) -/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; - * no use - */ -#define PCR_SARADC_CLK_EN (BIT(0)) -#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) -#define PCR_SARADC_CLK_EN_V 0x00000001U -#define PCR_SARADC_CLK_EN_S 0 -/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module - */ -#define PCR_SARADC_RST_EN (BIT(1)) -#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) -#define PCR_SARADC_RST_EN_V 0x00000001U -#define PCR_SARADC_RST_EN_S 1 -/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable saradc apb clock - */ -#define PCR_SARADC_REG_CLK_EN (BIT(2)) -#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) -#define PCR_SARADC_REG_CLK_EN_V 0x00000001U -#define PCR_SARADC_REG_CLK_EN_S 2 -/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module - */ -#define PCR_SARADC_REG_RST_EN (BIT(3)) -#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) -#define PCR_SARADC_REG_RST_EN_V 0x00000001U -#define PCR_SARADC_REG_RST_EN_S 3 - -/** PCR_SARADC_CLKM_CONF_REG register - * SARADC_CLKM configuration register - */ -#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) -/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the saradc function clock. - */ -#define PCR_SARADC_CLKM_DIV_A 0x0000003FU -#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) -#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU -#define PCR_SARADC_CLKM_DIV_A_S 0 -/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the saradc function clock. - */ -#define PCR_SARADC_CLKM_DIV_B 0x0000003FU -#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) -#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU -#define PCR_SARADC_CLKM_DIV_B_S 6 -/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; - * The integral part of the frequency divider factor of the saradc function clock. - */ -#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU -#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) -#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU -#define PCR_SARADC_CLKM_DIV_NUM_S 12 -/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: - * reserved. - */ -#define PCR_SARADC_CLKM_SEL 0x00000003U -#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) -#define PCR_SARADC_CLKM_SEL_V 0x00000003U -#define PCR_SARADC_CLKM_SEL_S 20 -/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable saradc function clock - */ -#define PCR_SARADC_CLKM_EN (BIT(22)) -#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) -#define PCR_SARADC_CLKM_EN_V 0x00000001U -#define PCR_SARADC_CLKM_EN_S 22 - -/** PCR_TSENS_CLK_CONF_REG register - * TSENS_CLK configuration register - */ -#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) -/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): FOSC, 1: XTAL. - */ -#define PCR_TSENS_CLK_SEL (BIT(20)) -#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) -#define PCR_TSENS_CLK_SEL_V 0x00000001U -#define PCR_TSENS_CLK_SEL_S 20 -/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable tsens clock - */ -#define PCR_TSENS_CLK_EN (BIT(22)) -#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) -#define PCR_TSENS_CLK_EN_V 0x00000001U -#define PCR_TSENS_CLK_EN_S 22 -/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module - */ -#define PCR_TSENS_RST_EN (BIT(23)) -#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) -#define PCR_TSENS_RST_EN_V 0x00000001U -#define PCR_TSENS_RST_EN_S 23 - -/** PCR_USB_DEVICE_CONF_REG register - * USB_DEVICE configuration register - */ -#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) -/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable usb_device clock - */ -#define PCR_USB_DEVICE_CLK_EN (BIT(0)) -#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) -#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U -#define PCR_USB_DEVICE_CLK_EN_S 0 -/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module - */ -#define PCR_USB_DEVICE_RST_EN (BIT(1)) -#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) -#define PCR_USB_DEVICE_RST_EN_V 0x00000001U -#define PCR_USB_DEVICE_RST_EN_S 1 - -/** PCR_INTMTX_CONF_REG register - * INTMTX configuration register - */ -#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) -/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable intmtx clock - */ -#define PCR_INTMTX_CLK_EN (BIT(0)) -#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) -#define PCR_INTMTX_CLK_EN_V 0x00000001U -#define PCR_INTMTX_CLK_EN_S 0 -/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module - */ -#define PCR_INTMTX_RST_EN (BIT(1)) -#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) -#define PCR_INTMTX_RST_EN_V 0x00000001U -#define PCR_INTMTX_RST_EN_S 1 - -/** PCR_PCNT_CONF_REG register - * PCNT configuration register - */ -#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) -/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable pcnt clock - */ -#define PCR_PCNT_CLK_EN (BIT(0)) -#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) -#define PCR_PCNT_CLK_EN_V 0x00000001U -#define PCR_PCNT_CLK_EN_S 0 -/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pcnt module - */ -#define PCR_PCNT_RST_EN (BIT(1)) -#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) -#define PCR_PCNT_RST_EN_V 0x00000001U -#define PCR_PCNT_RST_EN_S 1 - -/** PCR_ETM_CONF_REG register - * ETM configuration register - */ -#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) -/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable etm clock - */ -#define PCR_ETM_CLK_EN (BIT(0)) -#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) -#define PCR_ETM_CLK_EN_V 0x00000001U -#define PCR_ETM_CLK_EN_S 0 -/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module - */ -#define PCR_ETM_RST_EN (BIT(1)) -#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) -#define PCR_ETM_RST_EN_V 0x00000001U -#define PCR_ETM_RST_EN_S 1 - -/** PCR_PWM_CONF_REG register - * PWM configuration register - */ -#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) -/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable pwm clock - */ -#define PCR_PWM_CLK_EN (BIT(0)) -#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) -#define PCR_PWM_CLK_EN_V 0x00000001U -#define PCR_PWM_CLK_EN_S 0 -/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pwm module - */ -#define PCR_PWM_RST_EN (BIT(1)) -#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) -#define PCR_PWM_RST_EN_V 0x00000001U -#define PCR_PWM_RST_EN_S 1 - -/** PCR_PWM_CLK_CONF_REG register - * PWM_CLK configuration register - */ -#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) -/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; - * The integral part of the frequency divider factor of the pwm function clock. - */ -#define PCR_PWM_DIV_NUM 0x000000FFU -#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) -#define PCR_PWM_DIV_NUM_V 0x000000FFU -#define PCR_PWM_DIV_NUM_S 12 -/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): do not select anyone clock, 1: - * 160MHz, 2: XTAL, 3: FOSC. - */ -#define PCR_PWM_CLKM_SEL 0x00000003U -#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) -#define PCR_PWM_CLKM_SEL_V 0x00000003U -#define PCR_PWM_CLKM_SEL_S 20 -/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; - * set this field as 1 to activate pwm clkm. - */ -#define PCR_PWM_CLKM_EN (BIT(22)) -#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) -#define PCR_PWM_CLKM_EN_V 0x00000001U -#define PCR_PWM_CLKM_EN_S 22 - -/** PCR_PARL_IO_CONF_REG register - * PARL_IO configuration register - */ -#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) -/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable parl apb clock - */ -#define PCR_PARL_CLK_EN (BIT(0)) -#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) -#define PCR_PARL_CLK_EN_V 0x00000001U -#define PCR_PARL_CLK_EN_S 0 -/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset parl apb reg - */ -#define PCR_PARL_RST_EN (BIT(1)) -#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) -#define PCR_PARL_RST_EN_V 0x00000001U -#define PCR_PARL_RST_EN_S 1 - -/** PCR_PARL_CLK_RX_CONF_REG register - * PARL_CLK_RX configuration register - */ -#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) -/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; - * The integral part of the frequency divider factor of the parl rx clock. - */ -#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU -#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) -#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU -#define PCR_PARL_CLK_RX_DIV_NUM_S 0 -/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: - * user clock from pad. - */ -#define PCR_PARL_CLK_RX_SEL 0x00000003U -#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) -#define PCR_PARL_CLK_RX_SEL_V 0x00000003U -#define PCR_PARL_CLK_RX_SEL_S 16 -/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; - * Set 1 to enable parl rx clock - */ -#define PCR_PARL_CLK_RX_EN (BIT(18)) -#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) -#define PCR_PARL_CLK_RX_EN_V 0x00000001U -#define PCR_PARL_CLK_RX_EN_S 18 -/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl rx module - */ -#define PCR_PARL_RX_RST_EN (BIT(19)) -#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) -#define PCR_PARL_RX_RST_EN_V 0x00000001U -#define PCR_PARL_RX_RST_EN_S 19 - -/** PCR_PARL_CLK_TX_CONF_REG register - * PARL_CLK_TX configuration register - */ -#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) -/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; - * The integral part of the frequency divider factor of the parl tx clock. - */ -#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU -#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) -#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU -#define PCR_PARL_CLK_TX_DIV_NUM_S 0 -/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: - * user clock from pad. - */ -#define PCR_PARL_CLK_TX_SEL 0x00000003U -#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) -#define PCR_PARL_CLK_TX_SEL_V 0x00000003U -#define PCR_PARL_CLK_TX_SEL_S 16 -/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; - * Set 1 to enable parl tx clock - */ -#define PCR_PARL_CLK_TX_EN (BIT(18)) -#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) -#define PCR_PARL_CLK_TX_EN_V 0x00000001U -#define PCR_PARL_CLK_TX_EN_S 18 -/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl tx module - */ -#define PCR_PARL_TX_RST_EN (BIT(19)) -#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) -#define PCR_PARL_TX_RST_EN_V 0x00000001U -#define PCR_PARL_TX_RST_EN_S 19 - -/** PCR_SDIO_SLAVE_CONF_REG register - * SDIO_SLAVE configuration register - */ -#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0) -/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable sdio_slave clock - */ -#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) -#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) -#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U -#define PCR_SDIO_SLAVE_CLK_EN_S 0 -/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sdio_slave module - */ -#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) -#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) -#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U -#define PCR_SDIO_SLAVE_RST_EN_S 1 - -/** PCR_PVT_MONITOR_CONF_REG register - * PVT_MONITOR configuration register - */ -#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4) -/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable apb clock of pvt module - */ -#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) -#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) -#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U -#define PCR_PVT_MONITOR_CLK_EN_S 0 -/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset all pvt monitor module - */ -#define PCR_PVT_MONITOR_RST_EN (BIT(1)) -#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) -#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U -#define PCR_PVT_MONITOR_RST_EN_S 1 -/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable function clock of modem pvt module - */ -#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) -#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) -#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U -#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 -/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; - * Set 1 to enable function clock of cpu pvt module - */ -#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) -#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) -#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U -#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 -/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; - * Set 1 to enable function clock of hp_peri pvt module - */ -#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) -#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) -#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U -#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 - -/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register - * PVT_MONITOR function clock configuration register - */ -#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8) -/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; - * The integral part of the frequency divider factor of the pvt_monitor function clock. - */ -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 -/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL - * divided by 3. - */ -#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) -#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) -#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U -#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 -/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable source clock of pvt sitex - */ -#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) -#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) -#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U -#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 - -/** PCR_GDMA_CONF_REG register - * GDMA configuration register - */ -#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc) -/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable gdma clock - */ -#define PCR_GDMA_CLK_EN (BIT(0)) -#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) -#define PCR_GDMA_CLK_EN_V 0x00000001U -#define PCR_GDMA_CLK_EN_S 0 -/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module - */ -#define PCR_GDMA_RST_EN (BIT(1)) -#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) -#define PCR_GDMA_RST_EN_V 0x00000001U -#define PCR_GDMA_RST_EN_S 1 - -/** PCR_SPI2_CONF_REG register - * SPI2 configuration register - */ -#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0) -/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable spi2 apb clock - */ -#define PCR_SPI2_CLK_EN (BIT(0)) -#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) -#define PCR_SPI2_CLK_EN_V 0x00000001U -#define PCR_SPI2_CLK_EN_S 0 -/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module - */ -#define PCR_SPI2_RST_EN (BIT(1)) -#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) -#define PCR_SPI2_RST_EN_V 0x00000001U -#define PCR_SPI2_RST_EN_S 1 - -/** PCR_SPI2_CLKM_CONF_REG register - * SPI2_CLKM configuration register - */ -#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4) -/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: - * reserved. - */ -#define PCR_SPI2_CLKM_SEL 0x00000003U -#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) -#define PCR_SPI2_CLKM_SEL_V 0x00000003U -#define PCR_SPI2_CLKM_SEL_S 20 -/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable spi2 function clock - */ -#define PCR_SPI2_CLKM_EN (BIT(22)) -#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) -#define PCR_SPI2_CLKM_EN_V 0x00000001U -#define PCR_SPI2_CLKM_EN_S 22 - -/** PCR_AES_CONF_REG register - * AES configuration register - */ -#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8) -/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable aes clock - */ -#define PCR_AES_CLK_EN (BIT(0)) -#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) -#define PCR_AES_CLK_EN_V 0x00000001U -#define PCR_AES_CLK_EN_S 0 -/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module - */ -#define PCR_AES_RST_EN (BIT(1)) -#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) -#define PCR_AES_RST_EN_V 0x00000001U -#define PCR_AES_RST_EN_S 1 - -/** PCR_SHA_CONF_REG register - * SHA configuration register - */ -#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc) -/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable sha clock - */ -#define PCR_SHA_CLK_EN (BIT(0)) -#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) -#define PCR_SHA_CLK_EN_V 0x00000001U -#define PCR_SHA_CLK_EN_S 0 -/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module - */ -#define PCR_SHA_RST_EN (BIT(1)) -#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) -#define PCR_SHA_RST_EN_V 0x00000001U -#define PCR_SHA_RST_EN_S 1 - -/** PCR_RSA_CONF_REG register - * RSA configuration register - */ -#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0) -/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable rsa clock - */ -#define PCR_RSA_CLK_EN (BIT(0)) -#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) -#define PCR_RSA_CLK_EN_V 0x00000001U -#define PCR_RSA_CLK_EN_S 0 -/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module - */ -#define PCR_RSA_RST_EN (BIT(1)) -#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) -#define PCR_RSA_RST_EN_V 0x00000001U -#define PCR_RSA_RST_EN_S 1 - -/** PCR_RSA_PD_CTRL_REG register - * RSA power control register - */ -#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4) -/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to power down rsa internal memory. - */ -#define PCR_RSA_MEM_PD (BIT(0)) -#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) -#define PCR_RSA_MEM_PD_V 0x00000001U -#define PCR_RSA_MEM_PD_S 0 -/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power up rsa internal memory - */ -#define PCR_RSA_MEM_FORCE_PU (BIT(1)) -#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) -#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U -#define PCR_RSA_MEM_FORCE_PU_S 1 -/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power down rsa internal memory. - */ -#define PCR_RSA_MEM_FORCE_PD (BIT(2)) -#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) -#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U -#define PCR_RSA_MEM_FORCE_PD_S 2 - -/** PCR_ECC_CONF_REG register - * ECC configuration register - */ -#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8) -/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ecc clock - */ -#define PCR_ECC_CLK_EN (BIT(0)) -#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) -#define PCR_ECC_CLK_EN_V 0x00000001U -#define PCR_ECC_CLK_EN_S 0 -/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module - */ -#define PCR_ECC_RST_EN (BIT(1)) -#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) -#define PCR_ECC_RST_EN_V 0x00000001U -#define PCR_ECC_RST_EN_S 1 - -/** PCR_ECC_PD_CTRL_REG register - * ECC power control register - */ -#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc) -/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to power down ecc internal memory. - */ -#define PCR_ECC_MEM_PD (BIT(0)) -#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) -#define PCR_ECC_MEM_PD_V 0x00000001U -#define PCR_ECC_MEM_PD_S 0 -/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power up ecc internal memory - */ -#define PCR_ECC_MEM_FORCE_PU (BIT(1)) -#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) -#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U -#define PCR_ECC_MEM_FORCE_PU_S 1 -/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power down ecc internal memory. - */ -#define PCR_ECC_MEM_FORCE_PD (BIT(2)) -#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) -#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U -#define PCR_ECC_MEM_FORCE_PD_S 2 - -/** PCR_DS_CONF_REG register - * DS configuration register - */ -#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0) -/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ds clock - */ -#define PCR_DS_CLK_EN (BIT(0)) -#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) -#define PCR_DS_CLK_EN_V 0x00000001U -#define PCR_DS_CLK_EN_S 0 -/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module - */ -#define PCR_DS_RST_EN (BIT(1)) -#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) -#define PCR_DS_RST_EN_V 0x00000001U -#define PCR_DS_RST_EN_S 1 - -/** PCR_HMAC_CONF_REG register - * HMAC configuration register - */ -#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4) -/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable hmac clock - */ -#define PCR_HMAC_CLK_EN (BIT(0)) -#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) -#define PCR_HMAC_CLK_EN_V 0x00000001U -#define PCR_HMAC_CLK_EN_S 0 -/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module - */ -#define PCR_HMAC_RST_EN (BIT(1)) -#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) -#define PCR_HMAC_RST_EN_V 0x00000001U -#define PCR_HMAC_RST_EN_S 1 - -/** PCR_IOMUX_CONF_REG register - * IOMUX configuration register - */ -#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) -/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable iomux apb clock - */ -#define PCR_IOMUX_CLK_EN (BIT(0)) -#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) -#define PCR_IOMUX_CLK_EN_V 0x00000001U -#define PCR_IOMUX_CLK_EN_S 0 -/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module - */ -#define PCR_IOMUX_RST_EN (BIT(1)) -#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) -#define PCR_IOMUX_RST_EN_V 0x00000001U -#define PCR_IOMUX_RST_EN_S 1 - -/** PCR_IOMUX_CLK_CONF_REG register - * IOMUX_CLK configuration register - */ -#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) -/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3; - * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: - * FOSC, 3(default): XTAL. - */ -#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U -#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) -#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U -#define PCR_IOMUX_FUNC_CLK_SEL_S 20 -/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable iomux function clock - */ -#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) -#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) -#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U -#define PCR_IOMUX_FUNC_CLK_EN_S 22 - -/** PCR_MEM_MONITOR_CONF_REG register - * MEM_MONITOR configuration register - */ -#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) -/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable mem_monitor clock - */ -#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) -#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) -#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U -#define PCR_MEM_MONITOR_CLK_EN_S 0 -/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mem_monitor module - */ -#define PCR_MEM_MONITOR_RST_EN (BIT(1)) -#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) -#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U -#define PCR_MEM_MONITOR_RST_EN_S 1 - -/** PCR_REGDMA_CONF_REG register - * REGDMA configuration register - */ -#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) -/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set 1 to enable regdma clock - */ -#define PCR_REGDMA_CLK_EN (BIT(0)) -#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) -#define PCR_REGDMA_CLK_EN_V 0x00000001U -#define PCR_REGDMA_CLK_EN_S 0 -/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module - */ -#define PCR_REGDMA_RST_EN (BIT(1)) -#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) -#define PCR_REGDMA_RST_EN_V 0x00000001U -#define PCR_REGDMA_RST_EN_S 1 - -/** PCR_RETENTION_CONF_REG register - * retention configuration register - */ -#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8) -/** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set 1 to enable retention clock - */ -#define PCR_RETENTION_CLK_EN (BIT(0)) -#define PCR_RETENTION_CLK_EN_M (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S) -#define PCR_RETENTION_CLK_EN_V 0x00000001U -#define PCR_RETENTION_CLK_EN_S 0 -/** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset retention module - */ -#define PCR_RETENTION_RST_EN (BIT(1)) -#define PCR_RETENTION_RST_EN_M (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S) -#define PCR_RETENTION_RST_EN_V 0x00000001U -#define PCR_RETENTION_RST_EN_S 1 - -/** PCR_TRACE_CONF_REG register - * TRACE configuration register - */ -#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc) -/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable trace clock - */ -#define PCR_TRACE_CLK_EN (BIT(0)) -#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) -#define PCR_TRACE_CLK_EN_V 0x00000001U -#define PCR_TRACE_CLK_EN_S 0 -/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module - */ -#define PCR_TRACE_RST_EN (BIT(1)) -#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) -#define PCR_TRACE_RST_EN_V 0x00000001U -#define PCR_TRACE_RST_EN_S 1 - -/** PCR_ASSIST_CONF_REG register - * ASSIST configuration register - */ -#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100) -/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable assist clock - */ -#define PCR_ASSIST_CLK_EN (BIT(0)) -#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) -#define PCR_ASSIST_CLK_EN_V 0x00000001U -#define PCR_ASSIST_CLK_EN_S 0 -/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module - */ -#define PCR_ASSIST_RST_EN (BIT(1)) -#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) -#define PCR_ASSIST_RST_EN_V 0x00000001U -#define PCR_ASSIST_RST_EN_S 1 - -/** PCR_CACHE_CONF_REG register - * CACHE configuration register - */ -#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104) -/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable cache clock - */ -#define PCR_CACHE_CLK_EN (BIT(0)) -#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) -#define PCR_CACHE_CLK_EN_V 0x00000001U -#define PCR_CACHE_CLK_EN_S 0 -/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module - */ -#define PCR_CACHE_RST_EN (BIT(1)) -#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) -#define PCR_CACHE_RST_EN_V 0x00000001U -#define PCR_CACHE_RST_EN_S 1 - -/** PCR_MODEM_APB_CONF_REG register - * MODEM_APB configuration register - */ -#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108) -/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). - */ -#define PCR_MODEM_APB_CLK_EN (BIT(0)) -#define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) -#define PCR_MODEM_APB_CLK_EN_V 0x00000001U -#define PCR_MODEM_APB_CLK_EN_S 0 -/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set this file as 1 to reset modem-subsystem. - */ -#define PCR_MODEM_RST_EN (BIT(1)) -#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) -#define PCR_MODEM_RST_EN_V 0x00000001U -#define PCR_MODEM_RST_EN_S 1 - -/** PCR_TIMEOUT_CONF_REG register - * TIMEOUT configuration register - */ -#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) -/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module - */ -#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) -#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) -#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U -#define PCR_CPU_TIMEOUT_RST_EN_S 1 -/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module - */ -#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) -#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) -#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U -#define PCR_HP_TIMEOUT_RST_EN_S 2 - -/** PCR_SYSCLK_CONF_REG register - * SYSCLK configuration register - */ -#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) -/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; - * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed - * clock-source such as XTAL/FOSC. - */ -#define PCR_LS_DIV_NUM 0x000000FFU -#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) -#define PCR_LS_DIV_NUM_V 0x000000FFU -#define PCR_LS_DIV_NUM_S 0 -/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; - * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. - */ -#define PCR_HS_DIV_NUM 0x000000FFU -#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) -#define PCR_HS_DIV_NUM_V 0x000000FFU -#define PCR_HS_DIV_NUM_S 8 -/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. - */ -#define PCR_SOC_CLK_SEL 0x00000003U -#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) -#define PCR_SOC_CLK_SEL_V 0x00000003U -#define PCR_SOC_CLK_SEL_S 16 -/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; - * This field indicates the frequency(MHz) of XTAL. - */ -#define PCR_CLK_XTAL_FREQ 0x0000007FU -#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) -#define PCR_CLK_XTAL_FREQ_V 0x0000007FU -#define PCR_CLK_XTAL_FREQ_S 24 - -/** PCR_CPU_WAITI_CONF_REG register - * CPU_WAITI configuration register - */ -#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) -/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM - */ -#define PCR_CPUPERIOD_SEL 0x00000003U -#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) -#define PCR_CPUPERIOD_SEL_V 0x00000003U -#define PCR_CPUPERIOD_SEL_S 0 -/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM - */ -#define PCR_PLL_FREQ_SEL (BIT(2)) -#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) -#define PCR_PLL_FREQ_SEL_V 0x00000001U -#define PCR_PLL_FREQ_SEL_S 2 -/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; - * Set 1 to force cpu_waiti_clk enable. - */ -#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) -#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) -#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U -#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 -/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; - * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk - * will close - */ -#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU -#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) -#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU -#define PCR_CPU_WAITI_DELAY_NUM_S 4 - -/** PCR_CPU_FREQ_CONF_REG register - * CPU_FREQ configuration register - */ -#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) -/** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed - * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. - */ -#define PCR_CPU_LS_DIV_NUM 0x000000FFU -#define PCR_CPU_LS_DIV_NUM_M (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S) -#define PCR_CPU_LS_DIV_NUM_V 0x000000FFU -#define PCR_CPU_LS_DIV_NUM_S 0 -/** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed - * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. - */ -#define PCR_CPU_HS_DIV_NUM 0x000000FFU -#define PCR_CPU_HS_DIV_NUM_M (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S) -#define PCR_CPU_HS_DIV_NUM_V 0x000000FFU -#define PCR_CPU_HS_DIV_NUM_S 8 -/** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0; - * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. - * Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. - */ -#define PCR_CPU_HS_120M_FORCE (BIT(16)) -#define PCR_CPU_HS_120M_FORCE_M (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S) -#define PCR_CPU_HS_120M_FORCE_V 0x00000001U -#define PCR_CPU_HS_120M_FORCE_S 16 - -/** PCR_AHB_FREQ_CONF_REG register - * AHB_FREQ configuration register - */ -#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) -/** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb - * is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for - * low-speed clock-source such as XTAL/FOSC, and should be used together with - * PCR_CPU_LS_DIV_NUM. - */ -#define PCR_AHB_LS_DIV_NUM 0x000000FFU -#define PCR_AHB_LS_DIV_NUM_M (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S) -#define PCR_AHB_LS_DIV_NUM_V 0x000000FFU -#define PCR_AHB_LS_DIV_NUM_S 0 -/** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; - * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is - * div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed - * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. - */ -#define PCR_AHB_HS_DIV_NUM 0x000000FFU -#define PCR_AHB_HS_DIV_NUM_M (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S) -#define PCR_AHB_HS_DIV_NUM_V 0x000000FFU -#define PCR_AHB_HS_DIV_NUM_S 8 - -/** PCR_APB_FREQ_CONF_REG register - * APB_FREQ configuration register - */ -#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120) -/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be - * automatically down to clk_apb_decrease only when no access is on apb-bus, and will - * recover to the previous frequency when a new access appears on apb-bus. Set as one - * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note - * that enable this function will reduce performance. Users can set this field as zero - * to disable the auto-decrease-apb-freq function. By default, this function is - * disable. - */ -#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU -#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) -#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU -#define PCR_APB_DECREASE_DIV_NUM_S 0 -/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is - * div1(default)/div2/div4 of clk_ahb. - */ -#define PCR_APB_DIV_NUM 0x000000FFU -#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) -#define PCR_APB_DIV_NUM_V 0x000000FFU -#define PCR_APB_DIV_NUM_S 8 - -/** PCR_SYSCLK_FREQ_QUERY_0_REG register - * SYSCLK frequency query 0 register - */ -#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124) -/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20; - * This field indicates the frequency(MHz) of FOSC. - */ -#define PCR_FOSC_FREQ 0x000000FFU -#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) -#define PCR_FOSC_FREQ_V 0x000000FFU -#define PCR_FOSC_FREQ_S 0 -/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480; - * This field indicates the frequency(MHz) of SPLL. - */ -#define PCR_PLL_FREQ 0x000003FFU -#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) -#define PCR_PLL_FREQ_V 0x000003FFU -#define PCR_PLL_FREQ_S 8 - -/** PCR_PLL_DIV_CLK_EN_REG register - * SPLL DIV clock-gating configuration register - */ -#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) -/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_240M_CLK_EN (BIT(0)) -#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) -#define PCR_PLL_240M_CLK_EN_V 0x00000001U -#define PCR_PLL_240M_CLK_EN_S 0 -/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_160M_CLK_EN (BIT(1)) -#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) -#define PCR_PLL_160M_CLK_EN_V 0x00000001U -#define PCR_PLL_160M_CLK_EN_S 1 -/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_120M_CLK_EN (BIT(2)) -#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) -#define PCR_PLL_120M_CLK_EN_V 0x00000001U -#define PCR_PLL_120M_CLK_EN_S 2 -/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_80M_CLK_EN (BIT(3)) -#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) -#define PCR_PLL_80M_CLK_EN_V 0x00000001U -#define PCR_PLL_80M_CLK_EN_S 3 -/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_48M_CLK_EN (BIT(4)) -#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) -#define PCR_PLL_48M_CLK_EN_V 0x00000001U -#define PCR_PLL_48M_CLK_EN_S 4 -/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_40M_CLK_EN (BIT(5)) -#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) -#define PCR_PLL_40M_CLK_EN_V 0x00000001U -#define PCR_PLL_40M_CLK_EN_S 5 -/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_20M_CLK_EN (BIT(6)) -#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) -#define PCR_PLL_20M_CLK_EN_V 0x00000001U -#define PCR_PLL_20M_CLK_EN_S 6 - -/** PCR_CTRL_CLK_OUT_EN_REG register - * CLK_OUT_EN configuration register - */ -#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c) -/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable 20m clock - */ -#define PCR_CLK20_OEN (BIT(0)) -#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) -#define PCR_CLK20_OEN_V 0x00000001U -#define PCR_CLK20_OEN_S 0 -/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; - * Set 1 to enable 22m clock - */ -#define PCR_CLK22_OEN (BIT(1)) -#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) -#define PCR_CLK22_OEN_V 0x00000001U -#define PCR_CLK22_OEN_S 1 -/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable 44m clock - */ -#define PCR_CLK44_OEN (BIT(2)) -#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) -#define PCR_CLK44_OEN_V 0x00000001U -#define PCR_CLK44_OEN_S 2 -/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; - * Set 1 to enable bb clock - */ -#define PCR_CLK_BB_OEN (BIT(3)) -#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) -#define PCR_CLK_BB_OEN_V 0x00000001U -#define PCR_CLK_BB_OEN_S 3 -/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; - * Set 1 to enable 80m clock - */ -#define PCR_CLK80_OEN (BIT(4)) -#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) -#define PCR_CLK80_OEN_V 0x00000001U -#define PCR_CLK80_OEN_S 4 -/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; - * Set 1 to enable 160m clock - */ -#define PCR_CLK160_OEN (BIT(5)) -#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) -#define PCR_CLK160_OEN_V 0x00000001U -#define PCR_CLK160_OEN_S 5 -/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; - * Set 1 to enable 320m clock - */ -#define PCR_CLK_320M_OEN (BIT(6)) -#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) -#define PCR_CLK_320M_OEN_V 0x00000001U -#define PCR_CLK_320M_OEN_S 6 -/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; - * Reserved - */ -#define PCR_CLK_ADC_INF_OEN (BIT(7)) -#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) -#define PCR_CLK_ADC_INF_OEN_V 0x00000001U -#define PCR_CLK_ADC_INF_OEN_S 7 -/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; - * Reserved - */ -#define PCR_CLK_DAC_CPU_OEN (BIT(8)) -#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) -#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U -#define PCR_CLK_DAC_CPU_OEN_S 8 -/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; - * Set 1 to enable 40x_bb clock - */ -#define PCR_CLK40X_BB_OEN (BIT(9)) -#define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) -#define PCR_CLK40X_BB_OEN_V 0x00000001U -#define PCR_CLK40X_BB_OEN_S 9 -/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; - * Set 1 to enable xtal clock - */ -#define PCR_CLK_XTAL_OEN (BIT(10)) -#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) -#define PCR_CLK_XTAL_OEN_V 0x00000001U -#define PCR_CLK_XTAL_OEN_S 10 - -/** PCR_CTRL_TICK_CONF_REG register - * TICK configuration register - */ -#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130) -/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; - * ******* Description *********** - */ -#define PCR_XTAL_TICK_NUM 0x000000FFU -#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) -#define PCR_XTAL_TICK_NUM_V 0x000000FFU -#define PCR_XTAL_TICK_NUM_S 0 -/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; - * ******* Description *********** - */ -#define PCR_FOSC_TICK_NUM 0x000000FFU -#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) -#define PCR_FOSC_TICK_NUM_V 0x000000FFU -#define PCR_FOSC_TICK_NUM_S 8 -/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; - * ******* Description *********** - */ -#define PCR_TICK_ENABLE (BIT(16)) -#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) -#define PCR_TICK_ENABLE_V 0x00000001U -#define PCR_TICK_ENABLE_S 16 -/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; - * ******* Description *********** - */ -#define PCR_RST_TICK_CNT (BIT(17)) -#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) -#define PCR_RST_TICK_CNT_V 0x00000001U -#define PCR_RST_TICK_CNT_S 17 - -/** PCR_CTRL_32K_CONF_REG register - * 32KHz clock configuration register - */ -#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134) -/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; - * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and - * timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. - */ -#define PCR_32K_SEL 0x00000003U -#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) -#define PCR_32K_SEL_V 0x00000003U -#define PCR_32K_SEL_S 0 - -/** PCR_SRAM_POWER_CONF_REG register - * HP SRAM/ROM configuration register - */ -#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138) -/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; - * Set this bit to force power up SRAM - */ -#define PCR_SRAM_FORCE_PU 0x0000000FU -#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) -#define PCR_SRAM_FORCE_PU_V 0x0000000FU -#define PCR_SRAM_FORCE_PU_S 0 -/** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0; - * Set this bit to force power down SRAM. - */ -#define PCR_SRAM_FORCE_PD 0x0000000FU -#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) -#define PCR_SRAM_FORCE_PD_V 0x0000000FU -#define PCR_SRAM_FORCE_PD_S 4 -/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A - * gate-clock will be used when accessing the SRAM. - */ -#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000FU -#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) -#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU -#define PCR_SRAM_CLKGATE_FORCE_ON_S 8 -/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7; - * Set this bit to force power up ROM - */ -#define PCR_ROM_FORCE_PU 0x00000007U -#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) -#define PCR_ROM_FORCE_PU_V 0x00000007U -#define PCR_ROM_FORCE_PU_S 12 -/** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0; - * Set this bit to force power down ROM. - */ -#define PCR_ROM_FORCE_PD 0x00000007U -#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) -#define PCR_ROM_FORCE_PD_V 0x00000007U -#define PCR_ROM_FORCE_PD_S 15 -/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A - * gate-clock will be used when accessing the ROM. - */ -#define PCR_ROM_CLKGATE_FORCE_ON 0x00000007U -#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) -#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007U -#define PCR_ROM_CLKGATE_FORCE_ON_S 18 - -/** PCR_RESET_EVENT_BYPASS_REG register - * reset event bypass backdoor configuration register - */ -#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) -/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; - * This field is used to control reset event relationship for - * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset - * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg - * will not only be reset by power-reset, but also some reset event. - */ -#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) -#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) -#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U -#define PCR_RESET_EVENT_BYPASS_APM_S 0 -/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; - * This field is used to control reset event relationship for system-bus. 1: system - * bus (including arbiter/router) will only be reset by power-reset. some reset event - * will be bypass. 0: system bus (including arbiter/router) will not only be reset by - * power-reset, but also some reset event. - */ -#define PCR_RESET_EVENT_BYPASS (BIT(1)) -#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) -#define PCR_RESET_EVENT_BYPASS_V 0x00000001U -#define PCR_RESET_EVENT_BYPASS_S 1 - -/** PCR_FPGA_DEBUG_REG register - * fpga debug register - */ -#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) -/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; - * Only used in fpga debug. - */ -#define PCR_FPGA_DEBUG 0xFFFFFFFFU -#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) -#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU -#define PCR_FPGA_DEBUG_S 0 - -/** PCR_CLOCK_GATE_REG register - * PCR clock gating configure register - */ -#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) -/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. - */ -#define PCR_CLK_EN (BIT(0)) -#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) -#define PCR_CLK_EN_V 0x00000001U -#define PCR_CLK_EN_S 0 - -/** PCR_DATE_REG register - * Date register. - */ -#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) -/** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496; - * PCR version information. - */ -#define PCR_DATE 0x0FFFFFFFU -#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) -#define PCR_DATE_V 0x0FFFFFFFU -#define PCR_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/plic_reg.h b/components/soc/esp32p4/include/soc/plic_reg.h deleted file mode 100644 index 3ee0ca70ed..0000000000 --- a/components/soc/esp32p4/include/soc/plic_reg.h +++ /dev/null @@ -1,631 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define PLIC_MXINT_CONF_REG ( 0x200013FC ) -#define PLIC_UXINT_CONF_REG ( 0x200017FC ) - -#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) -#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4) - -/*PLIC MX*/ -#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0) -/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF -#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S)) -#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF -#define PLIC_CPU_MXINT_ENABLE_S 0 - -#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4) -/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF -#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S)) -#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF -#define PLIC_CPU_MXINT_TYPE_S 0 - -#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8) -/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF -#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S)) -#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF -#define PLIC_CPU_MXINT_CLEAR_S 0 - -#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC) -/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF -#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) -#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF -#define PLIC_CPU_EIP_STATUS_S 0 - -#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10) -/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT0_PRI 0x0000000F -#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S)) -#define PLIC_CPU_MXINT0_PRI_V 0xF -#define PLIC_CPU_MXINT0_PRI_S 0 - -#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14) -/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT1_PRI 0x0000000F -#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S)) -#define PLIC_CPU_MXINT1_PRI_V 0xF -#define PLIC_CPU_MXINT1_PRI_S 0 - -#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18) -/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT2_PRI 0x0000000F -#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S)) -#define PLIC_CPU_MXINT2_PRI_V 0xF -#define PLIC_CPU_MXINT2_PRI_S 0 - -#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C) -/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT3_PRI 0x0000000F -#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S)) -#define PLIC_CPU_MXINT3_PRI_V 0xF -#define PLIC_CPU_MXINT3_PRI_S 0 - -#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20) -/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT4_PRI 0x0000000F -#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S)) -#define PLIC_CPU_MXINT4_PRI_V 0xF -#define PLIC_CPU_MXINT4_PRI_S 0 - -#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24) -/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT5_PRI 0x0000000F -#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S)) -#define PLIC_CPU_MXINT5_PRI_V 0xF -#define PLIC_CPU_MXINT5_PRI_S 0 - -#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28) -/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT6_PRI 0x0000000F -#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S)) -#define PLIC_CPU_MXINT6_PRI_V 0xF -#define PLIC_CPU_MXINT6_PRI_S 0 - -#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C) -/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT7_PRI 0x0000000F -#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S)) -#define PLIC_CPU_MXINT7_PRI_V 0xF -#define PLIC_CPU_MXINT7_PRI_S 0 - -#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30) -/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT8_PRI 0x0000000F -#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S)) -#define PLIC_CPU_MXINT8_PRI_V 0xF -#define PLIC_CPU_MXINT8_PRI_S 0 - -#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34) -/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT9_PRI 0x0000000F -#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S)) -#define PLIC_CPU_MXINT9_PRI_V 0xF -#define PLIC_CPU_MXINT9_PRI_S 0 - -#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38) -/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT10_PRI 0x0000000F -#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S)) -#define PLIC_CPU_MXINT10_PRI_V 0xF -#define PLIC_CPU_MXINT10_PRI_S 0 - -#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C) -/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT11_PRI 0x0000000F -#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S)) -#define PLIC_CPU_MXINT11_PRI_V 0xF -#define PLIC_CPU_MXINT11_PRI_S 0 - -#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40) -/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT12_PRI 0x0000000F -#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S)) -#define PLIC_CPU_MXINT12_PRI_V 0xF -#define PLIC_CPU_MXINT12_PRI_S 0 - -#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44) -/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT13_PRI 0x0000000F -#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S)) -#define PLIC_CPU_MXINT13_PRI_V 0xF -#define PLIC_CPU_MXINT13_PRI_S 0 - -#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48) -/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT14_PRI 0x0000000F -#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S)) -#define PLIC_CPU_MXINT14_PRI_V 0xF -#define PLIC_CPU_MXINT14_PRI_S 0 - -#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C) -/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT15_PRI 0x0000000F -#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S)) -#define PLIC_CPU_MXINT15_PRI_V 0xF -#define PLIC_CPU_MXINT15_PRI_S 0 - -#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50) -/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT16_PRI 0x0000000F -#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S)) -#define PLIC_CPU_MXINT16_PRI_V 0xF -#define PLIC_CPU_MXINT16_PRI_S 0 - -#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54) -/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT17_PRI 0x0000000F -#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S)) -#define PLIC_CPU_MXINT17_PRI_V 0xF -#define PLIC_CPU_MXINT17_PRI_S 0 - -#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58) -/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT18_PRI 0x0000000F -#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S)) -#define PLIC_CPU_MXINT18_PRI_V 0xF -#define PLIC_CPU_MXINT18_PRI_S 0 - -#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C) -/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT19_PRI 0x0000000F -#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S)) -#define PLIC_CPU_MXINT19_PRI_V 0xF -#define PLIC_CPU_MXINT19_PRI_S 0 - -#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60) -/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT20_PRI 0x0000000F -#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S)) -#define PLIC_CPU_MXINT20_PRI_V 0xF -#define PLIC_CPU_MXINT20_PRI_S 0 - -#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64) -/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT21_PRI 0x0000000F -#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S)) -#define PLIC_CPU_MXINT21_PRI_V 0xF -#define PLIC_CPU_MXINT21_PRI_S 0 - -#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68) -/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT22_PRI 0x0000000F -#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S)) -#define PLIC_CPU_MXINT22_PRI_V 0xF -#define PLIC_CPU_MXINT22_PRI_S 0 - -#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C) -/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT23_PRI 0x0000000F -#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S)) -#define PLIC_CPU_MXINT23_PRI_V 0xF -#define PLIC_CPU_MXINT23_PRI_S 0 - -#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70) -/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT24_PRI 0x0000000F -#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S)) -#define PLIC_CPU_MXINT24_PRI_V 0xF -#define PLIC_CPU_MXINT24_PRI_S 0 - -#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74) -/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT25_PRI 0x0000000F -#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S)) -#define PLIC_CPU_MXINT25_PRI_V 0xF -#define PLIC_CPU_MXINT25_PRI_S 0 - -#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78) -/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT26_PRI 0x0000000F -#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S)) -#define PLIC_CPU_MXINT26_PRI_V 0xF -#define PLIC_CPU_MXINT26_PRI_S 0 - -#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C) -/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT27_PRI 0x0000000F -#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S)) -#define PLIC_CPU_MXINT27_PRI_V 0xF -#define PLIC_CPU_MXINT27_PRI_S 0 - -#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80) -/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT28_PRI 0x0000000F -#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S)) -#define PLIC_CPU_MXINT28_PRI_V 0xF -#define PLIC_CPU_MXINT28_PRI_S 0 - -#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84) -/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT29_PRI 0x0000000F -#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S)) -#define PLIC_CPU_MXINT29_PRI_V 0xF -#define PLIC_CPU_MXINT29_PRI_S 0 - -#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88) -/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT30_PRI 0x0000000F -#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S)) -#define PLIC_CPU_MXINT30_PRI_V 0xF -#define PLIC_CPU_MXINT30_PRI_S 0 - -#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C) -/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT31_PRI 0x0000000F -#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S)) -#define PLIC_CPU_MXINT31_PRI_V 0xF -#define PLIC_CPU_MXINT31_PRI_S 0 - -#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90) -/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ -/*description: .*/ -#define PLIC_CPU_MXINT_THRESH 0x000000FF -#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S)) -#define PLIC_CPU_MXINT_THRESH_V 0xFF -#define PLIC_CPU_MXINT_THRESH_S 0 - -#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94) -/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/ -#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF -#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S)) -#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF -#define PLIC_CPU_MXINT_CLAIM_S 0 - -/*PLIC UX*/ -#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0) -/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF -#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S)) -#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF -#define PLIC_CPU_UXINT_ENABLE_S 0 - -#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4) -/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF -#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S)) -#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF -#define PLIC_CPU_UXINT_TYPE_S 0 - -#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8) -/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF -#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S)) -#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF -#define PLIC_CPU_UXINT_CLEAR_S 0 - -#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC) -/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF -#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) -#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF -#define PLIC_CPU_EIP_STATUS_S 0 - -#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10) -/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT0_PRI 0x0000000F -#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S)) -#define PLIC_CPU_UXINT0_PRI_V 0xF -#define PLIC_CPU_UXINT0_PRI_S 0 - -#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14) -/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT1_PRI 0x0000000F -#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S)) -#define PLIC_CPU_UXINT1_PRI_V 0xF -#define PLIC_CPU_UXINT1_PRI_S 0 - -#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18) -/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT2_PRI 0x0000000F -#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S)) -#define PLIC_CPU_UXINT2_PRI_V 0xF -#define PLIC_CPU_UXINT2_PRI_S 0 - -#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C) -/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT3_PRI 0x0000000F -#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S)) -#define PLIC_CPU_UXINT3_PRI_V 0xF -#define PLIC_CPU_UXINT3_PRI_S 0 - -#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20) -/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT4_PRI 0x0000000F -#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S)) -#define PLIC_CPU_UXINT4_PRI_V 0xF -#define PLIC_CPU_UXINT4_PRI_S 0 - -#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24) -/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT5_PRI 0x0000000F -#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S)) -#define PLIC_CPU_UXINT5_PRI_V 0xF -#define PLIC_CPU_UXINT5_PRI_S 0 - -#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28) -/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT6_PRI 0x0000000F -#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S)) -#define PLIC_CPU_UXINT6_PRI_V 0xF -#define PLIC_CPU_UXINT6_PRI_S 0 - -#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C) -/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT7_PRI 0x0000000F -#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S)) -#define PLIC_CPU_UXINT7_PRI_V 0xF -#define PLIC_CPU_UXINT7_PRI_S 0 - -#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30) -/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT8_PRI 0x0000000F -#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S)) -#define PLIC_CPU_UXINT8_PRI_V 0xF -#define PLIC_CPU_UXINT8_PRI_S 0 - -#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34) -/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT9_PRI 0x0000000F -#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S)) -#define PLIC_CPU_UXINT9_PRI_V 0xF -#define PLIC_CPU_UXINT9_PRI_S 0 - -#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38) -/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT10_PRI 0x0000000F -#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S)) -#define PLIC_CPU_UXINT10_PRI_V 0xF -#define PLIC_CPU_UXINT10_PRI_S 0 - -#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C) -/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT11_PRI 0x0000000F -#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S)) -#define PLIC_CPU_UXINT11_PRI_V 0xF -#define PLIC_CPU_UXINT11_PRI_S 0 - -#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40) -/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT12_PRI 0x0000000F -#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S)) -#define PLIC_CPU_UXINT12_PRI_V 0xF -#define PLIC_CPU_UXINT12_PRI_S 0 - -#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44) -/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT13_PRI 0x0000000F -#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S)) -#define PLIC_CPU_UXINT13_PRI_V 0xF -#define PLIC_CPU_UXINT13_PRI_S 0 - -#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48) -/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT14_PRI 0x0000000F -#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S)) -#define PLIC_CPU_UXINT14_PRI_V 0xF -#define PLIC_CPU_UXINT14_PRI_S 0 - -#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C) -/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT15_PRI 0x0000000F -#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S)) -#define PLIC_CPU_UXINT15_PRI_V 0xF -#define PLIC_CPU_UXINT15_PRI_S 0 - -#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50) -/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT16_PRI 0x0000000F -#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S)) -#define PLIC_CPU_UXINT16_PRI_V 0xF -#define PLIC_CPU_UXINT16_PRI_S 0 - -#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54) -/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT17_PRI 0x0000000F -#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S)) -#define PLIC_CPU_UXINT17_PRI_V 0xF -#define PLIC_CPU_UXINT17_PRI_S 0 - -#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58) -/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT18_PRI 0x0000000F -#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S)) -#define PLIC_CPU_UXINT18_PRI_V 0xF -#define PLIC_CPU_UXINT18_PRI_S 0 - -#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C) -/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT19_PRI 0x0000000F -#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S)) -#define PLIC_CPU_UXINT19_PRI_V 0xF -#define PLIC_CPU_UXINT19_PRI_S 0 - -#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60) -/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT20_PRI 0x0000000F -#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S)) -#define PLIC_CPU_UXINT20_PRI_V 0xF -#define PLIC_CPU_UXINT20_PRI_S 0 - -#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64) -/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT21_PRI 0x0000000F -#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S)) -#define PLIC_CPU_UXINT21_PRI_V 0xF -#define PLIC_CPU_UXINT21_PRI_S 0 - -#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68) -/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT22_PRI 0x0000000F -#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S)) -#define PLIC_CPU_UXINT22_PRI_V 0xF -#define PLIC_CPU_UXINT22_PRI_S 0 - -#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C) -/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT23_PRI 0x0000000F -#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S)) -#define PLIC_CPU_UXINT23_PRI_V 0xF -#define PLIC_CPU_UXINT23_PRI_S 0 - -#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70) -/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT24_PRI 0x0000000F -#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S)) -#define PLIC_CPU_UXINT24_PRI_V 0xF -#define PLIC_CPU_UXINT24_PRI_S 0 - -#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74) -/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT25_PRI 0x0000000F -#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S)) -#define PLIC_CPU_UXINT25_PRI_V 0xF -#define PLIC_CPU_UXINT25_PRI_S 0 - -#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78) -/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT26_PRI 0x0000000F -#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S)) -#define PLIC_CPU_UXINT26_PRI_V 0xF -#define PLIC_CPU_UXINT26_PRI_S 0 - -#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C) -/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT27_PRI 0x0000000F -#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S)) -#define PLIC_CPU_UXINT27_PRI_V 0xF -#define PLIC_CPU_UXINT27_PRI_S 0 - -#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80) -/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT28_PRI 0x0000000F -#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S)) -#define PLIC_CPU_UXINT28_PRI_V 0xF -#define PLIC_CPU_UXINT28_PRI_S 0 - -#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84) -/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT29_PRI 0x0000000F -#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S)) -#define PLIC_CPU_UXINT29_PRI_V 0xF -#define PLIC_CPU_UXINT29_PRI_S 0 - -#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88) -/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT30_PRI 0x0000000F -#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S)) -#define PLIC_CPU_UXINT30_PRI_V 0xF -#define PLIC_CPU_UXINT30_PRI_S 0 - -#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C) -/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT31_PRI 0x0000000F -#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S)) -#define PLIC_CPU_UXINT31_PRI_V 0xF -#define PLIC_CPU_UXINT31_PRI_S 0 - -#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90) -/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT_THRESH 0x000000FF -#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S)) -#define PLIC_CPU_UXINT_THRESH_V 0xFF -#define PLIC_CPU_UXINT_THRESH_S 0 - -#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94) -/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF -#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S)) -#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF -#define PLIC_CPU_UXINT_CLAIM_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h index c4b995c52a..f2c4877096 100644 --- a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h +++ b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h @@ -1,68 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_ICG_MAP_H_ -#define _SOC_ICG_MAP_H_ - -#define PMU_ICG_APB_ENA_CAN0 18 -#define PMU_ICG_APB_ENA_CAN1 19 -#define PMU_ICG_APB_ENA_GDMA 1 -#define PMU_ICG_APB_ENA_I2C 13 -#define PMU_ICG_APB_ENA_I2S 4 -#define PMU_ICG_APB_ENA_INTMTX 3 -#define PMU_ICG_APB_ENA_IOMUX 26 -#define PMU_ICG_APB_ENA_LEDC 14 -#define PMU_ICG_APB_ENA_MEM_MONITOR 25 -#define PMU_ICG_APB_ENA_MSPI 5 -#define PMU_ICG_APB_ENA_PARL 23 -#define PMU_ICG_APB_ENA_PCNT 20 -#define PMU_ICG_APB_ENA_PVT_MONITOR 27 -#define PMU_ICG_APB_ENA_PWM 21 -#define PMU_ICG_APB_ENA_REGDMA 24 -#define PMU_ICG_APB_ENA_RMT 15 -#define PMU_ICG_APB_ENA_SARADC 9 -#define PMU_ICG_APB_ENA_SEC 0 -#define PMU_ICG_APB_ENA_SOC_ETM 22 -#define PMU_ICG_APB_ENA_SPI2 2 -#define PMU_ICG_APB_ENA_SYSTIMER 16 -#define PMU_ICG_APB_ENA_TG0 11 -#define PMU_ICG_APB_ENA_TG1 12 -#define PMU_ICG_APB_ENA_UART0 6 -#define PMU_ICG_APB_ENA_UART1 7 -#define PMU_ICG_APB_ENA_UHCI 8 -#define PMU_ICG_APB_ENA_USB_DEVICE 17 -#define PMU_ICG_FUNC_ENA_CAN0 31 -#define PMU_ICG_FUNC_ENA_CAN1 30 -#define PMU_ICG_FUNC_ENA_I2C 29 -#define PMU_ICG_FUNC_ENA_I2S_RX 2 -#define PMU_ICG_FUNC_ENA_I2S_TX 7 -#define PMU_ICG_FUNC_ENA_IOMUX 28 -#define PMU_ICG_FUNC_ENA_LEDC 27 -#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 -#define PMU_ICG_FUNC_ENA_MSPI 26 -#define PMU_ICG_FUNC_ENA_PARL_RX 25 -#define PMU_ICG_FUNC_ENA_PARL_TX 24 -#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 -#define PMU_ICG_FUNC_ENA_PWM 22 -#define PMU_ICG_FUNC_ENA_RMT 21 -#define PMU_ICG_FUNC_ENA_SARADC 20 -#define PMU_ICG_FUNC_ENA_SEC 19 -#define PMU_ICG_FUNC_ENA_SPI2 1 -#define PMU_ICG_FUNC_ENA_SYSTIMER 18 -#define PMU_ICG_FUNC_ENA_TG0 14 -#define PMU_ICG_FUNC_ENA_TG1 13 -#define PMU_ICG_FUNC_ENA_TSENS 12 -#define PMU_ICG_FUNC_ENA_UART0 3 -#define PMU_ICG_FUNC_ENA_UART1 4 -#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 -#define PMU_ICG_FUNC_ENA_GDMA 0 -#define PMU_ICG_FUNC_ENA_SOC_ETM 16 -#define PMU_ICG_FUNC_ENA_REGDMA 8 -#define PMU_ICG_FUNC_ENA_RETENTION 9 -#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 -#define PMU_ICG_FUNC_ENA_UHCI 5 -#define PMU_ICG_FUNC_ENA_HPCORE 17 -#define PMU_ICG_FUNC_ENA_HPBUS 15 -#endif /* _SOC_ICG_MAP_H_ */ diff --git a/components/soc/esp32p4/include/soc/pwm_reg.h b/components/soc/esp32p4/include/soc/pwm_reg.h deleted file mode 100644 index e526c38e60..0000000000 --- a/components/soc/esp32p4/include/soc/pwm_reg.h +++ /dev/null @@ -1,4514 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** MCPWM_CLK_CFG_REG register - * PWM clock prescaler register. - */ -#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0) -/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * - * (PWM_CLK_PRESCALE + 1). - */ -#define MCPWM_CLK_PRESCALE 0x000000FFU -#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) -#define MCPWM_CLK_PRESCALE_V 0x000000FFU -#define MCPWM_CLK_PRESCALE_S 0 - -/** MCPWM_TIMER0_CFG0_REG register - * PWM timer0 period and update method configuration register. - */ -#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4) -/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of timer0, so that the period of PT0_clk = Period of - * PWM_clk * (PWM_TIMER0_PRESCALE + 1) - */ -#define MCPWM_TIMER0_PRESCALE 0x000000FFU -#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) -#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU -#define MCPWM_TIMER0_PRESCALE_S 0 -/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; - * Configures the period shadow of PWM timer0 - */ -#define MCPWM_TIMER0_PERIOD 0x0000FFFFU -#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) -#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU -#define MCPWM_TIMER0_PERIOD_S 8 -/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; - * Configures the update method for active register of PWM timer0 period.\\0: - * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal - * zero event - */ -#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U -#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) -#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U -#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 - -/** MCPWM_TIMER0_CFG1_REG register - * PWM timer$n working mode and start/stop control register. - */ -#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8) -/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ -#define MCPWM_TIMER0_START 0x00000007U -#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) -#define MCPWM_TIMER0_START_V 0x00000007U -#define MCPWM_TIMER0_START_S 0 -/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ -#define MCPWM_TIMER0_MOD 0x00000003U -#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) -#define MCPWM_TIMER0_MOD_V 0x00000003U -#define MCPWM_TIMER0_MOD_S 3 - -/** MCPWM_TIMER0_SYNC_REG register - * PWM timer$n sync function configuration register. - */ -#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc) -/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ -#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) -#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U -#define MCPWM_TIMER0_SYNCI_EN_S 0 -/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ -#define MCPWM_TIMER0_SYNC_SW (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) -#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U -#define MCPWM_TIMER0_SYNC_SW_S 1 -/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ -#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U -#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) -#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U -#define MCPWM_TIMER0_SYNCO_SEL_S 2 -/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ -#define MCPWM_TIMER0_PHASE 0x0000FFFFU -#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) -#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU -#define MCPWM_TIMER0_PHASE_S 4 -/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ -#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) -#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) -#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U -#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 - -/** MCPWM_TIMER0_STATUS_REG register - * PWM timer$n status register. - */ -#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10) -/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ -#define MCPWM_TIMER0_VALUE 0x0000FFFFU -#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) -#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU -#define MCPWM_TIMER0_VALUE_S 0 -/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ -#define MCPWM_TIMER0_DIRECTION (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) -#define MCPWM_TIMER0_DIRECTION_V 0x00000001U -#define MCPWM_TIMER0_DIRECTION_S 16 - -/** MCPWM_TIMER1_CFG0_REG register - * PWM timer1 period and update method configuration register. - */ -#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14) -/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of timer1, so that the period of PT0_clk = Period of - * PWM_clk * (PWM_TIMER1_PRESCALE + 1) - */ -#define MCPWM_TIMER0_PRESCALE 0x000000FFU -#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) -#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU -#define MCPWM_TIMER0_PRESCALE_S 0 -/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; - * Configures the period shadow of PWM timer1 - */ -#define MCPWM_TIMER0_PERIOD 0x0000FFFFU -#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) -#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU -#define MCPWM_TIMER0_PERIOD_S 8 -/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; - * Configures the update method for active register of PWM timer1 period.\\0: - * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal - * zero event - */ -#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U -#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) -#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U -#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 - -/** MCPWM_TIMER1_CFG1_REG register - * PWM timer$n working mode and start/stop control register. - */ -#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18) -/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ -#define MCPWM_TIMER1_START 0x00000007U -#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) -#define MCPWM_TIMER1_START_V 0x00000007U -#define MCPWM_TIMER1_START_S 0 -/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ -#define MCPWM_TIMER1_MOD 0x00000003U -#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) -#define MCPWM_TIMER1_MOD_V 0x00000003U -#define MCPWM_TIMER1_MOD_S 3 - -/** MCPWM_TIMER1_SYNC_REG register - * PWM timer$n sync function configuration register. - */ -#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c) -/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ -#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) -#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U -#define MCPWM_TIMER1_SYNCI_EN_S 0 -/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ -#define MCPWM_TIMER1_SYNC_SW (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) -#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U -#define MCPWM_TIMER1_SYNC_SW_S 1 -/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ -#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U -#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) -#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U -#define MCPWM_TIMER1_SYNCO_SEL_S 2 -/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ -#define MCPWM_TIMER1_PHASE 0x0000FFFFU -#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) -#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU -#define MCPWM_TIMER1_PHASE_S 4 -/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ -#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) -#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) -#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U -#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 - -/** MCPWM_TIMER1_STATUS_REG register - * PWM timer$n status register. - */ -#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20) -/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ -#define MCPWM_TIMER1_VALUE 0x0000FFFFU -#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) -#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU -#define MCPWM_TIMER1_VALUE_S 0 -/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ -#define MCPWM_TIMER1_DIRECTION (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) -#define MCPWM_TIMER1_DIRECTION_V 0x00000001U -#define MCPWM_TIMER1_DIRECTION_S 16 - -/** MCPWM_TIMER2_CFG0_REG register - * PWM timer2 period and update method configuration register. - */ -#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24) -/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of timer2, so that the period of PT0_clk = Period of - * PWM_clk * (PWM_TIMER2_PRESCALE + 1) - */ -#define MCPWM_TIMER0_PRESCALE 0x000000FFU -#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) -#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU -#define MCPWM_TIMER0_PRESCALE_S 0 -/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; - * Configures the period shadow of PWM timer2 - */ -#define MCPWM_TIMER0_PERIOD 0x0000FFFFU -#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) -#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU -#define MCPWM_TIMER0_PERIOD_S 8 -/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; - * Configures the update method for active register of PWM timer2 period.\\0: - * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal - * zero event - */ -#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U -#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) -#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U -#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 - -/** MCPWM_TIMER2_CFG1_REG register - * PWM timer$n working mode and start/stop control register. - */ -#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28) -/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ -#define MCPWM_TIMER2_START 0x00000007U -#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) -#define MCPWM_TIMER2_START_V 0x00000007U -#define MCPWM_TIMER2_START_S 0 -/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ -#define MCPWM_TIMER2_MOD 0x00000003U -#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) -#define MCPWM_TIMER2_MOD_V 0x00000003U -#define MCPWM_TIMER2_MOD_S 3 - -/** MCPWM_TIMER2_SYNC_REG register - * PWM timer$n sync function configuration register. - */ -#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c) -/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ -#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) -#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U -#define MCPWM_TIMER2_SYNCI_EN_S 0 -/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ -#define MCPWM_TIMER2_SYNC_SW (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) -#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U -#define MCPWM_TIMER2_SYNC_SW_S 1 -/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ -#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U -#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) -#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U -#define MCPWM_TIMER2_SYNCO_SEL_S 2 -/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ -#define MCPWM_TIMER2_PHASE 0x0000FFFFU -#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) -#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU -#define MCPWM_TIMER2_PHASE_S 4 -/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ -#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) -#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) -#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U -#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 - -/** MCPWM_TIMER2_STATUS_REG register - * PWM timer$n status register. - */ -#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30) -/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ -#define MCPWM_TIMER2_VALUE 0x0000FFFFU -#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) -#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU -#define MCPWM_TIMER2_VALUE_S 0 -/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ -#define MCPWM_TIMER2_DIRECTION (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) -#define MCPWM_TIMER2_DIRECTION_V 0x00000001U -#define MCPWM_TIMER2_DIRECTION_S 16 - -/** MCPWM_TIMER_SYNCI_CFG_REG register - * Synchronization input selection register for PWM timers. - */ -#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34) -/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; - * Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: - * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 - * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - */ -#define MCPWM_TIMER0_SYNCISEL 0x00000007U -#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) -#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U -#define MCPWM_TIMER0_SYNCISEL_S 0 -/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; - * Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: - * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 - * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - */ -#define MCPWM_TIMER1_SYNCISEL 0x00000007U -#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) -#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U -#define MCPWM_TIMER1_SYNCISEL_S 3 -/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; - * Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: - * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 - * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - */ -#define MCPWM_TIMER2_SYNCISEL 0x00000007U -#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) -#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U -#define MCPWM_TIMER2_SYNCISEL_S 6 -/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; - * Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: - * Invert - */ -#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U -#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 -/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; - * Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: - * Invert - */ -#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U -#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 -/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: - * Invert - */ -#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U -#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 - -/** MCPWM_OPERATOR_TIMERSEL_REG register - * PWM operator's timer select register - */ -#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38) -/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator0.\\0: - * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - */ -#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U -#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) -#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U -#define MCPWM_OPERATOR0_TIMERSEL_S 0 -/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator1.\\0: - * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - */ -#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U -#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) -#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U -#define MCPWM_OPERATOR1_TIMERSEL_S 2 -/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator2.\\0: - * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - */ -#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U -#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) -#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U -#define MCPWM_OPERATOR2_TIMERSEL_S 4 - -/** MCPWM_GEN0_STMP_CFG_REG register - * Generator0 time stamp registers A and B transfer status and update method register - */ -#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c) -/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures the update method for PWM generator 0 time stamp A's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_CMPR0_A_UPMETHOD 0x0000000FU -#define MCPWM_CMPR0_A_UPMETHOD_M (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S) -#define MCPWM_CMPR0_A_UPMETHOD_V 0x0000000FU -#define MCPWM_CMPR0_A_UPMETHOD_S 0 -/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; - * Configures the update method for PWM generator 0 time stamp B's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_CMPR0_B_UPMETHOD 0x0000000FU -#define MCPWM_CMPR0_B_UPMETHOD_M (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S) -#define MCPWM_CMPR0_B_UPMETHOD_V 0x0000000FU -#define MCPWM_CMPR0_B_UPMETHOD_S 4 -/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; - * Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0: - * A's active reg has been updated with shadow register latest value.\\1: A's shadow - * reg is filled and waiting to be transferred to A's active reg - */ -#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR0_A_SHDW_FULL_M (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S) -#define MCPWM_CMPR0_A_SHDW_FULL_V 0x00000001U -#define MCPWM_CMPR0_A_SHDW_FULL_S 8 -/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; - * Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0: - * B's active reg has been updated with shadow register latest value.\\1: B's shadow - * reg is filled and waiting to be transferred to B's active reg - */ -#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR0_B_SHDW_FULL_M (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S) -#define MCPWM_CMPR0_B_SHDW_FULL_V 0x00000001U -#define MCPWM_CMPR0_B_SHDW_FULL_S 9 - -/** MCPWM_GEN0_TSTMP_A_REG register - * Generator$n time stamp A's shadow register - */ -#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40) -/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp A's shadow register. - */ -#define MCPWM_CMPR0_A 0x0000FFFFU -#define MCPWM_CMPR0_A_M (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S) -#define MCPWM_CMPR0_A_V 0x0000FFFFU -#define MCPWM_CMPR0_A_S 0 - -/** MCPWM_GEN0_TSTMP_B_REG register - * Generator$n time stamp B's shadow register - */ -#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44) -/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp B's shadow register. - */ -#define MCPWM_CMPR0_B 0x0000FFFFU -#define MCPWM_CMPR0_B_M (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S) -#define MCPWM_CMPR0_B_V 0x0000FFFFU -#define MCPWM_CMPR0_B_S 0 - -/** MCPWM_GEN0_CFG0_REG register - * Generator$n fault event T0 and T1 configuration register - */ -#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48) -/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures update method for PWM generator $n's active register.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU -#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) -#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU -#define MCPWM_GEN0_CFG_UPMETHOD_S 0 -/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; - * Configures source selection for PWM generator $n event_t0, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ -#define MCPWM_GEN0_T0_SEL 0x00000007U -#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) -#define MCPWM_GEN0_T0_SEL_V 0x00000007U -#define MCPWM_GEN0_T0_SEL_S 4 -/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; - * Configures source selection for PWM generator $n event_t1, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ -#define MCPWM_GEN0_T1_SEL 0x00000007U -#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) -#define MCPWM_GEN0_T1_SEL_V 0x00000007U -#define MCPWM_GEN0_T1_SEL_S 7 - -/** MCPWM_GEN0_FORCE_REG register - * Generator$n output signal force mode register. - */ -#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c) -/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; - * Configures update method for continuous software force of PWM generator$n.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable - * update. TEA/B here and below means an event generated when the timer's value equals - * to that of register A/B. - */ -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 -/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; - * Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ -#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U -#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) -#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U -#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 -/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; - * Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ -#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U -#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) -#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U -#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 -/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n A, a toggle will trigger a force event. - */ -#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) -#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U -#define MCPWM_GEN0_A_NCIFORCE_S 10 -/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n A.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ -#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U -#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) -#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U -#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 -/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n B, a toggle will trigger a force event. - */ -#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) -#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U -#define MCPWM_GEN0_B_NCIFORCE_S 13 -/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n B.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ -#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U -#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) -#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U -#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 - -/** MCPWM_GEN0_A_REG register - * PWM$n output signal A actions configuration register - */ -#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50) -/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_UTEZ 0x00000003U -#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) -#define MCPWM_GEN0_A_UTEZ_V 0x00000003U -#define MCPWM_GEN0_A_UTEZ_S 0 -/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_UTEP 0x00000003U -#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) -#define MCPWM_GEN0_A_UTEP_V 0x00000003U -#define MCPWM_GEN0_A_UTEP_S 2 -/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_UTEA 0x00000003U -#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) -#define MCPWM_GEN0_A_UTEA_V 0x00000003U -#define MCPWM_GEN0_A_UTEA_S 4 -/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_UTEB 0x00000003U -#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) -#define MCPWM_GEN0_A_UTEB_V 0x00000003U -#define MCPWM_GEN0_A_UTEB_S 6 -/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_UT0 0x00000003U -#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) -#define MCPWM_GEN0_A_UT0_V 0x00000003U -#define MCPWM_GEN0_A_UT0_S 8 -/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_UT1 0x00000003U -#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) -#define MCPWM_GEN0_A_UT1_V 0x00000003U -#define MCPWM_GEN0_A_UT1_S 10 -/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_DTEZ 0x00000003U -#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) -#define MCPWM_GEN0_A_DTEZ_V 0x00000003U -#define MCPWM_GEN0_A_DTEZ_S 12 -/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_DTEP 0x00000003U -#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) -#define MCPWM_GEN0_A_DTEP_V 0x00000003U -#define MCPWM_GEN0_A_DTEP_S 14 -/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_DTEA 0x00000003U -#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) -#define MCPWM_GEN0_A_DTEA_V 0x00000003U -#define MCPWM_GEN0_A_DTEA_S 16 -/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_DTEB 0x00000003U -#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) -#define MCPWM_GEN0_A_DTEB_V 0x00000003U -#define MCPWM_GEN0_A_DTEB_S 18 -/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_DT0 0x00000003U -#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) -#define MCPWM_GEN0_A_DT0_V 0x00000003U -#define MCPWM_GEN0_A_DT0_S 20 -/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_A_DT1 0x00000003U -#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) -#define MCPWM_GEN0_A_DT1_V 0x00000003U -#define MCPWM_GEN0_A_DT1_S 22 - -/** MCPWM_GEN0_B_REG register - * PWM$n output signal B actions configuration register - */ -#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54) -/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_UTEZ 0x00000003U -#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) -#define MCPWM_GEN0_B_UTEZ_V 0x00000003U -#define MCPWM_GEN0_B_UTEZ_S 0 -/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_UTEP 0x00000003U -#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) -#define MCPWM_GEN0_B_UTEP_V 0x00000003U -#define MCPWM_GEN0_B_UTEP_S 2 -/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_UTEA 0x00000003U -#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) -#define MCPWM_GEN0_B_UTEA_V 0x00000003U -#define MCPWM_GEN0_B_UTEA_S 4 -/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_UTEB 0x00000003U -#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) -#define MCPWM_GEN0_B_UTEB_V 0x00000003U -#define MCPWM_GEN0_B_UTEB_S 6 -/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_UT0 0x00000003U -#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) -#define MCPWM_GEN0_B_UT0_V 0x00000003U -#define MCPWM_GEN0_B_UT0_S 8 -/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_UT1 0x00000003U -#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) -#define MCPWM_GEN0_B_UT1_V 0x00000003U -#define MCPWM_GEN0_B_UT1_S 10 -/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_DTEZ 0x00000003U -#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) -#define MCPWM_GEN0_B_DTEZ_V 0x00000003U -#define MCPWM_GEN0_B_DTEZ_S 12 -/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_DTEP 0x00000003U -#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) -#define MCPWM_GEN0_B_DTEP_V 0x00000003U -#define MCPWM_GEN0_B_DTEP_S 14 -/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_DTEA 0x00000003U -#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) -#define MCPWM_GEN0_B_DTEA_V 0x00000003U -#define MCPWM_GEN0_B_DTEA_S 16 -/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_DTEB 0x00000003U -#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) -#define MCPWM_GEN0_B_DTEB_V 0x00000003U -#define MCPWM_GEN0_B_DTEB_S 18 -/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_DT0 0x00000003U -#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) -#define MCPWM_GEN0_B_DT0_V 0x00000003U -#define MCPWM_GEN0_B_DT0_S 20 -/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN0_B_DT1 0x00000003U -#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) -#define MCPWM_GEN0_B_DT1_V 0x00000003U -#define MCPWM_GEN0_B_DT1_S 22 - -/** MCPWM_DT0_CFG_REG register - * Dead time configuration register - */ -#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58) -/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures update method for FED (Falling edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_DB0_FED_UPMETHOD 0x0000000FU -#define MCPWM_DB0_FED_UPMETHOD_M (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S) -#define MCPWM_DB0_FED_UPMETHOD_V 0x0000000FU -#define MCPWM_DB0_FED_UPMETHOD_S 0 -/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; - * Configures update method for RED (rising edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_DB0_RED_UPMETHOD 0x0000000FU -#define MCPWM_DB0_RED_UPMETHOD_M (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S) -#define MCPWM_DB0_RED_UPMETHOD_V 0x0000000FU -#define MCPWM_DB0_RED_UPMETHOD_S 4 -/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0; - * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path - * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode - */ -#define MCPWM_DB0_DEB_MODE (BIT(8)) -#define MCPWM_DB0_DEB_MODE_M (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S) -#define MCPWM_DB0_DEB_MODE_V 0x00000001U -#define MCPWM_DB0_DEB_MODE_S 8 -/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; - * Configures S6 in table. - */ -#define MCPWM_DB0_A_OUTSWAP (BIT(9)) -#define MCPWM_DB0_A_OUTSWAP_M (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S) -#define MCPWM_DB0_A_OUTSWAP_V 0x00000001U -#define MCPWM_DB0_A_OUTSWAP_S 9 -/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; - * Configures S7 in table. - */ -#define MCPWM_DB0_B_OUTSWAP (BIT(10)) -#define MCPWM_DB0_B_OUTSWAP_M (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S) -#define MCPWM_DB0_B_OUTSWAP_V 0x00000001U -#define MCPWM_DB0_B_OUTSWAP_S 10 -/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0; - * Configures S4 in table. - */ -#define MCPWM_DB0_RED_INSEL (BIT(11)) -#define MCPWM_DB0_RED_INSEL_M (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S) -#define MCPWM_DB0_RED_INSEL_V 0x00000001U -#define MCPWM_DB0_RED_INSEL_S 11 -/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0; - * Configures S5 in table. - */ -#define MCPWM_DB0_FED_INSEL (BIT(12)) -#define MCPWM_DB0_FED_INSEL_M (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S) -#define MCPWM_DB0_FED_INSEL_V 0x00000001U -#define MCPWM_DB0_FED_INSEL_S 12 -/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; - * Configures S2 in table. - */ -#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB0_RED_OUTINVERT_M (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S) -#define MCPWM_DB0_RED_OUTINVERT_V 0x00000001U -#define MCPWM_DB0_RED_OUTINVERT_S 13 -/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; - * Configures S3 in table. - */ -#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB0_FED_OUTINVERT_M (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S) -#define MCPWM_DB0_FED_OUTINVERT_V 0x00000001U -#define MCPWM_DB0_FED_OUTINVERT_S 14 -/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; - * Configures S1 in table. - */ -#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB0_A_OUTBYPASS_M (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S) -#define MCPWM_DB0_A_OUTBYPASS_V 0x00000001U -#define MCPWM_DB0_A_OUTBYPASS_S 15 -/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; - * Configures S0 in table. - */ -#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB0_B_OUTBYPASS_M (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S) -#define MCPWM_DB0_B_OUTBYPASS_V 0x00000001U -#define MCPWM_DB0_B_OUTBYPASS_S 16 -/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0; - * Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk - */ -#define MCPWM_DB0_CLK_SEL (BIT(17)) -#define MCPWM_DB0_CLK_SEL_M (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S) -#define MCPWM_DB0_CLK_SEL_V 0x00000001U -#define MCPWM_DB0_CLK_SEL_S 17 - -/** MCPWM_DT0_FED_CFG_REG register - * Falling edge delay (FED) shadow register - */ -#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c) -/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for FED. - */ -#define MCPWM_DB0_FED 0x0000FFFFU -#define MCPWM_DB0_FED_M (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S) -#define MCPWM_DB0_FED_V 0x0000FFFFU -#define MCPWM_DB0_FED_S 0 - -/** MCPWM_DT0_RED_CFG_REG register - * Rising edge delay (RED) shadow register - */ -#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60) -/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for RED. - */ -#define MCPWM_DB0_RED 0x0000FFFFU -#define MCPWM_DB0_RED_M (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S) -#define MCPWM_DB0_RED_V 0x0000FFFFU -#define MCPWM_DB0_RED_S 0 - -/** MCPWM_CARRIER0_CFG_REG register - * Carrier$n configuration register - */ -#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64) -/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled - */ -#define MCPWM_CHOPPER0_EN (BIT(0)) -#define MCPWM_CHOPPER0_EN_M (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S) -#define MCPWM_CHOPPER0_EN_V 0x00000001U -#define MCPWM_CHOPPER0_EN_S 0 -/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; - * Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of - * PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1) - */ -#define MCPWM_CHOPPER0_PRESCALE 0x0000000FU -#define MCPWM_CHOPPER0_PRESCALE_M (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S) -#define MCPWM_CHOPPER0_PRESCALE_V 0x0000000FU -#define MCPWM_CHOPPER0_PRESCALE_S 1 -/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0; - * Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8 - */ -#define MCPWM_CHOPPER0_DUTY 0x00000007U -#define MCPWM_CHOPPER0_DUTY_M (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S) -#define MCPWM_CHOPPER0_DUTY_V 0x00000007U -#define MCPWM_CHOPPER0_DUTY_S 5 -/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; - * Configures width of the first pulse. Measurement unit: Periods of the carrier. - */ -#define MCPWM_CHOPPER0_OSHTWTH 0x0000000FU -#define MCPWM_CHOPPER0_OSHTWTH_M (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S) -#define MCPWM_CHOPPER0_OSHTWTH_V 0x0000000FU -#define MCPWM_CHOPPER0_OSHTWTH_S 8 -/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; - * Configures whether or not to invert the output of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ -#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER0_OUT_INVERT_M (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S) -#define MCPWM_CHOPPER0_OUT_INVERT_V 0x00000001U -#define MCPWM_CHOPPER0_OUT_INVERT_S 12 -/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0; - * Configures whether or not to invert the input of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ -#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER0_IN_INVERT_M (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S) -#define MCPWM_CHOPPER0_IN_INVERT_V 0x00000001U -#define MCPWM_CHOPPER0_IN_INVERT_S 13 - -/** MCPWM_FH0_CFG0_REG register - * PWM$n A and PWM$n B trip events actions configuration register - */ -#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68) -/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_SW_CBC (BIT(0)) -#define MCPWM_TZ0_SW_CBC_M (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S) -#define MCPWM_TZ0_SW_CBC_V 0x00000001U -#define MCPWM_TZ0_SW_CBC_S 0 -/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0; - * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_F2_CBC (BIT(1)) -#define MCPWM_TZ0_F2_CBC_M (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S) -#define MCPWM_TZ0_F2_CBC_V 0x00000001U -#define MCPWM_TZ0_F2_CBC_S 1 -/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0; - * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_F1_CBC (BIT(2)) -#define MCPWM_TZ0_F1_CBC_M (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S) -#define MCPWM_TZ0_F1_CBC_V 0x00000001U -#define MCPWM_TZ0_F1_CBC_S 2 -/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0; - * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_F0_CBC (BIT(3)) -#define MCPWM_TZ0_F0_CBC_M (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S) -#define MCPWM_TZ0_F0_CBC_V 0x00000001U -#define MCPWM_TZ0_F0_CBC_S 3 -/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable software force one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_SW_OST (BIT(4)) -#define MCPWM_TZ0_SW_OST_M (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S) -#define MCPWM_TZ0_SW_OST_V 0x00000001U -#define MCPWM_TZ0_SW_OST_S 4 -/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0; - * Configures whether or not event_f2 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_F2_OST (BIT(5)) -#define MCPWM_TZ0_F2_OST_M (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S) -#define MCPWM_TZ0_F2_OST_V 0x00000001U -#define MCPWM_TZ0_F2_OST_S 5 -/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0; - * Configures whether or not event_f1 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_F1_OST (BIT(6)) -#define MCPWM_TZ0_F1_OST_M (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S) -#define MCPWM_TZ0_F1_OST_V 0x00000001U -#define MCPWM_TZ0_F1_OST_S 6 -/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0; - * Configures whether or not event_f0 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ0_F0_OST (BIT(7)) -#define MCPWM_TZ0_F0_OST_M (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S) -#define MCPWM_TZ0_F0_OST_V 0x00000001U -#define MCPWM_TZ0_F0_OST_S 7 -/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_A_CBC_D 0x00000003U -#define MCPWM_TZ0_A_CBC_D_M (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S) -#define MCPWM_TZ0_A_CBC_D_V 0x00000003U -#define MCPWM_TZ0_A_CBC_D_S 8 -/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_A_CBC_U 0x00000003U -#define MCPWM_TZ0_A_CBC_U_M (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S) -#define MCPWM_TZ0_A_CBC_U_V 0x00000003U -#define MCPWM_TZ0_A_CBC_U_S 10 -/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_A_OST_D 0x00000003U -#define MCPWM_TZ0_A_OST_D_M (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S) -#define MCPWM_TZ0_A_OST_D_V 0x00000003U -#define MCPWM_TZ0_A_OST_D_S 12 -/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_A_OST_U 0x00000003U -#define MCPWM_TZ0_A_OST_U_M (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S) -#define MCPWM_TZ0_A_OST_U_V 0x00000003U -#define MCPWM_TZ0_A_OST_U_S 14 -/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_B_CBC_D 0x00000003U -#define MCPWM_TZ0_B_CBC_D_M (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S) -#define MCPWM_TZ0_B_CBC_D_V 0x00000003U -#define MCPWM_TZ0_B_CBC_D_S 16 -/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_B_CBC_U 0x00000003U -#define MCPWM_TZ0_B_CBC_U_M (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S) -#define MCPWM_TZ0_B_CBC_U_V 0x00000003U -#define MCPWM_TZ0_B_CBC_U_S 18 -/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_B_OST_D 0x00000003U -#define MCPWM_TZ0_B_OST_D_M (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S) -#define MCPWM_TZ0_B_OST_D_V 0x00000003U -#define MCPWM_TZ0_B_OST_D_S 20 -/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ0_B_OST_U 0x00000003U -#define MCPWM_TZ0_B_OST_U_M (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S) -#define MCPWM_TZ0_B_OST_U_V 0x00000003U -#define MCPWM_TZ0_B_OST_U_S 22 - -/** MCPWM_FH0_CFG1_REG register - * Software triggers for fault handler actions configuration register - */ -#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c) -/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0; - * Configures the generation of software one-shot mode action clear. A toggle - * (software negate its value) triggers a clear for on going one-shot mode action. - */ -#define MCPWM_TZ0_CLR_OST (BIT(0)) -#define MCPWM_TZ0_CLR_OST_M (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S) -#define MCPWM_TZ0_CLR_OST_V 0x00000001U -#define MCPWM_TZ0_CLR_OST_S 0 -/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; - * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select - * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP - */ -#define MCPWM_TZ0_CBCPULSE 0x00000003U -#define MCPWM_TZ0_CBCPULSE_M (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S) -#define MCPWM_TZ0_CBCPULSE_V 0x00000003U -#define MCPWM_TZ0_CBCPULSE_S 1 -/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0; - * Configures the generation of software cycle-by-cycle mode action. A toggle - * (software negate its value) triggers a cycle-by-cycle mode action. - */ -#define MCPWM_TZ0_FORCE_CBC (BIT(3)) -#define MCPWM_TZ0_FORCE_CBC_M (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S) -#define MCPWM_TZ0_FORCE_CBC_V 0x00000001U -#define MCPWM_TZ0_FORCE_CBC_S 3 -/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0; - * Configures the generation of software one-shot mode action. A toggle (software - * negate its value) triggers a one-shot mode action. - */ -#define MCPWM_TZ0_FORCE_OST (BIT(4)) -#define MCPWM_TZ0_FORCE_OST_M (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S) -#define MCPWM_TZ0_FORCE_OST_V 0x00000001U -#define MCPWM_TZ0_FORCE_OST_S 4 - -/** MCPWM_FH0_STATUS_REG register - * Fault events status register - */ -#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70) -/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0; - * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No - * action\\1: On going - */ -#define MCPWM_TZ0_CBC_ON (BIT(0)) -#define MCPWM_TZ0_CBC_ON_M (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S) -#define MCPWM_TZ0_CBC_ON_V 0x00000001U -#define MCPWM_TZ0_CBC_ON_S 0 -/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0; - * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On - * going - */ -#define MCPWM_TZ0_OST_ON (BIT(1)) -#define MCPWM_TZ0_OST_ON_M (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S) -#define MCPWM_TZ0_OST_ON_V 0x00000001U -#define MCPWM_TZ0_OST_ON_S 1 - -/** MCPWM_GEN1_STMP_CFG_REG register - * Generator1 time stamp registers A and B transfer status and update method register - */ -#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74) -/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures the update method for PWM generator 1 time stamp A's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_CMPR0_A_UPMETHOD 0x0000000FU -#define MCPWM_CMPR0_A_UPMETHOD_M (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S) -#define MCPWM_CMPR0_A_UPMETHOD_V 0x0000000FU -#define MCPWM_CMPR0_A_UPMETHOD_S 0 -/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; - * Configures the update method for PWM generator 1 time stamp B's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_CMPR0_B_UPMETHOD 0x0000000FU -#define MCPWM_CMPR0_B_UPMETHOD_M (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S) -#define MCPWM_CMPR0_B_UPMETHOD_V 0x0000000FU -#define MCPWM_CMPR0_B_UPMETHOD_S 4 -/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; - * Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0: - * A's active reg has been updated with shadow register latest value.\\1: A's shadow - * reg is filled and waiting to be transferred to A's active reg - */ -#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR0_A_SHDW_FULL_M (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S) -#define MCPWM_CMPR0_A_SHDW_FULL_V 0x00000001U -#define MCPWM_CMPR0_A_SHDW_FULL_S 8 -/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; - * Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0: - * B's active reg has been updated with shadow register latest value.\\1: B's shadow - * reg is filled and waiting to be transferred to B's active reg - */ -#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR0_B_SHDW_FULL_M (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S) -#define MCPWM_CMPR0_B_SHDW_FULL_V 0x00000001U -#define MCPWM_CMPR0_B_SHDW_FULL_S 9 - -/** MCPWM_GEN1_TSTMP_A_REG register - * Generator$n time stamp A's shadow register - */ -#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78) -/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp A's shadow register. - */ -#define MCPWM_CMPR1_A 0x0000FFFFU -#define MCPWM_CMPR1_A_M (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S) -#define MCPWM_CMPR1_A_V 0x0000FFFFU -#define MCPWM_CMPR1_A_S 0 - -/** MCPWM_GEN1_TSTMP_B_REG register - * Generator$n time stamp B's shadow register - */ -#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c) -/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp B's shadow register. - */ -#define MCPWM_CMPR1_B 0x0000FFFFU -#define MCPWM_CMPR1_B_M (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S) -#define MCPWM_CMPR1_B_V 0x0000FFFFU -#define MCPWM_CMPR1_B_S 0 - -/** MCPWM_GEN1_CFG0_REG register - * Generator$n fault event T0 and T1 configuration register - */ -#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80) -/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures update method for PWM generator $n's active register.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU -#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) -#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU -#define MCPWM_GEN1_CFG_UPMETHOD_S 0 -/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; - * Configures source selection for PWM generator $n event_t0, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ -#define MCPWM_GEN1_T0_SEL 0x00000007U -#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) -#define MCPWM_GEN1_T0_SEL_V 0x00000007U -#define MCPWM_GEN1_T0_SEL_S 4 -/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; - * Configures source selection for PWM generator $n event_t1, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ -#define MCPWM_GEN1_T1_SEL 0x00000007U -#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) -#define MCPWM_GEN1_T1_SEL_V 0x00000007U -#define MCPWM_GEN1_T1_SEL_S 7 - -/** MCPWM_GEN1_FORCE_REG register - * Generator$n output signal force mode register. - */ -#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84) -/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; - * Configures update method for continuous software force of PWM generator$n.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable - * update. TEA/B here and below means an event generated when the timer's value equals - * to that of register A/B. - */ -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 -/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; - * Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ -#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U -#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) -#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U -#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 -/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; - * Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ -#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U -#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) -#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U -#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 -/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n A, a toggle will trigger a force event. - */ -#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) -#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U -#define MCPWM_GEN1_A_NCIFORCE_S 10 -/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n A.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ -#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U -#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) -#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U -#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 -/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n B, a toggle will trigger a force event. - */ -#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) -#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U -#define MCPWM_GEN1_B_NCIFORCE_S 13 -/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n B.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ -#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U -#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) -#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U -#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 - -/** MCPWM_GEN1_A_REG register - * PWM$n output signal A actions configuration register - */ -#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88) -/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_UTEZ 0x00000003U -#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) -#define MCPWM_GEN1_A_UTEZ_V 0x00000003U -#define MCPWM_GEN1_A_UTEZ_S 0 -/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_UTEP 0x00000003U -#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) -#define MCPWM_GEN1_A_UTEP_V 0x00000003U -#define MCPWM_GEN1_A_UTEP_S 2 -/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_UTEA 0x00000003U -#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) -#define MCPWM_GEN1_A_UTEA_V 0x00000003U -#define MCPWM_GEN1_A_UTEA_S 4 -/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_UTEB 0x00000003U -#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) -#define MCPWM_GEN1_A_UTEB_V 0x00000003U -#define MCPWM_GEN1_A_UTEB_S 6 -/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_UT0 0x00000003U -#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) -#define MCPWM_GEN1_A_UT0_V 0x00000003U -#define MCPWM_GEN1_A_UT0_S 8 -/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_UT1 0x00000003U -#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) -#define MCPWM_GEN1_A_UT1_V 0x00000003U -#define MCPWM_GEN1_A_UT1_S 10 -/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_DTEZ 0x00000003U -#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) -#define MCPWM_GEN1_A_DTEZ_V 0x00000003U -#define MCPWM_GEN1_A_DTEZ_S 12 -/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_DTEP 0x00000003U -#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) -#define MCPWM_GEN1_A_DTEP_V 0x00000003U -#define MCPWM_GEN1_A_DTEP_S 14 -/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_DTEA 0x00000003U -#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) -#define MCPWM_GEN1_A_DTEA_V 0x00000003U -#define MCPWM_GEN1_A_DTEA_S 16 -/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_DTEB 0x00000003U -#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) -#define MCPWM_GEN1_A_DTEB_V 0x00000003U -#define MCPWM_GEN1_A_DTEB_S 18 -/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_DT0 0x00000003U -#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) -#define MCPWM_GEN1_A_DT0_V 0x00000003U -#define MCPWM_GEN1_A_DT0_S 20 -/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_A_DT1 0x00000003U -#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) -#define MCPWM_GEN1_A_DT1_V 0x00000003U -#define MCPWM_GEN1_A_DT1_S 22 - -/** MCPWM_GEN1_B_REG register - * PWM$n output signal B actions configuration register - */ -#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c) -/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_UTEZ 0x00000003U -#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) -#define MCPWM_GEN1_B_UTEZ_V 0x00000003U -#define MCPWM_GEN1_B_UTEZ_S 0 -/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_UTEP 0x00000003U -#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) -#define MCPWM_GEN1_B_UTEP_V 0x00000003U -#define MCPWM_GEN1_B_UTEP_S 2 -/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_UTEA 0x00000003U -#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) -#define MCPWM_GEN1_B_UTEA_V 0x00000003U -#define MCPWM_GEN1_B_UTEA_S 4 -/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_UTEB 0x00000003U -#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) -#define MCPWM_GEN1_B_UTEB_V 0x00000003U -#define MCPWM_GEN1_B_UTEB_S 6 -/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_UT0 0x00000003U -#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) -#define MCPWM_GEN1_B_UT0_V 0x00000003U -#define MCPWM_GEN1_B_UT0_S 8 -/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_UT1 0x00000003U -#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) -#define MCPWM_GEN1_B_UT1_V 0x00000003U -#define MCPWM_GEN1_B_UT1_S 10 -/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_DTEZ 0x00000003U -#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) -#define MCPWM_GEN1_B_DTEZ_V 0x00000003U -#define MCPWM_GEN1_B_DTEZ_S 12 -/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_DTEP 0x00000003U -#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) -#define MCPWM_GEN1_B_DTEP_V 0x00000003U -#define MCPWM_GEN1_B_DTEP_S 14 -/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_DTEA 0x00000003U -#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) -#define MCPWM_GEN1_B_DTEA_V 0x00000003U -#define MCPWM_GEN1_B_DTEA_S 16 -/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_DTEB 0x00000003U -#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) -#define MCPWM_GEN1_B_DTEB_V 0x00000003U -#define MCPWM_GEN1_B_DTEB_S 18 -/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_DT0 0x00000003U -#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) -#define MCPWM_GEN1_B_DT0_V 0x00000003U -#define MCPWM_GEN1_B_DT0_S 20 -/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN1_B_DT1 0x00000003U -#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) -#define MCPWM_GEN1_B_DT1_V 0x00000003U -#define MCPWM_GEN1_B_DT1_S 22 - -/** MCPWM_DT1_CFG_REG register - * Dead time configuration register - */ -#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90) -/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures update method for FED (Falling edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_DB1_FED_UPMETHOD 0x0000000FU -#define MCPWM_DB1_FED_UPMETHOD_M (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S) -#define MCPWM_DB1_FED_UPMETHOD_V 0x0000000FU -#define MCPWM_DB1_FED_UPMETHOD_S 0 -/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; - * Configures update method for RED (rising edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_DB1_RED_UPMETHOD 0x0000000FU -#define MCPWM_DB1_RED_UPMETHOD_M (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S) -#define MCPWM_DB1_RED_UPMETHOD_V 0x0000000FU -#define MCPWM_DB1_RED_UPMETHOD_S 4 -/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0; - * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path - * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode - */ -#define MCPWM_DB1_DEB_MODE (BIT(8)) -#define MCPWM_DB1_DEB_MODE_M (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S) -#define MCPWM_DB1_DEB_MODE_V 0x00000001U -#define MCPWM_DB1_DEB_MODE_S 8 -/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; - * Configures S6 in table. - */ -#define MCPWM_DB1_A_OUTSWAP (BIT(9)) -#define MCPWM_DB1_A_OUTSWAP_M (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S) -#define MCPWM_DB1_A_OUTSWAP_V 0x00000001U -#define MCPWM_DB1_A_OUTSWAP_S 9 -/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; - * Configures S7 in table. - */ -#define MCPWM_DB1_B_OUTSWAP (BIT(10)) -#define MCPWM_DB1_B_OUTSWAP_M (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S) -#define MCPWM_DB1_B_OUTSWAP_V 0x00000001U -#define MCPWM_DB1_B_OUTSWAP_S 10 -/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0; - * Configures S4 in table. - */ -#define MCPWM_DB1_RED_INSEL (BIT(11)) -#define MCPWM_DB1_RED_INSEL_M (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S) -#define MCPWM_DB1_RED_INSEL_V 0x00000001U -#define MCPWM_DB1_RED_INSEL_S 11 -/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0; - * Configures S5 in table. - */ -#define MCPWM_DB1_FED_INSEL (BIT(12)) -#define MCPWM_DB1_FED_INSEL_M (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S) -#define MCPWM_DB1_FED_INSEL_V 0x00000001U -#define MCPWM_DB1_FED_INSEL_S 12 -/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; - * Configures S2 in table. - */ -#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB1_RED_OUTINVERT_M (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S) -#define MCPWM_DB1_RED_OUTINVERT_V 0x00000001U -#define MCPWM_DB1_RED_OUTINVERT_S 13 -/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; - * Configures S3 in table. - */ -#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB1_FED_OUTINVERT_M (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S) -#define MCPWM_DB1_FED_OUTINVERT_V 0x00000001U -#define MCPWM_DB1_FED_OUTINVERT_S 14 -/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; - * Configures S1 in table. - */ -#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB1_A_OUTBYPASS_M (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S) -#define MCPWM_DB1_A_OUTBYPASS_V 0x00000001U -#define MCPWM_DB1_A_OUTBYPASS_S 15 -/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; - * Configures S0 in table. - */ -#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB1_B_OUTBYPASS_M (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S) -#define MCPWM_DB1_B_OUTBYPASS_V 0x00000001U -#define MCPWM_DB1_B_OUTBYPASS_S 16 -/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0; - * Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk - */ -#define MCPWM_DB1_CLK_SEL (BIT(17)) -#define MCPWM_DB1_CLK_SEL_M (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S) -#define MCPWM_DB1_CLK_SEL_V 0x00000001U -#define MCPWM_DB1_CLK_SEL_S 17 - -/** MCPWM_DT1_FED_CFG_REG register - * Falling edge delay (FED) shadow register - */ -#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94) -/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for FED. - */ -#define MCPWM_DB1_FED 0x0000FFFFU -#define MCPWM_DB1_FED_M (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S) -#define MCPWM_DB1_FED_V 0x0000FFFFU -#define MCPWM_DB1_FED_S 0 - -/** MCPWM_DT1_RED_CFG_REG register - * Rising edge delay (RED) shadow register - */ -#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98) -/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for RED. - */ -#define MCPWM_DB1_RED 0x0000FFFFU -#define MCPWM_DB1_RED_M (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S) -#define MCPWM_DB1_RED_V 0x0000FFFFU -#define MCPWM_DB1_RED_S 0 - -/** MCPWM_CARRIER1_CFG_REG register - * Carrier$n configuration register - */ -#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c) -/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled - */ -#define MCPWM_CHOPPER1_EN (BIT(0)) -#define MCPWM_CHOPPER1_EN_M (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S) -#define MCPWM_CHOPPER1_EN_V 0x00000001U -#define MCPWM_CHOPPER1_EN_S 0 -/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; - * Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of - * PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1) - */ -#define MCPWM_CHOPPER1_PRESCALE 0x0000000FU -#define MCPWM_CHOPPER1_PRESCALE_M (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S) -#define MCPWM_CHOPPER1_PRESCALE_V 0x0000000FU -#define MCPWM_CHOPPER1_PRESCALE_S 1 -/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0; - * Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8 - */ -#define MCPWM_CHOPPER1_DUTY 0x00000007U -#define MCPWM_CHOPPER1_DUTY_M (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S) -#define MCPWM_CHOPPER1_DUTY_V 0x00000007U -#define MCPWM_CHOPPER1_DUTY_S 5 -/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; - * Configures width of the first pulse. Measurement unit: Periods of the carrier. - */ -#define MCPWM_CHOPPER1_OSHTWTH 0x0000000FU -#define MCPWM_CHOPPER1_OSHTWTH_M (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S) -#define MCPWM_CHOPPER1_OSHTWTH_V 0x0000000FU -#define MCPWM_CHOPPER1_OSHTWTH_S 8 -/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; - * Configures whether or not to invert the output of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ -#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER1_OUT_INVERT_M (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S) -#define MCPWM_CHOPPER1_OUT_INVERT_V 0x00000001U -#define MCPWM_CHOPPER1_OUT_INVERT_S 12 -/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0; - * Configures whether or not to invert the input of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ -#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER1_IN_INVERT_M (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S) -#define MCPWM_CHOPPER1_IN_INVERT_V 0x00000001U -#define MCPWM_CHOPPER1_IN_INVERT_S 13 - -/** MCPWM_FH1_CFG0_REG register - * PWM$n A and PWM$n B trip events actions configuration register - */ -#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0) -/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_SW_CBC (BIT(0)) -#define MCPWM_TZ1_SW_CBC_M (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S) -#define MCPWM_TZ1_SW_CBC_V 0x00000001U -#define MCPWM_TZ1_SW_CBC_S 0 -/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0; - * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_F2_CBC (BIT(1)) -#define MCPWM_TZ1_F2_CBC_M (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S) -#define MCPWM_TZ1_F2_CBC_V 0x00000001U -#define MCPWM_TZ1_F2_CBC_S 1 -/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0; - * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_F1_CBC (BIT(2)) -#define MCPWM_TZ1_F1_CBC_M (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S) -#define MCPWM_TZ1_F1_CBC_V 0x00000001U -#define MCPWM_TZ1_F1_CBC_S 2 -/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0; - * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_F0_CBC (BIT(3)) -#define MCPWM_TZ1_F0_CBC_M (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S) -#define MCPWM_TZ1_F0_CBC_V 0x00000001U -#define MCPWM_TZ1_F0_CBC_S 3 -/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable software force one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_SW_OST (BIT(4)) -#define MCPWM_TZ1_SW_OST_M (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S) -#define MCPWM_TZ1_SW_OST_V 0x00000001U -#define MCPWM_TZ1_SW_OST_S 4 -/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0; - * Configures whether or not event_f2 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_F2_OST (BIT(5)) -#define MCPWM_TZ1_F2_OST_M (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S) -#define MCPWM_TZ1_F2_OST_V 0x00000001U -#define MCPWM_TZ1_F2_OST_S 5 -/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0; - * Configures whether or not event_f1 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_F1_OST (BIT(6)) -#define MCPWM_TZ1_F1_OST_M (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S) -#define MCPWM_TZ1_F1_OST_V 0x00000001U -#define MCPWM_TZ1_F1_OST_S 6 -/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0; - * Configures whether or not event_f0 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ1_F0_OST (BIT(7)) -#define MCPWM_TZ1_F0_OST_M (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S) -#define MCPWM_TZ1_F0_OST_V 0x00000001U -#define MCPWM_TZ1_F0_OST_S 7 -/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_A_CBC_D 0x00000003U -#define MCPWM_TZ1_A_CBC_D_M (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S) -#define MCPWM_TZ1_A_CBC_D_V 0x00000003U -#define MCPWM_TZ1_A_CBC_D_S 8 -/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_A_CBC_U 0x00000003U -#define MCPWM_TZ1_A_CBC_U_M (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S) -#define MCPWM_TZ1_A_CBC_U_V 0x00000003U -#define MCPWM_TZ1_A_CBC_U_S 10 -/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_A_OST_D 0x00000003U -#define MCPWM_TZ1_A_OST_D_M (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S) -#define MCPWM_TZ1_A_OST_D_V 0x00000003U -#define MCPWM_TZ1_A_OST_D_S 12 -/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_A_OST_U 0x00000003U -#define MCPWM_TZ1_A_OST_U_M (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S) -#define MCPWM_TZ1_A_OST_U_V 0x00000003U -#define MCPWM_TZ1_A_OST_U_S 14 -/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_B_CBC_D 0x00000003U -#define MCPWM_TZ1_B_CBC_D_M (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S) -#define MCPWM_TZ1_B_CBC_D_V 0x00000003U -#define MCPWM_TZ1_B_CBC_D_S 16 -/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_B_CBC_U 0x00000003U -#define MCPWM_TZ1_B_CBC_U_M (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S) -#define MCPWM_TZ1_B_CBC_U_V 0x00000003U -#define MCPWM_TZ1_B_CBC_U_S 18 -/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_B_OST_D 0x00000003U -#define MCPWM_TZ1_B_OST_D_M (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S) -#define MCPWM_TZ1_B_OST_D_V 0x00000003U -#define MCPWM_TZ1_B_OST_D_S 20 -/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ1_B_OST_U 0x00000003U -#define MCPWM_TZ1_B_OST_U_M (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S) -#define MCPWM_TZ1_B_OST_U_V 0x00000003U -#define MCPWM_TZ1_B_OST_U_S 22 - -/** MCPWM_FH1_CFG1_REG register - * Software triggers for fault handler actions configuration register - */ -#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4) -/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0; - * Configures the generation of software one-shot mode action clear. A toggle - * (software negate its value) triggers a clear for on going one-shot mode action. - */ -#define MCPWM_TZ1_CLR_OST (BIT(0)) -#define MCPWM_TZ1_CLR_OST_M (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S) -#define MCPWM_TZ1_CLR_OST_V 0x00000001U -#define MCPWM_TZ1_CLR_OST_S 0 -/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; - * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select - * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP - */ -#define MCPWM_TZ1_CBCPULSE 0x00000003U -#define MCPWM_TZ1_CBCPULSE_M (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S) -#define MCPWM_TZ1_CBCPULSE_V 0x00000003U -#define MCPWM_TZ1_CBCPULSE_S 1 -/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0; - * Configures the generation of software cycle-by-cycle mode action. A toggle - * (software negate its value) triggers a cycle-by-cycle mode action. - */ -#define MCPWM_TZ1_FORCE_CBC (BIT(3)) -#define MCPWM_TZ1_FORCE_CBC_M (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S) -#define MCPWM_TZ1_FORCE_CBC_V 0x00000001U -#define MCPWM_TZ1_FORCE_CBC_S 3 -/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0; - * Configures the generation of software one-shot mode action. A toggle (software - * negate its value) triggers a one-shot mode action. - */ -#define MCPWM_TZ1_FORCE_OST (BIT(4)) -#define MCPWM_TZ1_FORCE_OST_M (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S) -#define MCPWM_TZ1_FORCE_OST_V 0x00000001U -#define MCPWM_TZ1_FORCE_OST_S 4 - -/** MCPWM_FH1_STATUS_REG register - * Fault events status register - */ -#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8) -/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0; - * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No - * action\\1: On going - */ -#define MCPWM_TZ1_CBC_ON (BIT(0)) -#define MCPWM_TZ1_CBC_ON_M (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S) -#define MCPWM_TZ1_CBC_ON_V 0x00000001U -#define MCPWM_TZ1_CBC_ON_S 0 -/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0; - * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On - * going - */ -#define MCPWM_TZ1_OST_ON (BIT(1)) -#define MCPWM_TZ1_OST_ON_M (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S) -#define MCPWM_TZ1_OST_ON_V 0x00000001U -#define MCPWM_TZ1_OST_ON_S 1 - -/** MCPWM_GEN2_STMP_CFG_REG register - * Generator2 time stamp registers A and B transfer status and update method register - */ -#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac) -/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures the update method for PWM generator 2 time stamp A's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_CMPR0_A_UPMETHOD 0x0000000FU -#define MCPWM_CMPR0_A_UPMETHOD_M (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S) -#define MCPWM_CMPR0_A_UPMETHOD_V 0x0000000FU -#define MCPWM_CMPR0_A_UPMETHOD_S 0 -/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; - * Configures the update method for PWM generator 2 time stamp B's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_CMPR0_B_UPMETHOD 0x0000000FU -#define MCPWM_CMPR0_B_UPMETHOD_M (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S) -#define MCPWM_CMPR0_B_UPMETHOD_V 0x0000000FU -#define MCPWM_CMPR0_B_UPMETHOD_S 4 -/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; - * Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0: - * A's active reg has been updated with shadow register latest value.\\1: A's shadow - * reg is filled and waiting to be transferred to A's active reg - */ -#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR0_A_SHDW_FULL_M (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S) -#define MCPWM_CMPR0_A_SHDW_FULL_V 0x00000001U -#define MCPWM_CMPR0_A_SHDW_FULL_S 8 -/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; - * Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0: - * B's active reg has been updated with shadow register latest value.\\1: B's shadow - * reg is filled and waiting to be transferred to B's active reg - */ -#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR0_B_SHDW_FULL_M (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S) -#define MCPWM_CMPR0_B_SHDW_FULL_V 0x00000001U -#define MCPWM_CMPR0_B_SHDW_FULL_S 9 - -/** MCPWM_GEN2_TSTMP_A_REG register - * Generator$n time stamp A's shadow register - */ -#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0) -/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp A's shadow register. - */ -#define MCPWM_CMPR2_A 0x0000FFFFU -#define MCPWM_CMPR2_A_M (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S) -#define MCPWM_CMPR2_A_V 0x0000FFFFU -#define MCPWM_CMPR2_A_S 0 - -/** MCPWM_GEN2_TSTMP_B_REG register - * Generator$n time stamp B's shadow register - */ -#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4) -/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp B's shadow register. - */ -#define MCPWM_CMPR2_B 0x0000FFFFU -#define MCPWM_CMPR2_B_M (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S) -#define MCPWM_CMPR2_B_V 0x0000FFFFU -#define MCPWM_CMPR2_B_S 0 - -/** MCPWM_GEN2_CFG0_REG register - * Generator$n fault event T0 and T1 configuration register - */ -#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8) -/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures update method for PWM generator $n's active register.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU -#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) -#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU -#define MCPWM_GEN2_CFG_UPMETHOD_S 0 -/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; - * Configures source selection for PWM generator $n event_t0, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ -#define MCPWM_GEN2_T0_SEL 0x00000007U -#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) -#define MCPWM_GEN2_T0_SEL_V 0x00000007U -#define MCPWM_GEN2_T0_SEL_S 4 -/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; - * Configures source selection for PWM generator $n event_t1, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ -#define MCPWM_GEN2_T1_SEL 0x00000007U -#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) -#define MCPWM_GEN2_T1_SEL_V 0x00000007U -#define MCPWM_GEN2_T1_SEL_S 7 - -/** MCPWM_GEN2_FORCE_REG register - * Generator$n output signal force mode register. - */ -#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc) -/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; - * Configures update method for continuous software force of PWM generator$n.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable - * update. TEA/B here and below means an event generated when the timer's value equals - * to that of register A/B. - */ -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 -/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; - * Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ -#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U -#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) -#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U -#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 -/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; - * Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ -#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U -#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) -#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U -#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 -/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n A, a toggle will trigger a force event. - */ -#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) -#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U -#define MCPWM_GEN2_A_NCIFORCE_S 10 -/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n A.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ -#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U -#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) -#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U -#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 -/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n B, a toggle will trigger a force event. - */ -#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) -#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U -#define MCPWM_GEN2_B_NCIFORCE_S 13 -/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n B.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ -#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U -#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) -#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U -#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 - -/** MCPWM_GEN2_A_REG register - * PWM$n output signal A actions configuration register - */ -#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0) -/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_UTEZ 0x00000003U -#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) -#define MCPWM_GEN2_A_UTEZ_V 0x00000003U -#define MCPWM_GEN2_A_UTEZ_S 0 -/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_UTEP 0x00000003U -#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) -#define MCPWM_GEN2_A_UTEP_V 0x00000003U -#define MCPWM_GEN2_A_UTEP_S 2 -/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_UTEA 0x00000003U -#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) -#define MCPWM_GEN2_A_UTEA_V 0x00000003U -#define MCPWM_GEN2_A_UTEA_S 4 -/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_UTEB 0x00000003U -#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) -#define MCPWM_GEN2_A_UTEB_V 0x00000003U -#define MCPWM_GEN2_A_UTEB_S 6 -/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_UT0 0x00000003U -#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) -#define MCPWM_GEN2_A_UT0_V 0x00000003U -#define MCPWM_GEN2_A_UT0_S 8 -/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_UT1 0x00000003U -#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) -#define MCPWM_GEN2_A_UT1_V 0x00000003U -#define MCPWM_GEN2_A_UT1_S 10 -/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_DTEZ 0x00000003U -#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) -#define MCPWM_GEN2_A_DTEZ_V 0x00000003U -#define MCPWM_GEN2_A_DTEZ_S 12 -/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_DTEP 0x00000003U -#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) -#define MCPWM_GEN2_A_DTEP_V 0x00000003U -#define MCPWM_GEN2_A_DTEP_S 14 -/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_DTEA 0x00000003U -#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) -#define MCPWM_GEN2_A_DTEA_V 0x00000003U -#define MCPWM_GEN2_A_DTEA_S 16 -/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_DTEB 0x00000003U -#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) -#define MCPWM_GEN2_A_DTEB_V 0x00000003U -#define MCPWM_GEN2_A_DTEB_S 18 -/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_DT0 0x00000003U -#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) -#define MCPWM_GEN2_A_DT0_V 0x00000003U -#define MCPWM_GEN2_A_DT0_S 20 -/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_A_DT1 0x00000003U -#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) -#define MCPWM_GEN2_A_DT1_V 0x00000003U -#define MCPWM_GEN2_A_DT1_S 22 - -/** MCPWM_GEN2_B_REG register - * PWM$n output signal B actions configuration register - */ -#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4) -/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_UTEZ 0x00000003U -#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) -#define MCPWM_GEN2_B_UTEZ_V 0x00000003U -#define MCPWM_GEN2_B_UTEZ_S 0 -/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_UTEP 0x00000003U -#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) -#define MCPWM_GEN2_B_UTEP_V 0x00000003U -#define MCPWM_GEN2_B_UTEP_S 2 -/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_UTEA 0x00000003U -#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) -#define MCPWM_GEN2_B_UTEA_V 0x00000003U -#define MCPWM_GEN2_B_UTEA_S 4 -/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_UTEB 0x00000003U -#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) -#define MCPWM_GEN2_B_UTEB_V 0x00000003U -#define MCPWM_GEN2_B_UTEB_S 6 -/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_UT0 0x00000003U -#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) -#define MCPWM_GEN2_B_UT0_V 0x00000003U -#define MCPWM_GEN2_B_UT0_S 8 -/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_UT1 0x00000003U -#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) -#define MCPWM_GEN2_B_UT1_V 0x00000003U -#define MCPWM_GEN2_B_UT1_S 10 -/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_DTEZ 0x00000003U -#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) -#define MCPWM_GEN2_B_DTEZ_V 0x00000003U -#define MCPWM_GEN2_B_DTEZ_S 12 -/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_DTEP 0x00000003U -#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) -#define MCPWM_GEN2_B_DTEP_V 0x00000003U -#define MCPWM_GEN2_B_DTEP_S 14 -/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_DTEA 0x00000003U -#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) -#define MCPWM_GEN2_B_DTEA_V 0x00000003U -#define MCPWM_GEN2_B_DTEA_S 16 -/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_DTEB 0x00000003U -#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) -#define MCPWM_GEN2_B_DTEB_V 0x00000003U -#define MCPWM_GEN2_B_DTEB_S 18 -/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_DT0 0x00000003U -#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) -#define MCPWM_GEN2_B_DT0_V 0x00000003U -#define MCPWM_GEN2_B_DT0_S 20 -/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ -#define MCPWM_GEN2_B_DT1 0x00000003U -#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) -#define MCPWM_GEN2_B_DT1_V 0x00000003U -#define MCPWM_GEN2_B_DT1_S 22 - -/** MCPWM_DT2_CFG_REG register - * Dead time configuration register - */ -#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8) -/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; - * Configures update method for FED (Falling edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_DB2_FED_UPMETHOD 0x0000000FU -#define MCPWM_DB2_FED_UPMETHOD_M (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S) -#define MCPWM_DB2_FED_UPMETHOD_V 0x0000000FU -#define MCPWM_DB2_FED_UPMETHOD_S 0 -/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; - * Configures update method for RED (rising edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ -#define MCPWM_DB2_RED_UPMETHOD 0x0000000FU -#define MCPWM_DB2_RED_UPMETHOD_M (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S) -#define MCPWM_DB2_RED_UPMETHOD_V 0x0000000FU -#define MCPWM_DB2_RED_UPMETHOD_S 4 -/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0; - * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path - * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode - */ -#define MCPWM_DB2_DEB_MODE (BIT(8)) -#define MCPWM_DB2_DEB_MODE_M (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S) -#define MCPWM_DB2_DEB_MODE_V 0x00000001U -#define MCPWM_DB2_DEB_MODE_S 8 -/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; - * Configures S6 in table. - */ -#define MCPWM_DB2_A_OUTSWAP (BIT(9)) -#define MCPWM_DB2_A_OUTSWAP_M (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S) -#define MCPWM_DB2_A_OUTSWAP_V 0x00000001U -#define MCPWM_DB2_A_OUTSWAP_S 9 -/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; - * Configures S7 in table. - */ -#define MCPWM_DB2_B_OUTSWAP (BIT(10)) -#define MCPWM_DB2_B_OUTSWAP_M (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S) -#define MCPWM_DB2_B_OUTSWAP_V 0x00000001U -#define MCPWM_DB2_B_OUTSWAP_S 10 -/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0; - * Configures S4 in table. - */ -#define MCPWM_DB2_RED_INSEL (BIT(11)) -#define MCPWM_DB2_RED_INSEL_M (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S) -#define MCPWM_DB2_RED_INSEL_V 0x00000001U -#define MCPWM_DB2_RED_INSEL_S 11 -/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0; - * Configures S5 in table. - */ -#define MCPWM_DB2_FED_INSEL (BIT(12)) -#define MCPWM_DB2_FED_INSEL_M (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S) -#define MCPWM_DB2_FED_INSEL_V 0x00000001U -#define MCPWM_DB2_FED_INSEL_S 12 -/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; - * Configures S2 in table. - */ -#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB2_RED_OUTINVERT_M (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S) -#define MCPWM_DB2_RED_OUTINVERT_V 0x00000001U -#define MCPWM_DB2_RED_OUTINVERT_S 13 -/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; - * Configures S3 in table. - */ -#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB2_FED_OUTINVERT_M (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S) -#define MCPWM_DB2_FED_OUTINVERT_V 0x00000001U -#define MCPWM_DB2_FED_OUTINVERT_S 14 -/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; - * Configures S1 in table. - */ -#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB2_A_OUTBYPASS_M (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S) -#define MCPWM_DB2_A_OUTBYPASS_V 0x00000001U -#define MCPWM_DB2_A_OUTBYPASS_S 15 -/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; - * Configures S0 in table. - */ -#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB2_B_OUTBYPASS_M (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S) -#define MCPWM_DB2_B_OUTBYPASS_V 0x00000001U -#define MCPWM_DB2_B_OUTBYPASS_S 16 -/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0; - * Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk - */ -#define MCPWM_DB2_CLK_SEL (BIT(17)) -#define MCPWM_DB2_CLK_SEL_M (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S) -#define MCPWM_DB2_CLK_SEL_V 0x00000001U -#define MCPWM_DB2_CLK_SEL_S 17 - -/** MCPWM_DT2_FED_CFG_REG register - * Falling edge delay (FED) shadow register - */ -#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc) -/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for FED. - */ -#define MCPWM_DB2_FED 0x0000FFFFU -#define MCPWM_DB2_FED_M (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S) -#define MCPWM_DB2_FED_V 0x0000FFFFU -#define MCPWM_DB2_FED_S 0 - -/** MCPWM_DT2_RED_CFG_REG register - * Rising edge delay (RED) shadow register - */ -#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0) -/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for RED. - */ -#define MCPWM_DB2_RED 0x0000FFFFU -#define MCPWM_DB2_RED_M (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S) -#define MCPWM_DB2_RED_V 0x0000FFFFU -#define MCPWM_DB2_RED_S 0 - -/** MCPWM_CARRIER2_CFG_REG register - * Carrier$n configuration register - */ -#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4) -/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled - */ -#define MCPWM_CHOPPER2_EN (BIT(0)) -#define MCPWM_CHOPPER2_EN_M (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S) -#define MCPWM_CHOPPER2_EN_V 0x00000001U -#define MCPWM_CHOPPER2_EN_S 0 -/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; - * Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of - * PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1) - */ -#define MCPWM_CHOPPER2_PRESCALE 0x0000000FU -#define MCPWM_CHOPPER2_PRESCALE_M (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S) -#define MCPWM_CHOPPER2_PRESCALE_V 0x0000000FU -#define MCPWM_CHOPPER2_PRESCALE_S 1 -/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0; - * Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8 - */ -#define MCPWM_CHOPPER2_DUTY 0x00000007U -#define MCPWM_CHOPPER2_DUTY_M (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S) -#define MCPWM_CHOPPER2_DUTY_V 0x00000007U -#define MCPWM_CHOPPER2_DUTY_S 5 -/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; - * Configures width of the first pulse. Measurement unit: Periods of the carrier. - */ -#define MCPWM_CHOPPER2_OSHTWTH 0x0000000FU -#define MCPWM_CHOPPER2_OSHTWTH_M (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S) -#define MCPWM_CHOPPER2_OSHTWTH_V 0x0000000FU -#define MCPWM_CHOPPER2_OSHTWTH_S 8 -/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; - * Configures whether or not to invert the output of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ -#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER2_OUT_INVERT_M (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S) -#define MCPWM_CHOPPER2_OUT_INVERT_V 0x00000001U -#define MCPWM_CHOPPER2_OUT_INVERT_S 12 -/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0; - * Configures whether or not to invert the input of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ -#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER2_IN_INVERT_M (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S) -#define MCPWM_CHOPPER2_IN_INVERT_V 0x00000001U -#define MCPWM_CHOPPER2_IN_INVERT_S 13 - -/** MCPWM_FH2_CFG0_REG register - * PWM$n A and PWM$n B trip events actions configuration register - */ -#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8) -/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_SW_CBC (BIT(0)) -#define MCPWM_TZ2_SW_CBC_M (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S) -#define MCPWM_TZ2_SW_CBC_V 0x00000001U -#define MCPWM_TZ2_SW_CBC_S 0 -/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0; - * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_F2_CBC (BIT(1)) -#define MCPWM_TZ2_F2_CBC_M (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S) -#define MCPWM_TZ2_F2_CBC_V 0x00000001U -#define MCPWM_TZ2_F2_CBC_S 1 -/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0; - * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_F1_CBC (BIT(2)) -#define MCPWM_TZ2_F1_CBC_M (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S) -#define MCPWM_TZ2_F1_CBC_V 0x00000001U -#define MCPWM_TZ2_F1_CBC_S 2 -/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0; - * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_F0_CBC (BIT(3)) -#define MCPWM_TZ2_F0_CBC_M (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S) -#define MCPWM_TZ2_F0_CBC_V 0x00000001U -#define MCPWM_TZ2_F0_CBC_S 3 -/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable software force one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_SW_OST (BIT(4)) -#define MCPWM_TZ2_SW_OST_M (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S) -#define MCPWM_TZ2_SW_OST_V 0x00000001U -#define MCPWM_TZ2_SW_OST_S 4 -/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0; - * Configures whether or not event_f2 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_F2_OST (BIT(5)) -#define MCPWM_TZ2_F2_OST_M (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S) -#define MCPWM_TZ2_F2_OST_V 0x00000001U -#define MCPWM_TZ2_F2_OST_S 5 -/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0; - * Configures whether or not event_f1 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_F1_OST (BIT(6)) -#define MCPWM_TZ2_F1_OST_M (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S) -#define MCPWM_TZ2_F1_OST_V 0x00000001U -#define MCPWM_TZ2_F1_OST_S 6 -/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0; - * Configures whether or not event_f0 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TZ2_F0_OST (BIT(7)) -#define MCPWM_TZ2_F0_OST_M (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S) -#define MCPWM_TZ2_F0_OST_V 0x00000001U -#define MCPWM_TZ2_F0_OST_S 7 -/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_A_CBC_D 0x00000003U -#define MCPWM_TZ2_A_CBC_D_M (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S) -#define MCPWM_TZ2_A_CBC_D_V 0x00000003U -#define MCPWM_TZ2_A_CBC_D_S 8 -/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_A_CBC_U 0x00000003U -#define MCPWM_TZ2_A_CBC_U_M (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S) -#define MCPWM_TZ2_A_CBC_U_V 0x00000003U -#define MCPWM_TZ2_A_CBC_U_S 10 -/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_A_OST_D 0x00000003U -#define MCPWM_TZ2_A_OST_D_M (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S) -#define MCPWM_TZ2_A_OST_D_V 0x00000003U -#define MCPWM_TZ2_A_OST_D_S 12 -/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_A_OST_U 0x00000003U -#define MCPWM_TZ2_A_OST_U_M (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S) -#define MCPWM_TZ2_A_OST_U_V 0x00000003U -#define MCPWM_TZ2_A_OST_U_S 14 -/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_B_CBC_D 0x00000003U -#define MCPWM_TZ2_B_CBC_D_M (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S) -#define MCPWM_TZ2_B_CBC_D_V 0x00000003U -#define MCPWM_TZ2_B_CBC_D_S 16 -/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_B_CBC_U 0x00000003U -#define MCPWM_TZ2_B_CBC_U_M (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S) -#define MCPWM_TZ2_B_CBC_U_V 0x00000003U -#define MCPWM_TZ2_B_CBC_U_S 18 -/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_B_OST_D 0x00000003U -#define MCPWM_TZ2_B_OST_D_M (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S) -#define MCPWM_TZ2_B_OST_D_V 0x00000003U -#define MCPWM_TZ2_B_OST_D_S 20 -/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ -#define MCPWM_TZ2_B_OST_U 0x00000003U -#define MCPWM_TZ2_B_OST_U_M (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S) -#define MCPWM_TZ2_B_OST_U_V 0x00000003U -#define MCPWM_TZ2_B_OST_U_S 22 - -/** MCPWM_FH2_CFG1_REG register - * Software triggers for fault handler actions configuration register - */ -#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc) -/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0; - * Configures the generation of software one-shot mode action clear. A toggle - * (software negate its value) triggers a clear for on going one-shot mode action. - */ -#define MCPWM_TZ2_CLR_OST (BIT(0)) -#define MCPWM_TZ2_CLR_OST_M (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S) -#define MCPWM_TZ2_CLR_OST_V 0x00000001U -#define MCPWM_TZ2_CLR_OST_S 0 -/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; - * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select - * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP - */ -#define MCPWM_TZ2_CBCPULSE 0x00000003U -#define MCPWM_TZ2_CBCPULSE_M (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S) -#define MCPWM_TZ2_CBCPULSE_V 0x00000003U -#define MCPWM_TZ2_CBCPULSE_S 1 -/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0; - * Configures the generation of software cycle-by-cycle mode action. A toggle - * (software negate its value) triggers a cycle-by-cycle mode action. - */ -#define MCPWM_TZ2_FORCE_CBC (BIT(3)) -#define MCPWM_TZ2_FORCE_CBC_M (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S) -#define MCPWM_TZ2_FORCE_CBC_V 0x00000001U -#define MCPWM_TZ2_FORCE_CBC_S 3 -/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0; - * Configures the generation of software one-shot mode action. A toggle (software - * negate its value) triggers a one-shot mode action. - */ -#define MCPWM_TZ2_FORCE_OST (BIT(4)) -#define MCPWM_TZ2_FORCE_OST_M (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S) -#define MCPWM_TZ2_FORCE_OST_V 0x00000001U -#define MCPWM_TZ2_FORCE_OST_S 4 - -/** MCPWM_FH2_STATUS_REG register - * Fault events status register - */ -#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0) -/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0; - * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No - * action\\1: On going - */ -#define MCPWM_TZ2_CBC_ON (BIT(0)) -#define MCPWM_TZ2_CBC_ON_M (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S) -#define MCPWM_TZ2_CBC_ON_V 0x00000001U -#define MCPWM_TZ2_CBC_ON_S 0 -/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0; - * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On - * going - */ -#define MCPWM_TZ2_OST_ON (BIT(1)) -#define MCPWM_TZ2_OST_ON_M (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S) -#define MCPWM_TZ2_OST_ON_V 0x00000001U -#define MCPWM_TZ2_OST_ON_S 1 - -/** MCPWM_FAULT_DETECT_REG register - * Fault detection configuration and status register - */ -#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4) -/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable - */ -#define MCPWM_F0_EN (BIT(0)) -#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) -#define MCPWM_F0_EN_V 0x00000001U -#define MCPWM_F0_EN_S 0 -/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable - */ -#define MCPWM_F1_EN (BIT(1)) -#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) -#define MCPWM_F1_EN_V 0x00000001U -#define MCPWM_F1_EN_S 1 -/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable - */ -#define MCPWM_F2_EN (BIT(2)) -#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) -#define MCPWM_F2_EN_V 0x00000001U -#define MCPWM_F2_EN_S 2 -/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; - * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level - * low\\1: Level high - */ -#define MCPWM_F0_POLE (BIT(3)) -#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) -#define MCPWM_F0_POLE_V 0x00000001U -#define MCPWM_F0_POLE_S 3 -/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; - * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level - * low\\1: Level high - */ -#define MCPWM_F1_POLE (BIT(4)) -#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) -#define MCPWM_F1_POLE_V 0x00000001U -#define MCPWM_F1_POLE_S 4 -/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; - * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level - * low\\1: Level high - */ -#define MCPWM_F2_POLE (BIT(5)) -#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) -#define MCPWM_F2_POLE_V 0x00000001U -#define MCPWM_F2_POLE_S 5 -/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; - * Represents whether or not an event_f0 is on going.\\0: No action\\1: On going - */ -#define MCPWM_EVENT_F0 (BIT(6)) -#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) -#define MCPWM_EVENT_F0_V 0x00000001U -#define MCPWM_EVENT_F0_S 6 -/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; - * Represents whether or not an event_f1 is on going.\\0: No action\\1: On going - */ -#define MCPWM_EVENT_F1 (BIT(7)) -#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) -#define MCPWM_EVENT_F1_V 0x00000001U -#define MCPWM_EVENT_F1_S 7 -/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; - * Represents whether or not an event_f2 is on going.\\0: No action\\1: On going - */ -#define MCPWM_EVENT_F2 (BIT(8)) -#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) -#define MCPWM_EVENT_F2_V 0x00000001U -#define MCPWM_EVENT_F2_S 8 - -/** MCPWM_CAP_TIMER_CFG_REG register - * Capture timer configuration register - */ -#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8) -/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable - */ -#define MCPWM_CAP_TIMER_EN (BIT(0)) -#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) -#define MCPWM_CAP_TIMER_EN_V 0x00000001U -#define MCPWM_CAP_TIMER_EN_S 0 -/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable - */ -#define MCPWM_CAP_SYNCI_EN (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) -#define MCPWM_CAP_SYNCI_EN_V 0x00000001U -#define MCPWM_CAP_SYNCI_EN_S 1 -/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; - * Configures the selection of capture module sync input.\\0: None\\1: Timer0 - * sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: - * SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None - */ -#define MCPWM_CAP_SYNCI_SEL 0x00000007U -#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) -#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U -#define MCPWM_CAP_SYNCI_SEL_S 2 -/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; - * Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: - * Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with - * value in phase register - */ -#define MCPWM_CAP_SYNC_SW (BIT(5)) -#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) -#define MCPWM_CAP_SYNC_SW_V 0x00000001U -#define MCPWM_CAP_SYNC_SW_S 5 - -/** MCPWM_CAP_TIMER_PHASE_REG register - * Capture timer sync phase register - */ -#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec) -/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0; - * Configures phase value for capture timer sync operation. - */ -#define MCPWM_CAP_PHASE 0xFFFFFFFFU -#define MCPWM_CAP_PHASE_M (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S) -#define MCPWM_CAP_PHASE_V 0xFFFFFFFFU -#define MCPWM_CAP_PHASE_S 0 - -/** MCPWM_CAP_CH0_CFG_REG register - * Capture channel 0 configuration register - */ -#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0) -/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable - */ -#define MCPWM_CAP0_EN (BIT(0)) -#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) -#define MCPWM_CAP0_EN_V 0x00000001U -#define MCPWM_CAP0_EN_S 0 -/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; - * Configures which edge of capture on channel 0 after prescaling is used.\\0: - * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: - * Enable capture on the positive edge - */ -#define MCPWM_CAP0_MODE 0x00000003U -#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) -#define MCPWM_CAP0_MODE_V 0x00000003U -#define MCPWM_CAP0_MODE_S 1 -/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAP0. Prescale value = - * PWM_CAP0_PRESCALE + 1 - */ -#define MCPWM_CAP0_PRESCALE 0x000000FFU -#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) -#define MCPWM_CAP0_PRESCALE_V 0x000000FFU -#define MCPWM_CAP0_PRESCALE_S 3 -/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0: - * Normal\\1: Invert - */ -#define MCPWM_CAP0_IN_INVERT (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) -#define MCPWM_CAP0_IN_INVERT_V 0x00000001U -#define MCPWM_CAP0_IN_INVERT_S 11 -/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; - * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a - * software forced capture on channel 0 - */ -#define MCPWM_CAP0_SW (BIT(12)) -#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) -#define MCPWM_CAP0_SW_V 0x00000001U -#define MCPWM_CAP0_SW_S 12 - -/** MCPWM_CAP_CH1_CFG_REG register - * Capture channel 1 configuration register - */ -#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4) -/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable - */ -#define MCPWM_CAP0_EN (BIT(0)) -#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) -#define MCPWM_CAP0_EN_V 0x00000001U -#define MCPWM_CAP0_EN_S 0 -/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; - * Configures which edge of capture on channel 1 after prescaling is used.\\0: - * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: - * Enable capture on the positive edge - */ -#define MCPWM_CAP0_MODE 0x00000003U -#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) -#define MCPWM_CAP0_MODE_V 0x00000003U -#define MCPWM_CAP0_MODE_S 1 -/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAP1. Prescale value = - * PWM_CAP1_PRESCALE + 1 - */ -#define MCPWM_CAP0_PRESCALE 0x000000FFU -#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) -#define MCPWM_CAP0_PRESCALE_V 0x000000FFU -#define MCPWM_CAP0_PRESCALE_S 3 -/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0: - * Normal\\1: Invert - */ -#define MCPWM_CAP0_IN_INVERT (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) -#define MCPWM_CAP0_IN_INVERT_V 0x00000001U -#define MCPWM_CAP0_IN_INVERT_S 11 -/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; - * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a - * software forced capture on channel 1 - */ -#define MCPWM_CAP0_SW (BIT(12)) -#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) -#define MCPWM_CAP0_SW_V 0x00000001U -#define MCPWM_CAP0_SW_S 12 - -/** MCPWM_CAP_CH2_CFG_REG register - * Capture channel 2 configuration register - */ -#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8) -/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable - */ -#define MCPWM_CAP0_EN (BIT(0)) -#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) -#define MCPWM_CAP0_EN_V 0x00000001U -#define MCPWM_CAP0_EN_S 0 -/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; - * Configures which edge of capture on channel 2 after prescaling is used.\\0: - * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: - * Enable capture on the positive edge - */ -#define MCPWM_CAP0_MODE 0x00000003U -#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) -#define MCPWM_CAP0_MODE_V 0x00000003U -#define MCPWM_CAP0_MODE_S 1 -/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAP2. Prescale value = - * PWM_CAP2_PRESCALE + 1 - */ -#define MCPWM_CAP0_PRESCALE 0x000000FFU -#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) -#define MCPWM_CAP0_PRESCALE_V 0x000000FFU -#define MCPWM_CAP0_PRESCALE_S 3 -/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0: - * Normal\\1: Invert - */ -#define MCPWM_CAP0_IN_INVERT (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) -#define MCPWM_CAP0_IN_INVERT_V 0x00000001U -#define MCPWM_CAP0_IN_INVERT_S 11 -/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; - * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a - * software forced capture on channel 2 - */ -#define MCPWM_CAP0_SW (BIT(12)) -#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) -#define MCPWM_CAP0_SW_V 0x00000001U -#define MCPWM_CAP0_SW_S 12 - -/** MCPWM_CAP_CH0_REG register - * CAP0 capture value register - */ -#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc) -/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; - * Represents value of last capture on CAP0 - */ -#define MCPWM_CAP0_VALUE 0xFFFFFFFFU -#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) -#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU -#define MCPWM_CAP0_VALUE_S 0 - -/** MCPWM_CAP_CH1_REG register - * CAP1 capture value register - */ -#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100) -/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; - * Represents value of last capture on CAP1 - */ -#define MCPWM_CAP0_VALUE 0xFFFFFFFFU -#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) -#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU -#define MCPWM_CAP0_VALUE_S 0 - -/** MCPWM_CAP_CH2_REG register - * CAP2 capture value register - */ -#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104) -/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; - * Represents value of last capture on CAP2 - */ -#define MCPWM_CAP0_VALUE 0xFFFFFFFFU -#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) -#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU -#define MCPWM_CAP0_VALUE_S 0 - -/** MCPWM_CAP_STATUS_REG register - * Last capture trigger edge information register - */ -#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108) -/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; - * Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge - */ -#define MCPWM_CAP0_EDGE (BIT(0)) -#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) -#define MCPWM_CAP0_EDGE_V 0x00000001U -#define MCPWM_CAP0_EDGE_S 0 -/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; - * Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge - */ -#define MCPWM_CAP1_EDGE (BIT(1)) -#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) -#define MCPWM_CAP1_EDGE_V 0x00000001U -#define MCPWM_CAP1_EDGE_S 1 -/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; - * Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge - */ -#define MCPWM_CAP2_EDGE (BIT(2)) -#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) -#define MCPWM_CAP2_EDGE_V 0x00000001U -#define MCPWM_CAP2_EDGE_S 2 - -/** MCPWM_UPDATE_CFG_REG register - * Generator Update configuration register - */ -#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c) -/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable global update for all active registers in MCPWM - * module.\\0: Disable\\1: Enable - */ -#define MCPWM_GLOBAL_UP_EN (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) -#define MCPWM_GLOBAL_UP_EN_V 0x00000001U -#define MCPWM_GLOBAL_UP_EN_S 0 -/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; - * Configures the generation of global forced update for all active registers in MCPWM - * module. A toggle (software invert its value) will trigger a global forced update. - * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. - */ -#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) -#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U -#define MCPWM_GLOBAL_FORCE_UP_S 1 -/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator$n. - * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - */ -#define MCPWM_OP0_UP_EN (BIT(2)) -#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) -#define MCPWM_OP0_UP_EN_V 0x00000001U -#define MCPWM_OP0_UP_EN_S 2 -/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; - * Configures the generation of forced update for active registers in PWM operator0. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. - */ -#define MCPWM_OP0_FORCE_UP (BIT(3)) -#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) -#define MCPWM_OP0_FORCE_UP_V 0x00000001U -#define MCPWM_OP0_FORCE_UP_S 3 -/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator$n. - * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - */ -#define MCPWM_OP1_UP_EN (BIT(4)) -#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) -#define MCPWM_OP1_UP_EN_V 0x00000001U -#define MCPWM_OP1_UP_EN_S 4 -/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; - * Configures the generation of forced update for active registers in PWM operator1. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. - */ -#define MCPWM_OP1_FORCE_UP (BIT(5)) -#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) -#define MCPWM_OP1_FORCE_UP_V 0x00000001U -#define MCPWM_OP1_FORCE_UP_S 5 -/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator$n. - * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - */ -#define MCPWM_OP2_UP_EN (BIT(6)) -#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) -#define MCPWM_OP2_UP_EN_V 0x00000001U -#define MCPWM_OP2_UP_EN_S 6 -/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; - * Configures the generation of forced update for active registers in PWM operator2. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. - */ -#define MCPWM_OP2_FORCE_UP (BIT(7)) -#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) -#define MCPWM_OP2_FORCE_UP_V 0x00000001U -#define MCPWM_OP2_FORCE_UP_S 7 - -/** MCPWM_INT_ENA_REG register - * Interrupt enable register - */ -#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110) -/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. - */ -#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) -#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U -#define MCPWM_TIMER0_STOP_INT_ENA_S 0 -/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. - */ -#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) -#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U -#define MCPWM_TIMER1_STOP_INT_ENA_S 1 -/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. - */ -#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) -#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U -#define MCPWM_TIMER2_STOP_INT_ENA_S 2 -/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. - */ -#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) -#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U -#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 -/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. - */ -#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) -#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U -#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 -/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. - */ -#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) -#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U -#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 -/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. - */ -#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) -#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U -#define MCPWM_TIMER0_TEP_INT_ENA_S 6 -/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. - */ -#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) -#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U -#define MCPWM_TIMER1_TEP_INT_ENA_S 7 -/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. - */ -#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) -#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U -#define MCPWM_TIMER2_TEP_INT_ENA_S 8 -/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. - */ -#define MCPWM_FAULT0_INT_ENA (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) -#define MCPWM_FAULT0_INT_ENA_V 0x00000001U -#define MCPWM_FAULT0_INT_ENA_S 9 -/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. - */ -#define MCPWM_FAULT1_INT_ENA (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) -#define MCPWM_FAULT1_INT_ENA_V 0x00000001U -#define MCPWM_FAULT1_INT_ENA_S 10 -/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. - */ -#define MCPWM_FAULT2_INT_ENA (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) -#define MCPWM_FAULT2_INT_ENA_V 0x00000001U -#define MCPWM_FAULT2_INT_ENA_S 11 -/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. - */ -#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) -#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U -#define MCPWM_FAULT0_CLR_INT_ENA_S 12 -/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. - */ -#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) -#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U -#define MCPWM_FAULT1_CLR_INT_ENA_S 13 -/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. - */ -#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) -#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U -#define MCPWM_FAULT2_CLR_INT_ENA_S 14 -/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. - */ -#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ENA_M (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S) -#define MCPWM_CMPR0_TEA_INT_ENA_V 0x00000001U -#define MCPWM_CMPR0_TEA_INT_ENA_S 15 -/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. - */ -#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ENA_M (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S) -#define MCPWM_CMPR1_TEA_INT_ENA_V 0x00000001U -#define MCPWM_CMPR1_TEA_INT_ENA_S 16 -/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. - */ -#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ENA_M (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S) -#define MCPWM_CMPR2_TEA_INT_ENA_V 0x00000001U -#define MCPWM_CMPR2_TEA_INT_ENA_S 17 -/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. - */ -#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ENA_M (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S) -#define MCPWM_CMPR0_TEB_INT_ENA_V 0x00000001U -#define MCPWM_CMPR0_TEB_INT_ENA_S 18 -/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. - */ -#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ENA_M (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S) -#define MCPWM_CMPR1_TEB_INT_ENA_V 0x00000001U -#define MCPWM_CMPR1_TEB_INT_ENA_S 19 -/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. - */ -#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ENA_M (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S) -#define MCPWM_CMPR2_TEB_INT_ENA_V 0x00000001U -#define MCPWM_CMPR2_TEB_INT_ENA_S 20 -/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM0. - */ -#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ENA_M (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S) -#define MCPWM_TZ0_CBC_INT_ENA_V 0x00000001U -#define MCPWM_TZ0_CBC_INT_ENA_S 21 -/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM1. - */ -#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ENA_M (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S) -#define MCPWM_TZ1_CBC_INT_ENA_V 0x00000001U -#define MCPWM_TZ1_CBC_INT_ENA_S 22 -/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM2. - */ -#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ENA_M (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S) -#define MCPWM_TZ2_CBC_INT_ENA_V 0x00000001U -#define MCPWM_TZ2_CBC_INT_ENA_S 23 -/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM0. - */ -#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) -#define MCPWM_TZ0_OST_INT_ENA_M (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S) -#define MCPWM_TZ0_OST_INT_ENA_V 0x00000001U -#define MCPWM_TZ0_OST_INT_ENA_S 24 -/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM1. - */ -#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) -#define MCPWM_TZ1_OST_INT_ENA_M (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S) -#define MCPWM_TZ1_OST_INT_ENA_V 0x00000001U -#define MCPWM_TZ1_OST_INT_ENA_S 25 -/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM2. - */ -#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) -#define MCPWM_TZ2_OST_INT_ENA_M (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S) -#define MCPWM_TZ2_OST_INT_ENA_V 0x00000001U -#define MCPWM_TZ2_OST_INT_ENA_S 26 -/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. - */ -#define MCPWM_CAP0_INT_ENA (BIT(27)) -#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) -#define MCPWM_CAP0_INT_ENA_V 0x00000001U -#define MCPWM_CAP0_INT_ENA_S 27 -/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. - */ -#define MCPWM_CAP1_INT_ENA (BIT(28)) -#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) -#define MCPWM_CAP1_INT_ENA_V 0x00000001U -#define MCPWM_CAP1_INT_ENA_S 28 -/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. - */ -#define MCPWM_CAP2_INT_ENA (BIT(29)) -#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) -#define MCPWM_CAP2_INT_ENA_V 0x00000001U -#define MCPWM_CAP2_INT_ENA_S 29 - -/** MCPWM_INT_RAW_REG register - * Interrupt raw status register - */ -#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114) -/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 0 stops. - */ -#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) -#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U -#define MCPWM_TIMER0_STOP_INT_RAW_S 0 -/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 1 stops. - */ -#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) -#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U -#define MCPWM_TIMER1_STOP_INT_RAW_S 1 -/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 2 stops. - */ -#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) -#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U -#define MCPWM_TIMER2_STOP_INT_RAW_S 2 -/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 0 TEZ event. - */ -#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) -#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U -#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 -/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 1 TEZ event. - */ -#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) -#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U -#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 -/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 2 TEZ event. - */ -#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) -#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U -#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 -/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 0 TEP event. - */ -#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) -#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U -#define MCPWM_TIMER0_TEP_INT_RAW_S 6 -/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 1 TEP event. - */ -#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) -#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U -#define MCPWM_TIMER1_TEP_INT_RAW_S 7 -/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 2 TEP event. - */ -#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) -#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U -#define MCPWM_TIMER2_TEP_INT_RAW_S 8 -/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 - * starts. - */ -#define MCPWM_FAULT0_INT_RAW (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) -#define MCPWM_FAULT0_INT_RAW_V 0x00000001U -#define MCPWM_FAULT0_INT_RAW_S 9 -/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 - * starts. - */ -#define MCPWM_FAULT1_INT_RAW (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) -#define MCPWM_FAULT1_INT_RAW_V 0x00000001U -#define MCPWM_FAULT1_INT_RAW_S 10 -/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 - * starts. - */ -#define MCPWM_FAULT2_INT_RAW (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) -#define MCPWM_FAULT2_INT_RAW_V 0x00000001U -#define MCPWM_FAULT2_INT_RAW_S 11 -/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 - * clears. - */ -#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) -#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U -#define MCPWM_FAULT0_CLR_INT_RAW_S 12 -/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 - * clears. - */ -#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) -#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U -#define MCPWM_FAULT1_CLR_INT_RAW_S 13 -/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 - * clears. - */ -#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) -#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U -#define MCPWM_FAULT2_CLR_INT_RAW_S 14 -/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 0 TEA event - */ -#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_RAW_M (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S) -#define MCPWM_CMPR0_TEA_INT_RAW_V 0x00000001U -#define MCPWM_CMPR0_TEA_INT_RAW_S 15 -/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 1 TEA event - */ -#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_RAW_M (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S) -#define MCPWM_CMPR1_TEA_INT_RAW_V 0x00000001U -#define MCPWM_CMPR1_TEA_INT_RAW_S 16 -/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 2 TEA event - */ -#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_RAW_M (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S) -#define MCPWM_CMPR2_TEA_INT_RAW_V 0x00000001U -#define MCPWM_CMPR2_TEA_INT_RAW_S 17 -/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 0 TEB event - */ -#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_RAW_M (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S) -#define MCPWM_CMPR0_TEB_INT_RAW_V 0x00000001U -#define MCPWM_CMPR0_TEB_INT_RAW_S 18 -/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 1 TEB event - */ -#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_RAW_M (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S) -#define MCPWM_CMPR1_TEB_INT_RAW_V 0x00000001U -#define MCPWM_CMPR1_TEB_INT_RAW_S 19 -/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 2 TEB event - */ -#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_RAW_M (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S) -#define MCPWM_CMPR2_TEB_INT_RAW_V 0x00000001U -#define MCPWM_CMPR2_TEB_INT_RAW_S 20 -/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM0. - */ -#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) -#define MCPWM_TZ0_CBC_INT_RAW_M (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S) -#define MCPWM_TZ0_CBC_INT_RAW_V 0x00000001U -#define MCPWM_TZ0_CBC_INT_RAW_S 21 -/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM1. - */ -#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) -#define MCPWM_TZ1_CBC_INT_RAW_M (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S) -#define MCPWM_TZ1_CBC_INT_RAW_V 0x00000001U -#define MCPWM_TZ1_CBC_INT_RAW_S 22 -/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM2. - */ -#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) -#define MCPWM_TZ2_CBC_INT_RAW_M (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S) -#define MCPWM_TZ2_CBC_INT_RAW_V 0x00000001U -#define MCPWM_TZ2_CBC_INT_RAW_S 23 -/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM0. - */ -#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) -#define MCPWM_TZ0_OST_INT_RAW_M (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S) -#define MCPWM_TZ0_OST_INT_RAW_V 0x00000001U -#define MCPWM_TZ0_OST_INT_RAW_S 24 -/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM1. - */ -#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) -#define MCPWM_TZ1_OST_INT_RAW_M (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S) -#define MCPWM_TZ1_OST_INT_RAW_V 0x00000001U -#define MCPWM_TZ1_OST_INT_RAW_S 25 -/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM2. - */ -#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) -#define MCPWM_TZ2_OST_INT_RAW_M (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S) -#define MCPWM_TZ2_OST_INT_RAW_V 0x00000001U -#define MCPWM_TZ2_OST_INT_RAW_S 26 -/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP0. - */ -#define MCPWM_CAP0_INT_RAW (BIT(27)) -#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) -#define MCPWM_CAP0_INT_RAW_V 0x00000001U -#define MCPWM_CAP0_INT_RAW_S 27 -/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP1. - */ -#define MCPWM_CAP1_INT_RAW (BIT(28)) -#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) -#define MCPWM_CAP1_INT_RAW_V 0x00000001U -#define MCPWM_CAP1_INT_RAW_S 28 -/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP2. - */ -#define MCPWM_CAP2_INT_RAW (BIT(29)) -#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) -#define MCPWM_CAP2_INT_RAW_V 0x00000001U -#define MCPWM_CAP2_INT_RAW_S 29 - -/** MCPWM_INT_ST_REG register - * Interrupt masked status register - */ -#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118) -/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 0 stops. - */ -#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) -#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U -#define MCPWM_TIMER0_STOP_INT_ST_S 0 -/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 1 stops. - */ -#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) -#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U -#define MCPWM_TIMER1_STOP_INT_ST_S 1 -/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 2 stops. - */ -#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) -#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U -#define MCPWM_TIMER2_STOP_INT_ST_S 2 -/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 0 TEZ event. - */ -#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) -#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U -#define MCPWM_TIMER0_TEZ_INT_ST_S 3 -/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 1 TEZ event. - */ -#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) -#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U -#define MCPWM_TIMER1_TEZ_INT_ST_S 4 -/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 2 TEZ event. - */ -#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) -#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U -#define MCPWM_TIMER2_TEZ_INT_ST_S 5 -/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 0 TEP event. - */ -#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) -#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U -#define MCPWM_TIMER0_TEP_INT_ST_S 6 -/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 1 TEP event. - */ -#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) -#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U -#define MCPWM_TIMER1_TEP_INT_ST_S 7 -/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 2 TEP event. - */ -#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) -#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U -#define MCPWM_TIMER2_TEP_INT_ST_S 8 -/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f0 starts. - */ -#define MCPWM_FAULT0_INT_ST (BIT(9)) -#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) -#define MCPWM_FAULT0_INT_ST_V 0x00000001U -#define MCPWM_FAULT0_INT_ST_S 9 -/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f1 starts. - */ -#define MCPWM_FAULT1_INT_ST (BIT(10)) -#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) -#define MCPWM_FAULT1_INT_ST_V 0x00000001U -#define MCPWM_FAULT1_INT_ST_S 10 -/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f2 starts. - */ -#define MCPWM_FAULT2_INT_ST (BIT(11)) -#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) -#define MCPWM_FAULT2_INT_ST_V 0x00000001U -#define MCPWM_FAULT2_INT_ST_S 11 -/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f0 clears. - */ -#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) -#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U -#define MCPWM_FAULT0_CLR_INT_ST_S 12 -/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f1 clears. - */ -#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) -#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U -#define MCPWM_FAULT1_CLR_INT_ST_S 13 -/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f2 clears. - */ -#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) -#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U -#define MCPWM_FAULT2_CLR_INT_ST_S 14 -/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 0 TEA event - */ -#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ST_M (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S) -#define MCPWM_CMPR0_TEA_INT_ST_V 0x00000001U -#define MCPWM_CMPR0_TEA_INT_ST_S 15 -/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 1 TEA event - */ -#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ST_M (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S) -#define MCPWM_CMPR1_TEA_INT_ST_V 0x00000001U -#define MCPWM_CMPR1_TEA_INT_ST_S 16 -/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 2 TEA event - */ -#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ST_M (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S) -#define MCPWM_CMPR2_TEA_INT_ST_V 0x00000001U -#define MCPWM_CMPR2_TEA_INT_ST_S 17 -/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 0 TEB event - */ -#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ST_M (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S) -#define MCPWM_CMPR0_TEB_INT_ST_V 0x00000001U -#define MCPWM_CMPR0_TEB_INT_ST_S 18 -/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 1 TEB event - */ -#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ST_M (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S) -#define MCPWM_CMPR1_TEB_INT_ST_V 0x00000001U -#define MCPWM_CMPR1_TEB_INT_ST_S 19 -/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 2 TEB event - */ -#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ST_M (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S) -#define MCPWM_CMPR2_TEB_INT_ST_V 0x00000001U -#define MCPWM_CMPR2_TEB_INT_ST_S 20 -/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM0. - */ -#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ST_M (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S) -#define MCPWM_TZ0_CBC_INT_ST_V 0x00000001U -#define MCPWM_TZ0_CBC_INT_ST_S 21 -/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM1. - */ -#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ST_M (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S) -#define MCPWM_TZ1_CBC_INT_ST_V 0x00000001U -#define MCPWM_TZ1_CBC_INT_ST_S 22 -/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM2. - */ -#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ST_M (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S) -#define MCPWM_TZ2_CBC_INT_ST_V 0x00000001U -#define MCPWM_TZ2_CBC_INT_ST_S 23 -/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM0. - */ -#define MCPWM_TZ0_OST_INT_ST (BIT(24)) -#define MCPWM_TZ0_OST_INT_ST_M (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S) -#define MCPWM_TZ0_OST_INT_ST_V 0x00000001U -#define MCPWM_TZ0_OST_INT_ST_S 24 -/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM1. - */ -#define MCPWM_TZ1_OST_INT_ST (BIT(25)) -#define MCPWM_TZ1_OST_INT_ST_M (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S) -#define MCPWM_TZ1_OST_INT_ST_V 0x00000001U -#define MCPWM_TZ1_OST_INT_ST_S 25 -/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM2. - */ -#define MCPWM_TZ2_OST_INT_ST (BIT(26)) -#define MCPWM_TZ2_OST_INT_ST_M (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S) -#define MCPWM_TZ2_OST_INT_ST_V 0x00000001U -#define MCPWM_TZ2_OST_INT_ST_S 26 -/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP0. - */ -#define MCPWM_CAP0_INT_ST (BIT(27)) -#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) -#define MCPWM_CAP0_INT_ST_V 0x00000001U -#define MCPWM_CAP0_INT_ST_S 27 -/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP1. - */ -#define MCPWM_CAP1_INT_ST (BIT(28)) -#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) -#define MCPWM_CAP1_INT_ST_V 0x00000001U -#define MCPWM_CAP1_INT_ST_S 28 -/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP2. - */ -#define MCPWM_CAP2_INT_ST (BIT(29)) -#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) -#define MCPWM_CAP2_INT_ST_V 0x00000001U -#define MCPWM_CAP2_INT_ST_S 29 - -/** MCPWM_INT_CLR_REG register - * Interrupt clear register - */ -#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c) -/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. - */ -#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) -#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U -#define MCPWM_TIMER0_STOP_INT_CLR_S 0 -/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. - */ -#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) -#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U -#define MCPWM_TIMER1_STOP_INT_CLR_S 1 -/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. - */ -#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) -#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U -#define MCPWM_TIMER2_STOP_INT_CLR_S 2 -/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. - */ -#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) -#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U -#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 -/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. - */ -#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) -#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U -#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 -/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. - */ -#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) -#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U -#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 -/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. - */ -#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) -#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U -#define MCPWM_TIMER0_TEP_INT_CLR_S 6 -/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. - */ -#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) -#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U -#define MCPWM_TIMER1_TEP_INT_CLR_S 7 -/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. - */ -#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) -#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U -#define MCPWM_TIMER2_TEP_INT_CLR_S 8 -/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. - */ -#define MCPWM_FAULT0_INT_CLR (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) -#define MCPWM_FAULT0_INT_CLR_V 0x00000001U -#define MCPWM_FAULT0_INT_CLR_S 9 -/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. - */ -#define MCPWM_FAULT1_INT_CLR (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) -#define MCPWM_FAULT1_INT_CLR_V 0x00000001U -#define MCPWM_FAULT1_INT_CLR_S 10 -/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. - */ -#define MCPWM_FAULT2_INT_CLR (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) -#define MCPWM_FAULT2_INT_CLR_V 0x00000001U -#define MCPWM_FAULT2_INT_CLR_S 11 -/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. - */ -#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) -#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U -#define MCPWM_FAULT0_CLR_INT_CLR_S 12 -/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. - */ -#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) -#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U -#define MCPWM_FAULT1_CLR_INT_CLR_S 13 -/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. - */ -#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) -#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U -#define MCPWM_FAULT2_CLR_INT_CLR_S 14 -/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event - */ -#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_CLR_M (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S) -#define MCPWM_CMPR0_TEA_INT_CLR_V 0x00000001U -#define MCPWM_CMPR0_TEA_INT_CLR_S 15 -/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event - */ -#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_CLR_M (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S) -#define MCPWM_CMPR1_TEA_INT_CLR_V 0x00000001U -#define MCPWM_CMPR1_TEA_INT_CLR_S 16 -/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event - */ -#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_CLR_M (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S) -#define MCPWM_CMPR2_TEA_INT_CLR_V 0x00000001U -#define MCPWM_CMPR2_TEA_INT_CLR_S 17 -/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event - */ -#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_CLR_M (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S) -#define MCPWM_CMPR0_TEB_INT_CLR_V 0x00000001U -#define MCPWM_CMPR0_TEB_INT_CLR_S 18 -/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event - */ -#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_CLR_M (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S) -#define MCPWM_CMPR1_TEB_INT_CLR_V 0x00000001U -#define MCPWM_CMPR1_TEB_INT_CLR_S 19 -/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event - */ -#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_CLR_M (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S) -#define MCPWM_CMPR2_TEB_INT_CLR_V 0x00000001U -#define MCPWM_CMPR2_TEB_INT_CLR_S 20 -/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM0. - */ -#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) -#define MCPWM_TZ0_CBC_INT_CLR_M (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S) -#define MCPWM_TZ0_CBC_INT_CLR_V 0x00000001U -#define MCPWM_TZ0_CBC_INT_CLR_S 21 -/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM1. - */ -#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) -#define MCPWM_TZ1_CBC_INT_CLR_M (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S) -#define MCPWM_TZ1_CBC_INT_CLR_V 0x00000001U -#define MCPWM_TZ1_CBC_INT_CLR_S 22 -/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM2. - */ -#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) -#define MCPWM_TZ2_CBC_INT_CLR_M (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S) -#define MCPWM_TZ2_CBC_INT_CLR_V 0x00000001U -#define MCPWM_TZ2_CBC_INT_CLR_S 23 -/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM0. - */ -#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) -#define MCPWM_TZ0_OST_INT_CLR_M (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S) -#define MCPWM_TZ0_OST_INT_CLR_V 0x00000001U -#define MCPWM_TZ0_OST_INT_CLR_S 24 -/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM1. - */ -#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) -#define MCPWM_TZ1_OST_INT_CLR_M (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S) -#define MCPWM_TZ1_OST_INT_CLR_V 0x00000001U -#define MCPWM_TZ1_OST_INT_CLR_S 25 -/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM2. - */ -#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) -#define MCPWM_TZ2_OST_INT_CLR_M (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S) -#define MCPWM_TZ2_OST_INT_CLR_V 0x00000001U -#define MCPWM_TZ2_OST_INT_CLR_S 26 -/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. - */ -#define MCPWM_CAP0_INT_CLR (BIT(27)) -#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) -#define MCPWM_CAP0_INT_CLR_V 0x00000001U -#define MCPWM_CAP0_INT_CLR_S 27 -/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. - */ -#define MCPWM_CAP1_INT_CLR (BIT(28)) -#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) -#define MCPWM_CAP1_INT_CLR_V 0x00000001U -#define MCPWM_CAP1_INT_CLR_S 28 -/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. - */ -#define MCPWM_CAP2_INT_CLR (BIT(29)) -#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) -#define MCPWM_CAP2_INT_CLR_V 0x00000001U -#define MCPWM_CAP2_INT_CLR_S 29 - -/** MCPWM_EVT_EN_REG register - * Event enable register - */ -#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120) -/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_TIMER0_STOP_EN (BIT(0)) -#define MCPWM_EVT_TIMER0_STOP_EN_M (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S) -#define MCPWM_EVT_TIMER0_STOP_EN_V 0x00000001U -#define MCPWM_EVT_TIMER0_STOP_EN_S 0 -/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_TIMER1_STOP_EN (BIT(1)) -#define MCPWM_EVT_TIMER1_STOP_EN_M (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S) -#define MCPWM_EVT_TIMER1_STOP_EN_V 0x00000001U -#define MCPWM_EVT_TIMER1_STOP_EN_S 1 -/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_TIMER2_STOP_EN (BIT(2)) -#define MCPWM_EVT_TIMER2_STOP_EN_M (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S) -#define MCPWM_EVT_TIMER2_STOP_EN_V 0x00000001U -#define MCPWM_EVT_TIMER2_STOP_EN_S 2 -/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable timer0 equal zero event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TIMER0_TEZ_EN (BIT(3)) -#define MCPWM_EVT_TIMER0_TEZ_EN_M (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S) -#define MCPWM_EVT_TIMER0_TEZ_EN_V 0x00000001U -#define MCPWM_EVT_TIMER0_TEZ_EN_S 3 -/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable timer1 equal zero event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TIMER1_TEZ_EN (BIT(4)) -#define MCPWM_EVT_TIMER1_TEZ_EN_M (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S) -#define MCPWM_EVT_TIMER1_TEZ_EN_V 0x00000001U -#define MCPWM_EVT_TIMER1_TEZ_EN_S 4 -/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable timer2 equal zero event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TIMER2_TEZ_EN (BIT(5)) -#define MCPWM_EVT_TIMER2_TEZ_EN_M (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S) -#define MCPWM_EVT_TIMER2_TEZ_EN_V 0x00000001U -#define MCPWM_EVT_TIMER2_TEZ_EN_S 5 -/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable timer0 equal period event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TIMER0_TEP_EN (BIT(6)) -#define MCPWM_EVT_TIMER0_TEP_EN_M (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S) -#define MCPWM_EVT_TIMER0_TEP_EN_V 0x00000001U -#define MCPWM_EVT_TIMER0_TEP_EN_S 6 -/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable timer1 equal period event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TIMER1_TEP_EN (BIT(7)) -#define MCPWM_EVT_TIMER1_TEP_EN_M (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S) -#define MCPWM_EVT_TIMER1_TEP_EN_V 0x00000001U -#define MCPWM_EVT_TIMER1_TEP_EN_S 7 -/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable timer2 equal period event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TIMER2_TEP_EN (BIT(8)) -#define MCPWM_EVT_TIMER2_TEP_EN_M (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S) -#define MCPWM_EVT_TIMER2_TEP_EN_V 0x00000001U -#define MCPWM_EVT_TIMER2_TEP_EN_S 8 -/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal a event - * generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP0_TEA_EN (BIT(9)) -#define MCPWM_EVT_OP0_TEA_EN_M (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S) -#define MCPWM_EVT_OP0_TEA_EN_V 0x00000001U -#define MCPWM_EVT_OP0_TEA_EN_S 9 -/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal a event - * generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP1_TEA_EN (BIT(10)) -#define MCPWM_EVT_OP1_TEA_EN_M (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S) -#define MCPWM_EVT_OP1_TEA_EN_V 0x00000001U -#define MCPWM_EVT_OP1_TEA_EN_S 10 -/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal a event - * generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP2_TEA_EN (BIT(11)) -#define MCPWM_EVT_OP2_TEA_EN_M (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S) -#define MCPWM_EVT_OP2_TEA_EN_V 0x00000001U -#define MCPWM_EVT_OP2_TEA_EN_S 11 -/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal b event - * generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP0_TEB_EN (BIT(12)) -#define MCPWM_EVT_OP0_TEB_EN_M (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S) -#define MCPWM_EVT_OP0_TEB_EN_V 0x00000001U -#define MCPWM_EVT_OP0_TEB_EN_S 12 -/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal b event - * generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP1_TEB_EN (BIT(13)) -#define MCPWM_EVT_OP1_TEB_EN_M (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S) -#define MCPWM_EVT_OP1_TEB_EN_V 0x00000001U -#define MCPWM_EVT_OP1_TEB_EN_S 13 -/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal b event - * generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP2_TEB_EN (BIT(14)) -#define MCPWM_EVT_OP2_TEB_EN_M (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S) -#define MCPWM_EVT_OP2_TEB_EN_V 0x00000001U -#define MCPWM_EVT_OP2_TEB_EN_S 14 -/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_F0_EN (BIT(15)) -#define MCPWM_EVT_F0_EN_M (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S) -#define MCPWM_EVT_F0_EN_V 0x00000001U -#define MCPWM_EVT_F0_EN_S 15 -/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_F1_EN (BIT(16)) -#define MCPWM_EVT_F1_EN_M (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S) -#define MCPWM_EVT_F1_EN_V 0x00000001U -#define MCPWM_EVT_F1_EN_S 16 -/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_F2_EN (BIT(17)) -#define MCPWM_EVT_F2_EN_M (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S) -#define MCPWM_EVT_F2_EN_V 0x00000001U -#define MCPWM_EVT_F2_EN_S 17 -/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_F0_CLR_EN (BIT(18)) -#define MCPWM_EVT_F0_CLR_EN_M (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S) -#define MCPWM_EVT_F0_CLR_EN_V 0x00000001U -#define MCPWM_EVT_F0_CLR_EN_S 18 -/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_F1_CLR_EN (BIT(19)) -#define MCPWM_EVT_F1_CLR_EN_M (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S) -#define MCPWM_EVT_F1_CLR_EN_V 0x00000001U -#define MCPWM_EVT_F1_CLR_EN_S 19 -/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_F2_CLR_EN (BIT(20)) -#define MCPWM_EVT_F2_CLR_EN_M (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S) -#define MCPWM_EVT_F2_CLR_EN_V 0x00000001U -#define MCPWM_EVT_F2_CLR_EN_S 20 -/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TZ0_CBC_EN (BIT(21)) -#define MCPWM_EVT_TZ0_CBC_EN_M (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S) -#define MCPWM_EVT_TZ0_CBC_EN_V 0x00000001U -#define MCPWM_EVT_TZ0_CBC_EN_S 21 -/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TZ1_CBC_EN (BIT(22)) -#define MCPWM_EVT_TZ1_CBC_EN_M (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S) -#define MCPWM_EVT_TZ1_CBC_EN_V 0x00000001U -#define MCPWM_EVT_TZ1_CBC_EN_S 22 -/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: - * Disable\\1: Enable - */ -#define MCPWM_EVT_TZ2_CBC_EN (BIT(23)) -#define MCPWM_EVT_TZ2_CBC_EN_M (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S) -#define MCPWM_EVT_TZ2_CBC_EN_V 0x00000001U -#define MCPWM_EVT_TZ2_CBC_EN_S 23 -/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_TZ0_OST_EN (BIT(24)) -#define MCPWM_EVT_TZ0_OST_EN_M (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S) -#define MCPWM_EVT_TZ0_OST_EN_V 0x00000001U -#define MCPWM_EVT_TZ0_OST_EN_S 24 -/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_TZ1_OST_EN (BIT(25)) -#define MCPWM_EVT_TZ1_OST_EN_M (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S) -#define MCPWM_EVT_TZ1_OST_EN_V 0x00000001U -#define MCPWM_EVT_TZ1_OST_EN_S 25 -/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: - * Enable - */ -#define MCPWM_EVT_TZ2_OST_EN (BIT(26)) -#define MCPWM_EVT_TZ2_OST_EN_M (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S) -#define MCPWM_EVT_TZ2_OST_EN_V 0x00000001U -#define MCPWM_EVT_TZ2_OST_EN_S 26 -/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_CAP0_EN (BIT(27)) -#define MCPWM_EVT_CAP0_EN_M (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S) -#define MCPWM_EVT_CAP0_EN_V 0x00000001U -#define MCPWM_EVT_CAP0_EN_S 27 -/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_CAP1_EN (BIT(28)) -#define MCPWM_EVT_CAP1_EN_M (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S) -#define MCPWM_EVT_CAP1_EN_V 0x00000001U -#define MCPWM_EVT_CAP1_EN_S 28 -/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_CAP2_EN (BIT(29)) -#define MCPWM_EVT_CAP2_EN_M (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S) -#define MCPWM_EVT_CAP2_EN_V 0x00000001U -#define MCPWM_EVT_CAP2_EN_S 29 - -/** MCPWM_TASK_EN_REG register - * Task enable register - */ -#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124) -/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable PWM generator0 timer stamp A's shadow register - * update task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CMPR0_A_UP_EN (BIT(0)) -#define MCPWM_TASK_CMPR0_A_UP_EN_M (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S) -#define MCPWM_TASK_CMPR0_A_UP_EN_V 0x00000001U -#define MCPWM_TASK_CMPR0_A_UP_EN_S 0 -/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable PWM generator1 timer stamp A's shadow register - * update task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CMPR1_A_UP_EN (BIT(1)) -#define MCPWM_TASK_CMPR1_A_UP_EN_M (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S) -#define MCPWM_TASK_CMPR1_A_UP_EN_V 0x00000001U -#define MCPWM_TASK_CMPR1_A_UP_EN_S 1 -/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable PWM generator2 timer stamp A's shadow register - * update task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CMPR2_A_UP_EN (BIT(2)) -#define MCPWM_TASK_CMPR2_A_UP_EN_M (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S) -#define MCPWM_TASK_CMPR2_A_UP_EN_V 0x00000001U -#define MCPWM_TASK_CMPR2_A_UP_EN_S 2 -/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable PWM generator0 timer stamp B's shadow register - * update task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CMPR0_B_UP_EN (BIT(3)) -#define MCPWM_TASK_CMPR0_B_UP_EN_M (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S) -#define MCPWM_TASK_CMPR0_B_UP_EN_V 0x00000001U -#define MCPWM_TASK_CMPR0_B_UP_EN_S 3 -/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable PWM generator1 timer stamp B's shadow register - * update task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CMPR1_B_UP_EN (BIT(4)) -#define MCPWM_TASK_CMPR1_B_UP_EN_M (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S) -#define MCPWM_TASK_CMPR1_B_UP_EN_V 0x00000001U -#define MCPWM_TASK_CMPR1_B_UP_EN_S 4 -/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable PWM generator2 timer stamp B's shadow register - * update task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CMPR2_B_UP_EN (BIT(5)) -#define MCPWM_TASK_CMPR2_B_UP_EN_M (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S) -#define MCPWM_TASK_CMPR2_B_UP_EN_V 0x00000001U -#define MCPWM_TASK_CMPR2_B_UP_EN_S 5 -/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable all PWM generate stop task receive.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TASK_GEN_STOP_EN (BIT(6)) -#define MCPWM_TASK_GEN_STOP_EN_M (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S) -#define MCPWM_TASK_GEN_STOP_EN_V 0x00000001U -#define MCPWM_TASK_GEN_STOP_EN_S 6 -/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_TIMER0_SYNC_EN (BIT(7)) -#define MCPWM_TASK_TIMER0_SYNC_EN_M (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S) -#define MCPWM_TASK_TIMER0_SYNC_EN_V 0x00000001U -#define MCPWM_TASK_TIMER0_SYNC_EN_S 7 -/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_TIMER1_SYNC_EN (BIT(8)) -#define MCPWM_TASK_TIMER1_SYNC_EN_M (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S) -#define MCPWM_TASK_TIMER1_SYNC_EN_V 0x00000001U -#define MCPWM_TASK_TIMER1_SYNC_EN_S 8 -/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_TIMER2_SYNC_EN (BIT(9)) -#define MCPWM_TASK_TIMER2_SYNC_EN_M (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S) -#define MCPWM_TASK_TIMER2_SYNC_EN_V 0x00000001U -#define MCPWM_TASK_TIMER2_SYNC_EN_S 9 -/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable timer0 period update task receive.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TASK_TIMER0_PERIOD_UP_EN (BIT(10)) -#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S) -#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V 0x00000001U -#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S 10 -/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable timer1 period update task receive.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TASK_TIMER1_PERIOD_UP_EN (BIT(11)) -#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S) -#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V 0x00000001U -#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S 11 -/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable timer2 period update task receive.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TASK_TIMER2_PERIOD_UP_EN (BIT(12)) -#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S) -#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V 0x00000001U -#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S 12 -/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: - * Enable - */ -#define MCPWM_TASK_TZ0_OST_EN (BIT(13)) -#define MCPWM_TASK_TZ0_OST_EN_M (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S) -#define MCPWM_TASK_TZ0_OST_EN_V 0x00000001U -#define MCPWM_TASK_TZ0_OST_EN_S 13 -/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: - * Enable - */ -#define MCPWM_TASK_TZ1_OST_EN (BIT(14)) -#define MCPWM_TASK_TZ1_OST_EN_M (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S) -#define MCPWM_TASK_TZ1_OST_EN_V 0x00000001U -#define MCPWM_TASK_TZ1_OST_EN_S 14 -/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: - * Enable - */ -#define MCPWM_TASK_TZ2_OST_EN (BIT(15)) -#define MCPWM_TASK_TZ2_OST_EN_M (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S) -#define MCPWM_TASK_TZ2_OST_EN_V 0x00000001U -#define MCPWM_TASK_TZ2_OST_EN_S 15 -/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable one shot trip0 clear task receive.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TASK_CLR0_OST_EN (BIT(16)) -#define MCPWM_TASK_CLR0_OST_EN_M (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S) -#define MCPWM_TASK_CLR0_OST_EN_V 0x00000001U -#define MCPWM_TASK_CLR0_OST_EN_S 16 -/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable one shot trip1 clear task receive.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TASK_CLR1_OST_EN (BIT(17)) -#define MCPWM_TASK_CLR1_OST_EN_M (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S) -#define MCPWM_TASK_CLR1_OST_EN_V 0x00000001U -#define MCPWM_TASK_CLR1_OST_EN_S 17 -/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable one shot trip2 clear task receive.\\0: - * Disable\\1: Enable - */ -#define MCPWM_TASK_CLR2_OST_EN (BIT(18)) -#define MCPWM_TASK_CLR2_OST_EN_M (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S) -#define MCPWM_TASK_CLR2_OST_EN_V 0x00000001U -#define MCPWM_TASK_CLR2_OST_EN_S 18 -/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CAP0_EN (BIT(19)) -#define MCPWM_TASK_CAP0_EN_M (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S) -#define MCPWM_TASK_CAP0_EN_V 0x00000001U -#define MCPWM_TASK_CAP0_EN_S 19 -/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CAP1_EN (BIT(20)) -#define MCPWM_TASK_CAP1_EN_M (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S) -#define MCPWM_TASK_CAP1_EN_V 0x00000001U -#define MCPWM_TASK_CAP1_EN_S 20 -/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable - */ -#define MCPWM_TASK_CAP2_EN (BIT(21)) -#define MCPWM_TASK_CAP2_EN_M (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S) -#define MCPWM_TASK_CAP2_EN_V 0x00000001U -#define MCPWM_TASK_CAP2_EN_S 21 - -/** MCPWM_EVT_EN2_REG register - * Event enable register2 - */ -#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x128) -/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG - * event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP0_TEE1_EN (BIT(0)) -#define MCPWM_EVT_OP0_TEE1_EN_M (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S) -#define MCPWM_EVT_OP0_TEE1_EN_V 0x00000001U -#define MCPWM_EVT_OP0_TEE1_EN_S 0 -/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG - * event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP1_TEE1_EN (BIT(1)) -#define MCPWM_EVT_OP1_TEE1_EN_M (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S) -#define MCPWM_EVT_OP1_TEE1_EN_V 0x00000001U -#define MCPWM_EVT_OP1_TEE1_EN_S 1 -/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG - * event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP2_TEE1_EN (BIT(2)) -#define MCPWM_EVT_OP2_TEE1_EN_M (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S) -#define MCPWM_EVT_OP2_TEE1_EN_V 0x00000001U -#define MCPWM_EVT_OP2_TEE1_EN_S 2 -/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG - * event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP0_TEE2_EN (BIT(3)) -#define MCPWM_EVT_OP0_TEE2_EN_M (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S) -#define MCPWM_EVT_OP0_TEE2_EN_V 0x00000001U -#define MCPWM_EVT_OP0_TEE2_EN_S 3 -/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG - * event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP1_TEE2_EN (BIT(4)) -#define MCPWM_EVT_OP1_TEE2_EN_M (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S) -#define MCPWM_EVT_OP1_TEE2_EN_V 0x00000001U -#define MCPWM_EVT_OP1_TEE2_EN_S 4 -/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG - * event generate.\\0: Disable\\1: Enable - */ -#define MCPWM_EVT_OP2_TEE2_EN (BIT(5)) -#define MCPWM_EVT_OP2_TEE2_EN_M (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S) -#define MCPWM_EVT_OP2_TEE2_EN_V 0x00000001U -#define MCPWM_EVT_OP2_TEE2_EN_S 5 - -/** MCPWM_OP0_TSTMP_E1_REG register - * Generator0 timer stamp E1 value register - */ -#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x12c) -/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; - * Configures generator0 timer stamp E1 value register - */ -#define MCPWM_OP0_TSTMP_E1 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E1_M (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S) -#define MCPWM_OP0_TSTMP_E1_V 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E1_S 0 - -/** MCPWM_OP0_TSTMP_E2_REG register - * Generator$n timer stamp E2 value register - */ -#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x130) -/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; - * Configures generator$n timer stamp E2 value register - */ -#define MCPWM_OP0_TSTMP_E2 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E2_M (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S) -#define MCPWM_OP0_TSTMP_E2_V 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E2_S 0 - -/** MCPWM_OP1_TSTMP_E1_REG register - * Generator1 timer stamp E1 value register - */ -#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x134) -/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; - * Configures generator1 timer stamp E1 value register - */ -#define MCPWM_OP0_TSTMP_E1 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E1_M (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S) -#define MCPWM_OP0_TSTMP_E1_V 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E1_S 0 - -/** MCPWM_OP1_TSTMP_E2_REG register - * Generator$n timer stamp E2 value register - */ -#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x138) -/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; - * Configures generator$n timer stamp E2 value register - */ -#define MCPWM_OP1_TSTMP_E2 0x0000FFFFU -#define MCPWM_OP1_TSTMP_E2_M (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S) -#define MCPWM_OP1_TSTMP_E2_V 0x0000FFFFU -#define MCPWM_OP1_TSTMP_E2_S 0 - -/** MCPWM_OP2_TSTMP_E1_REG register - * Generator2 timer stamp E1 value register - */ -#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x13c) -/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; - * Configures generator2 timer stamp E1 value register - */ -#define MCPWM_OP0_TSTMP_E1 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E1_M (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S) -#define MCPWM_OP0_TSTMP_E1_V 0x0000FFFFU -#define MCPWM_OP0_TSTMP_E1_S 0 - -/** MCPWM_OP2_TSTMP_E2_REG register - * Generator$n timer stamp E2 value register - */ -#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x140) -/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; - * Configures generator$n timer stamp E2 value register - */ -#define MCPWM_OP2_TSTMP_E2 0x0000FFFFU -#define MCPWM_OP2_TSTMP_E2_M (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S) -#define MCPWM_OP2_TSTMP_E2_V 0x0000FFFFU -#define MCPWM_OP2_TSTMP_E2_S 0 - -/** MCPWM_CLK_REG register - * Global configuration register - */ -#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x144) -/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register - */ -#define MCPWM_CLK_EN (BIT(0)) -#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) -#define MCPWM_CLK_EN_V 0x00000001U -#define MCPWM_CLK_EN_S 0 - -/** MCPWM_VERSION_REG register - * Version register. - */ -#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x148) -/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968; - * Configures the version. - */ -#define MCPWM_DATE 0x0FFFFFFFU -#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) -#define MCPWM_DATE_V 0x0FFFFFFFU -#define MCPWM_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/pwm_struct.h b/components/soc/esp32p4/include/soc/pwm_struct.h deleted file mode 100644 index f48bd4cf69..0000000000 --- a/components/soc/esp32p4/include/soc/pwm_struct.h +++ /dev/null @@ -1,2166 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: clk_cfg */ -/** Type of clk_cfg register - * PWM clock prescaler register. - */ -typedef union { - struct { - /** clk_prescale : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * - * (PWM_CLK_PRESCALE + 1). - */ - uint32_t clk_prescale:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} mcpwm_clk_cfg_reg_t; - - -/** Group: timer */ -/** Type of timern_cfg0 register - * PWM timern period and update method configuration register. - */ -typedef union { - struct { - /** timer0_prescale : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of timern, so that the period of PT0_clk = Period of - * PWM_clk * (PWM_TIMERn_PRESCALE + 1) - */ - uint32_t timer0_prescale:8; - /** timer0_period : R/W; bitpos: [23:8]; default: 255; - * Configures the period shadow of PWM timern - */ - uint32_t timer0_period:16; - /** timer0_period_upmethod : R/W; bitpos: [25:24]; default: 0; - * Configures the update method for active register of PWM timern period.\\0: - * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal - * zero event - */ - uint32_t timer0_period_upmethod:2; - uint32_t reserved_26:6; - }; - uint32_t val; -} mcpwm_timer_cfg0_reg_t; - -/** Type of timer0_cfg1 register - * PWM timer$n working mode and start/stop control register. - */ -typedef union { - struct { - /** timer0_start : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ - uint32_t timer0_start:3; - /** timer0_mod : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ - uint32_t timer0_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timer_cfg1_reg_t; - -/** Type of timer0_sync register - * PWM timer$n sync function configuration register. - */ -typedef union { - struct { - /** timer0_synci_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ - uint32_t timer0_synci_en:1; - /** timer0_sync_sw : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ - uint32_t timer0_sync_sw:1; - /** timer0_synco_sel : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ - uint32_t timer0_synco_sel:2; - /** timer0_phase : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ - uint32_t timer0_phase:16; - /** timer0_phase_direction : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ - uint32_t timer0_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timer_sync_reg_t; - -/** Type of timer0_status register - * PWM timer$n status register. - */ -typedef union { - struct { - /** timer0_value : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ - uint32_t timer0_value:16; - /** timer0_direction : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ - uint32_t timer0_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timer_status_reg_t; - -/** Type of timer1_cfg1 register - * PWM timer$n working mode and start/stop control register. - */ -typedef union { - struct { - /** timer1_start : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ - uint32_t timer1_start:3; - /** timer1_mod : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ - uint32_t timer1_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timer1_cfg1_reg_t; - -/** Type of timer1_sync register - * PWM timer$n sync function configuration register. - */ -typedef union { - struct { - /** timer1_synci_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ - uint32_t timer1_synci_en:1; - /** timer1_sync_sw : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ - uint32_t timer1_sync_sw:1; - /** timer1_synco_sel : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ - uint32_t timer1_synco_sel:2; - /** timer1_phase : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ - uint32_t timer1_phase:16; - /** timer1_phase_direction : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ - uint32_t timer1_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timer1_sync_reg_t; - -/** Type of timer1_status register - * PWM timer$n status register. - */ -typedef union { - struct { - /** timer1_value : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ - uint32_t timer1_value:16; - /** timer1_direction : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ - uint32_t timer1_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timer1_status_reg_t; - -/** Type of timer2_cfg1 register - * PWM timer$n working mode and start/stop control register. - */ -typedef union { - struct { - /** timer2_start : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ - uint32_t timer2_start:3; - /** timer2_mod : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ - uint32_t timer2_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timer2_cfg1_reg_t; - -/** Type of timer2_sync register - * PWM timer$n sync function configuration register. - */ -typedef union { - struct { - /** timer2_synci_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ - uint32_t timer2_synci_en:1; - /** timer2_sync_sw : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ - uint32_t timer2_sync_sw:1; - /** timer2_synco_sel : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ - uint32_t timer2_synco_sel:2; - /** timer2_phase : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ - uint32_t timer2_phase:16; - /** timer2_phase_direction : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ - uint32_t timer2_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timer2_sync_reg_t; - -/** Type of timer2_status register - * PWM timer$n status register. - */ -typedef union { - struct { - /** timer2_value : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ - uint32_t timer2_value:16; - /** timer2_direction : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ - uint32_t timer2_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timer2_status_reg_t; - - -/** Group: timer_synci_cfg */ -/** Type of timer_synci_cfg register - * Synchronization input selection register for PWM timers. - */ -typedef union { - struct { - /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; - * Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: - * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 - * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - */ - uint32_t timer0_syncisel:3; - /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; - * Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: - * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 - * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - */ - uint32_t timer1_syncisel:3; - /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; - * Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: - * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 - * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - */ - uint32_t timer2_syncisel:3; - /** external_synci0_invert : R/W; bitpos: [9]; default: 0; - * Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: - * Invert - */ - uint32_t external_synci0_invert:1; - /** external_synci1_invert : R/W; bitpos: [10]; default: 0; - * Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: - * Invert - */ - uint32_t external_synci1_invert:1; - /** external_synci2_invert : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: - * Invert - */ - uint32_t external_synci2_invert:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} mcpwm_timer_synci_cfg_reg_t; - - -/** Group: operator_timersel */ -/** Type of operator_timersel register - * PWM operator's timer select register - */ -typedef union { - struct { - /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator0.\\0: - * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - */ - uint32_t operator0_timersel:2; - /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator1.\\0: - * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - */ - uint32_t operator1_timersel:2; - /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator2.\\0: - * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - */ - uint32_t operator2_timersel:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} mcpwm_operator_timersel_reg_t; - - -/** Group: operators */ -/** Type of genn_stmp_cfg register - * Generatorn time stamp registers A and B transfer status and update method register - */ -typedef union { - struct { - /** cmpr0_a_upmethod : R/W; bitpos: [3:0]; default: 0; - * Configures the update method for PWM generator n time stamp A's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ - uint32_t cmpr0_a_upmethod:4; - /** cmpr0_b_upmethod : R/W; bitpos: [7:4]; default: 0; - * Configures the update method for PWM generator n time stamp B's active - * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is - * set to 1: Sync\\Bit3 is set to 1: Disable the update - */ - uint32_t cmpr0_b_upmethod:4; - /** cmpr0_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; - * Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0: - * A's active reg has been updated with shadow register latest value.\\1: A's shadow - * reg is filled and waiting to be transferred to A's active reg - */ - uint32_t cmpr0_a_shdw_full:1; - /** cmpr0_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; - * Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0: - * B's active reg has been updated with shadow register latest value.\\1: B's shadow - * reg is filled and waiting to be transferred to B's active reg - */ - uint32_t cmpr0_b_shdw_full:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_gen_stmp_cfg_reg_t; - -/** Type of gen0_tstmp_a register - * Generator$n time stamp A's shadow register - */ -typedef union { - struct { - /** cmpr0_a : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp A's shadow register. - */ - uint32_t cmpr0_a:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen_tstmp_a_reg_t; - -/** Type of gen0_tstmp_b register - * Generator$n time stamp B's shadow register - */ -typedef union { - struct { - /** cmpr0_b : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp B's shadow register. - */ - uint32_t cmpr0_b:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen_tstmp_b_reg_t; - -/** Type of gen0_cfg0 register - * Generator$n fault event T0 and T1 configuration register - */ -typedef union { - struct { - /** gen0_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; - * Configures update method for PWM generator $n's active register.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ - uint32_t gen0_cfg_upmethod:4; - /** gen0_t0_sel : R/W; bitpos: [6:4]; default: 0; - * Configures source selection for PWM generator $n event_t0, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ - uint32_t gen0_t0_sel:3; - /** gen0_t1_sel : R/W; bitpos: [9:7]; default: 0; - * Configures source selection for PWM generator $n event_t1, take effect - * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: - * Invalid, Select nothing - */ - uint32_t gen0_t1_sel:3; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_gen_cfg0_reg_t; - -/** Type of gen0_force register - * Generator$n output signal force mode register. - */ -typedef union { - struct { - /** gen0_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; - * Configures update method for continuous software force of PWM generator$n.\\0: - * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable - * update. TEA/B here and below means an event generated when the timer's value equals - * to that of register A/B. - */ - uint32_t gen0_cntuforce_upmethod:6; - /** gen0_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; - * Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ - uint32_t gen0_a_cntuforce_mode:2; - /** gen0_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; - * Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2: - * High\\3: Disabled - */ - uint32_t gen0_b_cntuforce_mode:2; - /** gen0_a_nciforce : R/W; bitpos: [10]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n A, a toggle will trigger a force event. - */ - uint32_t gen0_a_nciforce:1; - /** gen0_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n A.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ - uint32_t gen0_a_nciforce_mode:2; - /** gen0_b_nciforce : R/W; bitpos: [13]; default: 0; - * Configures the generation of non-continuous immediate software-force event for - * PWM$n B, a toggle will trigger a force event. - */ - uint32_t gen0_b_nciforce:1; - /** gen0_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; - * Configures non-continuous immediate software force mode for PWM$n B.\\0: - * Disabled\\1: Low\\2: High\\3: Disabled - */ - uint32_t gen0_b_nciforce_mode:2; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen_force_reg_t; - -/** Type of gen0_a register - * PWM$n output signal A actions configuration register - */ -typedef union { - struct { - /** gen0_a_utez : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_utez:2; - /** gen0_a_utep : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_utep:2; - /** gen0_a_utea : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_utea:2; - /** gen0_a_uteb : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_uteb:2; - /** gen0_a_ut0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_ut0:2; - /** gen0_a_ut1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_ut1:2; - /** gen0_a_dtez : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_dtez:2; - /** gen0_a_dtep : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_dtep:2; - /** gen0_a_dtea : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_dtea:2; - /** gen0_a_dteb : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_dteb:2; - /** gen0_a_dt0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_dt0:2; - /** gen0_a_dt1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_a_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen_a_reg_t; - -/** Type of gen0_b register - * PWM$n output signal B actions configuration register - */ -typedef union { - struct { - /** gen0_b_utez : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_utez:2; - /** gen0_b_utep : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_utep:2; - /** gen0_b_utea : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_utea:2; - /** gen0_b_uteb : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_uteb:2; - /** gen0_b_ut0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_ut0:2; - /** gen0_b_ut1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_ut1:2; - /** gen0_b_dtez : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dtez:2; - /** gen0_b_dtep : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dtep:2; - /** gen0_b_dtea : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dtea:2; - /** gen0_b_dteb : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dteb:2; - /** gen0_b_dt0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dt0:2; - /** gen0_b_dt1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen_b_reg_t; - -/** Type of dt0_cfg register - * Dead time configuration register - */ -typedef union { - struct { - /** db0_fed_upmethod : R/W; bitpos: [3:0]; default: 0; - * Configures update method for FED (Falling edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ - uint32_t db0_fed_upmethod:4; - /** db0_red_upmethod : R/W; bitpos: [7:4]; default: 0; - * Configures update method for RED (rising edge delay) active register.\\0: - * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: - * Sync\\Bit3 is set to 1: Disable the update - */ - uint32_t db0_red_upmethod:4; - /** db0_deb_mode : R/W; bitpos: [8]; default: 0; - * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path - * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode - */ - uint32_t db0_deb_mode:1; - /** db0_a_outswap : R/W; bitpos: [9]; default: 0; - * Configures S6 in table. - */ - uint32_t db0_a_outswap:1; - /** db0_b_outswap : R/W; bitpos: [10]; default: 0; - * Configures S7 in table. - */ - uint32_t db0_b_outswap:1; - /** db0_red_insel : R/W; bitpos: [11]; default: 0; - * Configures S4 in table. - */ - uint32_t db0_red_insel:1; - /** db0_fed_insel : R/W; bitpos: [12]; default: 0; - * Configures S5 in table. - */ - uint32_t db0_fed_insel:1; - /** db0_red_outinvert : R/W; bitpos: [13]; default: 0; - * Configures S2 in table. - */ - uint32_t db0_red_outinvert:1; - /** db0_fed_outinvert : R/W; bitpos: [14]; default: 0; - * Configures S3 in table. - */ - uint32_t db0_fed_outinvert:1; - /** db0_a_outbypass : R/W; bitpos: [15]; default: 1; - * Configures S1 in table. - */ - uint32_t db0_a_outbypass:1; - /** db0_b_outbypass : R/W; bitpos: [16]; default: 1; - * Configures S0 in table. - */ - uint32_t db0_b_outbypass:1; - /** db0_clk_sel : R/W; bitpos: [17]; default: 0; - * Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk - */ - uint32_t db0_clk_sel:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} mcpwm_dt_cfg_reg_t; - -/** Type of dt0_fed_cfg register - * Falling edge delay (FED) shadow register - */ -typedef union { - struct { - /** db0_fed : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for FED. - */ - uint32_t db0_fed:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dt_fed_cfg_reg_t; - -/** Type of dt0_red_cfg register - * Rising edge delay (RED) shadow register - */ -typedef union { - struct { - /** db0_red : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for RED. - */ - uint32_t db0_red:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dt_red_cfg_reg_t; - -/** Type of carrier0_cfg register - * Carrier$n configuration register - */ -typedef union { - struct { - /** chopper0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled - */ - uint32_t chopper0_en:1; - /** chopper0_prescale : R/W; bitpos: [4:1]; default: 0; - * Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of - * PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1) - */ - uint32_t chopper0_prescale:4; - /** chopper0_duty : R/W; bitpos: [7:5]; default: 0; - * Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8 - */ - uint32_t chopper0_duty:3; - /** chopper0_oshtwth : R/W; bitpos: [11:8]; default: 0; - * Configures width of the first pulse. Measurement unit: Periods of the carrier. - */ - uint32_t chopper0_oshtwth:4; - /** chopper0_out_invert : R/W; bitpos: [12]; default: 0; - * Configures whether or not to invert the output of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ - uint32_t chopper0_out_invert:1; - /** chopper0_in_invert : R/W; bitpos: [13]; default: 0; - * Configures whether or not to invert the input of PWM$n A and PWM$n B for this - * submodule.\\0: Normal\\1: Invert - */ - uint32_t chopper0_in_invert:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} mcpwm_carrier_cfg_reg_t; - -/** Type of fh0_cfg0 register - * PWM$n A and PWM$n B trip events actions configuration register - */ -typedef union { - struct { - /** tz0_sw_cbc : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_sw_cbc:1; - /** tz0_f2_cbc : R/W; bitpos: [1]; default: 0; - * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_f2_cbc:1; - /** tz0_f1_cbc : R/W; bitpos: [2]; default: 0; - * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_f1_cbc:1; - /** tz0_f0_cbc : R/W; bitpos: [3]; default: 0; - * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_f0_cbc:1; - /** tz0_sw_ost : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable software force one-shot mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_sw_ost:1; - /** tz0_f2_ost : R/W; bitpos: [5]; default: 0; - * Configures whether or not event_f2 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_f2_ost:1; - /** tz0_f1_ost : R/W; bitpos: [6]; default: 0; - * Configures whether or not event_f1 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_f1_ost:1; - /** tz0_f0_ost : R/W; bitpos: [7]; default: 0; - * Configures whether or not event_f0 will trigger one-shot mode action.\\0: - * Disable\\1: Enable - */ - uint32_t tz0_f0_ost:1; - /** tz0_a_cbc_d : R/W; bitpos: [9:8]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_a_cbc_d:2; - /** tz0_a_cbc_u : R/W; bitpos: [11:10]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_a_cbc_u:2; - /** tz0_a_ost_d : R/W; bitpos: [13:12]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_a_ost_d:2; - /** tz0_a_ost_u : R/W; bitpos: [15:14]; default: 0; - * Configures one-shot mode action on PWM$n A when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_a_ost_u:2; - /** tz0_b_cbc_d : R/W; bitpos: [17:16]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_b_cbc_d:2; - /** tz0_b_cbc_u : R/W; bitpos: [19:18]; default: 0; - * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer - * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_b_cbc_u:2; - /** tz0_b_ost_d : R/W; bitpos: [21:20]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_b_ost_d:2; - /** tz0_b_ost_u : R/W; bitpos: [23:22]; default: 0; - * Configures one-shot mode action on PWM$n B when fault event occurs and timer is - * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - */ - uint32_t tz0_b_ost_u:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_fh_cfg0_reg_t; - -/** Type of fh0_cfg1 register - * Software triggers for fault handler actions configuration register - */ -typedef union { - struct { - /** tz0_clr_ost : R/W; bitpos: [0]; default: 0; - * Configures the generation of software one-shot mode action clear. A toggle - * (software negate its value) triggers a clear for on going one-shot mode action. - */ - uint32_t tz0_clr_ost:1; - /** tz0_cbcpulse : R/W; bitpos: [2:1]; default: 0; - * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select - * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP - */ - uint32_t tz0_cbcpulse:2; - /** tz0_force_cbc : R/W; bitpos: [3]; default: 0; - * Configures the generation of software cycle-by-cycle mode action. A toggle - * (software negate its value) triggers a cycle-by-cycle mode action. - */ - uint32_t tz0_force_cbc:1; - /** tz0_force_ost : R/W; bitpos: [4]; default: 0; - * Configures the generation of software one-shot mode action. A toggle (software - * negate its value) triggers a one-shot mode action. - */ - uint32_t tz0_force_ost:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_fh_cfg1_reg_t; - -/** Type of fh0_status register - * Fault events status register - */ -typedef union { - struct { - /** tz0_cbc_on : RO; bitpos: [0]; default: 0; - * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No - * action\\1: On going - */ - uint32_t tz0_cbc_on:1; - /** tz0_ost_on : RO; bitpos: [1]; default: 0; - * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On - * going - */ - uint32_t tz0_ost_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} mcpwm_fh_status_reg_t; - -/** Group: fault_detect */ -/** Type of fault_detect register - * Fault detection configuration and status register - */ -typedef union { - struct { - /** f0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable - */ - uint32_t f0_en:1; - /** f1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable - */ - uint32_t f1_en:1; - /** f2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable - */ - uint32_t f2_en:1; - /** f0_pole : R/W; bitpos: [3]; default: 0; - * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level - * low\\1: Level high - */ - uint32_t f0_pole:1; - /** f1_pole : R/W; bitpos: [4]; default: 0; - * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level - * low\\1: Level high - */ - uint32_t f1_pole:1; - /** f2_pole : R/W; bitpos: [5]; default: 0; - * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level - * low\\1: Level high - */ - uint32_t f2_pole:1; - /** event_f0 : RO; bitpos: [6]; default: 0; - * Represents whether or not an event_f0 is on going.\\0: No action\\1: On going - */ - uint32_t event_f0:1; - /** event_f1 : RO; bitpos: [7]; default: 0; - * Represents whether or not an event_f1 is on going.\\0: No action\\1: On going - */ - uint32_t event_f1:1; - /** event_f2 : RO; bitpos: [8]; default: 0; - * Represents whether or not an event_f2 is on going.\\0: No action\\1: On going - */ - uint32_t event_f2:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} mcpwm_fault_detect_reg_t; - - -/** Group: cap_timer_cfg */ -/** Type of cap_timer_cfg register - * Capture timer configuration register - */ -typedef union { - struct { - /** cap_timer_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable - */ - uint32_t cap_timer_en:1; - /** cap_synci_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable - */ - uint32_t cap_synci_en:1; - /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; - * Configures the selection of capture module sync input.\\0: None\\1: Timer0 - * sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: - * SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None - */ - uint32_t cap_synci_sel:3; - /** cap_sync_sw : WT; bitpos: [5]; default: 0; - * Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: - * Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with - * value in phase register - */ - uint32_t cap_sync_sw:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} mcpwm_cap_timer_cfg_reg_t; - - -/** Group: cap_timer_phase */ -/** Type of cap_timer_phase register - * Capture timer sync phase register - */ -typedef union { - struct { - /** cap_phase : R/W; bitpos: [31:0]; default: 0; - * Configures phase value for capture timer sync operation. - */ - uint32_t cap_phase:32; - }; - uint32_t val; -} mcpwm_cap_timer_phase_reg_t; - - -/** Group: cap_chn_cfg */ -/** Type of cap_chn_cfg register - * Capture channel n configuration register - */ -typedef union { - struct { - /** cap0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable - */ - uint32_t cap0_en:1; - /** cap0_mode : R/W; bitpos: [2:1]; default: 0; - * Configures which edge of capture on channel n after prescaling is used.\\0: - * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: - * Enable capture on the positive edge - */ - uint32_t cap0_mode:2; - /** cap0_prescale : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on possitive edge of CAPn. Prescale value = - * PWM_CAPn_PRESCALE + 1 - */ - uint32_t cap0_prescale:8; - /** cap0_in_invert : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0: - * Normal\\1: Invert - */ - uint32_t cap0_in_invert:1; - /** cap0_sw : WT; bitpos: [12]; default: 0; - * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a - * software forced capture on channel n - */ - uint32_t cap0_sw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} mcpwm_cap_chn_cfg_reg_t; - - -/** Group: cap_chn */ -/** Type of cap_chn register - * CAPn capture value register - */ -typedef union { - struct { - /** cap0_value : RO; bitpos: [31:0]; default: 0; - * Represents value of last capture on CAPn - */ - uint32_t cap0_value:32; - }; - uint32_t val; -} mcpwm_cap_chn_reg_t; - - -/** Group: cap_status */ -/** Type of cap_status register - * Last capture trigger edge information register - */ -typedef union { - struct { - /** cap0_edge : RO; bitpos: [0]; default: 0; - * Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge - */ - uint32_t cap0_edge:1; - /** cap1_edge : RO; bitpos: [1]; default: 0; - * Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge - */ - uint32_t cap1_edge:1; - /** cap2_edge : RO; bitpos: [2]; default: 0; - * Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge - */ - uint32_t cap2_edge:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} mcpwm_cap_status_reg_t; - - -/** Group: update_cfg */ -/** Type of update_cfg register - * Generator Update configuration register - */ -typedef union { - struct { - /** global_up_en : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable global update for all active registers in MCPWM - * module.\\0: Disable\\1: Enable - */ - uint32_t global_up_en:1; - /** global_force_up : R/W; bitpos: [1]; default: 0; - * Configures the generation of global forced update for all active registers in MCPWM - * module. A toggle (software invert its value) will trigger a global forced update. - * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. - */ - uint32_t global_force_up:1; - /** op0_up_en : R/W; bitpos: [2]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator$n. - * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - */ - uint32_t op0_up_en:1; - /** op0_force_up : R/W; bitpos: [3]; default: 0; - * Configures the generation of forced update for active registers in PWM operator0. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. - */ - uint32_t op0_force_up:1; - /** op1_up_en : R/W; bitpos: [4]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator$n. - * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - */ - uint32_t op1_up_en:1; - /** op1_force_up : R/W; bitpos: [5]; default: 0; - * Configures the generation of forced update for active registers in PWM operator1. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. - */ - uint32_t op1_force_up:1; - /** op2_up_en : R/W; bitpos: [6]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator$n. - * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - */ - uint32_t op2_up_en:1; - /** op2_force_up : R/W; bitpos: [7]; default: 0; - * Configures the generation of forced update for active registers in PWM operator2. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. - */ - uint32_t op2_force_up:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} mcpwm_update_cfg_reg_t; - - -/** Group: int_ena */ -/** Type of int_ena register - * Interrupt enable register - */ -typedef union { - struct { - /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. - */ - uint32_t timer0_stop_int_ena:1; - /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. - */ - uint32_t timer1_stop_int_ena:1; - /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. - */ - uint32_t timer2_stop_int_ena:1; - /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. - */ - uint32_t timer0_tez_int_ena:1; - /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. - */ - uint32_t timer1_tez_int_ena:1; - /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. - */ - uint32_t timer2_tez_int_ena:1; - /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. - */ - uint32_t timer0_tep_int_ena:1; - /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. - */ - uint32_t timer1_tep_int_ena:1; - /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. - */ - uint32_t timer2_tep_int_ena:1; - /** fault0_int_ena : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. - */ - uint32_t fault0_int_ena:1; - /** fault1_int_ena : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. - */ - uint32_t fault1_int_ena:1; - /** fault2_int_ena : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. - */ - uint32_t fault2_int_ena:1; - /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. - */ - uint32_t fault0_clr_int_ena:1; - /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. - */ - uint32_t fault1_clr_int_ena:1; - /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. - */ - uint32_t fault2_clr_int_ena:1; - /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. - */ - uint32_t cmpr0_tea_int_ena:1; - /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. - */ - uint32_t cmpr1_tea_int_ena:1; - /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. - */ - uint32_t cmpr2_tea_int_ena:1; - /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. - */ - uint32_t cmpr0_teb_int_ena:1; - /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. - */ - uint32_t cmpr1_teb_int_ena:1; - /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. - */ - uint32_t cmpr2_teb_int_ena:1; - /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM0. - */ - uint32_t tz0_cbc_int_ena:1; - /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM1. - */ - uint32_t tz1_cbc_int_ena:1; - /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM2. - */ - uint32_t tz2_cbc_int_ena:1; - /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM0. - */ - uint32_t tz0_ost_int_ena:1; - /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM1. - */ - uint32_t tz1_ost_int_ena:1; - /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM2. - */ - uint32_t tz2_ost_int_ena:1; - /** cap0_int_ena : R/W; bitpos: [27]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. - */ - uint32_t cap0_int_ena:1; - /** cap1_int_ena : R/W; bitpos: [28]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. - */ - uint32_t cap1_int_ena:1; - /** cap2_int_ena : R/W; bitpos: [29]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. - */ - uint32_t cap2_int_ena:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_ena_reg_t; - - -/** Group: int_raw */ -/** Type of int_raw register - * Interrupt raw status register - */ -typedef union { - struct { - /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 0 stops. - */ - uint32_t timer0_stop_int_raw:1; - /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 1 stops. - */ - uint32_t timer1_stop_int_raw:1; - /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 2 stops. - */ - uint32_t timer2_stop_int_raw:1; - /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 0 TEZ event. - */ - uint32_t timer0_tez_int_raw:1; - /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 1 TEZ event. - */ - uint32_t timer1_tez_int_raw:1; - /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 2 TEZ event. - */ - uint32_t timer2_tez_int_raw:1; - /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 0 TEP event. - */ - uint32_t timer0_tep_int_raw:1; - /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 1 TEP event. - */ - uint32_t timer1_tep_int_raw:1; - /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 2 TEP event. - */ - uint32_t timer2_tep_int_raw:1; - /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 - * starts. - */ - uint32_t fault0_int_raw:1; - /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 - * starts. - */ - uint32_t fault1_int_raw:1; - /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 - * starts. - */ - uint32_t fault2_int_raw:1; - /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 - * clears. - */ - uint32_t fault0_clr_int_raw:1; - /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 - * clears. - */ - uint32_t fault1_clr_int_raw:1; - /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 - * clears. - */ - uint32_t fault2_clr_int_raw:1; - /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 0 TEA event - */ - uint32_t cmpr0_tea_int_raw:1; - /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 1 TEA event - */ - uint32_t cmpr1_tea_int_raw:1; - /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 2 TEA event - */ - uint32_t cmpr2_tea_int_raw:1; - /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 0 TEB event - */ - uint32_t cmpr0_teb_int_raw:1; - /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 1 TEB event - */ - uint32_t cmpr1_teb_int_raw:1; - /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 2 TEB event - */ - uint32_t cmpr2_teb_int_raw:1; - /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM0. - */ - uint32_t tz0_cbc_int_raw:1; - /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM1. - */ - uint32_t tz1_cbc_int_raw:1; - /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM2. - */ - uint32_t tz2_cbc_int_raw:1; - /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM0. - */ - uint32_t tz0_ost_int_raw:1; - /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM1. - */ - uint32_t tz1_ost_int_raw:1; - /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM2. - */ - uint32_t tz2_ost_int_raw:1; - /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP0. - */ - uint32_t cap0_int_raw:1; - /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP1. - */ - uint32_t cap1_int_raw:1; - /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP2. - */ - uint32_t cap2_int_raw:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_raw_reg_t; - - -/** Group: int_st */ -/** Type of int_st register - * Interrupt masked status register - */ -typedef union { - struct { - /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 0 stops. - */ - uint32_t timer0_stop_int_st:1; - /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 1 stops. - */ - uint32_t timer1_stop_int_st:1; - /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 2 stops. - */ - uint32_t timer2_stop_int_st:1; - /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 0 TEZ event. - */ - uint32_t timer0_tez_int_st:1; - /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 1 TEZ event. - */ - uint32_t timer1_tez_int_st:1; - /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 2 TEZ event. - */ - uint32_t timer2_tez_int_st:1; - /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 0 TEP event. - */ - uint32_t timer0_tep_int_st:1; - /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 1 TEP event. - */ - uint32_t timer1_tep_int_st:1; - /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 2 TEP event. - */ - uint32_t timer2_tep_int_st:1; - /** fault0_int_st : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f0 starts. - */ - uint32_t fault0_int_st:1; - /** fault1_int_st : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f1 starts. - */ - uint32_t fault1_int_st:1; - /** fault2_int_st : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f2 starts. - */ - uint32_t fault2_int_st:1; - /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f0 clears. - */ - uint32_t fault0_clr_int_st:1; - /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f1 clears. - */ - uint32_t fault1_clr_int_st:1; - /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f2 clears. - */ - uint32_t fault2_clr_int_st:1; - /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 0 TEA event - */ - uint32_t cmpr0_tea_int_st:1; - /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 1 TEA event - */ - uint32_t cmpr1_tea_int_st:1; - /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 2 TEA event - */ - uint32_t cmpr2_tea_int_st:1; - /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 0 TEB event - */ - uint32_t cmpr0_teb_int_st:1; - /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 1 TEB event - */ - uint32_t cmpr1_teb_int_st:1; - /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 2 TEB event - */ - uint32_t cmpr2_teb_int_st:1; - /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM0. - */ - uint32_t tz0_cbc_int_st:1; - /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM1. - */ - uint32_t tz1_cbc_int_st:1; - /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM2. - */ - uint32_t tz2_cbc_int_st:1; - /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM0. - */ - uint32_t tz0_ost_int_st:1; - /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM1. - */ - uint32_t tz1_ost_int_st:1; - /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM2. - */ - uint32_t tz2_ost_int_st:1; - /** cap0_int_st : RO; bitpos: [27]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP0. - */ - uint32_t cap0_int_st:1; - /** cap1_int_st : RO; bitpos: [28]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP1. - */ - uint32_t cap1_int_st:1; - /** cap2_int_st : RO; bitpos: [29]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP2. - */ - uint32_t cap2_int_st:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_st_reg_t; - - -/** Group: int_clr */ -/** Type of int_clr register - * Interrupt clear register - */ -typedef union { - struct { - /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. - */ - uint32_t timer0_stop_int_clr:1; - /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. - */ - uint32_t timer1_stop_int_clr:1; - /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. - */ - uint32_t timer2_stop_int_clr:1; - /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. - */ - uint32_t timer0_tez_int_clr:1; - /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. - */ - uint32_t timer1_tez_int_clr:1; - /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. - */ - uint32_t timer2_tez_int_clr:1; - /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. - */ - uint32_t timer0_tep_int_clr:1; - /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. - */ - uint32_t timer1_tep_int_clr:1; - /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. - */ - uint32_t timer2_tep_int_clr:1; - /** fault0_int_clr : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. - */ - uint32_t fault0_int_clr:1; - /** fault1_int_clr : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. - */ - uint32_t fault1_int_clr:1; - /** fault2_int_clr : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. - */ - uint32_t fault2_int_clr:1; - /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. - */ - uint32_t fault0_clr_int_clr:1; - /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. - */ - uint32_t fault1_clr_int_clr:1; - /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. - */ - uint32_t fault2_clr_int_clr:1; - /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event - */ - uint32_t cmpr0_tea_int_clr:1; - /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event - */ - uint32_t cmpr1_tea_int_clr:1; - /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event - */ - uint32_t cmpr2_tea_int_clr:1; - /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event - */ - uint32_t cmpr0_teb_int_clr:1; - /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event - */ - uint32_t cmpr1_teb_int_clr:1; - /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event - */ - uint32_t cmpr2_teb_int_clr:1; - /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM0. - */ - uint32_t tz0_cbc_int_clr:1; - /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM1. - */ - uint32_t tz1_cbc_int_clr:1; - /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM2. - */ - uint32_t tz2_cbc_int_clr:1; - /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM0. - */ - uint32_t tz0_ost_int_clr:1; - /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM1. - */ - uint32_t tz1_ost_int_clr:1; - /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM2. - */ - uint32_t tz2_ost_int_clr:1; - /** cap0_int_clr : WT; bitpos: [27]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. - */ - uint32_t cap0_int_clr:1; - /** cap1_int_clr : WT; bitpos: [28]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. - */ - uint32_t cap1_int_clr:1; - /** cap2_int_clr : WT; bitpos: [29]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. - */ - uint32_t cap2_int_clr:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_clr_reg_t; - - -/** Group: evt_en */ -/** Type of evt_en register - * Event enable register - */ -typedef union { - struct { - /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer0_stop_en:1; - /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer1_stop_en:1; - /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer2_stop_en:1; - /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable timer0 equal zero event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_timer0_tez_en:1; - /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable timer1 equal zero event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_timer1_tez_en:1; - /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable timer2 equal zero event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_timer2_tez_en:1; - /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable timer0 equal period event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_timer0_tep_en:1; - /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable timer1 equal period event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_timer1_tep_en:1; - /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable timer2 equal period event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_timer2_tep_en:1; - /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal a event - * generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op0_tea_en:1; - /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal a event - * generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op1_tea_en:1; - /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal a event - * generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op2_tea_en:1; - /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal b event - * generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op0_teb_en:1; - /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal b event - * generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op1_teb_en:1; - /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal b event - * generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op2_teb_en:1; - /** evt_f0_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_f0_en:1; - /** evt_f1_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_f1_en:1; - /** evt_f2_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_f2_en:1; - /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_f0_clr_en:1; - /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_f1_clr_en:1; - /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_f2_clr_en:1; - /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_tz0_cbc_en:1; - /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_tz1_cbc_en:1; - /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: - * Disable\\1: Enable - */ - uint32_t evt_tz2_cbc_en:1; - /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_tz0_ost_en:1; - /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_tz1_ost_en:1; - /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: - * Enable - */ - uint32_t evt_tz2_ost_en:1; - /** evt_cap0_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_cap0_en:1; - /** evt_cap1_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_cap1_en:1; - /** evt_cap2_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_cap2_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_evt_en_reg_t; - - -/** Group: task_en */ -/** Type of task_en register - * Task enable register - */ -typedef union { - struct { - /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable PWM generator0 timer stamp A's shadow register - * update task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cmpr0_a_up_en:1; - /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable PWM generator1 timer stamp A's shadow register - * update task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cmpr1_a_up_en:1; - /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable PWM generator2 timer stamp A's shadow register - * update task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cmpr2_a_up_en:1; - /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable PWM generator0 timer stamp B's shadow register - * update task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cmpr0_b_up_en:1; - /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable PWM generator1 timer stamp B's shadow register - * update task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cmpr1_b_up_en:1; - /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable PWM generator2 timer stamp B's shadow register - * update task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cmpr2_b_up_en:1; - /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable all PWM generate stop task receive.\\0: - * Disable\\1: Enable - */ - uint32_t task_gen_stop_en:1; - /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable - */ - uint32_t task_timer0_sync_en:1; - /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable - */ - uint32_t task_timer1_sync_en:1; - /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable - */ - uint32_t task_timer2_sync_en:1; - /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable timer0 period update task receive.\\0: - * Disable\\1: Enable - */ - uint32_t task_timer0_period_up_en:1; - /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable timer1 period update task receive.\\0: - * Disable\\1: Enable - */ - uint32_t task_timer1_period_up_en:1; - /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable timer2 period update task receive.\\0: - * Disable\\1: Enable - */ - uint32_t task_timer2_period_up_en:1; - /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: - * Enable - */ - uint32_t task_tz0_ost_en:1; - /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: - * Enable - */ - uint32_t task_tz1_ost_en:1; - /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: - * Enable - */ - uint32_t task_tz2_ost_en:1; - /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable one shot trip0 clear task receive.\\0: - * Disable\\1: Enable - */ - uint32_t task_clr0_ost_en:1; - /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable one shot trip1 clear task receive.\\0: - * Disable\\1: Enable - */ - uint32_t task_clr1_ost_en:1; - /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable one shot trip2 clear task receive.\\0: - * Disable\\1: Enable - */ - uint32_t task_clr2_ost_en:1; - /** task_cap0_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cap0_en:1; - /** task_cap1_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cap1_en:1; - /** task_cap2_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable - */ - uint32_t task_cap2_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} mcpwm_task_en_reg_t; - - -/** Group: evt_en2 */ -/** Type of evt_en2 register - * Event enable register2 - */ -typedef union { - struct { - /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG - * event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op0_tee1_en:1; - /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG - * event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op1_tee1_en:1; - /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG - * event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op2_tee1_en:1; - /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG - * event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op0_tee2_en:1; - /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG - * event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op1_tee2_en:1; - /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG - * event generate.\\0: Disable\\1: Enable - */ - uint32_t evt_op2_tee2_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} mcpwm_evt_en2_reg_t; - - -/** Group: Configuration register */ -/** Type of opn_tstmp_e1 register - * Generatorn timer stamp E1 value register - */ -typedef union { - struct { - /** op0_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; - * Configures generatorn timer stamp E1 value register - */ - uint32_t op0_tstmp_e1:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_op_tstmp_e1_reg_t; - -/** Type of op0_tstmp_e2 register - * Generator$n timer stamp E2 value register - */ -typedef union { - struct { - /** op0_tstmp_e2 : R/W; bitpos: [15:0]; default: 0; - * Configures generator$n timer stamp E2 value register - */ - uint32_t op0_tstmp_e2:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_op_tstmp_e2_reg_t; - -/** Type of clk register - * Global configuration register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} mcpwm_clk_reg_t; - - -/** Group: Version register */ -/** Type of version register - * Version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35725968; - * Configures the version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} mcpwm_version_reg_t; - -typedef struct { - volatile mcpwm_timer_cfg0_reg_t cfg0; - volatile mcpwm_timer_cfg1_reg_t cfg1; - volatile mcpwm_timer_sync_reg_t sync; - volatile mcpwm_timer_status_reg_t status; -} mcpwm_timer_regs_t; - -typedef struct { - volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; - volatile mcpwm_gen_tstmp_a_reg_t gen_tstmp_a; - volatile mcpwm_gen_tstmp_b_reg_t gen_tstmp_b; - volatile mcpwm_gen_cfg0_reg_t gen_cfg0; - volatile mcpwm_gen_force_reg_t gen_force; - volatile mcpwm_gen_a_reg_t gen_a; - volatile mcpwm_gen_b_reg_t gen_b; - volatile mcpwm_dt_cfg_reg_t dt_cfg; - volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; - volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg; - volatile mcpwm_carrier_cfg_reg_t carrier_cfg; - volatile mcpwm_fh_cfg0_reg_t fh_cfg0; - volatile mcpwm_fh_cfg1_reg_t fh_cfg1; - volatile mcpwm_fh_status_reg_t fh_status; -} mcpwm_operator_reg_t; - -typedef struct { - volatile mcpwm_op_tstmp_e1_reg_t tstmp_e1; - volatile mcpwm_op_tstmp_e2_reg_t tstmp_e2; -} mcpwm_operator_tstmp_reg_t; - -typedef struct { - volatile mcpwm_clk_cfg_reg_t clk_cfg; - volatile mcpwm_timer_regs_t timer[3]; - volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; - volatile mcpwm_operator_timersel_reg_t operator_timersel; - volatile mcpwm_operator_reg_t operators[3]; - volatile mcpwm_fault_detect_reg_t fault_detect; - volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; - volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; - volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; - volatile mcpwm_cap_chn_reg_t cap_chn[3]; - volatile mcpwm_cap_status_reg_t cap_status; - volatile mcpwm_update_cfg_reg_t update_cfg; - volatile mcpwm_int_ena_reg_t int_ena; - volatile mcpwm_int_raw_reg_t int_raw; - volatile mcpwm_int_st_reg_t int_st; - volatile mcpwm_int_clr_reg_t int_clr; - volatile mcpwm_evt_en_reg_t evt_en; - volatile mcpwm_task_en_reg_t task_en; - volatile mcpwm_evt_en2_reg_t evt_en2; - volatile mcpwm_operator_tstmp_reg_t op_tstmp[3]; - volatile mcpwm_clk_reg_t clk; - volatile mcpwm_version_reg_t version; -} mcpwm_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h index bdb3e63aae..c6397f4729 100644 --- a/components/soc/esp32p4/include/soc/reg_base.h +++ b/components/soc/esp32p4/include/soc/reg_base.h @@ -4,11 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -//#define DR_REG_PLIC_MX_BASE 0x20001000 -//#define DR_REG_PLIC_UX_BASE 0x20001400 -//#define DR_REG_CLINT_M_BASE 0x20001800 -//#define DR_REG_CLINT_U_BASE 0x20001C00 - /* Basic address */ #define DR_REG_HPCPUTCP_BASE 0x3FF00000 #define DR_REG_HPPERIPH0_BASE 0x50000000 @@ -127,7 +122,7 @@ * @size: 64KB */ #define DR_REG_LP_SYS_BASE (DR_REG_LPAON_BASE + 0x0) -#define DR_REG_LP_AONCLKRST_BASE (DR_REG_LPAON_BASE + 0x1000) +#define DR_REG_LP_CLKRST_BASE (DR_REG_LPAON_BASE + 0x1000) #define DR_REG_LP_TIMER_BASE (DR_REG_LPAON_BASE + 0x2000) #define DR_REG_LP_ANAPERI_BASE (DR_REG_LPAON_BASE + 0x3000) #define DR_REG_LP_HUK_BASE (DR_REG_LPAON_BASE + 0x4000) @@ -153,30 +148,24 @@ #define DR_REG_LP_ADC_BASE (DR_REG_LPPERIPH_BASE + 0x7000) #define DR_REG_LP_TOUCH_BASE (DR_REG_LPPERIPH_BASE + 0x8000) #define DR_REG_LP_GPIO_BASE (DR_REG_LPPERIPH_BASE + 0xA000) +#define DR_REG_LP_IOMUX_BASE (DR_REG_LPPERIPH_BASE + 0xB000) #define DR_REG_LP_INTR_BASE (DR_REG_LPPERIPH_BASE + 0xC000) -#define DR_REG_LP_IOMUX_BASE 0 // just for compile, need remove later #define DR_REG_EFUSE_BASE (DR_REG_LPPERIPH_BASE + 0xD000) #define DR_REG_LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE000) #define DR_REG_HP2LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE800) #define DR_REG_LP_TSENSOR_BASE (DR_REG_LPPERIPH_BASE + 0xF000) -/* this is some module helper MACROs for quick module reference +/** + * This are module helper MACROs for quick module reference * including some module(renamed) address */ #define DR_REG_UART_BASE DR_REG_UART0_BASE -// ESP32P4-TODO: check this -#define DR_REG_I2C_EXT_BASE 0x60004000 #define DR_REG_UHCI0_BASE DR_REG_UHCI_BASE #define DR_REG_TIMERGROUP0_BASE DR_REG_TIMG0_BASE #define DR_REG_TIMERGROUP1_BASE DR_REG_TIMG1_BASE #define DR_REG_I2S_BASE DR_REG_I2S0_BASE -// ESP32P4-TODO: check this -#define DR_REG_APB_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE DR_REG_USB2JTAG_BASE #define DR_REG_INTERRUPT_MATRIX_BASE DR_REG_INTR_BASE -// ESP32P4-TODO: check this -#define DR_REG_ATOMIC_BASE 0x60011000 -// ESP32P4-TODO: check this #define DR_REG_SOC_ETM_BASE DR_REG_ETM_BASE #define DR_REG_MCPWM_BASE DR_REG_MCPWM0_BASE #define DR_REG_PARL_IO_BASE DR_REG_PARIO_BASE @@ -189,41 +178,31 @@ #define DR_REG_DIGITAL_SIGNATURE_BASE DR_REG_DS_BASE #define DR_REG_HMAC_BASE (DR_REG_CRYPTO_BASE + 0x5000) #define DR_REG_ECDSA_BASE (DR_REG_CRYPTO_BASE + 0x6000) -// ESP32P4-TODO: check this -#define DR_REG_GPIO_EXT_BASE 0x60091f00 //ESP32C6-TODO #define DR_REG_MEM_MONITOR_BASE DR_REG_L2MEM_MON_BASE -// ESP32P4-TODO: check this -#define DR_REG_PAU_BASE 0x60093000 -// ESP32P4-TODO: check this -#define DR_REG_HP_SYSTEM_BASE 0x60095000 -// ESP32P4-TODO: should remove this -#define DR_REG_SYSTEM_BASE DR_REG_HP_SYS_BASE -// ESP32P4-TODO: should remove this -#define DR_REG_RTCCNTL_BASE 0x60008000 -// ESP32P4-TODO: should remove this -#define DR_REG_AES_XTS_BASE 0x600CC000 -#define DR_REG_PCR_BASE 0x60096000 -#define DR_REG_TEE_BASE 0x60098000 -#define DR_REG_HP_APM_BASE 0x60099000 -#define DR_REG_LP_APM0_BASE 0x60099800 -#define DR_REG_MISC_BASE 0x6009F000 - #define DR_REG_HP_CLKRST_BASE DR_REG_HP_SYS_CLKRST_BASE -#define DR_REG_DSPI_MEM_BASE (DR_REG_PSRAM_MSPI0_BASE) +#define DR_REG_DSPI_MEM_BASE DR_REG_PSRAM_MSPI0_BASE #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTR_BASE #define DR_REG_INTERRUPT_CORE1_BASE (DR_REG_INTR_BASE + 0x800) - -#define DR_REG_LP_CLKRST_BASE 0x600B0400 -#define DR_REG_LP_AON_BASE 0x600B1000 -#define DR_REG_LP_IO_BASE 0x600B2000 -#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 #define DR_REG_LPPERI_BASE DR_REG_LP_PERI_CLKRST_BASE -#define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00 -#define DR_REG_LP_TEE_BASE 0x600B3400 -#define DR_REG_LP_APM_BASE 0x600B3800 -#define DR_REG_OPT_DEBUG_BASE 0x600B3C00 +#define DR_REG_CPU_BUS_MONITOR_BASE DR_REG_CPU_BUS_MON_BASE -#define DR_REG_TRACE_BASE 0x600C0000 + +//TODO: IDF-7481, TODO: IDF-7479, TODO: IDF-7551 +// #define DR_REG_GPIO_EXT_BASE 0x60091f00 + +//TODO: IDF-7542 +// #define DR_REG_TEE_BASE 0x60098000 +// #define DR_REG_HP_APM_BASE 0x60099000 +// #define DR_REG_LP_APM0_BASE 0x60099800 +// #define DR_REG_LP_TEE_BASE 0x600B3400 +// #define DR_REG_LP_APM_BASE 0x600B3800 + +//TODO: IDF-7531 +// #define DR_REG_PAU_BASE 0x60093000 +// #define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00 +// #define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 +// #define DR_REG_LP_AON_BASE 0x600B1000 + +//TODO: IDF-7688 +// #define DR_REG_TRACE_BASE 0x600C0000 #define DR_REG_ASSIST_DEBUG_BASE 0x3FF06000 -#define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000 -#define DR_REG_INTPRI_BASE 0x600C5000 diff --git a/components/soc/esp32p4/include/soc/regi2c_bbpll.h b/components/soc/esp32p4/include/soc/regi2c_bbpll.h index 0b0cb7af45..235bca28dd 100644 --- a/components/soc/esp32p4/include/soc/regi2c_bbpll.h +++ b/components/soc/esp32p4/include/soc/regi2c_bbpll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,162 +14,3 @@ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by * rtc_clk_cpu_freq_set function in rtc_clk.c. */ - -#define I2C_BBPLL 0x66 -#define I2C_BBPLL_HOSTID 0 - -#define I2C_BBPLL_IR_CAL_DELAY 0 -#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 -#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 - -#define I2C_BBPLL_IR_CAL_CK_DIV 0 -#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 -#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 - -#define I2C_BBPLL_IR_CAL_EXT_CAP 1 -#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 -#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 - -#define I2C_BBPLL_IR_CAL_ENX_CAP 1 -#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 -#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 - -#define I2C_BBPLL_IR_CAL_RSTB 1 -#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 -#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 - -#define I2C_BBPLL_IR_CAL_START 1 -#define I2C_BBPLL_IR_CAL_START_MSB 6 -#define I2C_BBPLL_IR_CAL_START_LSB 6 - -#define I2C_BBPLL_IR_CAL_UNSTOP 1 -#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 -#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 - -#define I2C_BBPLL_OC_REF_DIV 2 -#define I2C_BBPLL_OC_REF_DIV_MSB 3 -#define I2C_BBPLL_OC_REF_DIV_LSB 0 - -#define I2C_BBPLL_OC_DCHGP 2 -#define I2C_BBPLL_OC_DCHGP_MSB 6 -#define I2C_BBPLL_OC_DCHGP_LSB 4 - -#define I2C_BBPLL_OC_ENB_FCAL 2 -#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 -#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 - -#define I2C_BBPLL_OC_DIV_7_0 3 -#define I2C_BBPLL_OC_DIV_7_0_MSB 7 -#define I2C_BBPLL_OC_DIV_7_0_LSB 0 - -#define I2C_BBPLL_RSTB_DIV_ADC 4 -#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 -#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 - -#define I2C_BBPLL_MODE_HF 4 -#define I2C_BBPLL_MODE_HF_MSB 1 -#define I2C_BBPLL_MODE_HF_LSB 1 - -#define I2C_BBPLL_DIV_ADC 4 -#define I2C_BBPLL_DIV_ADC_MSB 3 -#define I2C_BBPLL_DIV_ADC_LSB 2 - -#define I2C_BBPLL_DIV_DAC 4 -#define I2C_BBPLL_DIV_DAC_MSB 4 -#define I2C_BBPLL_DIV_DAC_LSB 4 - -#define I2C_BBPLL_DIV_CPU 4 -#define I2C_BBPLL_DIV_CPU_MSB 5 -#define I2C_BBPLL_DIV_CPU_LSB 5 - -#define I2C_BBPLL_OC_ENB_VCON 4 -#define I2C_BBPLL_OC_ENB_VCON_MSB 6 -#define I2C_BBPLL_OC_ENB_VCON_LSB 6 - -#define I2C_BBPLL_OC_TSCHGP 4 -#define I2C_BBPLL_OC_TSCHGP_MSB 7 -#define I2C_BBPLL_OC_TSCHGP_LSB 7 - -#define I2C_BBPLL_OC_DR1 5 -#define I2C_BBPLL_OC_DR1_MSB 2 -#define I2C_BBPLL_OC_DR1_LSB 0 - -#define I2C_BBPLL_OC_DR3 5 -#define I2C_BBPLL_OC_DR3_MSB 6 -#define I2C_BBPLL_OC_DR3_LSB 4 - -#define I2C_BBPLL_EN_USB 5 -#define I2C_BBPLL_EN_USB_MSB 7 -#define I2C_BBPLL_EN_USB_LSB 7 - -#define I2C_BBPLL_OC_DCUR 6 -#define I2C_BBPLL_OC_DCUR_MSB 2 -#define I2C_BBPLL_OC_DCUR_LSB 0 - -#define I2C_BBPLL_INC_CUR 6 -#define I2C_BBPLL_INC_CUR_MSB 3 -#define I2C_BBPLL_INC_CUR_LSB 3 - -#define I2C_BBPLL_OC_DHREF_SEL 6 -#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 -#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 - -#define I2C_BBPLL_OC_DLREF_SEL 6 -#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 -#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 - -#define I2C_BBPLL_OR_CAL_CAP 8 -#define I2C_BBPLL_OR_CAL_CAP_MSB 3 -#define I2C_BBPLL_OR_CAL_CAP_LSB 0 - -#define I2C_BBPLL_OR_CAL_UDF 8 -#define I2C_BBPLL_OR_CAL_UDF_MSB 4 -#define I2C_BBPLL_OR_CAL_UDF_LSB 4 - -#define I2C_BBPLL_OR_CAL_OVF 8 -#define I2C_BBPLL_OR_CAL_OVF_MSB 5 -#define I2C_BBPLL_OR_CAL_OVF_LSB 5 - -#define I2C_BBPLL_OR_CAL_END 8 -#define I2C_BBPLL_OR_CAL_END_MSB 6 -#define I2C_BBPLL_OR_CAL_END_LSB 6 - -#define I2C_BBPLL_OR_LOCK 8 -#define I2C_BBPLL_OR_LOCK_MSB 7 -#define I2C_BBPLL_OR_LOCK_LSB 7 - -#define I2C_BBPLL_OC_VCO_DBIAS 9 -#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1 -#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 - -#define I2C_BBPLL_BBADC_DELAY2 9 -#define I2C_BBPLL_BBADC_DELAY2_MSB 3 -#define I2C_BBPLL_BBADC_DELAY2_LSB 2 - -#define I2C_BBPLL_BBADC_DVDD 9 -#define I2C_BBPLL_BBADC_DVDD_MSB 5 -#define I2C_BBPLL_BBADC_DVDD_LSB 4 - -#define I2C_BBPLL_BBADC_DREF 9 -#define I2C_BBPLL_BBADC_DREF_MSB 7 -#define I2C_BBPLL_BBADC_DREF_LSB 6 - -#define I2C_BBPLL_BBADC_DCUR 10 -#define I2C_BBPLL_BBADC_DCUR_MSB 1 -#define I2C_BBPLL_BBADC_DCUR_LSB 0 - -#define I2C_BBPLL_BBADC_INPUT_SHORT 10 -#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 -#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 - -#define I2C_BBPLL_ENT_PLL 10 -#define I2C_BBPLL_ENT_PLL_MSB 3 -#define I2C_BBPLL_ENT_PLL_LSB 3 - -#define I2C_BBPLL_DTEST 10 -#define I2C_BBPLL_DTEST_MSB 5 -#define I2C_BBPLL_DTEST_LSB 4 - -#define I2C_BBPLL_ENT_ADC 10 -#define I2C_BBPLL_ENT_ADC_MSB 7 -#define I2C_BBPLL_ENT_ADC_LSB 6 diff --git a/components/soc/esp32p4/include/soc/regi2c_bias.h b/components/soc/esp32p4/include/soc/regi2c_bias.h index fba5d6dbb5..c3abe087e8 100644 --- a/components/soc/esp32p4/include/soc/regi2c_bias.h +++ b/components/soc/esp32p4/include/soc/regi2c_bias.h @@ -13,10 +13,3 @@ * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by * bootloader_hardware_init function in bootloader_esp32c6.c. */ - -#define I2C_BIAS 0X6A -#define I2C_BIAS_HOSTID 0 - -#define I2C_BIAS_DREG_1P1_PVT 1 -#define I2C_BIAS_DREG_1P1_PVT_MSB 3 -#define I2C_BIAS_DREG_1P1_PVT_LSB 0 diff --git a/components/soc/esp32p4/include/soc/regi2c_brownout.h b/components/soc/esp32p4/include/soc/regi2c_brownout.h index 6a5ca15769..24377f9356 100644 --- a/components/soc/esp32p4/include/soc/regi2c_brownout.h +++ b/components/soc/esp32p4/include/soc/regi2c_brownout.h @@ -13,10 +13,3 @@ * This file lists register fields of the brownout detector, located on an internal configuration * bus. These definitions are used via macros defined in regi2c_ctrl.h. */ - -#define I2C_BOD 0x61 -#define I2C_BOD_HOSTID 0 - -#define I2C_BOD_THRESHOLD 0x5 -#define I2C_BOD_THRESHOLD_MSB 2 -#define I2C_BOD_THRESHOLD_LSB 0 diff --git a/components/soc/esp32p4/include/soc/regi2c_defs.h b/components/soc/esp32p4/include/soc/regi2c_defs.h index f9a2415bda..38db4f1595 100644 --- a/components/soc/esp32p4/include/soc/regi2c_defs.h +++ b/components/soc/esp32p4/include/soc/regi2c_defs.h @@ -27,11 +27,3 @@ #define ANA_CONFIG2_M BIT(18) #define ANA_I2C_SAR_FORCE_PU BIT(16) - - -/** - * Restore regi2c analog calibration related configuration registers. - * This is a workaround, and is fixed on later chips - */ -#define REGI2C_ANA_CALI_PD_WORKAROUND 1 -#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32p4/include/soc/regi2c_lp_bias.h b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h index 5ca1c6833e..2388cd02fd 100644 --- a/components/soc/esp32p4/include/soc/regi2c_lp_bias.h +++ b/components/soc/esp32p4/include/soc/regi2c_lp_bias.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,42 +14,3 @@ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by * rtc_init function in rtc_init.c. */ - -#define I2C_ULP 0x61 -#define I2C_ULP_HOSTID 0 - -#define I2C_ULP_IR_RESETB 0 -#define I2C_ULP_IR_RESETB_MSB 0 -#define I2C_ULP_IR_RESETB_LSB 0 - -#define I2C_ULP_IR_FORCE_XPD_CK 0 -#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2 -#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2 - -#define I2C_ULP_IR_FORCE_XPD_IPH 0 -#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4 -#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4 - -#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0 -#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6 -#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6 - -#define I2C_ULP_O_DONE_FLAG 3 -#define I2C_ULP_O_DONE_FLAG_MSB 0 -#define I2C_ULP_O_DONE_FLAG_LSB 0 - -#define I2C_ULP_BG_O_DONE_FLAG 3 -#define I2C_ULP_BG_O_DONE_FLAG_MSB 3 -#define I2C_ULP_BG_O_DONE_FLAG_LSB 3 - -#define I2C_ULP_OCODE 4 -#define I2C_ULP_OCODE_MSB 7 -#define I2C_ULP_OCODE_LSB 0 - -#define I2C_ULP_IR_FORCE_CODE 5 -#define I2C_ULP_IR_FORCE_CODE_MSB 6 -#define I2C_ULP_IR_FORCE_CODE_LSB 6 - -#define I2C_ULP_EXT_CODE 6 -#define I2C_ULP_EXT_CODE_MSB 7 -#define I2C_ULP_EXT_CODE_LSB 0 diff --git a/components/soc/esp32p4/include/soc/regi2c_saradc.h b/components/soc/esp32p4/include/soc/regi2c_saradc.h index ea76c6620d..7511dfa4e2 100644 --- a/components/soc/esp32p4/include/soc/regi2c_saradc.h +++ b/components/soc/esp32p4/include/soc/regi2c_saradc.h @@ -14,66 +14,3 @@ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by * function in adc_ll.h. */ - -#define I2C_SAR_ADC 0X69 -#define I2C_SAR_ADC_HOSTID 0 - -#define ADC_SAR1_ENCAL_GND_ADDR 0x7 -#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5 -#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5 - -#define ADC_SAR2_ENCAL_GND_ADDR 0x7 -#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 -#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 - -#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 -#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 -#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 - -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 - -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 - -#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 -#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 -#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 - -#define ADC_SAR1_DREF_ADDR 0x2 -#define ADC_SAR1_DREF_ADDR_MSB 0x6 -#define ADC_SAR1_DREF_ADDR_LSB 0x4 - -#define ADC_SAR2_DREF_ADDR 0x5 -#define ADC_SAR2_DREF_ADDR_MSB 0x6 -#define ADC_SAR2_DREF_ADDR_LSB 0x4 - -#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 -#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 -#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 - -#define ADC_SARADC_DTEST_RTC_ADDR 0x7 -#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1 -#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0 - -#define ADC_SARADC_ENT_TSENS_ADDR 0x7 -#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2 -#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2 - -#define ADC_SARADC_ENT_RTC_ADDR 0x7 -#define ADC_SARADC_ENT_RTC_ADDR_MSB 3 -#define ADC_SARADC_ENT_RTC_ADDR_LSB 3 - -#define ADC_SARADC1_ENCAL_REF_ADDR 0x7 -#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4 -#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4 - -#define ADC_SARADC2_ENCAL_REF_ADDR 0x7 -#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6 -#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6 - -#define I2C_SARADC_TSENS_DAC 0x6 -#define I2C_SARADC_TSENS_DAC_MSB 3 -#define I2C_SARADC_TSENS_DAC_LSB 0 diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h index 5a4e577205..b7e3b101a2 100644 --- a/components/soc/esp32p4/include/soc/reset_reasons.h +++ b/components/soc/esp32p4/include/soc/reset_reasons.h @@ -23,7 +23,7 @@ extern "C" { #endif -// TODO: IDF-5719 +// TODO: IDF-7791 /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter diff --git a/components/soc/esp32p4/include/soc/rtc.h b/components/soc/esp32p4/include/soc/rtc.h index 407e6d636e..a27bacea55 100644 --- a/components/soc/esp32p4/include/soc/rtc.h +++ b/components/soc/esp32p4/include/soc/rtc.h @@ -51,7 +51,7 @@ extern "C" { #define OTHER_BLOCKS_POWERUP 1 #define OTHER_BLOCKS_WAIT 1 -// TODO: IDF-5781 +// TODO: IDF-7528, TODO: IDF-7529 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. */ @@ -75,7 +75,7 @@ extern "C" { #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 #define SOC_DELAY_RC32K_ENABLE 300 -/* Core voltage: // TODO: IDF-5781 +/* Core voltage: // TODO: IDF-7528, TODO: IDF-7529 * Currently, ESP32C6 never adjust its wake voltage in runtime * Only sets dig/rtc voltage dbias at startup time */ diff --git a/components/soc/esp32p4/include/soc/rtc_io_channel.h b/components/soc/esp32p4/include/soc/rtc_io_channel.h index a3e2090e3b..d2aa55b41e 100644 --- a/components/soc/esp32p4/include/soc/rtc_io_channel.h +++ b/components/soc/esp32p4/include/soc/rtc_io_channel.h @@ -5,28 +5,3 @@ */ #pragma once - -//RTC GPIO channels -#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0 -#define RTCIO_CHANNEL_0_GPIO_NUM 0 - -#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1 -#define RTCIO_CHANNEL_1_GPIO_NUM 1 - -#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2 -#define RTCIO_CHANNEL_2_GPIO_NUM 2 - -#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3 -#define RTCIO_CHANNEL_3_GPIO_NUM 3 - -#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4 -#define RTCIO_CHANNEL_4_GPIO_NUM 4 - -#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5 -#define RTCIO_CHANNEL_5_GPIO_NUM 5 - -#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6 -#define RTCIO_CHANNEL_6_GPIO_NUM 6 - -#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7 -#define RTCIO_CHANNEL_7_GPIO_NUM 7 diff --git a/components/soc/esp32p4/include/soc/rtc_io_reg.h b/components/soc/esp32p4/include/soc/rtc_io_reg.h index a687a96dec..c053494821 100644 --- a/components/soc/esp32p4/include/soc/rtc_io_reg.h +++ b/components/soc/esp32p4/include/soc/rtc_io_reg.h @@ -5,4 +5,5 @@ */ #pragma once -#include "soc/lp_io_reg.h" +#include "soc/lp_gpio_reg.h" +#include "soc/lp_iomux_reg.h" diff --git a/components/soc/esp32p4/include/soc/rtc_io_struct.h b/components/soc/esp32p4/include/soc/rtc_io_struct.h index 67de8aadad..5e314ff7d8 100644 --- a/components/soc/esp32p4/include/soc/rtc_io_struct.h +++ b/components/soc/esp32p4/include/soc/rtc_io_struct.h @@ -5,14 +5,14 @@ */ #pragma once -#include "soc/lp_io_struct.h" +#include "soc/lp_gpio_struct.h" #ifdef __cplusplus extern "C" { #endif -typedef lp_io_dev_t rtc_io_dev_t; -#define RTCIO LP_IO +typedef lp_gpio_dev_t rtc_io_dev_t; +#define RTCIO LP_GPIO #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/sdio_slave_pins.h b/components/soc/esp32p4/include/soc/sdio_slave_pins.h deleted file mode 100644 index e7f4d11db2..0000000000 --- a/components/soc/esp32p4/include/soc/sdio_slave_pins.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD 18 -#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK 19 -#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0 20 -#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1 21 -#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2 22 -#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3 23 -#define SDIO_SLAVE_SLOT0_FUNC 0 diff --git a/components/soc/esp32p4/include/soc/sdmmc_pins.h b/components/soc/esp32p4/include/soc/sdmmc_pins.h index 1399d210fb..2a5810ff32 100644 --- a/components/soc/esp32p4/include/soc/sdmmc_pins.h +++ b/components/soc/esp32p4/include/soc/sdmmc_pins.h @@ -1,34 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SDMMC_PINS_H_ -#define _SOC_SDMMC_PINS_H_ - -#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 39 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 40 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 41 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 42 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 43 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 44 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 45 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5 46 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6 47 -#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7 48 -#define SDMMC_SLOT0_FUNC 0 - -#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK 53 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD 54 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0 55 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1 56 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2 57 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3 58 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D4 59 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D5 60 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D6 61 -#define SDMMC_SLOT1_IOMUX_PIN_NUM_D7 62 -#define SDMMC_SLOT1_FUNC 0 - -#endif /* _SOC_SDMMC_PINS_H_ */ +#pragma once diff --git a/components/soc/esp32p4/include/soc/slc_reg.h b/components/soc/esp32p4/include/soc/slc_reg.h deleted file mode 100644 index d47cf53dbe..0000000000 --- a/components/soc/esp32p4/include/soc/slc_reg.h +++ /dev/null @@ -1,4301 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SDIO_SLCCONF0_REG register - * ******* Description *********** - */ -#define SDIO_SLCCONF0_REG (DR_REG_SLC_BASE + 0x0) -/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0; - * Set 1 to reset tx fsm in dma slc0. - */ -#define SDIO_SLC0_TX_RST (BIT(0)) -#define SDIO_SLC0_TX_RST_M (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S) -#define SDIO_SLC0_TX_RST_V 0x00000001U -#define SDIO_SLC0_TX_RST_S 0 -/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0; - * Set 1 to reset rx fsm in dma slc0. - */ -#define SDIO_SLC0_RX_RST (BIT(1)) -#define SDIO_SLC0_RX_RST_M (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S) -#define SDIO_SLC0_RX_RST_V 0x00000001U -#define SDIO_SLC0_RX_RST_S 1 -/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; - * reset the command fifo of AHB bus of sdio slave - */ -#define SDIO_SLC_AHBM_FIFO_RST (BIT(2)) -#define SDIO_SLC_AHBM_FIFO_RST_M (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S) -#define SDIO_SLC_AHBM_FIFO_RST_V 0x00000001U -#define SDIO_SLC_AHBM_FIFO_RST_S 2 -/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0; - * reset the AHB bus of sdio slave - */ -#define SDIO_SLC_AHBM_RST (BIT(3)) -#define SDIO_SLC_AHBM_RST_M (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S) -#define SDIO_SLC_AHBM_RST_V 0x00000001U -#define SDIO_SLC_AHBM_RST_S 3 -/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0; - * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. - */ -#define SDIO_SLC0_TX_LOOP_TEST (BIT(4)) -#define SDIO_SLC0_TX_LOOP_TEST_M (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S) -#define SDIO_SLC0_TX_LOOP_TEST_V 0x00000001U -#define SDIO_SLC0_TX_LOOP_TEST_S 4 -/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0; - * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. - */ -#define SDIO_SLC0_RX_LOOP_TEST (BIT(5)) -#define SDIO_SLC0_RX_LOOP_TEST_M (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S) -#define SDIO_SLC0_RX_LOOP_TEST_V 0x00000001U -#define SDIO_SLC0_RX_LOOP_TEST_S 5 -/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; - * Set 1 to enable change the owner bit of rx link descriptor - */ -#define SDIO_SLC0_RX_AUTO_WRBACK (BIT(6)) -#define SDIO_SLC0_RX_AUTO_WRBACK_M (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S) -#define SDIO_SLC0_RX_AUTO_WRBACK_V 0x00000001U -#define SDIO_SLC0_RX_AUTO_WRBACK_S 6 -/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_NO_RESTART_CLR (BIT(7)) -#define SDIO_SLC0_RX_NO_RESTART_CLR_M (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S) -#define SDIO_SLC0_RX_NO_RESTART_CLR_V 0x00000001U -#define SDIO_SLC0_RX_NO_RESTART_CLR_S 7 -/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1; - * 0- AHB burst type is single when slave read rx-descriptor from memory through - * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory - * through slc0 - */ -#define SDIO_SLC0_RXDSCR_BURST_EN (BIT(8)) -#define SDIO_SLC0_RXDSCR_BURST_EN_M (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S) -#define SDIO_SLC0_RXDSCR_BURST_EN_V 0x00000001U -#define SDIO_SLC0_RXDSCR_BURST_EN_S 8 -/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1; - * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type - * is not single when slave receives data from memory - */ -#define SDIO_SLC0_RXDATA_BURST_EN (BIT(9)) -#define SDIO_SLC0_RXDATA_BURST_EN_M (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S) -#define SDIO_SLC0_RXDATA_BURST_EN_V 0x00000001U -#define SDIO_SLC0_RXDATA_BURST_EN_S 9 -/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1; - * enable the function that when host reading packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ -#define SDIO_SLC0_RXLINK_AUTO_RET (BIT(10)) -#define SDIO_SLC0_RXLINK_AUTO_RET_M (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S) -#define SDIO_SLC0_RXLINK_AUTO_RET_V 0x00000001U -#define SDIO_SLC0_RXLINK_AUTO_RET_S 10 -/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1; - * enable the function that when host sending packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ -#define SDIO_SLC0_TXLINK_AUTO_RET (BIT(11)) -#define SDIO_SLC0_TXLINK_AUTO_RET_M (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S) -#define SDIO_SLC0_TXLINK_AUTO_RET_V 0x00000001U -#define SDIO_SLC0_TXLINK_AUTO_RET_S 11 -/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1; - * 0- AHB burst type is single when slave read tx-descriptor from memory through - * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory - * through slc0 - */ -#define SDIO_SLC0_TXDSCR_BURST_EN (BIT(12)) -#define SDIO_SLC0_TXDSCR_BURST_EN_M (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S) -#define SDIO_SLC0_TXDSCR_BURST_EN_V 0x00000001U -#define SDIO_SLC0_TXDSCR_BURST_EN_S 12 -/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1; - * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not - * single when slave send data to memory - */ -#define SDIO_SLC0_TXDATA_BURST_EN (BIT(13)) -#define SDIO_SLC0_TXDATA_BURST_EN_M (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S) -#define SDIO_SLC0_TXDATA_BURST_EN_V 0x00000001U -#define SDIO_SLC0_TXDATA_BURST_EN_S 13 -/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1; - * auto clear slc0_token1 enable - */ -#define SDIO_SLC0_TOKEN_AUTO_CLR (BIT(14)) -#define SDIO_SLC0_TOKEN_AUTO_CLR_M (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S) -#define SDIO_SLC0_TOKEN_AUTO_CLR_V 0x00000001U -#define SDIO_SLC0_TOKEN_AUTO_CLR_S 14 -/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1; - * reserved - */ -#define SDIO_SLC0_TOKEN_SEL (BIT(15)) -#define SDIO_SLC0_TOKEN_SEL_M (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S) -#define SDIO_SLC0_TOKEN_SEL_V 0x00000001U -#define SDIO_SLC0_TOKEN_SEL_S 15 -/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0; - * Set 1 to reset tx fsm in dma slc0. - */ -#define SDIO_SLC1_TX_RST (BIT(16)) -#define SDIO_SLC1_TX_RST_M (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S) -#define SDIO_SLC1_TX_RST_V 0x00000001U -#define SDIO_SLC1_TX_RST_S 16 -/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0; - * Set 1 to reset rx fsm in dma slc0. - */ -#define SDIO_SLC1_RX_RST (BIT(17)) -#define SDIO_SLC1_RX_RST_M (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S) -#define SDIO_SLC1_RX_RST_V 0x00000001U -#define SDIO_SLC1_RX_RST_S 17 -/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1; - * reserved - */ -#define SDIO_SLC0_WR_RETRY_MASK_EN (BIT(18)) -#define SDIO_SLC0_WR_RETRY_MASK_EN_M (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S) -#define SDIO_SLC0_WR_RETRY_MASK_EN_V 0x00000001U -#define SDIO_SLC0_WR_RETRY_MASK_EN_S 18 -/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1; - * reserved - */ -#define SDIO_SLC1_WR_RETRY_MASK_EN (BIT(19)) -#define SDIO_SLC1_WR_RETRY_MASK_EN_M (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S) -#define SDIO_SLC1_WR_RETRY_MASK_EN_V 0x00000001U -#define SDIO_SLC1_WR_RETRY_MASK_EN_S 19 -/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1; - * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. - */ -#define SDIO_SLC1_TX_LOOP_TEST (BIT(20)) -#define SDIO_SLC1_TX_LOOP_TEST_M (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S) -#define SDIO_SLC1_TX_LOOP_TEST_V 0x00000001U -#define SDIO_SLC1_TX_LOOP_TEST_S 20 -/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1; - * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. - */ -#define SDIO_SLC1_RX_LOOP_TEST (BIT(21)) -#define SDIO_SLC1_RX_LOOP_TEST_M (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S) -#define SDIO_SLC1_RX_LOOP_TEST_V 0x00000001U -#define SDIO_SLC1_RX_LOOP_TEST_S 21 -/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0; - * Set 1 to enable change the owner bit of rx link descriptor - */ -#define SDIO_SLC1_RX_AUTO_WRBACK (BIT(22)) -#define SDIO_SLC1_RX_AUTO_WRBACK_M (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S) -#define SDIO_SLC1_RX_AUTO_WRBACK_V 0x00000001U -#define SDIO_SLC1_RX_AUTO_WRBACK_S 22 -/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0; - * ******* Description *********** - */ -#define SDIO_SLC1_RX_NO_RESTART_CLR (BIT(23)) -#define SDIO_SLC1_RX_NO_RESTART_CLR_M (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S) -#define SDIO_SLC1_RX_NO_RESTART_CLR_V 0x00000001U -#define SDIO_SLC1_RX_NO_RESTART_CLR_S 23 -/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1; - * 0- AHB burst type is single when slave read rx-descriptor from memory through - * slc1,1-AHB burst type is not single when slave read rx-descriptor from memory - * through slc1 - */ -#define SDIO_SLC1_RXDSCR_BURST_EN (BIT(24)) -#define SDIO_SLC1_RXDSCR_BURST_EN_M (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S) -#define SDIO_SLC1_RXDSCR_BURST_EN_V 0x00000001U -#define SDIO_SLC1_RXDSCR_BURST_EN_S 24 -/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1; - * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type - * is not single when slave receives data from memory - */ -#define SDIO_SLC1_RXDATA_BURST_EN (BIT(25)) -#define SDIO_SLC1_RXDATA_BURST_EN_M (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S) -#define SDIO_SLC1_RXDATA_BURST_EN_V 0x00000001U -#define SDIO_SLC1_RXDATA_BURST_EN_S 25 -/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1; - * enable the function that when host reading packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ -#define SDIO_SLC1_RXLINK_AUTO_RET (BIT(26)) -#define SDIO_SLC1_RXLINK_AUTO_RET_M (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S) -#define SDIO_SLC1_RXLINK_AUTO_RET_V 0x00000001U -#define SDIO_SLC1_RXLINK_AUTO_RET_S 26 -/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1; - * enable the function that when host sending packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ -#define SDIO_SLC1_TXLINK_AUTO_RET (BIT(27)) -#define SDIO_SLC1_TXLINK_AUTO_RET_M (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S) -#define SDIO_SLC1_TXLINK_AUTO_RET_V 0x00000001U -#define SDIO_SLC1_TXLINK_AUTO_RET_S 27 -/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1; - * 0- AHB burst type is single when slave read tx-descriptor from memory through - * slc1,1-AHB burst type is not single when slave read tx-descriptor from memory - * through slc1 - */ -#define SDIO_SLC1_TXDSCR_BURST_EN (BIT(28)) -#define SDIO_SLC1_TXDSCR_BURST_EN_M (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S) -#define SDIO_SLC1_TXDSCR_BURST_EN_V 0x00000001U -#define SDIO_SLC1_TXDSCR_BURST_EN_S 28 -/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1; - * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not - * single when slave send data to memory - */ -#define SDIO_SLC1_TXDATA_BURST_EN (BIT(29)) -#define SDIO_SLC1_TXDATA_BURST_EN_M (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S) -#define SDIO_SLC1_TXDATA_BURST_EN_V 0x00000001U -#define SDIO_SLC1_TXDATA_BURST_EN_S 29 -/** SDIO_SLC1_TOKEN_AUTO_CLR : R/W; bitpos: [30]; default: 1; - * auto clear slc1_token1 enable - */ -#define SDIO_SLC1_TOKEN_AUTO_CLR (BIT(30)) -#define SDIO_SLC1_TOKEN_AUTO_CLR_M (SDIO_SLC1_TOKEN_AUTO_CLR_V << SDIO_SLC1_TOKEN_AUTO_CLR_S) -#define SDIO_SLC1_TOKEN_AUTO_CLR_V 0x00000001U -#define SDIO_SLC1_TOKEN_AUTO_CLR_S 30 -/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1; - * reserved - */ -#define SDIO_SLC1_TOKEN_SEL (BIT(31)) -#define SDIO_SLC1_TOKEN_SEL_M (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S) -#define SDIO_SLC1_TOKEN_SEL_V 0x00000001U -#define SDIO_SLC1_TOKEN_SEL_S 31 - -/** SDIO_SLC0INT_RAW_REG register - * ******* Description *********** - */ -#define SDIO_SLC0INT_RAW_REG (DR_REG_SLC_BASE + 0x4) -/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT0_INT_RAW (BIT(0)) -#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S 0 -/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT1_INT_RAW (BIT(1)) -#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S 1 -/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT2_INT_RAW (BIT(2)) -#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S 2 -/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT3_INT_RAW (BIT(3)) -#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S 3 -/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT4_INT_RAW (BIT(4)) -#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S 4 -/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT5_INT_RAW (BIT(5)) -#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S 5 -/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT6_INT_RAW (BIT(6)) -#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S 6 -/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT7_INT_RAW (BIT(7)) -#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S 7 -/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_START_INT_RAW (BIT(8)) -#define SDIO_SLC0_RX_START_INT_RAW_M (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S) -#define SDIO_SLC0_RX_START_INT_RAW_V 0x00000001U -#define SDIO_SLC0_RX_START_INT_RAW_S 8 -/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_START_INT_RAW (BIT(9)) -#define SDIO_SLC0_TX_START_INT_RAW_M (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S) -#define SDIO_SLC0_TX_START_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TX_START_INT_RAW_S 9 -/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_UDF_INT_RAW (BIT(10)) -#define SDIO_SLC0_RX_UDF_INT_RAW_M (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S) -#define SDIO_SLC0_RX_UDF_INT_RAW_V 0x00000001U -#define SDIO_SLC0_RX_UDF_INT_RAW_S 10 -/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_OVF_INT_RAW (BIT(11)) -#define SDIO_SLC0_TX_OVF_INT_RAW_M (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S) -#define SDIO_SLC0_TX_OVF_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TX_OVF_INT_RAW_S 11 -/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) -#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S) -#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S 12 -/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) -#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S) -#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S 13 -/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * The raw interrupt bit of slc0 finishing receiving data to one buffer - */ -#define SDIO_SLC0_TX_DONE_INT_RAW (BIT(14)) -#define SDIO_SLC0_TX_DONE_INT_RAW_M (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S) -#define SDIO_SLC0_TX_DONE_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TX_DONE_INT_RAW_S 14 -/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * The raw interrupt bit of slc0 finishing receiving data - */ -#define SDIO_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) -#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S) -#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S 15 -/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * The raw interrupt bit of slc0 finishing sending data from one buffer - */ -#define SDIO_SLC0_RX_DONE_INT_RAW (BIT(16)) -#define SDIO_SLC0_RX_DONE_INT_RAW_M (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S) -#define SDIO_SLC0_RX_DONE_INT_RAW_V 0x00000001U -#define SDIO_SLC0_RX_DONE_INT_RAW_S 16 -/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * The raw interrupt bit of slc0 finishing sending data - */ -#define SDIO_SLC0_RX_EOF_INT_RAW (BIT(17)) -#define SDIO_SLC0_RX_EOF_INT_RAW_M (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S) -#define SDIO_SLC0_RX_EOF_INT_RAW_V 0x00000001U -#define SDIO_SLC0_RX_EOF_INT_RAW_S 17 -/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOHOST_INT_RAW (BIT(18)) -#define SDIO_SLC0_TOHOST_INT_RAW_M (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S) -#define SDIO_SLC0_TOHOST_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TOHOST_INT_RAW_S 18 -/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * The raw interrupt bit of slc0 tx link descriptor error - */ -#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) -#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S) -#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S 19 -/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; - * The raw interrupt bit of slc0 rx link descriptor error - */ -#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) -#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S) -#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V 0x00000001U -#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S 20 -/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 -/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) -#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S) -#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V 0x00000001U -#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S 22 -/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) -#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S) -#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V 0x00000001U -#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S 23 -/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) -#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S) -#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V 0x00000001U -#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S 24 -/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; - * reserved - */ -#define SDIO_CMD_DTC_INT_RAW (BIT(25)) -#define SDIO_CMD_DTC_INT_RAW_M (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S) -#define SDIO_CMD_DTC_INT_RAW_V 0x00000001U -#define SDIO_CMD_DTC_INT_RAW_S 25 -/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) -#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S) -#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V 0x00000001U -#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S 26 -/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x00000001U -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 -/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_HDA_RECV_DONE_INT_RAW (BIT(28)) -#define SDIO_HDA_RECV_DONE_INT_RAW_M (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S) -#define SDIO_HDA_RECV_DONE_INT_RAW_V 0x00000001U -#define SDIO_HDA_RECV_DONE_INT_RAW_S 28 - -/** SDIO_SLC0INT_ST_REG register - * ******* Description *********** - */ -#define SDIO_SLC0INT_ST_REG (DR_REG_SLC_BASE + 0x8) -/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT0_INT_ST (BIT(0)) -#define SDIO_SLC_FRHOST_BIT0_INT_ST_M (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT0_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT0_INT_ST_S 0 -/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT1_INT_ST (BIT(1)) -#define SDIO_SLC_FRHOST_BIT1_INT_ST_M (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT1_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT1_INT_ST_S 1 -/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT2_INT_ST (BIT(2)) -#define SDIO_SLC_FRHOST_BIT2_INT_ST_M (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT2_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT2_INT_ST_S 2 -/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT3_INT_ST (BIT(3)) -#define SDIO_SLC_FRHOST_BIT3_INT_ST_M (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT3_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT3_INT_ST_S 3 -/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT4_INT_ST (BIT(4)) -#define SDIO_SLC_FRHOST_BIT4_INT_ST_M (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT4_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT4_INT_ST_S 4 -/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT5_INT_ST (BIT(5)) -#define SDIO_SLC_FRHOST_BIT5_INT_ST_M (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT5_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT5_INT_ST_S 5 -/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT6_INT_ST (BIT(6)) -#define SDIO_SLC_FRHOST_BIT6_INT_ST_M (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT6_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT6_INT_ST_S 6 -/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT7_INT_ST (BIT(7)) -#define SDIO_SLC_FRHOST_BIT7_INT_ST_M (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT7_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT7_INT_ST_S 7 -/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_START_INT_ST (BIT(8)) -#define SDIO_SLC0_RX_START_INT_ST_M (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S) -#define SDIO_SLC0_RX_START_INT_ST_V 0x00000001U -#define SDIO_SLC0_RX_START_INT_ST_S 8 -/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_START_INT_ST (BIT(9)) -#define SDIO_SLC0_TX_START_INT_ST_M (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S) -#define SDIO_SLC0_TX_START_INT_ST_V 0x00000001U -#define SDIO_SLC0_TX_START_INT_ST_S 9 -/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_UDF_INT_ST (BIT(10)) -#define SDIO_SLC0_RX_UDF_INT_ST_M (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S) -#define SDIO_SLC0_RX_UDF_INT_ST_V 0x00000001U -#define SDIO_SLC0_RX_UDF_INT_ST_S 10 -/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_OVF_INT_ST (BIT(11)) -#define SDIO_SLC0_TX_OVF_INT_ST_M (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S) -#define SDIO_SLC0_TX_OVF_INT_ST_V 0x00000001U -#define SDIO_SLC0_TX_OVF_INT_ST_S 11 -/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S 12 -/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S 13 -/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DONE_INT_ST (BIT(14)) -#define SDIO_SLC0_TX_DONE_INT_ST_M (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S) -#define SDIO_SLC0_TX_DONE_INT_ST_V 0x00000001U -#define SDIO_SLC0_TX_DONE_INT_ST_S 14 -/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) -#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S) -#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V 0x00000001U -#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S 15 -/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DONE_INT_ST (BIT(16)) -#define SDIO_SLC0_RX_DONE_INT_ST_M (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S) -#define SDIO_SLC0_RX_DONE_INT_ST_V 0x00000001U -#define SDIO_SLC0_RX_DONE_INT_ST_S 16 -/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_EOF_INT_ST (BIT(17)) -#define SDIO_SLC0_RX_EOF_INT_ST_M (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S) -#define SDIO_SLC0_RX_EOF_INT_ST_V 0x00000001U -#define SDIO_SLC0_RX_EOF_INT_ST_S 17 -/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOHOST_INT_ST (BIT(18)) -#define SDIO_SLC0_TOHOST_INT_ST_M (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S) -#define SDIO_SLC0_TOHOST_INT_ST_V 0x00000001U -#define SDIO_SLC0_TOHOST_INT_ST_S 18 -/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S 19 -/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V 0x00000001U -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S 20 -/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 -/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) -#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S) -#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V 0x00000001U -#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S 22 -/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V 0x00000001U -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S 23 -/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) -#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S) -#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V 0x00000001U -#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S 24 -/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0; - * reserved - */ -#define SDIO_CMD_DTC_INT_ST (BIT(25)) -#define SDIO_CMD_DTC_INT_ST_M (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S) -#define SDIO_CMD_DTC_INT_ST_V 0x00000001U -#define SDIO_CMD_DTC_INT_ST_S 25 -/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V 0x00000001U -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S 26 -/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x00000001U -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 -/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_HDA_RECV_DONE_INT_ST (BIT(28)) -#define SDIO_HDA_RECV_DONE_INT_ST_M (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S) -#define SDIO_HDA_RECV_DONE_INT_ST_V 0x00000001U -#define SDIO_HDA_RECV_DONE_INT_ST_S 28 - -/** SDIO_SLC0INT_ENA_REG register - * ******* Description *********** - */ -#define SDIO_SLC0INT_ENA_REG (DR_REG_SLC_BASE + 0xc) -/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT0_INT_ENA (BIT(0)) -#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S 0 -/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT1_INT_ENA (BIT(1)) -#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S 1 -/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT2_INT_ENA (BIT(2)) -#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S 2 -/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT3_INT_ENA (BIT(3)) -#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S 3 -/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT4_INT_ENA (BIT(4)) -#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S 4 -/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT5_INT_ENA (BIT(5)) -#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S 5 -/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT6_INT_ENA (BIT(6)) -#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S 6 -/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT7_INT_ENA (BIT(7)) -#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S 7 -/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_START_INT_ENA (BIT(8)) -#define SDIO_SLC0_RX_START_INT_ENA_M (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S) -#define SDIO_SLC0_RX_START_INT_ENA_V 0x00000001U -#define SDIO_SLC0_RX_START_INT_ENA_S 8 -/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_START_INT_ENA (BIT(9)) -#define SDIO_SLC0_TX_START_INT_ENA_M (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S) -#define SDIO_SLC0_TX_START_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TX_START_INT_ENA_S 9 -/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_UDF_INT_ENA (BIT(10)) -#define SDIO_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S) -#define SDIO_SLC0_RX_UDF_INT_ENA_V 0x00000001U -#define SDIO_SLC0_RX_UDF_INT_ENA_S 10 -/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_OVF_INT_ENA (BIT(11)) -#define SDIO_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S) -#define SDIO_SLC0_TX_OVF_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TX_OVF_INT_ENA_S 11 -/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S 12 -/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S 13 -/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DONE_INT_ENA (BIT(14)) -#define SDIO_SLC0_TX_DONE_INT_ENA_M (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S) -#define SDIO_SLC0_TX_DONE_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TX_DONE_INT_ENA_S 14 -/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S) -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S 15 -/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DONE_INT_ENA (BIT(16)) -#define SDIO_SLC0_RX_DONE_INT_ENA_M (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S) -#define SDIO_SLC0_RX_DONE_INT_ENA_V 0x00000001U -#define SDIO_SLC0_RX_DONE_INT_ENA_S 16 -/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_EOF_INT_ENA (BIT(17)) -#define SDIO_SLC0_RX_EOF_INT_ENA_M (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S) -#define SDIO_SLC0_RX_EOF_INT_ENA_V 0x00000001U -#define SDIO_SLC0_RX_EOF_INT_ENA_S 17 -/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOHOST_INT_ENA (BIT(18)) -#define SDIO_SLC0_TOHOST_INT_ENA_M (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S) -#define SDIO_SLC0_TOHOST_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TOHOST_INT_ENA_S 18 -/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S 19 -/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V 0x00000001U -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S 20 -/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 -/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S) -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V 0x00000001U -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S 22 -/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V 0x00000001U -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S 23 -/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S) -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V 0x00000001U -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S 24 -/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0; - * reserved - */ -#define SDIO_CMD_DTC_INT_ENA (BIT(25)) -#define SDIO_CMD_DTC_INT_ENA_M (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S) -#define SDIO_CMD_DTC_INT_ENA_V 0x00000001U -#define SDIO_CMD_DTC_INT_ENA_S 25 -/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V 0x00000001U -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S 26 -/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x00000001U -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 -/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_HDA_RECV_DONE_INT_ENA (BIT(28)) -#define SDIO_HDA_RECV_DONE_INT_ENA_M (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S) -#define SDIO_HDA_RECV_DONE_INT_ENA_V 0x00000001U -#define SDIO_HDA_RECV_DONE_INT_ENA_S 28 - -/** SDIO_SLC0INT_CLR_REG register - * ******* Description *********** - */ -#define SDIO_SLC0INT_CLR_REG (DR_REG_SLC_BASE + 0x10) -/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT0_INT_CLR (BIT(0)) -#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S 0 -/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT1_INT_CLR (BIT(1)) -#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S 1 -/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT2_INT_CLR (BIT(2)) -#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S 2 -/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT3_INT_CLR (BIT(3)) -#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S 3 -/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT4_INT_CLR (BIT(4)) -#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S 4 -/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT5_INT_CLR (BIT(5)) -#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S 5 -/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT6_INT_CLR (BIT(6)) -#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S 6 -/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT7_INT_CLR (BIT(7)) -#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S 7 -/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_START_INT_CLR (BIT(8)) -#define SDIO_SLC0_RX_START_INT_CLR_M (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S) -#define SDIO_SLC0_RX_START_INT_CLR_V 0x00000001U -#define SDIO_SLC0_RX_START_INT_CLR_S 8 -/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_START_INT_CLR (BIT(9)) -#define SDIO_SLC0_TX_START_INT_CLR_M (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S) -#define SDIO_SLC0_TX_START_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TX_START_INT_CLR_S 9 -/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_UDF_INT_CLR (BIT(10)) -#define SDIO_SLC0_RX_UDF_INT_CLR_M (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S) -#define SDIO_SLC0_RX_UDF_INT_CLR_V 0x00000001U -#define SDIO_SLC0_RX_UDF_INT_CLR_S 10 -/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_OVF_INT_CLR (BIT(11)) -#define SDIO_SLC0_TX_OVF_INT_CLR_M (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S) -#define SDIO_SLC0_TX_OVF_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TX_OVF_INT_CLR_S 11 -/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) -#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S) -#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S 12 -/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) -#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S) -#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S 13 -/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DONE_INT_CLR (BIT(14)) -#define SDIO_SLC0_TX_DONE_INT_CLR_M (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S) -#define SDIO_SLC0_TX_DONE_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TX_DONE_INT_CLR_S 14 -/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) -#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S) -#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S 15 -/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DONE_INT_CLR (BIT(16)) -#define SDIO_SLC0_RX_DONE_INT_CLR_M (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S) -#define SDIO_SLC0_RX_DONE_INT_CLR_V 0x00000001U -#define SDIO_SLC0_RX_DONE_INT_CLR_S 16 -/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_EOF_INT_CLR (BIT(17)) -#define SDIO_SLC0_RX_EOF_INT_CLR_M (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S) -#define SDIO_SLC0_RX_EOF_INT_CLR_V 0x00000001U -#define SDIO_SLC0_RX_EOF_INT_CLR_S 17 -/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOHOST_INT_CLR (BIT(18)) -#define SDIO_SLC0_TOHOST_INT_CLR_M (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S) -#define SDIO_SLC0_TOHOST_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TOHOST_INT_CLR_S 18 -/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) -#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S) -#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S 19 -/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) -#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S) -#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V 0x00000001U -#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S 20 -/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 -/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) -#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S) -#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V 0x00000001U -#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S 22 -/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) -#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S) -#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V 0x00000001U -#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S 23 -/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) -#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S) -#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V 0x00000001U -#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S 24 -/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0; - * reserved - */ -#define SDIO_CMD_DTC_INT_CLR (BIT(25)) -#define SDIO_CMD_DTC_INT_CLR_M (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S) -#define SDIO_CMD_DTC_INT_CLR_V 0x00000001U -#define SDIO_CMD_DTC_INT_CLR_S 25 -/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) -#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S) -#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V 0x00000001U -#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S 26 -/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x00000001U -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 -/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_HDA_RECV_DONE_INT_CLR (BIT(28)) -#define SDIO_HDA_RECV_DONE_INT_CLR_M (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S) -#define SDIO_HDA_RECV_DONE_INT_CLR_V 0x00000001U -#define SDIO_HDA_RECV_DONE_INT_CLR_S 28 - -/** SDIO_SLC1INT_RAW_REG register - * reserved - */ -#define SDIO_SLC1INT_RAW_REG (DR_REG_SLC_BASE + 0x14) -/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT8_INT_RAW (BIT(0)) -#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S 0 -/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT9_INT_RAW (BIT(1)) -#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S 1 -/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT10_INT_RAW (BIT(2)) -#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S 2 -/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT11_INT_RAW (BIT(3)) -#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S 3 -/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT12_INT_RAW (BIT(4)) -#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S 4 -/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT13_INT_RAW (BIT(5)) -#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S 5 -/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT14_INT_RAW (BIT(6)) -#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S 6 -/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT15_INT_RAW (BIT(7)) -#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S) -#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S 7 -/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_START_INT_RAW (BIT(8)) -#define SDIO_SLC1_RX_START_INT_RAW_M (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S) -#define SDIO_SLC1_RX_START_INT_RAW_V 0x00000001U -#define SDIO_SLC1_RX_START_INT_RAW_S 8 -/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_START_INT_RAW (BIT(9)) -#define SDIO_SLC1_TX_START_INT_RAW_M (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S) -#define SDIO_SLC1_TX_START_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TX_START_INT_RAW_S 9 -/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_UDF_INT_RAW (BIT(10)) -#define SDIO_SLC1_RX_UDF_INT_RAW_M (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S) -#define SDIO_SLC1_RX_UDF_INT_RAW_V 0x00000001U -#define SDIO_SLC1_RX_UDF_INT_RAW_S 10 -/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_OVF_INT_RAW (BIT(11)) -#define SDIO_SLC1_TX_OVF_INT_RAW_M (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S) -#define SDIO_SLC1_TX_OVF_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TX_OVF_INT_RAW_S 11 -/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12)) -#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S) -#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S 12 -/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13)) -#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S) -#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S 13 -/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DONE_INT_RAW (BIT(14)) -#define SDIO_SLC1_TX_DONE_INT_RAW_M (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S) -#define SDIO_SLC1_TX_DONE_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TX_DONE_INT_RAW_S 14 -/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_SUC_EOF_INT_RAW (BIT(15)) -#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S) -#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S 15 -/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DONE_INT_RAW (BIT(16)) -#define SDIO_SLC1_RX_DONE_INT_RAW_M (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S) -#define SDIO_SLC1_RX_DONE_INT_RAW_V 0x00000001U -#define SDIO_SLC1_RX_DONE_INT_RAW_S 16 -/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_EOF_INT_RAW (BIT(17)) -#define SDIO_SLC1_RX_EOF_INT_RAW_M (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S) -#define SDIO_SLC1_RX_EOF_INT_RAW_V 0x00000001U -#define SDIO_SLC1_RX_EOF_INT_RAW_S 17 -/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOHOST_INT_RAW (BIT(18)) -#define SDIO_SLC1_TOHOST_INT_RAW_M (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S) -#define SDIO_SLC1_TOHOST_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TOHOST_INT_RAW_S 18 -/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19)) -#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S) -#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S 19 -/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20)) -#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S) -#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V 0x00000001U -#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S 20 -/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21)) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21 -/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC1_HOST_RD_ACK_INT_RAW (BIT(22)) -#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S) -#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V 0x00000001U -#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S 22 -/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23)) -#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S) -#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V 0x00000001U -#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S 23 -/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_ERR_EOF_INT_RAW (BIT(24)) -#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S) -#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V 0x00000001U -#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S 24 - -/** SDIO_SLC1INT_ST_REG register - * reserved - */ -#define SDIO_SLC1INT_ST_REG (DR_REG_SLC_BASE + 0x18) -/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT8_INT_ST (BIT(0)) -#define SDIO_SLC_FRHOST_BIT8_INT_ST_M (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT8_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT8_INT_ST_S 0 -/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT9_INT_ST (BIT(1)) -#define SDIO_SLC_FRHOST_BIT9_INT_ST_M (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT9_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT9_INT_ST_S 1 -/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT10_INT_ST (BIT(2)) -#define SDIO_SLC_FRHOST_BIT10_INT_ST_M (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT10_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT10_INT_ST_S 2 -/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT11_INT_ST (BIT(3)) -#define SDIO_SLC_FRHOST_BIT11_INT_ST_M (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT11_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT11_INT_ST_S 3 -/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT12_INT_ST (BIT(4)) -#define SDIO_SLC_FRHOST_BIT12_INT_ST_M (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT12_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT12_INT_ST_S 4 -/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT13_INT_ST (BIT(5)) -#define SDIO_SLC_FRHOST_BIT13_INT_ST_M (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT13_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT13_INT_ST_S 5 -/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT14_INT_ST (BIT(6)) -#define SDIO_SLC_FRHOST_BIT14_INT_ST_M (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT14_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT14_INT_ST_S 6 -/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT15_INT_ST (BIT(7)) -#define SDIO_SLC_FRHOST_BIT15_INT_ST_M (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S) -#define SDIO_SLC_FRHOST_BIT15_INT_ST_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT15_INT_ST_S 7 -/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_START_INT_ST (BIT(8)) -#define SDIO_SLC1_RX_START_INT_ST_M (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S) -#define SDIO_SLC1_RX_START_INT_ST_V 0x00000001U -#define SDIO_SLC1_RX_START_INT_ST_S 8 -/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_START_INT_ST (BIT(9)) -#define SDIO_SLC1_TX_START_INT_ST_M (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S) -#define SDIO_SLC1_TX_START_INT_ST_V 0x00000001U -#define SDIO_SLC1_TX_START_INT_ST_S 9 -/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_UDF_INT_ST (BIT(10)) -#define SDIO_SLC1_RX_UDF_INT_ST_M (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S) -#define SDIO_SLC1_RX_UDF_INT_ST_V 0x00000001U -#define SDIO_SLC1_RX_UDF_INT_ST_S 10 -/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_OVF_INT_ST (BIT(11)) -#define SDIO_SLC1_TX_OVF_INT_ST_M (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S) -#define SDIO_SLC1_TX_OVF_INT_ST_V 0x00000001U -#define SDIO_SLC1_TX_OVF_INT_ST_S 11 -/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST (BIT(12)) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S 12 -/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST (BIT(13)) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S 13 -/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DONE_INT_ST (BIT(14)) -#define SDIO_SLC1_TX_DONE_INT_ST_M (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S) -#define SDIO_SLC1_TX_DONE_INT_ST_V 0x00000001U -#define SDIO_SLC1_TX_DONE_INT_ST_S 14 -/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_SUC_EOF_INT_ST (BIT(15)) -#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S) -#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V 0x00000001U -#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S 15 -/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DONE_INT_ST (BIT(16)) -#define SDIO_SLC1_RX_DONE_INT_ST_M (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S) -#define SDIO_SLC1_RX_DONE_INT_ST_V 0x00000001U -#define SDIO_SLC1_RX_DONE_INT_ST_S 16 -/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_EOF_INT_ST (BIT(17)) -#define SDIO_SLC1_RX_EOF_INT_ST_M (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S) -#define SDIO_SLC1_RX_EOF_INT_ST_V 0x00000001U -#define SDIO_SLC1_RX_EOF_INT_ST_S 17 -/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOHOST_INT_ST (BIT(18)) -#define SDIO_SLC1_TOHOST_INT_ST_M (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S) -#define SDIO_SLC1_TOHOST_INT_ST_V 0x00000001U -#define SDIO_SLC1_TOHOST_INT_ST_S 18 -/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST (BIT(19)) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S 19 -/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST (BIT(20)) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V 0x00000001U -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S 20 -/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21)) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S 21 -/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC1_HOST_RD_ACK_INT_ST (BIT(22)) -#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S) -#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V 0x00000001U -#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S 22 -/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST (BIT(23)) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V 0x00000001U -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S 23 -/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_ERR_EOF_INT_ST (BIT(24)) -#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S) -#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V 0x00000001U -#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S 24 - -/** SDIO_SLC1INT_ENA_REG register - * reserved - */ -#define SDIO_SLC1INT_ENA_REG (DR_REG_SLC_BASE + 0x1c) -/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT8_INT_ENA (BIT(0)) -#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S 0 -/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT9_INT_ENA (BIT(1)) -#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S 1 -/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT10_INT_ENA (BIT(2)) -#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S 2 -/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT11_INT_ENA (BIT(3)) -#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S 3 -/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT12_INT_ENA (BIT(4)) -#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S 4 -/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT13_INT_ENA (BIT(5)) -#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S 5 -/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT14_INT_ENA (BIT(6)) -#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S 6 -/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT15_INT_ENA (BIT(7)) -#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S) -#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S 7 -/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_START_INT_ENA (BIT(8)) -#define SDIO_SLC1_RX_START_INT_ENA_M (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S) -#define SDIO_SLC1_RX_START_INT_ENA_V 0x00000001U -#define SDIO_SLC1_RX_START_INT_ENA_S 8 -/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_START_INT_ENA (BIT(9)) -#define SDIO_SLC1_TX_START_INT_ENA_M (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S) -#define SDIO_SLC1_TX_START_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TX_START_INT_ENA_S 9 -/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_UDF_INT_ENA (BIT(10)) -#define SDIO_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S) -#define SDIO_SLC1_RX_UDF_INT_ENA_V 0x00000001U -#define SDIO_SLC1_RX_UDF_INT_ENA_S 10 -/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_OVF_INT_ENA (BIT(11)) -#define SDIO_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S) -#define SDIO_SLC1_TX_OVF_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TX_OVF_INT_ENA_S 11 -/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12)) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S 12 -/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13)) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S 13 -/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DONE_INT_ENA (BIT(14)) -#define SDIO_SLC1_TX_DONE_INT_ENA_M (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S) -#define SDIO_SLC1_TX_DONE_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TX_DONE_INT_ENA_S 14 -/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA (BIT(15)) -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S) -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S 15 -/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DONE_INT_ENA (BIT(16)) -#define SDIO_SLC1_RX_DONE_INT_ENA_M (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S) -#define SDIO_SLC1_RX_DONE_INT_ENA_V 0x00000001U -#define SDIO_SLC1_RX_DONE_INT_ENA_S 16 -/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_EOF_INT_ENA (BIT(17)) -#define SDIO_SLC1_RX_EOF_INT_ENA_M (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S) -#define SDIO_SLC1_RX_EOF_INT_ENA_V 0x00000001U -#define SDIO_SLC1_RX_EOF_INT_ENA_S 17 -/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOHOST_INT_ENA (BIT(18)) -#define SDIO_SLC1_TOHOST_INT_ENA_M (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S) -#define SDIO_SLC1_TOHOST_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TOHOST_INT_ENA_S 18 -/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19)) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S 19 -/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20)) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V 0x00000001U -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S 20 -/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21)) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21 -/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA (BIT(22)) -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S) -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V 0x00000001U -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S 22 -/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23)) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V 0x00000001U -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S 23 -/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA (BIT(24)) -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S) -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V 0x00000001U -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S 24 - -/** SDIO_SLC1INT_CLR_REG register - * reserved - */ -#define SDIO_SLC1INT_CLR_REG (DR_REG_SLC_BASE + 0x20) -/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT8_INT_CLR (BIT(0)) -#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S 0 -/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT9_INT_CLR (BIT(1)) -#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S 1 -/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT10_INT_CLR (BIT(2)) -#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S 2 -/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT11_INT_CLR (BIT(3)) -#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S 3 -/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT12_INT_CLR (BIT(4)) -#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S 4 -/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT13_INT_CLR (BIT(5)) -#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S 5 -/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT14_INT_CLR (BIT(6)) -#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S 6 -/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT15_INT_CLR (BIT(7)) -#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S) -#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S 7 -/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_START_INT_CLR (BIT(8)) -#define SDIO_SLC1_RX_START_INT_CLR_M (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S) -#define SDIO_SLC1_RX_START_INT_CLR_V 0x00000001U -#define SDIO_SLC1_RX_START_INT_CLR_S 8 -/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_START_INT_CLR (BIT(9)) -#define SDIO_SLC1_TX_START_INT_CLR_M (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S) -#define SDIO_SLC1_TX_START_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TX_START_INT_CLR_S 9 -/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_UDF_INT_CLR (BIT(10)) -#define SDIO_SLC1_RX_UDF_INT_CLR_M (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S) -#define SDIO_SLC1_RX_UDF_INT_CLR_V 0x00000001U -#define SDIO_SLC1_RX_UDF_INT_CLR_S 10 -/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_OVF_INT_CLR (BIT(11)) -#define SDIO_SLC1_TX_OVF_INT_CLR_M (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S) -#define SDIO_SLC1_TX_OVF_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TX_OVF_INT_CLR_S 11 -/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12)) -#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S) -#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S 12 -/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13)) -#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S) -#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S 13 -/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DONE_INT_CLR (BIT(14)) -#define SDIO_SLC1_TX_DONE_INT_CLR_M (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S) -#define SDIO_SLC1_TX_DONE_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TX_DONE_INT_CLR_S 14 -/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_SUC_EOF_INT_CLR (BIT(15)) -#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S) -#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S 15 -/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DONE_INT_CLR (BIT(16)) -#define SDIO_SLC1_RX_DONE_INT_CLR_M (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S) -#define SDIO_SLC1_RX_DONE_INT_CLR_V 0x00000001U -#define SDIO_SLC1_RX_DONE_INT_CLR_S 16 -/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_EOF_INT_CLR (BIT(17)) -#define SDIO_SLC1_RX_EOF_INT_CLR_M (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S) -#define SDIO_SLC1_RX_EOF_INT_CLR_V 0x00000001U -#define SDIO_SLC1_RX_EOF_INT_CLR_S 17 -/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOHOST_INT_CLR (BIT(18)) -#define SDIO_SLC1_TOHOST_INT_CLR_M (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S) -#define SDIO_SLC1_TOHOST_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TOHOST_INT_CLR_S 18 -/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19)) -#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S) -#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S 19 -/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20)) -#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S) -#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V 0x00000001U -#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S 20 -/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21)) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21 -/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC1_HOST_RD_ACK_INT_CLR (BIT(22)) -#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S) -#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V 0x00000001U -#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S 22 -/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23)) -#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S) -#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V 0x00000001U -#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S 23 -/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_ERR_EOF_INT_CLR (BIT(24)) -#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S) -#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V 0x00000001U -#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S 24 - -/** SDIO_SLCRX_STATUS_REG register - * ******* Description *********** - */ -#define SDIO_SLCRX_STATUS_REG (DR_REG_SLC_BASE + 0x24) -/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_FULL (BIT(0)) -#define SDIO_SLC0_RX_FULL_M (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S) -#define SDIO_SLC0_RX_FULL_V 0x00000001U -#define SDIO_SLC0_RX_FULL_S 0 -/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1; - * reserved - */ -#define SDIO_SLC0_RX_EMPTY (BIT(1)) -#define SDIO_SLC0_RX_EMPTY_M (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S) -#define SDIO_SLC0_RX_EMPTY_V 0x00000001U -#define SDIO_SLC0_RX_EMPTY_S 1 -/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0; - * the current buffer length when slc0 reads data from rx link - */ -#define SDIO_SLC0_RX_BUF_LEN 0x00003FFFU -#define SDIO_SLC0_RX_BUF_LEN_M (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S) -#define SDIO_SLC0_RX_BUF_LEN_V 0x00003FFFU -#define SDIO_SLC0_RX_BUF_LEN_S 2 -/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_FULL (BIT(16)) -#define SDIO_SLC1_RX_FULL_M (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S) -#define SDIO_SLC1_RX_FULL_V 0x00000001U -#define SDIO_SLC1_RX_FULL_S 16 -/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1; - * reserved - */ -#define SDIO_SLC1_RX_EMPTY (BIT(17)) -#define SDIO_SLC1_RX_EMPTY_M (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S) -#define SDIO_SLC1_RX_EMPTY_V 0x00000001U -#define SDIO_SLC1_RX_EMPTY_S 17 -/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0; - * the current buffer length when slc1 reads data from rx link - */ -#define SDIO_SLC1_RX_BUF_LEN 0x00003FFFU -#define SDIO_SLC1_RX_BUF_LEN_M (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S) -#define SDIO_SLC1_RX_BUF_LEN_V 0x00003FFFU -#define SDIO_SLC1_RX_BUF_LEN_S 18 - -/** SDIO_SLC0RXFIFO_PUSH_REG register - * ******* Description *********** - */ -#define SDIO_SLC0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28) -/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXFIFO_WDATA 0x000001FFU -#define SDIO_SLC0_RXFIFO_WDATA_M (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S) -#define SDIO_SLC0_RXFIFO_WDATA_V 0x000001FFU -#define SDIO_SLC0_RXFIFO_WDATA_S 0 -/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXFIFO_PUSH (BIT(16)) -#define SDIO_SLC0_RXFIFO_PUSH_M (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S) -#define SDIO_SLC0_RXFIFO_PUSH_V 0x00000001U -#define SDIO_SLC0_RXFIFO_PUSH_S 16 - -/** SDIO_SLC1RXFIFO_PUSH_REG register - * reserved - */ -#define SDIO_SLC1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2c) -/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXFIFO_WDATA 0x000001FFU -#define SDIO_SLC1_RXFIFO_WDATA_M (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S) -#define SDIO_SLC1_RXFIFO_WDATA_V 0x000001FFU -#define SDIO_SLC1_RXFIFO_WDATA_S 0 -/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXFIFO_PUSH (BIT(16)) -#define SDIO_SLC1_RXFIFO_PUSH_M (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S) -#define SDIO_SLC1_RXFIFO_PUSH_V 0x00000001U -#define SDIO_SLC1_RXFIFO_PUSH_S 16 - -/** SDIO_SLCTX_STATUS_REG register - * ******* Description *********** - */ -#define SDIO_SLCTX_STATUS_REG (DR_REG_SLC_BASE + 0x30) -/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_FULL (BIT(0)) -#define SDIO_SLC0_TX_FULL_M (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S) -#define SDIO_SLC0_TX_FULL_V 0x00000001U -#define SDIO_SLC0_TX_FULL_S 0 -/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1; - * reserved - */ -#define SDIO_SLC0_TX_EMPTY (BIT(1)) -#define SDIO_SLC0_TX_EMPTY_M (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S) -#define SDIO_SLC0_TX_EMPTY_V 0x00000001U -#define SDIO_SLC0_TX_EMPTY_S 1 -/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_FULL (BIT(16)) -#define SDIO_SLC1_TX_FULL_M (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S) -#define SDIO_SLC1_TX_FULL_V 0x00000001U -#define SDIO_SLC1_TX_FULL_S 16 -/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1; - * reserved - */ -#define SDIO_SLC1_TX_EMPTY (BIT(17)) -#define SDIO_SLC1_TX_EMPTY_M (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S) -#define SDIO_SLC1_TX_EMPTY_V 0x00000001U -#define SDIO_SLC1_TX_EMPTY_S 17 - -/** SDIO_SLC0TXFIFO_POP_REG register - * reserved - */ -#define SDIO_SLC0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34) -/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; - * reserved - */ -#define SDIO_SLC0_TXFIFO_RDATA 0x000007FFU -#define SDIO_SLC0_TXFIFO_RDATA_M (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S) -#define SDIO_SLC0_TXFIFO_RDATA_V 0x000007FFU -#define SDIO_SLC0_TXFIFO_RDATA_S 0 -/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXFIFO_POP (BIT(16)) -#define SDIO_SLC0_TXFIFO_POP_M (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S) -#define SDIO_SLC0_TXFIFO_POP_V 0x00000001U -#define SDIO_SLC0_TXFIFO_POP_S 16 - -/** SDIO_SLC1TXFIFO_POP_REG register - * reserved - */ -#define SDIO_SLC1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38) -/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; - * reserved - */ -#define SDIO_SLC1_TXFIFO_RDATA 0x000007FFU -#define SDIO_SLC1_TXFIFO_RDATA_M (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S) -#define SDIO_SLC1_TXFIFO_RDATA_V 0x000007FFU -#define SDIO_SLC1_TXFIFO_RDATA_S 0 -/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXFIFO_POP (BIT(16)) -#define SDIO_SLC1_TXFIFO_POP_M (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S) -#define SDIO_SLC1_TXFIFO_POP_V 0x00000001U -#define SDIO_SLC1_TXFIFO_POP_S 16 - -/** SDIO_SLC0RX_LINK_REG register - * reserved - */ -#define SDIO_SLC0RX_LINK_REG (DR_REG_SLC_BASE + 0x3c) -/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXLINK_STOP (BIT(28)) -#define SDIO_SLC0_RXLINK_STOP_M (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S) -#define SDIO_SLC0_RXLINK_STOP_V 0x00000001U -#define SDIO_SLC0_RXLINK_STOP_S 28 -/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXLINK_START (BIT(29)) -#define SDIO_SLC0_RXLINK_START_M (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S) -#define SDIO_SLC0_RXLINK_START_V 0x00000001U -#define SDIO_SLC0_RXLINK_START_S 29 -/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXLINK_RESTART (BIT(30)) -#define SDIO_SLC0_RXLINK_RESTART_M (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S) -#define SDIO_SLC0_RXLINK_RESTART_V 0x00000001U -#define SDIO_SLC0_RXLINK_RESTART_S 30 -/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1; - * reserved - */ -#define SDIO_SLC0_RXLINK_PARK (BIT(31)) -#define SDIO_SLC0_RXLINK_PARK_M (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S) -#define SDIO_SLC0_RXLINK_PARK_V 0x00000001U -#define SDIO_SLC0_RXLINK_PARK_S 31 - -/** SDIO_SLC0RX_LINK_ADDR_REG register - * reserved - */ -#define SDIO_SLC0RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x40) -/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXLINK_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_ADDR_M (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S) -#define SDIO_SLC0_RXLINK_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_ADDR_S 0 - -/** SDIO_SLC0TX_LINK_REG register - * reserved - */ -#define SDIO_SLC0TX_LINK_REG (DR_REG_SLC_BASE + 0x44) -/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXLINK_STOP (BIT(28)) -#define SDIO_SLC0_TXLINK_STOP_M (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S) -#define SDIO_SLC0_TXLINK_STOP_V 0x00000001U -#define SDIO_SLC0_TXLINK_STOP_S 28 -/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXLINK_START (BIT(29)) -#define SDIO_SLC0_TXLINK_START_M (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S) -#define SDIO_SLC0_TXLINK_START_V 0x00000001U -#define SDIO_SLC0_TXLINK_START_S 29 -/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXLINK_RESTART (BIT(30)) -#define SDIO_SLC0_TXLINK_RESTART_M (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S) -#define SDIO_SLC0_TXLINK_RESTART_V 0x00000001U -#define SDIO_SLC0_TXLINK_RESTART_S 30 -/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1; - * reserved - */ -#define SDIO_SLC0_TXLINK_PARK (BIT(31)) -#define SDIO_SLC0_TXLINK_PARK_M (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S) -#define SDIO_SLC0_TXLINK_PARK_V 0x00000001U -#define SDIO_SLC0_TXLINK_PARK_S 31 - -/** SDIO_SLC0TX_LINK_ADDR_REG register - * reserved - */ -#define SDIO_SLC0TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x48) -/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXLINK_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_ADDR_M (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S) -#define SDIO_SLC0_TXLINK_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_ADDR_S 0 - -/** SDIO_SLC1RX_LINK_REG register - * reserved - */ -#define SDIO_SLC1RX_LINK_REG (DR_REG_SLC_BASE + 0x4c) -/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1; - * reserved - */ -#define SDIO_SLC1_BT_PACKET (BIT(20)) -#define SDIO_SLC1_BT_PACKET_M (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S) -#define SDIO_SLC1_BT_PACKET_V 0x00000001U -#define SDIO_SLC1_BT_PACKET_S 20 -/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXLINK_STOP (BIT(28)) -#define SDIO_SLC1_RXLINK_STOP_M (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S) -#define SDIO_SLC1_RXLINK_STOP_V 0x00000001U -#define SDIO_SLC1_RXLINK_STOP_S 28 -/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXLINK_START (BIT(29)) -#define SDIO_SLC1_RXLINK_START_M (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S) -#define SDIO_SLC1_RXLINK_START_V 0x00000001U -#define SDIO_SLC1_RXLINK_START_S 29 -/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXLINK_RESTART (BIT(30)) -#define SDIO_SLC1_RXLINK_RESTART_M (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S) -#define SDIO_SLC1_RXLINK_RESTART_V 0x00000001U -#define SDIO_SLC1_RXLINK_RESTART_S 30 -/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1; - * reserved - */ -#define SDIO_SLC1_RXLINK_PARK (BIT(31)) -#define SDIO_SLC1_RXLINK_PARK_M (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S) -#define SDIO_SLC1_RXLINK_PARK_V 0x00000001U -#define SDIO_SLC1_RXLINK_PARK_S 31 - -/** SDIO_SLC1RX_LINK_ADDR_REG register - * reserved - */ -#define SDIO_SLC1RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x50) -/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXLINK_ADDR 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_ADDR_M (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S) -#define SDIO_SLC1_RXLINK_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_ADDR_S 0 - -/** SDIO_SLC1TX_LINK_REG register - * reserved - */ -#define SDIO_SLC1TX_LINK_REG (DR_REG_SLC_BASE + 0x54) -/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXLINK_STOP (BIT(28)) -#define SDIO_SLC1_TXLINK_STOP_M (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S) -#define SDIO_SLC1_TXLINK_STOP_V 0x00000001U -#define SDIO_SLC1_TXLINK_STOP_S 28 -/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXLINK_START (BIT(29)) -#define SDIO_SLC1_TXLINK_START_M (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S) -#define SDIO_SLC1_TXLINK_START_V 0x00000001U -#define SDIO_SLC1_TXLINK_START_S 29 -/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXLINK_RESTART (BIT(30)) -#define SDIO_SLC1_TXLINK_RESTART_M (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S) -#define SDIO_SLC1_TXLINK_RESTART_V 0x00000001U -#define SDIO_SLC1_TXLINK_RESTART_S 30 -/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1; - * reserved - */ -#define SDIO_SLC1_TXLINK_PARK (BIT(31)) -#define SDIO_SLC1_TXLINK_PARK_M (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S) -#define SDIO_SLC1_TXLINK_PARK_V 0x00000001U -#define SDIO_SLC1_TXLINK_PARK_S 31 - -/** SDIO_SLC1TX_LINK_ADDR_REG register - * reserved - */ -#define SDIO_SLC1TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x58) -/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXLINK_ADDR 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_ADDR_M (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S) -#define SDIO_SLC1_TXLINK_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_ADDR_S 0 - -/** SDIO_SLCINTVEC_TOHOST_REG register - * reserved - */ -#define SDIO_SLCINTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x5c) -/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOHOST_INTVEC 0x000000FFU -#define SDIO_SLC0_TOHOST_INTVEC_M (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S) -#define SDIO_SLC0_TOHOST_INTVEC_V 0x000000FFU -#define SDIO_SLC0_TOHOST_INTVEC_S 0 -/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOHOST_INTVEC 0x000000FFU -#define SDIO_SLC1_TOHOST_INTVEC_M (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S) -#define SDIO_SLC1_TOHOST_INTVEC_V 0x000000FFU -#define SDIO_SLC1_TOHOST_INTVEC_S 16 - -/** SDIO_SLC0TOKEN0_REG register - * reserved - */ -#define SDIO_SLC0TOKEN0_REG (DR_REG_SLC_BASE + 0x60) -/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_WDATA 0x00000FFFU -#define SDIO_SLC0_TOKEN0_WDATA_M (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S) -#define SDIO_SLC0_TOKEN0_WDATA_V 0x00000FFFU -#define SDIO_SLC0_TOKEN0_WDATA_S 0 -/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_WR (BIT(12)) -#define SDIO_SLC0_TOKEN0_WR_M (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S) -#define SDIO_SLC0_TOKEN0_WR_V 0x00000001U -#define SDIO_SLC0_TOKEN0_WR_S 12 -/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_INC (BIT(13)) -#define SDIO_SLC0_TOKEN0_INC_M (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S) -#define SDIO_SLC0_TOKEN0_INC_V 0x00000001U -#define SDIO_SLC0_TOKEN0_INC_S 13 -/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_INC_MORE (BIT(14)) -#define SDIO_SLC0_TOKEN0_INC_MORE_M (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S) -#define SDIO_SLC0_TOKEN0_INC_MORE_V 0x00000001U -#define SDIO_SLC0_TOKEN0_INC_MORE_S 14 -/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0 0x00000FFFU -#define SDIO_SLC0_TOKEN0_M (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S) -#define SDIO_SLC0_TOKEN0_V 0x00000FFFU -#define SDIO_SLC0_TOKEN0_S 16 - -/** SDIO_SLC0TOKEN1_REG register - * reserved - */ -#define SDIO_SLC0TOKEN1_REG (DR_REG_SLC_BASE + 0x64) -/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; - * slc0 token1 wdata - */ -#define SDIO_SLC0_TOKEN1_WDATA 0x00000FFFU -#define SDIO_SLC0_TOKEN1_WDATA_M (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S) -#define SDIO_SLC0_TOKEN1_WDATA_V 0x00000FFFU -#define SDIO_SLC0_TOKEN1_WDATA_S 0 -/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0; - * update slc0_token1_wdata into slc0 token1 - */ -#define SDIO_SLC0_TOKEN1_WR (BIT(12)) -#define SDIO_SLC0_TOKEN1_WR_M (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S) -#define SDIO_SLC0_TOKEN1_WR_V 0x00000001U -#define SDIO_SLC0_TOKEN1_WR_S 12 -/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0; - * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 - */ -#define SDIO_SLC0_TOKEN1_INC (BIT(13)) -#define SDIO_SLC0_TOKEN1_INC_M (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S) -#define SDIO_SLC0_TOKEN1_INC_V 0x00000001U -#define SDIO_SLC0_TOKEN1_INC_S 13 -/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; - * slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add - * slc0_token1_wdata to slc0_token1 - */ -#define SDIO_SLC0_TOKEN1_INC_MORE (BIT(14)) -#define SDIO_SLC0_TOKEN1_INC_MORE_M (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S) -#define SDIO_SLC0_TOKEN1_INC_MORE_V 0x00000001U -#define SDIO_SLC0_TOKEN1_INC_MORE_S 14 -/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN1 0x00000FFFU -#define SDIO_SLC0_TOKEN1_M (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S) -#define SDIO_SLC0_TOKEN1_V 0x00000FFFU -#define SDIO_SLC0_TOKEN1_S 16 - -/** SDIO_SLC1TOKEN0_REG register - * ******* Description *********** - */ -#define SDIO_SLC1TOKEN0_REG (DR_REG_SLC_BASE + 0x68) -/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_WDATA 0x00000FFFU -#define SDIO_SLC1_TOKEN0_WDATA_M (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S) -#define SDIO_SLC1_TOKEN0_WDATA_V 0x00000FFFU -#define SDIO_SLC1_TOKEN0_WDATA_S 0 -/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_WR (BIT(12)) -#define SDIO_SLC1_TOKEN0_WR_M (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S) -#define SDIO_SLC1_TOKEN0_WR_V 0x00000001U -#define SDIO_SLC1_TOKEN0_WR_S 12 -/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0; - * Add 1 to slc1_token0 - */ -#define SDIO_SLC1_TOKEN0_INC (BIT(13)) -#define SDIO_SLC1_TOKEN0_INC_M (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S) -#define SDIO_SLC1_TOKEN0_INC_V 0x00000001U -#define SDIO_SLC1_TOKEN0_INC_S 13 -/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; - * Add slc1_token0_wdata to slc1_token0 - */ -#define SDIO_SLC1_TOKEN0_INC_MORE (BIT(14)) -#define SDIO_SLC1_TOKEN0_INC_MORE_M (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S) -#define SDIO_SLC1_TOKEN0_INC_MORE_V 0x00000001U -#define SDIO_SLC1_TOKEN0_INC_MORE_S 14 -/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0 0x00000FFFU -#define SDIO_SLC1_TOKEN0_M (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S) -#define SDIO_SLC1_TOKEN0_V 0x00000FFFU -#define SDIO_SLC1_TOKEN0_S 16 - -/** SDIO_SLC1TOKEN1_REG register - * reserved - */ -#define SDIO_SLC1TOKEN1_REG (DR_REG_SLC_BASE + 0x6c) -/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_WDATA 0x00000FFFU -#define SDIO_SLC1_TOKEN1_WDATA_M (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S) -#define SDIO_SLC1_TOKEN1_WDATA_V 0x00000FFFU -#define SDIO_SLC1_TOKEN1_WDATA_S 0 -/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0; - * update slc1_token1_wdata into slc1 token1 - */ -#define SDIO_SLC1_TOKEN1_WR (BIT(12)) -#define SDIO_SLC1_TOKEN1_WR_M (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S) -#define SDIO_SLC1_TOKEN1_WR_V 0x00000001U -#define SDIO_SLC1_TOKEN1_WR_S 12 -/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_INC (BIT(13)) -#define SDIO_SLC1_TOKEN1_INC_M (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S) -#define SDIO_SLC1_TOKEN1_INC_V 0x00000001U -#define SDIO_SLC1_TOKEN1_INC_S 13 -/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_INC_MORE (BIT(14)) -#define SDIO_SLC1_TOKEN1_INC_MORE_M (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S) -#define SDIO_SLC1_TOKEN1_INC_MORE_V 0x00000001U -#define SDIO_SLC1_TOKEN1_INC_MORE_S 14 -/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1 0x00000FFFU -#define SDIO_SLC1_TOKEN1_M (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S) -#define SDIO_SLC1_TOKEN1_V 0x00000FFFU -#define SDIO_SLC1_TOKEN1_S 16 - -/** SDIO_SLCCONF1_REG register - * reserved - */ -#define SDIO_SLCCONF1_REG (DR_REG_SLC_BASE + 0x70) -/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC0_CHECK_OWNER (BIT(0)) -#define SDIO_SLC0_CHECK_OWNER_M (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S) -#define SDIO_SLC0_CHECK_OWNER_V 0x00000001U -#define SDIO_SLC0_CHECK_OWNER_S 0 -/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_CHECK_SUM_EN (BIT(1)) -#define SDIO_SLC0_TX_CHECK_SUM_EN_M (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S) -#define SDIO_SLC0_TX_CHECK_SUM_EN_V 0x00000001U -#define SDIO_SLC0_TX_CHECK_SUM_EN_S 1 -/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_CHECK_SUM_EN (BIT(2)) -#define SDIO_SLC0_RX_CHECK_SUM_EN_M (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S) -#define SDIO_SLC0_RX_CHECK_SUM_EN_V 0x00000001U -#define SDIO_SLC0_RX_CHECK_SUM_EN_S 2 -/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1; - * reserved - */ -#define SDIO_SDIO_CMD_HOLD_EN (BIT(3)) -#define SDIO_SDIO_CMD_HOLD_EN_M (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S) -#define SDIO_SDIO_CMD_HOLD_EN_V 0x00000001U -#define SDIO_SDIO_CMD_HOLD_EN_S 3 -/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1; - * reserved - */ -#define SDIO_SLC0_LEN_AUTO_CLR (BIT(4)) -#define SDIO_SLC0_LEN_AUTO_CLR_M (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S) -#define SDIO_SLC0_LEN_AUTO_CLR_V 0x00000001U -#define SDIO_SLC0_LEN_AUTO_CLR_S 4 -/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1; - * reserved - */ -#define SDIO_SLC0_TX_STITCH_EN (BIT(5)) -#define SDIO_SLC0_TX_STITCH_EN_M (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S) -#define SDIO_SLC0_TX_STITCH_EN_V 0x00000001U -#define SDIO_SLC0_TX_STITCH_EN_S 5 -/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1; - * reserved - */ -#define SDIO_SLC0_RX_STITCH_EN (BIT(6)) -#define SDIO_SLC0_RX_STITCH_EN_M (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S) -#define SDIO_SLC0_RX_STITCH_EN_V 0x00000001U -#define SDIO_SLC0_RX_STITCH_EN_S 6 -/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_CHECK_OWNER (BIT(16)) -#define SDIO_SLC1_CHECK_OWNER_M (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S) -#define SDIO_SLC1_CHECK_OWNER_V 0x00000001U -#define SDIO_SLC1_CHECK_OWNER_S 16 -/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_CHECK_SUM_EN (BIT(17)) -#define SDIO_SLC1_TX_CHECK_SUM_EN_M (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S) -#define SDIO_SLC1_TX_CHECK_SUM_EN_V 0x00000001U -#define SDIO_SLC1_TX_CHECK_SUM_EN_S 17 -/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_CHECK_SUM_EN (BIT(18)) -#define SDIO_SLC1_RX_CHECK_SUM_EN_M (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S) -#define SDIO_SLC1_RX_CHECK_SUM_EN_V 0x00000001U -#define SDIO_SLC1_RX_CHECK_SUM_EN_S 18 -/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_HOST_INT_LEVEL_SEL (BIT(19)) -#define SDIO_HOST_INT_LEVEL_SEL_M (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S) -#define SDIO_HOST_INT_LEVEL_SEL_V 0x00000001U -#define SDIO_HOST_INT_LEVEL_SEL_S 19 -/** SDIO_SLC1_TX_STITCH_EN : R/W; bitpos: [20]; default: 1; - * reserved - */ -#define SDIO_SLC1_TX_STITCH_EN (BIT(20)) -#define SDIO_SLC1_TX_STITCH_EN_M (SDIO_SLC1_TX_STITCH_EN_V << SDIO_SLC1_TX_STITCH_EN_S) -#define SDIO_SLC1_TX_STITCH_EN_V 0x00000001U -#define SDIO_SLC1_TX_STITCH_EN_S 20 -/** SDIO_SLC1_RX_STITCH_EN : R/W; bitpos: [21]; default: 1; - * reserved - */ -#define SDIO_SLC1_RX_STITCH_EN (BIT(21)) -#define SDIO_SLC1_RX_STITCH_EN_M (SDIO_SLC1_RX_STITCH_EN_V << SDIO_SLC1_RX_STITCH_EN_S) -#define SDIO_SLC1_RX_STITCH_EN_V 0x00000001U -#define SDIO_SLC1_RX_STITCH_EN_S 21 -/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SDIO_CLK_EN (BIT(22)) -#define SDIO_SDIO_CLK_EN_M (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S) -#define SDIO_SDIO_CLK_EN_V 0x00000001U -#define SDIO_SDIO_CLK_EN_S 22 - -/** SDIO_SLC0_STATE0_REG register - * reserved - */ -#define SDIO_SLC0_STATE0_REG (DR_REG_SLC_BASE + 0x74) -/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_STATE0 0xFFFFFFFFU -#define SDIO_SLC0_STATE0_M (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S) -#define SDIO_SLC0_STATE0_V 0xFFFFFFFFU -#define SDIO_SLC0_STATE0_S 0 - -/** SDIO_SLC0_STATE1_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_STATE1_REG (DR_REG_SLC_BASE + 0x78) -/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0; - * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] - * rx_link fsm state, [30:24] rx_fifo_cnt - */ -#define SDIO_SLC0_STATE1 0xFFFFFFFFU -#define SDIO_SLC0_STATE1_M (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S) -#define SDIO_SLC0_STATE1_V 0xFFFFFFFFU -#define SDIO_SLC0_STATE1_S 0 - -/** SDIO_SLC1_STATE0_REG register - * ******* Description *********** - */ -#define SDIO_SLC1_STATE0_REG (DR_REG_SLC_BASE + 0x7c) -/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_STATE0 0xFFFFFFFFU -#define SDIO_SLC1_STATE0_M (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S) -#define SDIO_SLC1_STATE0_V 0xFFFFFFFFU -#define SDIO_SLC1_STATE0_S 0 - -/** SDIO_SLC1_STATE1_REG register - * ******* Description *********** - */ -#define SDIO_SLC1_STATE1_REG (DR_REG_SLC_BASE + 0x80) -/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0; - * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] - * rx_link fsm state, [30:24] rx_fifo_cnt - */ -#define SDIO_SLC1_STATE1 0xFFFFFFFFU -#define SDIO_SLC1_STATE1_M (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S) -#define SDIO_SLC1_STATE1_V 0xFFFFFFFFU -#define SDIO_SLC1_STATE1_S 0 - -/** SDIO_SLCBRIDGE_CONF_REG register - * ******* Description *********** - */ -#define SDIO_SLCBRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x84) -/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32; - * reserved - */ -#define SDIO_SLC_TXEOF_ENA 0x0000003FU -#define SDIO_SLC_TXEOF_ENA_M (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S) -#define SDIO_SLC_TXEOF_ENA_V 0x0000003FU -#define SDIO_SLC_TXEOF_ENA_S 0 -/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7; - * reserved - */ -#define SDIO_SLC_FIFO_MAP_ENA 0x0000000FU -#define SDIO_SLC_FIFO_MAP_ENA_M (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S) -#define SDIO_SLC_FIFO_MAP_ENA_V 0x0000000FU -#define SDIO_SLC_FIFO_MAP_ENA_S 8 -/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1; - * reserved - */ -#define SDIO_SLC0_TX_DUMMY_MODE (BIT(12)) -#define SDIO_SLC0_TX_DUMMY_MODE_M (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S) -#define SDIO_SLC0_TX_DUMMY_MODE_V 0x00000001U -#define SDIO_SLC0_TX_DUMMY_MODE_S 12 -/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1; - * reserved - */ -#define SDIO_SLC_HDA_MAP_128K (BIT(13)) -#define SDIO_SLC_HDA_MAP_128K_M (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S) -#define SDIO_SLC_HDA_MAP_128K_V 0x00000001U -#define SDIO_SLC_HDA_MAP_128K_S 13 -/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1; - * reserved - */ -#define SDIO_SLC1_TX_DUMMY_MODE (BIT(14)) -#define SDIO_SLC1_TX_DUMMY_MODE_M (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S) -#define SDIO_SLC1_TX_DUMMY_MODE_V 0x00000001U -#define SDIO_SLC1_TX_DUMMY_MODE_S 14 -/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10; - * reserved - */ -#define SDIO_SLC_TX_PUSH_IDLE_NUM 0x0000FFFFU -#define SDIO_SLC_TX_PUSH_IDLE_NUM_M (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S) -#define SDIO_SLC_TX_PUSH_IDLE_NUM_V 0x0000FFFFU -#define SDIO_SLC_TX_PUSH_IDLE_NUM_S 16 - -/** SDIO_SLC0_TO_EOF_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88) -/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TO_EOF_DES_ADDR_M (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S) -#define SDIO_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TO_EOF_DES_ADDR_S 0 - -/** SDIO_SLC0_TX_EOF_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8c) -/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S) -#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S 0 - -/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x90) -/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S) -#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S 0 - -/** SDIO_SLC1_TO_EOF_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x94) -/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC1_TO_EOF_DES_ADDR_M (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S) -#define SDIO_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC1_TO_EOF_DES_ADDR_S 0 - -/** SDIO_SLC1_TX_EOF_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x98) -/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S) -#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S 0 - -/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x9c) -/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S) -#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S 0 - -/** SDIO_SLC_AHB_TEST_REG register - * reserved - */ -#define SDIO_SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0xa0) -/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; - * reserved - */ -#define SDIO_SLC_AHB_TESTMODE 0x00000007U -#define SDIO_SLC_AHB_TESTMODE_M (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S) -#define SDIO_SLC_AHB_TESTMODE_V 0x00000007U -#define SDIO_SLC_AHB_TESTMODE_S 0 -/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; - * reserved - */ -#define SDIO_SLC_AHB_TESTADDR 0x00000003U -#define SDIO_SLC_AHB_TESTADDR_M (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S) -#define SDIO_SLC_AHB_TESTADDR_V 0x00000003U -#define SDIO_SLC_AHB_TESTADDR_S 4 - -/** SDIO_SLC_SDIO_ST_REG register - * reserved - */ -#define SDIO_SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0xa4) -/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0; - * reserved - */ -#define SDIO_CMD_ST 0x00000007U -#define SDIO_CMD_ST_M (SDIO_CMD_ST_V << SDIO_CMD_ST_S) -#define SDIO_CMD_ST_V 0x00000007U -#define SDIO_CMD_ST_S 0 -/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0; - * reserved - */ -#define SDIO_FUNC_ST 0x0000000FU -#define SDIO_FUNC_ST_M (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S) -#define SDIO_FUNC_ST_V 0x0000000FU -#define SDIO_FUNC_ST_S 4 -/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SDIO_WAKEUP (BIT(8)) -#define SDIO_SDIO_WAKEUP_M (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S) -#define SDIO_SDIO_WAKEUP_V 0x00000001U -#define SDIO_SDIO_WAKEUP_S 8 -/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0; - * reserved - */ -#define SDIO_BUS_ST 0x00000007U -#define SDIO_BUS_ST_M (SDIO_BUS_ST_V << SDIO_BUS_ST_S) -#define SDIO_BUS_ST_V 0x00000007U -#define SDIO_BUS_ST_S 12 -/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0; - * reserved - */ -#define SDIO_FUNC1_ACC_STATE 0x0000001FU -#define SDIO_FUNC1_ACC_STATE_M (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S) -#define SDIO_FUNC1_ACC_STATE_V 0x0000001FU -#define SDIO_FUNC1_ACC_STATE_S 16 -/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0; - * reserved - */ -#define SDIO_FUNC2_ACC_STATE 0x0000001FU -#define SDIO_FUNC2_ACC_STATE_M (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S) -#define SDIO_FUNC2_ACC_STATE_V 0x0000001FU -#define SDIO_FUNC2_ACC_STATE_S 24 - -/** SDIO_SLC_RX_DSCR_CONF_REG register - * reserved - */ -#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xa8) -/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN_NO_REPLACE (BIT(0)) -#define SDIO_SLC0_TOKEN_NO_REPLACE_M (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S) -#define SDIO_SLC0_TOKEN_NO_REPLACE_V 0x00000001U -#define SDIO_SLC0_TOKEN_NO_REPLACE_S 0 -/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1; - * reserved - */ -#define SDIO_SLC0_INFOR_NO_REPLACE (BIT(1)) -#define SDIO_SLC0_INFOR_NO_REPLACE_M (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S) -#define SDIO_SLC0_INFOR_NO_REPLACE_V 0x00000001U -#define SDIO_SLC0_INFOR_NO_REPLACE_S 1 -/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0; - * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next - * pop doesn't occur after 255 cycles since the current pop - */ -#define SDIO_SLC0_RX_FILL_MODE (BIT(2)) -#define SDIO_SLC0_RX_FILL_MODE_M (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S) -#define SDIO_SLC0_RX_FILL_MODE_V 0x00000001U -#define SDIO_SLC0_RX_FILL_MODE_S 2 -/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1; - * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof - */ -#define SDIO_SLC0_RX_EOF_MODE (BIT(3)) -#define SDIO_SLC0_RX_EOF_MODE_M (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S) -#define SDIO_SLC0_RX_EOF_MODE_V 0x00000001U -#define SDIO_SLC0_RX_EOF_MODE_S 3 -/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1; - * reserved - */ -#define SDIO_SLC0_RX_FILL_EN (BIT(4)) -#define SDIO_SLC0_RX_FILL_EN_M (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S) -#define SDIO_SLC0_RX_FILL_EN_V 0x00000001U -#define SDIO_SLC0_RX_FILL_EN_S 4 -/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128; - * reserved - */ -#define SDIO_SLC0_RD_RETRY_THRESHOLD 0x000007FFU -#define SDIO_SLC0_RD_RETRY_THRESHOLD_M (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S) -#define SDIO_SLC0_RD_RETRY_THRESHOLD_V 0x000007FFU -#define SDIO_SLC0_RD_RETRY_THRESHOLD_S 5 -/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1; - * reserved - */ -#define SDIO_SLC1_TOKEN_NO_REPLACE (BIT(16)) -#define SDIO_SLC1_TOKEN_NO_REPLACE_M (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S) -#define SDIO_SLC1_TOKEN_NO_REPLACE_V 0x00000001U -#define SDIO_SLC1_TOKEN_NO_REPLACE_S 16 -/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1; - * reserved - */ -#define SDIO_SLC1_INFOR_NO_REPLACE (BIT(17)) -#define SDIO_SLC1_INFOR_NO_REPLACE_M (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S) -#define SDIO_SLC1_INFOR_NO_REPLACE_V 0x00000001U -#define SDIO_SLC1_INFOR_NO_REPLACE_S 17 -/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0; - * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next - * pop doesn't occur after 255 cycles since the current pop - */ -#define SDIO_SLC1_RX_FILL_MODE (BIT(18)) -#define SDIO_SLC1_RX_FILL_MODE_M (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S) -#define SDIO_SLC1_RX_FILL_MODE_V 0x00000001U -#define SDIO_SLC1_RX_FILL_MODE_S 18 -/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1; - * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof - */ -#define SDIO_SLC1_RX_EOF_MODE (BIT(19)) -#define SDIO_SLC1_RX_EOF_MODE_M (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S) -#define SDIO_SLC1_RX_EOF_MODE_V 0x00000001U -#define SDIO_SLC1_RX_EOF_MODE_S 19 -/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1; - * reserved - */ -#define SDIO_SLC1_RX_FILL_EN (BIT(20)) -#define SDIO_SLC1_RX_FILL_EN_M (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S) -#define SDIO_SLC1_RX_FILL_EN_V 0x00000001U -#define SDIO_SLC1_RX_FILL_EN_S 20 -/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128; - * reserved - */ -#define SDIO_SLC1_RD_RETRY_THRESHOLD 0x000007FFU -#define SDIO_SLC1_RD_RETRY_THRESHOLD_M (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S) -#define SDIO_SLC1_RD_RETRY_THRESHOLD_V 0x000007FFU -#define SDIO_SLC1_RD_RETRY_THRESHOLD_S 21 - -/** SDIO_SLC0_TXLINK_DSCR_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xac) -/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXLINK_DSCR 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_DSCR_M (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S) -#define SDIO_SLC0_TXLINK_DSCR_V 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_DSCR_S 0 - -/** SDIO_SLC0_TXLINK_DSCR_BF0_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xb0) -/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_DSCR_BF0_M (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S) -#define SDIO_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_DSCR_BF0_S 0 - -/** SDIO_SLC0_TXLINK_DSCR_BF1_REG register - * reserved - */ -#define SDIO_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xb4) -/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_DSCR_BF1_M (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S) -#define SDIO_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFFU -#define SDIO_SLC0_TXLINK_DSCR_BF1_S 0 - -/** SDIO_SLC0_RXLINK_DSCR_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xb8) -/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; - * the third word of slc0 link descriptor, or known as the next descriptor address - */ -#define SDIO_SLC0_RXLINK_DSCR 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_DSCR_M (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S) -#define SDIO_SLC0_RXLINK_DSCR_V 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_DSCR_S 0 - -/** SDIO_SLC0_RXLINK_DSCR_BF0_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xbc) -/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_DSCR_BF0_M (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S) -#define SDIO_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_DSCR_BF0_S 0 - -/** SDIO_SLC0_RXLINK_DSCR_BF1_REG register - * reserved - */ -#define SDIO_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xc0) -/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_DSCR_BF1_M (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S) -#define SDIO_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFFU -#define SDIO_SLC0_RXLINK_DSCR_BF1_S 0 - -/** SDIO_SLC1_TXLINK_DSCR_REG register - * reserved - */ -#define SDIO_SLC1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xc4) -/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXLINK_DSCR 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_DSCR_M (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S) -#define SDIO_SLC1_TXLINK_DSCR_V 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_DSCR_S 0 - -/** SDIO_SLC1_TXLINK_DSCR_BF0_REG register - * reserved - */ -#define SDIO_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xc8) -/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_DSCR_BF0_M (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S) -#define SDIO_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_DSCR_BF0_S 0 - -/** SDIO_SLC1_TXLINK_DSCR_BF1_REG register - * reserved - */ -#define SDIO_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xcc) -/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_DSCR_BF1_M (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S) -#define SDIO_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFFU -#define SDIO_SLC1_TXLINK_DSCR_BF1_S 0 - -/** SDIO_SLC1_RXLINK_DSCR_REG register - * ******* Description *********** - */ -#define SDIO_SLC1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xd0) -/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; - * the third word of slc1 link descriptor, or known as the next descriptor address - */ -#define SDIO_SLC1_RXLINK_DSCR 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_DSCR_M (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S) -#define SDIO_SLC1_RXLINK_DSCR_V 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_DSCR_S 0 - -/** SDIO_SLC1_RXLINK_DSCR_BF0_REG register - * ******* Description *********** - */ -#define SDIO_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xd4) -/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_DSCR_BF0_M (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S) -#define SDIO_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_DSCR_BF0_S 0 - -/** SDIO_SLC1_RXLINK_DSCR_BF1_REG register - * reserved - */ -#define SDIO_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xd8) -/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_DSCR_BF1_M (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S) -#define SDIO_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFFU -#define SDIO_SLC1_RXLINK_DSCR_BF1_S 0 - -/** SDIO_SLC0_TX_ERREOF_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xdc) -/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S) -#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S 0 - -/** SDIO_SLC1_TX_ERREOF_DES_ADDR_REG register - * reserved - */ -#define SDIO_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xe0) -/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S) -#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S 0 - -/** SDIO_SLC_TOKEN_LAT_REG register - * reserved - */ -#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xe4) -/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN 0x00000FFFU -#define SDIO_SLC0_TOKEN_M (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S) -#define SDIO_SLC0_TOKEN_V 0x00000FFFU -#define SDIO_SLC0_TOKEN_S 0 -/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN 0x00000FFFU -#define SDIO_SLC1_TOKEN_M (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S) -#define SDIO_SLC1_TOKEN_V 0x00000FFFU -#define SDIO_SLC1_TOKEN_S 16 - -/** SDIO_SLC_TX_DSCR_CONF_REG register - * reserved - */ -#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xe8) -/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128; - * reserved - */ -#define SDIO_SLC_WR_RETRY_THRESHOLD 0x000007FFU -#define SDIO_SLC_WR_RETRY_THRESHOLD_M (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S) -#define SDIO_SLC_WR_RETRY_THRESHOLD_V 0x000007FFU -#define SDIO_SLC_WR_RETRY_THRESHOLD_S 0 - -/** SDIO_SLC_CMD_INFOR0_REG register - * reserved - */ -#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xec) -/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_CMD_CONTENT0 0xFFFFFFFFU -#define SDIO_CMD_CONTENT0_M (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S) -#define SDIO_CMD_CONTENT0_V 0xFFFFFFFFU -#define SDIO_CMD_CONTENT0_S 0 - -/** SDIO_SLC_CMD_INFOR1_REG register - * reserved - */ -#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xf0) -/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_CMD_CONTENT1 0xFFFFFFFFU -#define SDIO_CMD_CONTENT1_M (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S) -#define SDIO_CMD_CONTENT1_V 0xFFFFFFFFU -#define SDIO_CMD_CONTENT1_S 0 - -/** SDIO_SLC0_LEN_CONF_REG register - * reserved - */ -#define SDIO_SLC0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xf4) -/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_LEN_WDATA 0x000FFFFFU -#define SDIO_SLC0_LEN_WDATA_M (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S) -#define SDIO_SLC0_LEN_WDATA_V 0x000FFFFFU -#define SDIO_SLC0_LEN_WDATA_S 0 -/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC0_LEN_WR (BIT(20)) -#define SDIO_SLC0_LEN_WR_M (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S) -#define SDIO_SLC0_LEN_WR_V 0x00000001U -#define SDIO_SLC0_LEN_WR_S 20 -/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC0_LEN_INC (BIT(21)) -#define SDIO_SLC0_LEN_INC_M (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S) -#define SDIO_SLC0_LEN_INC_V 0x00000001U -#define SDIO_SLC0_LEN_INC_S 21 -/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC0_LEN_INC_MORE (BIT(22)) -#define SDIO_SLC0_LEN_INC_MORE_M (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S) -#define SDIO_SLC0_LEN_INC_MORE_V 0x00000001U -#define SDIO_SLC0_LEN_INC_MORE_S 22 -/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_PACKET_LOAD_EN (BIT(23)) -#define SDIO_SLC0_RX_PACKET_LOAD_EN_M (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S) -#define SDIO_SLC0_RX_PACKET_LOAD_EN_V 0x00000001U -#define SDIO_SLC0_RX_PACKET_LOAD_EN_S 23 -/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_PACKET_LOAD_EN (BIT(24)) -#define SDIO_SLC0_TX_PACKET_LOAD_EN_M (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S) -#define SDIO_SLC0_TX_PACKET_LOAD_EN_V 0x00000001U -#define SDIO_SLC0_TX_PACKET_LOAD_EN_S 24 -/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_GET_USED_DSCR (BIT(25)) -#define SDIO_SLC0_RX_GET_USED_DSCR_M (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S) -#define SDIO_SLC0_RX_GET_USED_DSCR_V 0x00000001U -#define SDIO_SLC0_RX_GET_USED_DSCR_S 25 -/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_GET_USED_DSCR (BIT(26)) -#define SDIO_SLC0_TX_GET_USED_DSCR_M (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S) -#define SDIO_SLC0_TX_GET_USED_DSCR_V 0x00000001U -#define SDIO_SLC0_TX_GET_USED_DSCR_S 26 -/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_NEW_PKT_IND (BIT(27)) -#define SDIO_SLC0_RX_NEW_PKT_IND_M (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S) -#define SDIO_SLC0_RX_NEW_PKT_IND_V 0x00000001U -#define SDIO_SLC0_RX_NEW_PKT_IND_S 27 -/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1; - * reserved - */ -#define SDIO_SLC0_TX_NEW_PKT_IND (BIT(28)) -#define SDIO_SLC0_TX_NEW_PKT_IND_M (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S) -#define SDIO_SLC0_TX_NEW_PKT_IND_V 0x00000001U -#define SDIO_SLC0_TX_NEW_PKT_IND_S 28 -/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST (BIT(29)) -#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S) -#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V 0x00000001U -#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S 29 -/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST (BIT(30)) -#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S) -#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V 0x00000001U -#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S 30 - -/** SDIO_SLC0_LENGTH_REG register - * reserved - */ -#define SDIO_SLC0_LENGTH_REG (DR_REG_SLC_BASE + 0xf8) -/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_LEN 0x000FFFFFU -#define SDIO_SLC0_LEN_M (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S) -#define SDIO_SLC0_LEN_V 0x000FFFFFU -#define SDIO_SLC0_LEN_S 0 - -/** SDIO_SLC0_TXPKT_H_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xfc) -/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S) -#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S 0 - -/** SDIO_SLC0_TXPKT_E_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x100) -/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S) -#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S 0 - -/** SDIO_SLC0_RXPKT_H_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0x104) -/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S) -#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S 0 - -/** SDIO_SLC0_RXPKT_E_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x108) -/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S) -#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S 0 - -/** SDIO_SLC0_TXPKTU_H_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x10c) -/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S) -#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S 0 - -/** SDIO_SLC0_TXPKTU_E_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x110) -/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S) -#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S 0 - -/** SDIO_SLC0_RXPKTU_H_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x114) -/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S) -#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S 0 - -/** SDIO_SLC0_RXPKTU_E_DSCR_REG register - * reserved - */ -#define SDIO_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x118) -/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S) -#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S 0 - -/** SDIO_SLC_SEQ_POSITION_REG register - * reserved - */ -#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x11c) -/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9; - * reserved - */ -#define SDIO_SLC0_SEQ_POSITION 0x000000FFU -#define SDIO_SLC0_SEQ_POSITION_M (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S) -#define SDIO_SLC0_SEQ_POSITION_V 0x000000FFU -#define SDIO_SLC0_SEQ_POSITION_S 0 -/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5; - * reserved - */ -#define SDIO_SLC1_SEQ_POSITION 0x000000FFU -#define SDIO_SLC1_SEQ_POSITION_M (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S) -#define SDIO_SLC1_SEQ_POSITION_V 0x000000FFU -#define SDIO_SLC1_SEQ_POSITION_S 8 - -/** SDIO_SLC0_DSCR_REC_CONF_REG register - * reserved - */ -#define SDIO_SLC0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x120) -/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023; - * reserved - */ -#define SDIO_SLC0_RX_DSCR_REC_LIM 0x000003FFU -#define SDIO_SLC0_RX_DSCR_REC_LIM_M (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S) -#define SDIO_SLC0_RX_DSCR_REC_LIM_V 0x000003FFU -#define SDIO_SLC0_RX_DSCR_REC_LIM_S 0 - -/** SDIO_SLC_SDIO_CRC_ST0_REG register - * reserved - */ -#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x124) -/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; - * reserved - */ -#define SDIO_DAT0_CRC_ERR_CNT 0x000000FFU -#define SDIO_DAT0_CRC_ERR_CNT_M (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S) -#define SDIO_DAT0_CRC_ERR_CNT_V 0x000000FFU -#define SDIO_DAT0_CRC_ERR_CNT_S 0 -/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0; - * reserved - */ -#define SDIO_DAT1_CRC_ERR_CNT 0x000000FFU -#define SDIO_DAT1_CRC_ERR_CNT_M (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S) -#define SDIO_DAT1_CRC_ERR_CNT_V 0x000000FFU -#define SDIO_DAT1_CRC_ERR_CNT_S 8 -/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0; - * reserved - */ -#define SDIO_DAT2_CRC_ERR_CNT 0x000000FFU -#define SDIO_DAT2_CRC_ERR_CNT_M (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S) -#define SDIO_DAT2_CRC_ERR_CNT_V 0x000000FFU -#define SDIO_DAT2_CRC_ERR_CNT_S 16 -/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0; - * reserved - */ -#define SDIO_DAT3_CRC_ERR_CNT 0x000000FFU -#define SDIO_DAT3_CRC_ERR_CNT_M (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S) -#define SDIO_DAT3_CRC_ERR_CNT_V 0x000000FFU -#define SDIO_DAT3_CRC_ERR_CNT_S 24 - -/** SDIO_SLC_SDIO_CRC_ST1_REG register - * reserved - */ -#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x128) -/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; - * reserved - */ -#define SDIO_CMD_CRC_ERR_CNT 0x000000FFU -#define SDIO_CMD_CRC_ERR_CNT_M (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S) -#define SDIO_CMD_CRC_ERR_CNT_V 0x000000FFU -#define SDIO_CMD_CRC_ERR_CNT_S 0 -/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0; - * reserved - */ -#define SDIO_ERR_CNT_CLR (BIT(31)) -#define SDIO_ERR_CNT_CLR_M (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S) -#define SDIO_ERR_CNT_CLR_V 0x00000001U -#define SDIO_ERR_CNT_CLR_S 31 - -/** SDIO_SLC0_EOF_START_DES_REG register - * reserved - */ -#define SDIO_SLC0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x12c) -/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SLC0_EOF_START_DES_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_EOF_START_DES_ADDR_M (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S) -#define SDIO_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_EOF_START_DES_ADDR_S 0 - -/** SDIO_SLC0_PUSH_DSCR_ADDR_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x130) -/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; - * the current descriptor address when slc0 gets a link descriptor, aligned with word - */ -#define SDIO_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S) -#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S 0 - -/** SDIO_SLC0_DONE_DSCR_ADDR_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x134) -/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; - * the current descriptor address when slc0 finishes reading data from one buffer, - * aligned with word - */ -#define SDIO_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S) -#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S 0 - -/** SDIO_SLC0_SUB_START_DES_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x138) -/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; - * the current descriptor address when slc0 gets a link descriptor, aligned with word - */ -#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFFU -#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S) -#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFFU -#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 - -/** SDIO_SLC0_DSCR_CNT_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x13c) -/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0; - * the number of descriptors got by slc0 when it tries to read data from memory - */ -#define SDIO_SLC0_RX_DSCR_CNT_LAT 0x000003FFU -#define SDIO_SLC0_RX_DSCR_CNT_LAT_M (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S) -#define SDIO_SLC0_RX_DSCR_CNT_LAT_V 0x000003FFU -#define SDIO_SLC0_RX_DSCR_CNT_LAT_S 0 -/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_GET_EOF_OCC (BIT(16)) -#define SDIO_SLC0_RX_GET_EOF_OCC_M (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S) -#define SDIO_SLC0_RX_GET_EOF_OCC_V 0x00000001U -#define SDIO_SLC0_RX_GET_EOF_OCC_S 16 - -/** SDIO_SLC0_LEN_LIM_CONF_REG register - * ******* Description *********** - */ -#define SDIO_SLC0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x140) -/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504; - * reserved - */ -#define SDIO_SLC0_LEN_LIM 0x000FFFFFU -#define SDIO_SLC0_LEN_LIM_M (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S) -#define SDIO_SLC0_LEN_LIM_V 0x000FFFFFU -#define SDIO_SLC0_LEN_LIM_S 0 - -/** SDIO_SLC0INT_ST1_REG register - * reserved - */ -#define SDIO_SLC0INT_ST1_REG (DR_REG_SLC_BASE + 0x144) -/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) -#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S 0 -/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) -#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S 1 -/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) -#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S 2 -/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) -#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S 3 -/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) -#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S 4 -/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) -#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S 5 -/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) -#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S 6 -/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) -#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S 7 -/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_START_INT_ST1 (BIT(8)) -#define SDIO_SLC0_RX_START_INT_ST1_M (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S) -#define SDIO_SLC0_RX_START_INT_ST1_V 0x00000001U -#define SDIO_SLC0_RX_START_INT_ST1_S 8 -/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_START_INT_ST1 (BIT(9)) -#define SDIO_SLC0_TX_START_INT_ST1_M (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S) -#define SDIO_SLC0_TX_START_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TX_START_INT_ST1_S 9 -/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_UDF_INT_ST1 (BIT(10)) -#define SDIO_SLC0_RX_UDF_INT_ST1_M (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S) -#define SDIO_SLC0_RX_UDF_INT_ST1_V 0x00000001U -#define SDIO_SLC0_RX_UDF_INT_ST1_S 10 -/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_OVF_INT_ST1 (BIT(11)) -#define SDIO_SLC0_TX_OVF_INT_ST1_M (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S) -#define SDIO_SLC0_TX_OVF_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TX_OVF_INT_ST1_S 11 -/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S 12 -/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S 13 -/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DONE_INT_ST1 (BIT(14)) -#define SDIO_SLC0_TX_DONE_INT_ST1_M (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S) -#define SDIO_SLC0_TX_DONE_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TX_DONE_INT_ST1_S 14 -/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) -#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S) -#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S 15 -/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DONE_INT_ST1 (BIT(16)) -#define SDIO_SLC0_RX_DONE_INT_ST1_M (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S) -#define SDIO_SLC0_RX_DONE_INT_ST1_V 0x00000001U -#define SDIO_SLC0_RX_DONE_INT_ST1_S 16 -/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_EOF_INT_ST1 (BIT(17)) -#define SDIO_SLC0_RX_EOF_INT_ST1_M (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S) -#define SDIO_SLC0_RX_EOF_INT_ST1_V 0x00000001U -#define SDIO_SLC0_RX_EOF_INT_ST1_S 17 -/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOHOST_INT_ST1 (BIT(18)) -#define SDIO_SLC0_TOHOST_INT_ST1_M (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S) -#define SDIO_SLC0_TOHOST_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TOHOST_INT_ST1_S 18 -/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S 19 -/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V 0x00000001U -#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S 20 -/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 -/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) -#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S) -#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V 0x00000001U -#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S 22 -/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V 0x00000001U -#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S 23 -/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) -#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S) -#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V 0x00000001U -#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S 24 -/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0; - * reserved - */ -#define SDIO_CMD_DTC_INT_ST1 (BIT(25)) -#define SDIO_CMD_DTC_INT_ST1_M (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S) -#define SDIO_CMD_DTC_INT_ST1_V 0x00000001U -#define SDIO_CMD_DTC_INT_ST1_S 25 -/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V 0x00000001U -#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S 26 -/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x00000001U -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 -/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_HDA_RECV_DONE_INT_ST1 (BIT(28)) -#define SDIO_HDA_RECV_DONE_INT_ST1_M (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S) -#define SDIO_HDA_RECV_DONE_INT_ST1_V 0x00000001U -#define SDIO_HDA_RECV_DONE_INT_ST1_S 28 - -/** SDIO_SLC0INT_ENA1_REG register - * reserved - */ -#define SDIO_SLC0INT_ENA1_REG (DR_REG_SLC_BASE + 0x148) -/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) -#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S 0 -/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) -#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S 1 -/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) -#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S 2 -/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) -#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S 3 -/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) -#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S 4 -/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) -#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S 5 -/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) -#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S 6 -/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) -#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S 7 -/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_START_INT_ENA1 (BIT(8)) -#define SDIO_SLC0_RX_START_INT_ENA1_M (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S) -#define SDIO_SLC0_RX_START_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_RX_START_INT_ENA1_S 8 -/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_START_INT_ENA1 (BIT(9)) -#define SDIO_SLC0_TX_START_INT_ENA1_M (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S) -#define SDIO_SLC0_TX_START_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TX_START_INT_ENA1_S 9 -/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_UDF_INT_ENA1 (BIT(10)) -#define SDIO_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S) -#define SDIO_SLC0_RX_UDF_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_RX_UDF_INT_ENA1_S 10 -/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_OVF_INT_ENA1 (BIT(11)) -#define SDIO_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S) -#define SDIO_SLC0_TX_OVF_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TX_OVF_INT_ENA1_S 11 -/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S) -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 -/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S) -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 -/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DONE_INT_ENA1 (BIT(14)) -#define SDIO_SLC0_TX_DONE_INT_ENA1_M (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S) -#define SDIO_SLC0_TX_DONE_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TX_DONE_INT_ENA1_S 14 -/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S) -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S 15 -/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DONE_INT_ENA1 (BIT(16)) -#define SDIO_SLC0_RX_DONE_INT_ENA1_M (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S) -#define SDIO_SLC0_RX_DONE_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_RX_DONE_INT_ENA1_S 16 -/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_EOF_INT_ENA1 (BIT(17)) -#define SDIO_SLC0_RX_EOF_INT_ENA1_M (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S) -#define SDIO_SLC0_RX_EOF_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_RX_EOF_INT_ENA1_S 17 -/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC0_TOHOST_INT_ENA1 (BIT(18)) -#define SDIO_SLC0_TOHOST_INT_ENA1_M (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S) -#define SDIO_SLC0_TOHOST_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TOHOST_INT_ENA1_S 18 -/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S) -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 -/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S) -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 -/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S) -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 -/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S) -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S 22 -/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S) -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 -/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S) -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S 24 -/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0; - * reserved - */ -#define SDIO_CMD_DTC_INT_ENA1 (BIT(25)) -#define SDIO_CMD_DTC_INT_ENA1_M (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S) -#define SDIO_CMD_DTC_INT_ENA1_V 0x00000001U -#define SDIO_CMD_DTC_INT_ENA1_S 25 -/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0; - * reserved - */ -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S) -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 -/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0; - * reserved - */ -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S) -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x00000001U -#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 -/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0; - * reserved - */ -#define SDIO_HDA_RECV_DONE_INT_ENA1 (BIT(28)) -#define SDIO_HDA_RECV_DONE_INT_ENA1_M (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S) -#define SDIO_HDA_RECV_DONE_INT_ENA1_V 0x00000001U -#define SDIO_HDA_RECV_DONE_INT_ENA1_S 28 - -/** SDIO_SLC1INT_ST1_REG register - * reserved - */ -#define SDIO_SLC1INT_ST1_REG (DR_REG_SLC_BASE + 0x14c) -/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT8_INT_ST1 (BIT(0)) -#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S 0 -/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT9_INT_ST1 (BIT(1)) -#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S 1 -/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT10_INT_ST1 (BIT(2)) -#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S 2 -/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT11_INT_ST1 (BIT(3)) -#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S 3 -/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT12_INT_ST1 (BIT(4)) -#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S 4 -/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT13_INT_ST1 (BIT(5)) -#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S 5 -/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT14_INT_ST1 (BIT(6)) -#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S 6 -/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT15_INT_ST1 (BIT(7)) -#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S) -#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S 7 -/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_START_INT_ST1 (BIT(8)) -#define SDIO_SLC1_RX_START_INT_ST1_M (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S) -#define SDIO_SLC1_RX_START_INT_ST1_V 0x00000001U -#define SDIO_SLC1_RX_START_INT_ST1_S 8 -/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_START_INT_ST1 (BIT(9)) -#define SDIO_SLC1_TX_START_INT_ST1_M (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S) -#define SDIO_SLC1_TX_START_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TX_START_INT_ST1_S 9 -/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_UDF_INT_ST1 (BIT(10)) -#define SDIO_SLC1_RX_UDF_INT_ST1_M (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S) -#define SDIO_SLC1_RX_UDF_INT_ST1_V 0x00000001U -#define SDIO_SLC1_RX_UDF_INT_ST1_S 10 -/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_OVF_INT_ST1 (BIT(11)) -#define SDIO_SLC1_TX_OVF_INT_ST1_M (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S) -#define SDIO_SLC1_TX_OVF_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TX_OVF_INT_ST1_S 11 -/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12)) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S 12 -/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13)) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S 13 -/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DONE_INT_ST1 (BIT(14)) -#define SDIO_SLC1_TX_DONE_INT_ST1_M (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S) -#define SDIO_SLC1_TX_DONE_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TX_DONE_INT_ST1_S 14 -/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15)) -#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S) -#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S 15 -/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DONE_INT_ST1 (BIT(16)) -#define SDIO_SLC1_RX_DONE_INT_ST1_M (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S) -#define SDIO_SLC1_RX_DONE_INT_ST1_V 0x00000001U -#define SDIO_SLC1_RX_DONE_INT_ST1_S 16 -/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_EOF_INT_ST1 (BIT(17)) -#define SDIO_SLC1_RX_EOF_INT_ST1_M (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S) -#define SDIO_SLC1_RX_EOF_INT_ST1_V 0x00000001U -#define SDIO_SLC1_RX_EOF_INT_ST1_S 17 -/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOHOST_INT_ST1 (BIT(18)) -#define SDIO_SLC1_TOHOST_INT_ST1_M (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S) -#define SDIO_SLC1_TOHOST_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TOHOST_INT_ST1_S 18 -/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19)) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S 19 -/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20)) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V 0x00000001U -#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S 20 -/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21 -/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22)) -#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S) -#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V 0x00000001U -#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S 22 -/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23)) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V 0x00000001U -#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S 23 -/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24)) -#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S) -#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V 0x00000001U -#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S 24 - -/** SDIO_SLC1INT_ENA1_REG register - * reserved - */ -#define SDIO_SLC1INT_ENA1_REG (DR_REG_SLC_BASE + 0x150) -/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT8_INT_ENA1 (BIT(0)) -#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S 0 -/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT9_INT_ENA1 (BIT(1)) -#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S 1 -/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT10_INT_ENA1 (BIT(2)) -#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S 2 -/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT11_INT_ENA1 (BIT(3)) -#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S 3 -/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT12_INT_ENA1 (BIT(4)) -#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S 4 -/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT13_INT_ENA1 (BIT(5)) -#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S 5 -/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT14_INT_ENA1 (BIT(6)) -#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S 6 -/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0; - * reserved - */ -#define SDIO_SLC_FRHOST_BIT15_INT_ENA1 (BIT(7)) -#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S) -#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V 0x00000001U -#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S 7 -/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_START_INT_ENA1 (BIT(8)) -#define SDIO_SLC1_RX_START_INT_ENA1_M (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S) -#define SDIO_SLC1_RX_START_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_RX_START_INT_ENA1_S 8 -/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_START_INT_ENA1 (BIT(9)) -#define SDIO_SLC1_TX_START_INT_ENA1_M (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S) -#define SDIO_SLC1_TX_START_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TX_START_INT_ENA1_S 9 -/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_UDF_INT_ENA1 (BIT(10)) -#define SDIO_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S) -#define SDIO_SLC1_RX_UDF_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_RX_UDF_INT_ENA1_S 10 -/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_OVF_INT_ENA1 (BIT(11)) -#define SDIO_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S) -#define SDIO_SLC1_TX_OVF_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TX_OVF_INT_ENA1_S 11 -/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12)) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S) -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S 12 -/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13)) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S) -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S 13 -/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DONE_INT_ENA1 (BIT(14)) -#define SDIO_SLC1_TX_DONE_INT_ENA1_M (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S) -#define SDIO_SLC1_TX_DONE_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TX_DONE_INT_ENA1_S 14 -/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15)) -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S) -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S 15 -/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DONE_INT_ENA1 (BIT(16)) -#define SDIO_SLC1_RX_DONE_INT_ENA1_M (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S) -#define SDIO_SLC1_RX_DONE_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_RX_DONE_INT_ENA1_S 16 -/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_EOF_INT_ENA1 (BIT(17)) -#define SDIO_SLC1_RX_EOF_INT_ENA1_M (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S) -#define SDIO_SLC1_RX_EOF_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_RX_EOF_INT_ENA1_S 17 -/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; - * reserved - */ -#define SDIO_SLC1_TOHOST_INT_ENA1 (BIT(18)) -#define SDIO_SLC1_TOHOST_INT_ENA1_M (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S) -#define SDIO_SLC1_TOHOST_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TOHOST_INT_ENA1_S 18 -/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19)) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S) -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S 19 -/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; - * reserved - */ -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20)) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S) -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S 20 -/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S) -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21 -/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; - * reserved - */ -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22)) -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S) -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S 22 -/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; - * reserved - */ -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23)) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S) -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S 23 -/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; - * reserved - */ -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24)) -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S) -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V 0x00000001U -#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S 24 - -/** SDIO_SLC0_TX_SHAREMEM_START_REG register - * reserved - */ -#define SDIO_SLC0_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x154) -/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S) -#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S 0 - -/** SDIO_SLC0_TX_SHAREMEM_END_REG register - * reserved - */ -#define SDIO_SLC0_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x158) -/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S) -#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S 0 - -/** SDIO_SLC0_RX_SHAREMEM_START_REG register - * reserved - */ -#define SDIO_SLC0_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x15c) -/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S) -#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S 0 - -/** SDIO_SLC0_RX_SHAREMEM_END_REG register - * reserved - */ -#define SDIO_SLC0_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x160) -/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S) -#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S 0 - -/** SDIO_SLC1_TX_SHAREMEM_START_REG register - * reserved - */ -#define SDIO_SLC1_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x164) -/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S) -#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S 0 - -/** SDIO_SLC1_TX_SHAREMEM_END_REG register - * reserved - */ -#define SDIO_SLC1_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x168) -/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S) -#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S 0 - -/** SDIO_SLC1_RX_SHAREMEM_START_REG register - * reserved - */ -#define SDIO_SLC1_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x16c) -/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S) -#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S 0 - -/** SDIO_SLC1_RX_SHAREMEM_END_REG register - * reserved - */ -#define SDIO_SLC1_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x170) -/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ -#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S) -#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S 0 - -/** SDIO_HDA_TX_SHAREMEM_START_REG register - * reserved - */ -#define SDIO_HDA_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x174) -/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S) -#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S 0 - -/** SDIO_HDA_RX_SHAREMEM_START_REG register - * reserved - */ -#define SDIO_HDA_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x178) -/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * reserved - */ -#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU -#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S) -#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU -#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S 0 - -/** SDIO_SLC_BURST_LEN_REG register - * reserved - */ -#define SDIO_SLC_BURST_LEN_REG (DR_REG_SLC_BASE + 0x17c) -/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1; - * 0-incr4,1-incr8 - */ -#define SDIO_SLC0_TXDATA_BURST_LEN (BIT(0)) -#define SDIO_SLC0_TXDATA_BURST_LEN_M (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S) -#define SDIO_SLC0_TXDATA_BURST_LEN_V 0x00000001U -#define SDIO_SLC0_TXDATA_BURST_LEN_S 0 -/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1; - * 0-incr4,1-incr8 - */ -#define SDIO_SLC0_RXDATA_BURST_LEN (BIT(1)) -#define SDIO_SLC0_RXDATA_BURST_LEN_M (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S) -#define SDIO_SLC0_RXDATA_BURST_LEN_V 0x00000001U -#define SDIO_SLC0_RXDATA_BURST_LEN_S 1 -/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1; - * 0-incr4,1-incr8 - */ -#define SDIO_SLC1_TXDATA_BURST_LEN (BIT(2)) -#define SDIO_SLC1_TXDATA_BURST_LEN_M (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S) -#define SDIO_SLC1_TXDATA_BURST_LEN_V 0x00000001U -#define SDIO_SLC1_TXDATA_BURST_LEN_S 2 -/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1; - * 0-incr4,1-incr8 - */ -#define SDIO_SLC1_RXDATA_BURST_LEN (BIT(3)) -#define SDIO_SLC1_RXDATA_BURST_LEN_M (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S) -#define SDIO_SLC1_RXDATA_BURST_LEN_V 0x00000001U -#define SDIO_SLC1_RXDATA_BURST_LEN_S 3 - -/** SDIO_SLCDATE_REG register - * ******* Description *********** - */ -#define SDIO_SLCDATE_REG (DR_REG_SLC_BASE + 0x1f8) -/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400; - * reserved - */ -#define SDIO_SLC_DATE 0xFFFFFFFFU -#define SDIO_SLC_DATE_M (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S) -#define SDIO_SLC_DATE_V 0xFFFFFFFFU -#define SDIO_SLC_DATE_S 0 - -/** SDIO_SLCID_REG register - * ******* Description *********** - */ -#define SDIO_SLCID_REG (DR_REG_SLC_BASE + 0x1fc) -/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256; - * reserved - */ -#define SDIO_SLC_ID 0xFFFFFFFFU -#define SDIO_SLC_ID_M (SDIO_SLC_ID_V << SDIO_SLC_ID_S) -#define SDIO_SLC_ID_V 0xFFFFFFFFU -#define SDIO_SLC_ID_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/slc_struct.h b/components/soc/esp32p4/include/soc/slc_struct.h deleted file mode 100644 index 7d57757704..0000000000 --- a/components/soc/esp32p4/include/soc/slc_struct.h +++ /dev/null @@ -1,3253 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration registers */ -/** Type of slcconf0 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_tx_rst : R/W; bitpos: [0]; default: 0; - * Set 1 to reset tx fsm in dma slc0. - */ - uint32_t slc0_tx_rst:1; - /** slc0_rx_rst : R/W; bitpos: [1]; default: 0; - * Set 1 to reset rx fsm in dma slc0. - */ - uint32_t slc0_rx_rst:1; - /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0; - * reset the command fifo of AHB bus of sdio slave - */ - uint32_t slc_ahbm_fifo_rst:1; - /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0; - * reset the AHB bus of sdio slave - */ - uint32_t slc_ahbm_rst:1; - /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0; - * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. - */ - uint32_t slc0_tx_loop_test:1; - /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0; - * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. - */ - uint32_t slc0_rx_loop_test:1; - /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0; - * Set 1 to enable change the owner bit of rx link descriptor - */ - uint32_t slc0_rx_auto_wrback:1; - /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc0_rx_no_restart_clr:1; - /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1; - * 0- AHB burst type is single when slave read rx-descriptor from memory through - * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory - * through slc0 - */ - uint32_t slc0_rxdscr_burst_en:1; - /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1; - * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type - * is not single when slave receives data from memory - */ - uint32_t slc0_rxdata_burst_en:1; - /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1; - * enable the function that when host reading packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ - uint32_t slc0_rxlink_auto_ret:1; - /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1; - * enable the function that when host sending packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ - uint32_t slc0_txlink_auto_ret:1; - /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1; - * 0- AHB burst type is single when slave read tx-descriptor from memory through - * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory - * through slc0 - */ - uint32_t slc0_txdscr_burst_en:1; - /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1; - * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not - * single when slave send data to memory - */ - uint32_t slc0_txdata_burst_en:1; - /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1; - * auto clear slc0_token1 enable - */ - uint32_t slc0_token_auto_clr:1; - /** slc0_token_sel : R/W; bitpos: [15]; default: 1; - * reserved - */ - uint32_t slc0_token_sel:1; - /** slc1_tx_rst : R/W; bitpos: [16]; default: 0; - * Set 1 to reset tx fsm in dma slc0. - */ - uint32_t slc1_tx_rst:1; - /** slc1_rx_rst : R/W; bitpos: [17]; default: 0; - * Set 1 to reset rx fsm in dma slc0. - */ - uint32_t slc1_rx_rst:1; - /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1; - * reserved - */ - uint32_t slc0_wr_retry_mask_en:1; - /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1; - * reserved - */ - uint32_t slc1_wr_retry_mask_en:1; - /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1; - * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. - */ - uint32_t slc1_tx_loop_test:1; - /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1; - * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. - */ - uint32_t slc1_rx_loop_test:1; - /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0; - * Set 1 to enable change the owner bit of rx link descriptor - */ - uint32_t slc1_rx_auto_wrback:1; - /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0; - * ******* Description *********** - */ - uint32_t slc1_rx_no_restart_clr:1; - /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1; - * 0- AHB burst type is single when slave read rx-descriptor from memory through - * slc1,1-AHB burst type is not single when slave read rx-descriptor from memory - * through slc1 - */ - uint32_t slc1_rxdscr_burst_en:1; - /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1; - * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type - * is not single when slave receives data from memory - */ - uint32_t slc1_rxdata_burst_en:1; - /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1; - * enable the function that when host reading packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ - uint32_t slc1_rxlink_auto_ret:1; - /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1; - * enable the function that when host sending packet retries, slc1 will automatically - * jump to the start descriptor of the previous packet. - */ - uint32_t slc1_txlink_auto_ret:1; - /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1; - * 0- AHB burst type is single when slave read tx-descriptor from memory through - * slc1,1-AHB burst type is not single when slave read tx-descriptor from memory - * through slc1 - */ - uint32_t slc1_txdscr_burst_en:1; - /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1; - * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not - * single when slave send data to memory - */ - uint32_t slc1_txdata_burst_en:1; - /** slc1_token_auto_clr : R/W; bitpos: [30]; default: 1; - * auto clear slc1_token1 enable - */ - uint32_t slc1_token_auto_clr:1; - /** slc1_token_sel : R/W; bitpos: [31]; default: 1; - * reserved - */ - uint32_t slc1_token_sel:1; - }; - uint32_t val; -} sdio_slcconf0_reg_t; - -/** Type of slc0rxfifo_push register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; - * reserved - */ - uint32_t slc0_rxfifo_wdata:9; - uint32_t reserved_9:7; - /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_rxfifo_push:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} sdio_slc0rxfifo_push_reg_t; - -/** Type of slc1rxfifo_push register - * reserved - */ -typedef union { - struct { - /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; - * reserved - */ - uint32_t slc1_rxfifo_wdata:9; - uint32_t reserved_9:7; - /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rxfifo_push:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} sdio_slc1rxfifo_push_reg_t; - -/** Type of slc0rx_link register - * reserved - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ - uint32_t slc0_rxlink_stop:1; - /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ - uint32_t slc0_rxlink_start:1; - /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ - uint32_t slc0_rxlink_restart:1; - /** slc0_rxlink_park : RO; bitpos: [31]; default: 1; - * reserved - */ - uint32_t slc0_rxlink_park:1; - }; - uint32_t val; -} sdio_slc0rx_link_reg_t; - -/** Type of slc0rx_link_addr register - * reserved - */ -typedef union { - struct { - /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_rxlink_addr:32; - }; - uint32_t val; -} sdio_slc0rx_link_addr_reg_t; - -/** Type of slc0tx_link register - * reserved - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ - uint32_t slc0_txlink_stop:1; - /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ - uint32_t slc0_txlink_start:1; - /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ - uint32_t slc0_txlink_restart:1; - /** slc0_txlink_park : RO; bitpos: [31]; default: 1; - * reserved - */ - uint32_t slc0_txlink_park:1; - }; - uint32_t val; -} sdio_slc0tx_link_reg_t; - -/** Type of slc0tx_link_addr register - * reserved - */ -typedef union { - struct { - /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_txlink_addr:32; - }; - uint32_t val; -} sdio_slc0tx_link_addr_reg_t; - -/** Type of slc1rx_link register - * reserved - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** slc1_bt_packet : R/W; bitpos: [20]; default: 1; - * reserved - */ - uint32_t slc1_bt_packet:1; - uint32_t reserved_21:7; - /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ - uint32_t slc1_rxlink_stop:1; - /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ - uint32_t slc1_rxlink_start:1; - /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ - uint32_t slc1_rxlink_restart:1; - /** slc1_rxlink_park : RO; bitpos: [31]; default: 1; - * reserved - */ - uint32_t slc1_rxlink_park:1; - }; - uint32_t val; -} sdio_slc1rx_link_reg_t; - -/** Type of slc1rx_link_addr register - * reserved - */ -typedef union { - struct { - /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_rxlink_addr:32; - }; - uint32_t val; -} sdio_slc1rx_link_addr_reg_t; - -/** Type of slc1tx_link register - * reserved - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0; - * reserved - */ - uint32_t slc1_txlink_stop:1; - /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0; - * reserved - */ - uint32_t slc1_txlink_start:1; - /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0; - * reserved - */ - uint32_t slc1_txlink_restart:1; - /** slc1_txlink_park : RO; bitpos: [31]; default: 1; - * reserved - */ - uint32_t slc1_txlink_park:1; - }; - uint32_t val; -} sdio_slc1tx_link_reg_t; - -/** Type of slc1tx_link_addr register - * reserved - */ -typedef union { - struct { - /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_txlink_addr:32; - }; - uint32_t val; -} sdio_slc1tx_link_addr_reg_t; - -/** Type of slcintvec_tohost register - * reserved - */ -typedef union { - struct { - /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0; - * reserved - */ - uint32_t slc0_tohost_intvec:8; - uint32_t reserved_8:8; - /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0; - * reserved - */ - uint32_t slc1_tohost_intvec:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} sdio_slcintvec_tohost_reg_t; - -/** Type of slc0token0 register - * reserved - */ -typedef union { - struct { - /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0; - * reserved - */ - uint32_t slc0_token0_wdata:12; - /** slc0_token0_wr : WT; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc0_token0_wr:1; - /** slc0_token0_inc : WT; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc0_token0_inc:1; - /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc0_token0_inc_more:1; - uint32_t reserved_15:1; - /** slc0_token0 : RO; bitpos: [27:16]; default: 0; - * reserved - */ - uint32_t slc0_token0:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} sdio_slc0token0_reg_t; - -/** Type of slc0token1 register - * reserved - */ -typedef union { - struct { - /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0; - * slc0 token1 wdata - */ - uint32_t slc0_token1_wdata:12; - /** slc0_token1_wr : WT; bitpos: [12]; default: 0; - * update slc0_token1_wdata into slc0 token1 - */ - uint32_t slc0_token1_wr:1; - /** slc0_token1_inc : WT; bitpos: [13]; default: 0; - * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 - */ - uint32_t slc0_token1_inc:1; - /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0; - * slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add - * slc0_token1_wdata to slc0_token1 - */ - uint32_t slc0_token1_inc_more:1; - uint32_t reserved_15:1; - /** slc0_token1 : RO; bitpos: [27:16]; default: 0; - * reserved - */ - uint32_t slc0_token1:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} sdio_slc0token1_reg_t; - -/** Type of slc1token0 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0; - * reserved - */ - uint32_t slc1_token0_wdata:12; - /** slc1_token0_wr : WT; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc1_token0_wr:1; - /** slc1_token0_inc : WT; bitpos: [13]; default: 0; - * Add 1 to slc1_token0 - */ - uint32_t slc1_token0_inc:1; - /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0; - * Add slc1_token0_wdata to slc1_token0 - */ - uint32_t slc1_token0_inc_more:1; - uint32_t reserved_15:1; - /** slc1_token0 : RO; bitpos: [27:16]; default: 0; - * reserved - */ - uint32_t slc1_token0:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} sdio_slc1token0_reg_t; - -/** Type of slc1token1 register - * reserved - */ -typedef union { - struct { - /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0; - * reserved - */ - uint32_t slc1_token1_wdata:12; - /** slc1_token1_wr : WT; bitpos: [12]; default: 0; - * update slc1_token1_wdata into slc1 token1 - */ - uint32_t slc1_token1_wr:1; - /** slc1_token1_inc : WT; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc1_token1_inc:1; - /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc1_token1_inc_more:1; - uint32_t reserved_15:1; - /** slc1_token1 : RO; bitpos: [27:16]; default: 0; - * reserved - */ - uint32_t slc1_token1:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} sdio_slc1token1_reg_t; - -/** Type of slcconf1 register - * reserved - */ -typedef union { - struct { - /** slc0_check_owner : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc0_check_owner:1; - /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc0_tx_check_sum_en:1; - /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc0_rx_check_sum_en:1; - /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1; - * reserved - */ - uint32_t sdio_cmd_hold_en:1; - /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1; - * reserved - */ - uint32_t slc0_len_auto_clr:1; - /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1; - * reserved - */ - uint32_t slc0_tx_stitch_en:1; - /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1; - * reserved - */ - uint32_t slc0_rx_stitch_en:1; - uint32_t reserved_7:9; - /** slc1_check_owner : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_check_owner:1; - /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc1_tx_check_sum_en:1; - /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc1_rx_check_sum_en:1; - /** host_int_level_sel : R/W; bitpos: [19]; default: 0; - * reserved - */ - uint32_t host_int_level_sel:1; - /** slc1_tx_stitch_en : R/W; bitpos: [20]; default: 1; - * reserved - */ - uint32_t slc1_tx_stitch_en:1; - /** slc1_rx_stitch_en : R/W; bitpos: [21]; default: 1; - * reserved - */ - uint32_t slc1_rx_stitch_en:1; - /** sdio_clk_en : R/W; bitpos: [22]; default: 0; - * reserved - */ - uint32_t sdio_clk_en:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} sdio_slcconf1_reg_t; - -/** Type of slcbridge_conf register - * ******* Description *********** - */ -typedef union { - struct { - /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32; - * reserved - */ - uint32_t slc_txeof_ena:6; - uint32_t reserved_6:2; - /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7; - * reserved - */ - uint32_t slc_fifo_map_ena:4; - /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1; - * reserved - */ - uint32_t slc0_tx_dummy_mode:1; - /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1; - * reserved - */ - uint32_t slc_hda_map_128k:1; - /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1; - * reserved - */ - uint32_t slc1_tx_dummy_mode:1; - uint32_t reserved_15:1; - /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10; - * reserved - */ - uint32_t slc_tx_push_idle_num:16; - }; - uint32_t val; -} sdio_slcbridge_conf_reg_t; - -/** Type of slc0_to_eof_des_addr register - * reserved - */ -typedef union { - struct { - /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_to_eof_des_addr:32; - }; - uint32_t val; -} sdio_slc0_to_eof_des_addr_reg_t; - -/** Type of slc0_tx_eof_des_addr register - * reserved - */ -typedef union { - struct { - /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_tx_suc_eof_des_addr:32; - }; - uint32_t val; -} sdio_slc0_tx_eof_des_addr_reg_t; - -/** Type of slc0_to_eof_bfr_des_addr register - * reserved - */ -typedef union { - struct { - /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_to_eof_bfr_des_addr:32; - }; - uint32_t val; -} sdio_slc0_to_eof_bfr_des_addr_reg_t; - -/** Type of slc1_to_eof_des_addr register - * reserved - */ -typedef union { - struct { - /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_to_eof_des_addr:32; - }; - uint32_t val; -} sdio_slc1_to_eof_des_addr_reg_t; - -/** Type of slc1_tx_eof_des_addr register - * reserved - */ -typedef union { - struct { - /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_tx_suc_eof_des_addr:32; - }; - uint32_t val; -} sdio_slc1_tx_eof_des_addr_reg_t; - -/** Type of slc1_to_eof_bfr_des_addr register - * reserved - */ -typedef union { - struct { - /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_to_eof_bfr_des_addr:32; - }; - uint32_t val; -} sdio_slc1_to_eof_bfr_des_addr_reg_t; - -/** Type of slc_rx_dscr_conf register - * reserved - */ -typedef union { - struct { - /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc0_token_no_replace:1; - /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1; - * reserved - */ - uint32_t slc0_infor_no_replace:1; - /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0; - * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next - * pop doesn't occur after 255 cycles since the current pop - */ - uint32_t slc0_rx_fill_mode:1; - /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1; - * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof - */ - uint32_t slc0_rx_eof_mode:1; - /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1; - * reserved - */ - uint32_t slc0_rx_fill_en:1; - /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128; - * reserved - */ - uint32_t slc0_rd_retry_threshold:11; - /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1; - * reserved - */ - uint32_t slc1_token_no_replace:1; - /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1; - * reserved - */ - uint32_t slc1_infor_no_replace:1; - /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0; - * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next - * pop doesn't occur after 255 cycles since the current pop - */ - uint32_t slc1_rx_fill_mode:1; - /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1; - * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof - */ - uint32_t slc1_rx_eof_mode:1; - /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1; - * reserved - */ - uint32_t slc1_rx_fill_en:1; - /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128; - * reserved - */ - uint32_t slc1_rd_retry_threshold:11; - }; - uint32_t val; -} sdio_slc_rx_dscr_conf_reg_t; - -/** Type of slc_tx_dscr_conf register - * reserved - */ -typedef union { - struct { - /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128; - * reserved - */ - uint32_t slc_wr_retry_threshold:11; - uint32_t reserved_11:21; - }; - uint32_t val; -} sdio_slc_tx_dscr_conf_reg_t; - -/** Type of slc0_len_conf register - * reserved - */ -typedef union { - struct { - /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0; - * reserved - */ - uint32_t slc0_len_wdata:20; - /** slc0_len_wr : WT; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc0_len_wr:1; - /** slc0_len_inc : WT; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc0_len_inc:1; - /** slc0_len_inc_more : WT; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc0_len_inc_more:1; - /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc0_rx_packet_load_en:1; - /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc0_tx_packet_load_en:1; - /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0; - * reserved - */ - uint32_t slc0_rx_get_used_dscr:1; - /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0; - * reserved - */ - uint32_t slc0_tx_get_used_dscr:1; - /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t slc0_rx_new_pkt_ind:1; - /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1; - * reserved - */ - uint32_t slc0_tx_new_pkt_ind:1; - /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0; - * reserved - */ - uint32_t slc0_rx_packet_load_en_st:1; - /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0; - * reserved - */ - uint32_t slc0_tx_packet_load_en_st:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} sdio_slc0_len_conf_reg_t; - -/** Type of slc0_txpkt_h_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_tx_pkt_h_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_txpkt_h_dscr_reg_t; - -/** Type of slc0_txpkt_e_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_tx_pkt_e_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_txpkt_e_dscr_reg_t; - -/** Type of slc0_rxpkt_h_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_rx_pkt_h_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_rxpkt_h_dscr_reg_t; - -/** Type of slc0_rxpkt_e_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_rx_pkt_e_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_rxpkt_e_dscr_reg_t; - -/** Type of slc0_txpktu_h_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_tx_pkt_start_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_txpktu_h_dscr_reg_t; - -/** Type of slc0_txpktu_e_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_tx_pkt_end_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_txpktu_e_dscr_reg_t; - -/** Type of slc0_rxpktu_h_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_rx_pkt_start_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_rxpktu_h_dscr_reg_t; - -/** Type of slc0_rxpktu_e_dscr register - * reserved - */ -typedef union { - struct { - /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_rx_pkt_end_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_rxpktu_e_dscr_reg_t; - -/** Type of slc_seq_position register - * reserved - */ -typedef union { - struct { - /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9; - * reserved - */ - uint32_t slc0_seq_position:8; - /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5; - * reserved - */ - uint32_t slc1_seq_position:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} sdio_slc_seq_position_reg_t; - -/** Type of slc0_dscr_rec_conf register - * reserved - */ -typedef union { - struct { - /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023; - * reserved - */ - uint32_t slc0_rx_dscr_rec_lim:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} sdio_slc0_dscr_rec_conf_reg_t; - -/** Type of slc_sdio_crc_st1 register - * reserved - */ -typedef union { - struct { - /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0; - * reserved - */ - uint32_t cmd_crc_err_cnt:8; - uint32_t reserved_8:23; - /** err_cnt_clr : R/W; bitpos: [31]; default: 0; - * reserved - */ - uint32_t err_cnt_clr:1; - }; - uint32_t val; -} sdio_slc_sdio_crc_st1_reg_t; - -/** Type of slc0_len_lim_conf register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504; - * reserved - */ - uint32_t slc0_len_lim:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} sdio_slc0_len_lim_conf_reg_t; - -/** Type of slc0_tx_sharemem_start register - * reserved - */ -typedef union { - struct { - /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t sdio_slc0_tx_sharemem_start_addr:32; - }; - uint32_t val; -} sdio_slc0_tx_sharemem_start_reg_t; - -/** Type of slc0_tx_sharemem_end register - * reserved - */ -typedef union { - struct { - /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ - uint32_t sdio_slc0_tx_sharemem_end_addr:32; - }; - uint32_t val; -} sdio_slc0_tx_sharemem_end_reg_t; - -/** Type of slc0_rx_sharemem_start register - * reserved - */ -typedef union { - struct { - /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t sdio_slc0_rx_sharemem_start_addr:32; - }; - uint32_t val; -} sdio_slc0_rx_sharemem_start_reg_t; - -/** Type of slc0_rx_sharemem_end register - * reserved - */ -typedef union { - struct { - /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ - uint32_t sdio_slc0_rx_sharemem_end_addr:32; - }; - uint32_t val; -} sdio_slc0_rx_sharemem_end_reg_t; - -/** Type of slc1_tx_sharemem_start register - * reserved - */ -typedef union { - struct { - /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t sdio_slc1_tx_sharemem_start_addr:32; - }; - uint32_t val; -} sdio_slc1_tx_sharemem_start_reg_t; - -/** Type of slc1_tx_sharemem_end register - * reserved - */ -typedef union { - struct { - /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ - uint32_t sdio_slc1_tx_sharemem_end_addr:32; - }; - uint32_t val; -} sdio_slc1_tx_sharemem_end_reg_t; - -/** Type of slc1_rx_sharemem_start register - * reserved - */ -typedef union { - struct { - /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t sdio_slc1_rx_sharemem_start_addr:32; - }; - uint32_t val; -} sdio_slc1_rx_sharemem_start_reg_t; - -/** Type of slc1_rx_sharemem_end register - * reserved - */ -typedef union { - struct { - /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; - * reserved - */ - uint32_t sdio_slc1_rx_sharemem_end_addr:32; - }; - uint32_t val; -} sdio_slc1_rx_sharemem_end_reg_t; - -/** Type of hda_tx_sharemem_start register - * reserved - */ -typedef union { - struct { - /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t sdio_hda_tx_sharemem_start_addr:32; - }; - uint32_t val; -} sdio_hda_tx_sharemem_start_reg_t; - -/** Type of hda_rx_sharemem_start register - * reserved - */ -typedef union { - struct { - /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t sdio_hda_rx_sharemem_start_addr:32; - }; - uint32_t val; -} sdio_hda_rx_sharemem_start_reg_t; - -/** Type of slc_burst_len register - * reserved - */ -typedef union { - struct { - /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1; - * 0-incr4,1-incr8 - */ - uint32_t slc0_txdata_burst_len:1; - /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1; - * 0-incr4,1-incr8 - */ - uint32_t slc0_rxdata_burst_len:1; - /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1; - * 0-incr4,1-incr8 - */ - uint32_t slc1_txdata_burst_len:1; - /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1; - * 0-incr4,1-incr8 - */ - uint32_t slc1_rxdata_burst_len:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} sdio_slc_burst_len_reg_t; - -/** Type of slcid register - * ******* Description *********** - */ -typedef union { - struct { - /** slc_id : R/W; bitpos: [31:0]; default: 256; - * reserved - */ - uint32_t slc_id:32; - }; - uint32_t val; -} sdio_slcid_reg_t; - - -/** Group: Interrupt registers */ -/** Type of slc0int_raw register - * ******* Description *********** - */ -typedef union { - struct { - /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit0_int_raw:1; - /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit1_int_raw:1; - /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit2_int_raw:1; - /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit3_int_raw:1; - /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit4_int_raw:1; - /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit5_int_raw:1; - /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit6_int_raw:1; - /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit7_int_raw:1; - /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc0_rx_start_int_raw:1; - /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc0_tx_start_int_raw:1; - /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc0_rx_udf_int_raw:1; - /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc0_tx_ovf_int_raw:1; - /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc0_token0_1to0_int_raw:1; - /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc0_token1_1to0_int_raw:1; - /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The raw interrupt bit of slc0 finishing receiving data to one buffer - */ - uint32_t slc0_tx_done_int_raw:1; - /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The raw interrupt bit of slc0 finishing receiving data - */ - uint32_t slc0_tx_suc_eof_int_raw:1; - /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * The raw interrupt bit of slc0 finishing sending data from one buffer - */ - uint32_t slc0_rx_done_int_raw:1; - /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * The raw interrupt bit of slc0 finishing sending data - */ - uint32_t slc0_rx_eof_int_raw:1; - /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc0_tohost_int_raw:1; - /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * The raw interrupt bit of slc0 tx link descriptor error - */ - uint32_t slc0_tx_dscr_err_int_raw:1; - /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * The raw interrupt bit of slc0 rx link descriptor error - */ - uint32_t slc0_rx_dscr_err_int_raw:1; - /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_empty_int_raw:1; - /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc0_host_rd_ack_int_raw:1; - /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc0_wr_retry_done_int_raw:1; - /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc0_tx_err_eof_int_raw:1; - /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * reserved - */ - uint32_t cmd_dtc_int_raw:1; - /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * reserved - */ - uint32_t slc0_rx_quick_eof_int_raw:1; - /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * reserved - */ - uint32_t slc0_host_pop_eof_err_int_raw:1; - /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * reserved - */ - uint32_t hda_recv_done_int_raw:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} sdio_slc0int_raw_reg_t; - -/** Type of slc0int_st register - * ******* Description *********** - */ -typedef union { - struct { - /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit0_int_st:1; - /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit1_int_st:1; - /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit2_int_st:1; - /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit3_int_st:1; - /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit4_int_st:1; - /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit5_int_st:1; - /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit6_int_st:1; - /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit7_int_st:1; - /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc0_rx_start_int_st:1; - /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc0_tx_start_int_st:1; - /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc0_rx_udf_int_st:1; - /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc0_tx_ovf_int_st:1; - /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc0_token0_1to0_int_st:1; - /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc0_token1_1to0_int_st:1; - /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc0_tx_done_int_st:1; - /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc0_tx_suc_eof_int_st:1; - /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_rx_done_int_st:1; - /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc0_rx_eof_int_st:1; - /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc0_tohost_int_st:1; - /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_err_int_st:1; - /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc0_rx_dscr_err_int_st:1; - /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_empty_int_st:1; - /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc0_host_rd_ack_int_st:1; - /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc0_wr_retry_done_int_st:1; - /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc0_tx_err_eof_int_st:1; - /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0; - * reserved - */ - uint32_t cmd_dtc_int_st:1; - /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0; - * reserved - */ - uint32_t slc0_rx_quick_eof_int_st:1; - /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t slc0_host_pop_eof_err_int_st:1; - /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0; - * reserved - */ - uint32_t hda_recv_done_int_st:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} sdio_slc0int_st_reg_t; - -/** Type of slc0int_ena register - * ******* Description *********** - */ -typedef union { - struct { - /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit0_int_ena:1; - /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit1_int_ena:1; - /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit2_int_ena:1; - /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit3_int_ena:1; - /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit4_int_ena:1; - /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit5_int_ena:1; - /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit6_int_ena:1; - /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit7_int_ena:1; - /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc0_rx_start_int_ena:1; - /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc0_tx_start_int_ena:1; - /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc0_rx_udf_int_ena:1; - /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc0_tx_ovf_int_ena:1; - /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc0_token0_1to0_int_ena:1; - /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc0_token1_1to0_int_ena:1; - /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc0_tx_done_int_ena:1; - /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc0_tx_suc_eof_int_ena:1; - /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_rx_done_int_ena:1; - /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc0_rx_eof_int_ena:1; - /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc0_tohost_int_ena:1; - /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_err_int_ena:1; - /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc0_rx_dscr_err_int_ena:1; - /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_empty_int_ena:1; - /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc0_host_rd_ack_int_ena:1; - /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc0_wr_retry_done_int_ena:1; - /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc0_tx_err_eof_int_ena:1; - /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0; - * reserved - */ - uint32_t cmd_dtc_int_ena:1; - /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0; - * reserved - */ - uint32_t slc0_rx_quick_eof_int_ena:1; - /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0; - * reserved - */ - uint32_t slc0_host_pop_eof_err_int_ena:1; - /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0; - * reserved - */ - uint32_t hda_recv_done_int_ena:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} sdio_slc0int_ena_reg_t; - -/** Type of slc0int_clr register - * ******* Description *********** - */ -typedef union { - struct { - /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit0_int_clr:1; - /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit1_int_clr:1; - /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit2_int_clr:1; - /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit3_int_clr:1; - /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit4_int_clr:1; - /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit5_int_clr:1; - /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit6_int_clr:1; - /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit7_int_clr:1; - /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc0_rx_start_int_clr:1; - /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc0_tx_start_int_clr:1; - /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc0_rx_udf_int_clr:1; - /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc0_tx_ovf_int_clr:1; - /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc0_token0_1to0_int_clr:1; - /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc0_token1_1to0_int_clr:1; - /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc0_tx_done_int_clr:1; - /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc0_tx_suc_eof_int_clr:1; - /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_rx_done_int_clr:1; - /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc0_rx_eof_int_clr:1; - /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc0_tohost_int_clr:1; - /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_err_int_clr:1; - /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc0_rx_dscr_err_int_clr:1; - /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_empty_int_clr:1; - /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc0_host_rd_ack_int_clr:1; - /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc0_wr_retry_done_int_clr:1; - /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc0_tx_err_eof_int_clr:1; - /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0; - * reserved - */ - uint32_t cmd_dtc_int_clr:1; - /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0; - * reserved - */ - uint32_t slc0_rx_quick_eof_int_clr:1; - /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0; - * reserved - */ - uint32_t slc0_host_pop_eof_err_int_clr:1; - /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0; - * reserved - */ - uint32_t hda_recv_done_int_clr:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} sdio_slc0int_clr_reg_t; - -/** Type of slc1int_raw register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit8_int_raw:1; - /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit9_int_raw:1; - /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit10_int_raw:1; - /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit11_int_raw:1; - /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit12_int_raw:1; - /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit13_int_raw:1; - /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit14_int_raw:1; - /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit15_int_raw:1; - /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc1_rx_start_int_raw:1; - /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc1_tx_start_int_raw:1; - /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc1_rx_udf_int_raw:1; - /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc1_tx_ovf_int_raw:1; - /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc1_token0_1to0_int_raw:1; - /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc1_token1_1to0_int_raw:1; - /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc1_tx_done_int_raw:1; - /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc1_tx_suc_eof_int_raw:1; - /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rx_done_int_raw:1; - /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc1_rx_eof_int_raw:1; - /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc1_tohost_int_raw:1; - /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_err_int_raw:1; - /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc1_rx_dscr_err_int_raw:1; - /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_empty_int_raw:1; - /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc1_host_rd_ack_int_raw:1; - /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc1_wr_retry_done_int_raw:1; - /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc1_tx_err_eof_int_raw:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} sdio_slc1int_raw_reg_t; - -/** Type of slc1int_st register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit8_int_st:1; - /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit9_int_st:1; - /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit10_int_st:1; - /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit11_int_st:1; - /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit12_int_st:1; - /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit13_int_st:1; - /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit14_int_st:1; - /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit15_int_st:1; - /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc1_rx_start_int_st:1; - /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc1_tx_start_int_st:1; - /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc1_rx_udf_int_st:1; - /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc1_tx_ovf_int_st:1; - /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc1_token0_1to0_int_st:1; - /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc1_token1_1to0_int_st:1; - /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc1_tx_done_int_st:1; - /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc1_tx_suc_eof_int_st:1; - /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rx_done_int_st:1; - /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc1_rx_eof_int_st:1; - /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc1_tohost_int_st:1; - /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_err_int_st:1; - /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc1_rx_dscr_err_int_st:1; - /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_empty_int_st:1; - /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc1_host_rd_ack_int_st:1; - /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc1_wr_retry_done_int_st:1; - /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc1_tx_err_eof_int_st:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} sdio_slc1int_st_reg_t; - -/** Type of slc1int_ena register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit8_int_ena:1; - /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit9_int_ena:1; - /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit10_int_ena:1; - /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit11_int_ena:1; - /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit12_int_ena:1; - /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit13_int_ena:1; - /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit14_int_ena:1; - /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit15_int_ena:1; - /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc1_rx_start_int_ena:1; - /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc1_tx_start_int_ena:1; - /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc1_rx_udf_int_ena:1; - /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc1_tx_ovf_int_ena:1; - /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc1_token0_1to0_int_ena:1; - /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc1_token1_1to0_int_ena:1; - /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc1_tx_done_int_ena:1; - /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc1_tx_suc_eof_int_ena:1; - /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rx_done_int_ena:1; - /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc1_rx_eof_int_ena:1; - /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc1_tohost_int_ena:1; - /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_err_int_ena:1; - /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc1_rx_dscr_err_int_ena:1; - /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_empty_int_ena:1; - /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc1_host_rd_ack_int_ena:1; - /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc1_wr_retry_done_int_ena:1; - /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc1_tx_err_eof_int_ena:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} sdio_slc1int_ena_reg_t; - -/** Type of slc1int_clr register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit8_int_clr:1; - /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit9_int_clr:1; - /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit10_int_clr:1; - /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit11_int_clr:1; - /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit12_int_clr:1; - /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit13_int_clr:1; - /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit14_int_clr:1; - /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit15_int_clr:1; - /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc1_rx_start_int_clr:1; - /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc1_tx_start_int_clr:1; - /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc1_rx_udf_int_clr:1; - /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc1_tx_ovf_int_clr:1; - /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc1_token0_1to0_int_clr:1; - /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc1_token1_1to0_int_clr:1; - /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc1_tx_done_int_clr:1; - /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc1_tx_suc_eof_int_clr:1; - /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rx_done_int_clr:1; - /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc1_rx_eof_int_clr:1; - /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc1_tohost_int_clr:1; - /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_err_int_clr:1; - /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc1_rx_dscr_err_int_clr:1; - /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_empty_int_clr:1; - /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc1_host_rd_ack_int_clr:1; - /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc1_wr_retry_done_int_clr:1; - /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc1_tx_err_eof_int_clr:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} sdio_slc1int_clr_reg_t; - -/** Type of slc0int_st1 register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit0_int_st1:1; - /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit1_int_st1:1; - /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit2_int_st1:1; - /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit3_int_st1:1; - /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit4_int_st1:1; - /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit5_int_st1:1; - /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit6_int_st1:1; - /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit7_int_st1:1; - /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc0_rx_start_int_st1:1; - /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc0_tx_start_int_st1:1; - /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc0_rx_udf_int_st1:1; - /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc0_tx_ovf_int_st1:1; - /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc0_token0_1to0_int_st1:1; - /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc0_token1_1to0_int_st1:1; - /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc0_tx_done_int_st1:1; - /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc0_tx_suc_eof_int_st1:1; - /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_rx_done_int_st1:1; - /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc0_rx_eof_int_st1:1; - /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc0_tohost_int_st1:1; - /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_err_int_st1:1; - /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc0_rx_dscr_err_int_st1:1; - /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_empty_int_st1:1; - /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc0_host_rd_ack_int_st1:1; - /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc0_wr_retry_done_int_st1:1; - /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc0_tx_err_eof_int_st1:1; - /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0; - * reserved - */ - uint32_t cmd_dtc_int_st1:1; - /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0; - * reserved - */ - uint32_t slc0_rx_quick_eof_int_st1:1; - /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t slc0_host_pop_eof_err_int_st1:1; - /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0; - * reserved - */ - uint32_t hda_recv_done_int_st1:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} sdio_slc0int_st1_reg_t; - -/** Type of slc0int_ena1 register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit0_int_ena1:1; - /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit1_int_ena1:1; - /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit2_int_ena1:1; - /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit3_int_ena1:1; - /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit4_int_ena1:1; - /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit5_int_ena1:1; - /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit6_int_ena1:1; - /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit7_int_ena1:1; - /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc0_rx_start_int_ena1:1; - /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc0_tx_start_int_ena1:1; - /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc0_rx_udf_int_ena1:1; - /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc0_tx_ovf_int_ena1:1; - /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc0_token0_1to0_int_ena1:1; - /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc0_token1_1to0_int_ena1:1; - /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc0_tx_done_int_ena1:1; - /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc0_tx_suc_eof_int_ena1:1; - /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_rx_done_int_ena1:1; - /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc0_rx_eof_int_ena1:1; - /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc0_tohost_int_ena1:1; - /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_err_int_ena1:1; - /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc0_rx_dscr_err_int_ena1:1; - /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc0_tx_dscr_empty_int_ena1:1; - /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc0_host_rd_ack_int_ena1:1; - /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc0_wr_retry_done_int_ena1:1; - /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc0_tx_err_eof_int_ena1:1; - /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0; - * reserved - */ - uint32_t cmd_dtc_int_ena1:1; - /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0; - * reserved - */ - uint32_t slc0_rx_quick_eof_int_ena1:1; - /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0; - * reserved - */ - uint32_t slc0_host_pop_eof_err_int_ena1:1; - /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0; - * reserved - */ - uint32_t hda_recv_done_int_ena1:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} sdio_slc0int_ena1_reg_t; - -/** Type of slc1int_st1 register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit8_int_st1:1; - /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit9_int_st1:1; - /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit10_int_st1:1; - /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit11_int_st1:1; - /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit12_int_st1:1; - /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit13_int_st1:1; - /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit14_int_st1:1; - /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit15_int_st1:1; - /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc1_rx_start_int_st1:1; - /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc1_tx_start_int_st1:1; - /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc1_rx_udf_int_st1:1; - /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc1_tx_ovf_int_st1:1; - /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc1_token0_1to0_int_st1:1; - /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc1_token1_1to0_int_st1:1; - /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc1_tx_done_int_st1:1; - /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc1_tx_suc_eof_int_st1:1; - /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rx_done_int_st1:1; - /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc1_rx_eof_int_st1:1; - /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc1_tohost_int_st1:1; - /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_err_int_st1:1; - /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc1_rx_dscr_err_int_st1:1; - /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_empty_int_st1:1; - /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc1_host_rd_ack_int_st1:1; - /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc1_wr_retry_done_int_st1:1; - /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc1_tx_err_eof_int_st1:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} sdio_slc1int_st1_reg_t; - -/** Type of slc1int_ena1 register - * reserved - */ -typedef union { - struct { - /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit8_int_ena1:1; - /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit9_int_ena1:1; - /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit10_int_ena1:1; - /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit11_int_ena1:1; - /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit12_int_ena1:1; - /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit13_int_ena1:1; - /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit14_int_ena1:1; - /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0; - * reserved - */ - uint32_t slc_frhost_bit15_int_ena1:1; - /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; - * reserved - */ - uint32_t slc1_rx_start_int_ena1:1; - /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; - * reserved - */ - uint32_t slc1_tx_start_int_ena1:1; - /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; - * reserved - */ - uint32_t slc1_rx_udf_int_ena1:1; - /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; - * reserved - */ - uint32_t slc1_tx_ovf_int_ena1:1; - /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; - * reserved - */ - uint32_t slc1_token0_1to0_int_ena1:1; - /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; - * reserved - */ - uint32_t slc1_token1_1to0_int_ena1:1; - /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; - * reserved - */ - uint32_t slc1_tx_done_int_ena1:1; - /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; - * reserved - */ - uint32_t slc1_tx_suc_eof_int_ena1:1; - /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rx_done_int_ena1:1; - /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; - * reserved - */ - uint32_t slc1_rx_eof_int_ena1:1; - /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; - * reserved - */ - uint32_t slc1_tohost_int_ena1:1; - /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_err_int_ena1:1; - /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; - * reserved - */ - uint32_t slc1_rx_dscr_err_int_ena1:1; - /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; - * reserved - */ - uint32_t slc1_tx_dscr_empty_int_ena1:1; - /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; - * reserved - */ - uint32_t slc1_host_rd_ack_int_ena1:1; - /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; - * reserved - */ - uint32_t slc1_wr_retry_done_int_ena1:1; - /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; - * reserved - */ - uint32_t slc1_tx_err_eof_int_ena1:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} sdio_slc1int_ena1_reg_t; - - -/** Group: Status registers */ -/** Type of slcrx_status register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_rx_full : RO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc0_rx_full:1; - /** slc0_rx_empty : RO; bitpos: [1]; default: 1; - * reserved - */ - uint32_t slc0_rx_empty:1; - /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0; - * the current buffer length when slc0 reads data from rx link - */ - uint32_t slc0_rx_buf_len:14; - /** slc1_rx_full : RO; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_rx_full:1; - /** slc1_rx_empty : RO; bitpos: [17]; default: 1; - * reserved - */ - uint32_t slc1_rx_empty:1; - /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0; - * the current buffer length when slc1 reads data from rx link - */ - uint32_t slc1_rx_buf_len:14; - }; - uint32_t val; -} sdio_slcrx_status_reg_t; - -/** Type of slctx_status register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_tx_full : RO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t slc0_tx_full:1; - /** slc0_tx_empty : RO; bitpos: [1]; default: 1; - * reserved - */ - uint32_t slc0_tx_empty:1; - uint32_t reserved_2:14; - /** slc1_tx_full : RO; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_tx_full:1; - /** slc1_tx_empty : RO; bitpos: [17]; default: 1; - * reserved - */ - uint32_t slc1_tx_empty:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} sdio_slctx_status_reg_t; - -/** Type of slc0_state0 register - * reserved - */ -typedef union { - struct { - /** slc0_state0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_state0:32; - }; - uint32_t val; -} sdio_slc0_state0_reg_t; - -/** Type of slc0_state1 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_state1 : RO; bitpos: [31:0]; default: 0; - * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] - * rx_link fsm state, [30:24] rx_fifo_cnt - */ - uint32_t slc0_state1:32; - }; - uint32_t val; -} sdio_slc0_state1_reg_t; - -/** Type of slc1_state0 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc1_state0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_state0:32; - }; - uint32_t val; -} sdio_slc1_state0_reg_t; - -/** Type of slc1_state1 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc1_state1 : RO; bitpos: [31:0]; default: 0; - * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] - * rx_link fsm state, [30:24] rx_fifo_cnt - */ - uint32_t slc1_state1:32; - }; - uint32_t val; -} sdio_slc1_state1_reg_t; - -/** Type of slc_sdio_st register - * reserved - */ -typedef union { - struct { - /** cmd_st : RO; bitpos: [2:0]; default: 0; - * reserved - */ - uint32_t cmd_st:3; - uint32_t reserved_3:1; - /** func_st : RO; bitpos: [7:4]; default: 0; - * reserved - */ - uint32_t func_st:4; - /** sdio_wakeup : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t sdio_wakeup:1; - uint32_t reserved_9:3; - /** bus_st : RO; bitpos: [14:12]; default: 0; - * reserved - */ - uint32_t bus_st:3; - uint32_t reserved_15:1; - /** func1_acc_state : RO; bitpos: [20:16]; default: 0; - * reserved - */ - uint32_t func1_acc_state:5; - uint32_t reserved_21:3; - /** func2_acc_state : RO; bitpos: [28:24]; default: 0; - * reserved - */ - uint32_t func2_acc_state:5; - uint32_t reserved_29:3; - }; - uint32_t val; -} sdio_slc_sdio_st_reg_t; - -/** Type of slc0_txlink_dscr register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_txlink_dscr:32; - }; - uint32_t val; -} sdio_slc0_txlink_dscr_reg_t; - -/** Type of slc0_txlink_dscr_bf0 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_txlink_dscr_bf0:32; - }; - uint32_t val; -} sdio_slc0_txlink_dscr_bf0_reg_t; - -/** Type of slc0_txlink_dscr_bf1 register - * reserved - */ -typedef union { - struct { - /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_txlink_dscr_bf1:32; - }; - uint32_t val; -} sdio_slc0_txlink_dscr_bf1_reg_t; - -/** Type of slc0_rxlink_dscr register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0; - * the third word of slc0 link descriptor, or known as the next descriptor address - */ - uint32_t slc0_rxlink_dscr:32; - }; - uint32_t val; -} sdio_slc0_rxlink_dscr_reg_t; - -/** Type of slc0_rxlink_dscr_bf0 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_rxlink_dscr_bf0:32; - }; - uint32_t val; -} sdio_slc0_rxlink_dscr_bf0_reg_t; - -/** Type of slc0_rxlink_dscr_bf1 register - * reserved - */ -typedef union { - struct { - /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_rxlink_dscr_bf1:32; - }; - uint32_t val; -} sdio_slc0_rxlink_dscr_bf1_reg_t; - -/** Type of slc1_txlink_dscr register - * reserved - */ -typedef union { - struct { - /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_txlink_dscr:32; - }; - uint32_t val; -} sdio_slc1_txlink_dscr_reg_t; - -/** Type of slc1_txlink_dscr_bf0 register - * reserved - */ -typedef union { - struct { - /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_txlink_dscr_bf0:32; - }; - uint32_t val; -} sdio_slc1_txlink_dscr_bf0_reg_t; - -/** Type of slc1_txlink_dscr_bf1 register - * reserved - */ -typedef union { - struct { - /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_txlink_dscr_bf1:32; - }; - uint32_t val; -} sdio_slc1_txlink_dscr_bf1_reg_t; - -/** Type of slc1_rxlink_dscr register - * ******* Description *********** - */ -typedef union { - struct { - /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0; - * the third word of slc1 link descriptor, or known as the next descriptor address - */ - uint32_t slc1_rxlink_dscr:32; - }; - uint32_t val; -} sdio_slc1_rxlink_dscr_reg_t; - -/** Type of slc1_rxlink_dscr_bf0 register - * ******* Description *********** - */ -typedef union { - struct { - /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_rxlink_dscr_bf0:32; - }; - uint32_t val; -} sdio_slc1_rxlink_dscr_bf0_reg_t; - -/** Type of slc1_rxlink_dscr_bf1 register - * reserved - */ -typedef union { - struct { - /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_rxlink_dscr_bf1:32; - }; - uint32_t val; -} sdio_slc1_rxlink_dscr_bf1_reg_t; - -/** Type of slc0_tx_erreof_des_addr register - * reserved - */ -typedef union { - struct { - /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_tx_err_eof_des_addr:32; - }; - uint32_t val; -} sdio_slc0_tx_erreof_des_addr_reg_t; - -/** Type of slc1_tx_erreof_des_addr register - * reserved - */ -typedef union { - struct { - /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc1_tx_err_eof_des_addr:32; - }; - uint32_t val; -} sdio_slc1_tx_erreof_des_addr_reg_t; - -/** Type of slc_token_lat register - * reserved - */ -typedef union { - struct { - /** slc0_token : RO; bitpos: [11:0]; default: 0; - * reserved - */ - uint32_t slc0_token:12; - uint32_t reserved_12:4; - /** slc1_token : RO; bitpos: [27:16]; default: 0; - * reserved - */ - uint32_t slc1_token:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} sdio_slc_token_lat_reg_t; - -/** Type of slc_cmd_infor0 register - * reserved - */ -typedef union { - struct { - /** cmd_content0 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t cmd_content0:32; - }; - uint32_t val; -} sdio_slc_cmd_infor0_reg_t; - -/** Type of slc_cmd_infor1 register - * reserved - */ -typedef union { - struct { - /** cmd_content1 : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t cmd_content1:32; - }; - uint32_t val; -} sdio_slc_cmd_infor1_reg_t; - -/** Type of slc0_length register - * reserved - */ -typedef union { - struct { - /** slc0_len : RO; bitpos: [19:0]; default: 0; - * reserved - */ - uint32_t slc0_len:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} sdio_slc0_length_reg_t; - -/** Type of slc_sdio_crc_st0 register - * reserved - */ -typedef union { - struct { - /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0; - * reserved - */ - uint32_t dat0_crc_err_cnt:8; - /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0; - * reserved - */ - uint32_t dat1_crc_err_cnt:8; - /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0; - * reserved - */ - uint32_t dat2_crc_err_cnt:8; - /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0; - * reserved - */ - uint32_t dat3_crc_err_cnt:8; - }; - uint32_t val; -} sdio_slc_sdio_crc_st0_reg_t; - -/** Type of slc0_eof_start_des register - * reserved - */ -typedef union { - struct { - /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0; - * reserved - */ - uint32_t slc0_eof_start_des_addr:32; - }; - uint32_t val; -} sdio_slc0_eof_start_des_reg_t; - -/** Type of slc0_push_dscr_addr register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0; - * the current descriptor address when slc0 gets a link descriptor, aligned with word - */ - uint32_t slc0_rx_push_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_push_dscr_addr_reg_t; - -/** Type of slc0_done_dscr_addr register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0; - * the current descriptor address when slc0 finishes reading data from one buffer, - * aligned with word - */ - uint32_t slc0_rx_done_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_done_dscr_addr_reg_t; - -/** Type of slc0_sub_start_des register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0; - * the current descriptor address when slc0 gets a link descriptor, aligned with word - */ - uint32_t slc0_sub_pac_start_dscr_addr:32; - }; - uint32_t val; -} sdio_slc0_sub_start_des_reg_t; - -/** Type of slc0_dscr_cnt register - * ******* Description *********** - */ -typedef union { - struct { - /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0; - * the number of descriptors got by slc0 when it tries to read data from memory - */ - uint32_t slc0_rx_dscr_cnt_lat:10; - uint32_t reserved_10:6; - /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_rx_get_eof_occ:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} sdio_slc0_dscr_cnt_reg_t; - - -/** Group: Debud registers */ -/** Type of slc0txfifo_pop register - * reserved - */ -typedef union { - struct { - /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; - * reserved - */ - uint32_t slc0_txfifo_rdata:11; - uint32_t reserved_11:5; - /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc0_txfifo_pop:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} sdio_slc0txfifo_pop_reg_t; - -/** Type of slc1txfifo_pop register - * reserved - */ -typedef union { - struct { - /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; - * reserved - */ - uint32_t slc1_txfifo_rdata:11; - uint32_t reserved_11:5; - /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; - * reserved - */ - uint32_t slc1_txfifo_pop:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} sdio_slc1txfifo_pop_reg_t; - -/** Type of slc_ahb_test register - * reserved - */ -typedef union { - struct { - /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0; - * reserved - */ - uint32_t slc_ahb_testmode:3; - uint32_t reserved_3:1; - /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0; - * reserved - */ - uint32_t slc_ahb_testaddr:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} sdio_slc_ahb_test_reg_t; - - -/** Group: Version registers */ -/** Type of slcdate register - * ******* Description *********** - */ -typedef union { - struct { - /** slc_date : R/W; bitpos: [31:0]; default: 554182400; - * reserved - */ - uint32_t slc_date:32; - }; - uint32_t val; -} sdio_slcdate_reg_t; - - -typedef struct slc_dev_t { - volatile sdio_slcconf0_reg_t slcconf0; - volatile sdio_slc0int_raw_reg_t slc0int_raw; - volatile sdio_slc0int_st_reg_t slc0int_st; - volatile sdio_slc0int_ena_reg_t slc0int_ena; - volatile sdio_slc0int_clr_reg_t slc0int_clr; - volatile sdio_slc1int_raw_reg_t slc1int_raw; - volatile sdio_slc1int_st_reg_t slc1int_st; - volatile sdio_slc1int_ena_reg_t slc1int_ena; - volatile sdio_slc1int_clr_reg_t slc1int_clr; - volatile sdio_slcrx_status_reg_t slcrx_status; - volatile sdio_slc0rxfifo_push_reg_t slc0rxfifo_push; - volatile sdio_slc1rxfifo_push_reg_t slc1rxfifo_push; - volatile sdio_slctx_status_reg_t slctx_status; - volatile sdio_slc0txfifo_pop_reg_t slc0txfifo_pop; - volatile sdio_slc1txfifo_pop_reg_t slc1txfifo_pop; - volatile sdio_slc0rx_link_reg_t slc0rx_link; - volatile sdio_slc0rx_link_addr_reg_t slc0rx_link_addr; - volatile sdio_slc0tx_link_reg_t slc0tx_link; - volatile sdio_slc0tx_link_addr_reg_t slc0tx_link_addr; - volatile sdio_slc1rx_link_reg_t slc1rx_link; - volatile sdio_slc1rx_link_addr_reg_t slc1rx_link_addr; - volatile sdio_slc1tx_link_reg_t slc1tx_link; - volatile sdio_slc1tx_link_addr_reg_t slc1tx_link_addr; - volatile sdio_slcintvec_tohost_reg_t slcintvec_tohost; - volatile sdio_slc0token0_reg_t slc0token0; - volatile sdio_slc0token1_reg_t slc0token1; - volatile sdio_slc1token0_reg_t slc1token0; - volatile sdio_slc1token1_reg_t slc1token1; - volatile sdio_slcconf1_reg_t slcconf1; - volatile sdio_slc0_state0_reg_t slc0_state0; - volatile sdio_slc0_state1_reg_t slc0_state1; - volatile sdio_slc1_state0_reg_t slc1_state0; - volatile sdio_slc1_state1_reg_t slc1_state1; - volatile sdio_slcbridge_conf_reg_t slcbridge_conf; - volatile sdio_slc0_to_eof_des_addr_reg_t slc0_to_eof_des_addr; - volatile sdio_slc0_tx_eof_des_addr_reg_t slc0_tx_eof_des_addr; - volatile sdio_slc0_to_eof_bfr_des_addr_reg_t slc0_to_eof_bfr_des_addr; - volatile sdio_slc1_to_eof_des_addr_reg_t slc1_to_eof_des_addr; - volatile sdio_slc1_tx_eof_des_addr_reg_t slc1_tx_eof_des_addr; - volatile sdio_slc1_to_eof_bfr_des_addr_reg_t slc1_to_eof_bfr_des_addr; - volatile sdio_slc_ahb_test_reg_t slc_ahb_test; - volatile sdio_slc_sdio_st_reg_t slc_sdio_st; - volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf; - volatile sdio_slc0_txlink_dscr_reg_t slc0_txlink_dscr; - volatile sdio_slc0_txlink_dscr_bf0_reg_t slc0_txlink_dscr_bf0; - volatile sdio_slc0_txlink_dscr_bf1_reg_t slc0_txlink_dscr_bf1; - volatile sdio_slc0_rxlink_dscr_reg_t slc0_rxlink_dscr; - volatile sdio_slc0_rxlink_dscr_bf0_reg_t slc0_rxlink_dscr_bf0; - volatile sdio_slc0_rxlink_dscr_bf1_reg_t slc0_rxlink_dscr_bf1; - volatile sdio_slc1_txlink_dscr_reg_t slc1_txlink_dscr; - volatile sdio_slc1_txlink_dscr_bf0_reg_t slc1_txlink_dscr_bf0; - volatile sdio_slc1_txlink_dscr_bf1_reg_t slc1_txlink_dscr_bf1; - volatile sdio_slc1_rxlink_dscr_reg_t slc1_rxlink_dscr; - volatile sdio_slc1_rxlink_dscr_bf0_reg_t slc1_rxlink_dscr_bf0; - volatile sdio_slc1_rxlink_dscr_bf1_reg_t slc1_rxlink_dscr_bf1; - volatile sdio_slc0_tx_erreof_des_addr_reg_t slc0_tx_erreof_des_addr; - volatile sdio_slc1_tx_erreof_des_addr_reg_t slc1_tx_erreof_des_addr; - volatile sdio_slc_token_lat_reg_t slc_token_lat; - volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf; - volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0; - volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1; - volatile sdio_slc0_len_conf_reg_t slc0_len_conf; - volatile sdio_slc0_length_reg_t slc0_length; - volatile sdio_slc0_txpkt_h_dscr_reg_t slc0_txpkt_h_dscr; - volatile sdio_slc0_txpkt_e_dscr_reg_t slc0_txpkt_e_dscr; - volatile sdio_slc0_rxpkt_h_dscr_reg_t slc0_rxpkt_h_dscr; - volatile sdio_slc0_rxpkt_e_dscr_reg_t slc0_rxpkt_e_dscr; - volatile sdio_slc0_txpktu_h_dscr_reg_t slc0_txpktu_h_dscr; - volatile sdio_slc0_txpktu_e_dscr_reg_t slc0_txpktu_e_dscr; - volatile sdio_slc0_rxpktu_h_dscr_reg_t slc0_rxpktu_h_dscr; - volatile sdio_slc0_rxpktu_e_dscr_reg_t slc0_rxpktu_e_dscr; - volatile sdio_slc_seq_position_reg_t slc_seq_position; - volatile sdio_slc0_dscr_rec_conf_reg_t slc0_dscr_rec_conf; - volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0; - volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1; - volatile sdio_slc0_eof_start_des_reg_t slc0_eof_start_des; - volatile sdio_slc0_push_dscr_addr_reg_t slc0_push_dscr_addr; - volatile sdio_slc0_done_dscr_addr_reg_t slc0_done_dscr_addr; - volatile sdio_slc0_sub_start_des_reg_t slc0_sub_start_des; - volatile sdio_slc0_dscr_cnt_reg_t slc0_dscr_cnt; - volatile sdio_slc0_len_lim_conf_reg_t slc0_len_lim_conf; - volatile sdio_slc0int_st1_reg_t slc0int_st1; - volatile sdio_slc0int_ena1_reg_t slc0int_ena1; - volatile sdio_slc1int_st1_reg_t slc1int_st1; - volatile sdio_slc1int_ena1_reg_t slc1int_ena1; - volatile sdio_slc0_tx_sharemem_start_reg_t slc0_tx_sharemem_start; - volatile sdio_slc0_tx_sharemem_end_reg_t slc0_tx_sharemem_end; - volatile sdio_slc0_rx_sharemem_start_reg_t slc0_rx_sharemem_start; - volatile sdio_slc0_rx_sharemem_end_reg_t slc0_rx_sharemem_end; - volatile sdio_slc1_tx_sharemem_start_reg_t slc1_tx_sharemem_start; - volatile sdio_slc1_tx_sharemem_end_reg_t slc1_tx_sharemem_end; - volatile sdio_slc1_rx_sharemem_start_reg_t slc1_rx_sharemem_start; - volatile sdio_slc1_rx_sharemem_end_reg_t slc1_rx_sharemem_end; - volatile sdio_hda_tx_sharemem_start_reg_t hda_tx_sharemem_start; - volatile sdio_hda_rx_sharemem_start_reg_t hda_rx_sharemem_start; - volatile sdio_slc_burst_len_reg_t slc_burst_len; - uint32_t reserved_180[30]; - volatile sdio_slcdate_reg_t slcdate; - volatile sdio_slcid_reg_t slcid; -} slc_dev_t; - -extern slc_dev_t SLC; - -#ifndef __cplusplus -_Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index a0e2870af6..ba04102638 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -134,6 +134,7 @@ #endif /* !__ASSEMBLER__ */ //}} +//TODO: IDF-7526 //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM diff --git a/components/soc/esp32p4/include/soc/spi_mem_struct.h b/components/soc/esp32p4/include/soc/spi_mem_struct.h index 888ad4e031..73af7d2536 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_struct.h +++ b/components/soc/esp32p4/include/soc/spi_mem_struct.h @@ -10,7 +10,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct spi_mem_dev_s { union { struct { uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/ diff --git a/components/soc/esp32p4/include/soc/spi_pins.h b/components/soc/esp32p4/include/soc/spi_pins.h index bdfce943a2..d2aa55b41e 100644 --- a/components/soc/esp32p4/include/soc/spi_pins.h +++ b/components/soc/esp32p4/include/soc/spi_pins.h @@ -4,23 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SPI_PINS_H_ -#define _SOC_SPI_PINS_H_ - -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_HD 12 -#define SPI_IOMUX_PIN_NUM_CS 14 -#define SPI_IOMUX_PIN_NUM_MOSI 16 -#define SPI_IOMUX_PIN_NUM_CLK 15 -#define SPI_IOMUX_PIN_NUM_MISO 17 -#define SPI_IOMUX_PIN_NUM_WP 13 - -#define SPI2_FUNC_NUM 2 -#define SPI2_IOMUX_PIN_NUM_MISO 2 -#define SPI2_IOMUX_PIN_NUM_HD 4 -#define SPI2_IOMUX_PIN_NUM_WP 5 -#define SPI2_IOMUX_PIN_NUM_CLK 6 -#define SPI2_IOMUX_PIN_NUM_MOSI 7 -#define SPI2_IOMUX_PIN_NUM_CS 10 - -#endif +#pragma once diff --git a/components/soc/esp32p4/include/soc/sys_clkrst_reg.h b/components/soc/esp32p4/include/soc/sys_clkrst_reg.h deleted file mode 100644 index 202223cf00..0000000000 --- a/components/soc/esp32p4/include/soc/sys_clkrst_reg.h +++ /dev/null @@ -1,1118 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_SYS_CLKRST_REG_H_ -#define _SOC_SYS_CLKRST_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" - -#define SYS_CLKRST_SYS_CLK_VER_DATE_REG (DR_REG_SYS_CLKRST_BASE + 0x0) -/* SYS_CLKRST_VER_DATE : R/W ;bitpos:[31:0] ;default: 32'h20210610 ; */ -/*description: .*/ -#define SYS_CLKRST_VER_DATE 0xFFFFFFFF -#define SYS_CLKRST_VER_DATE_M ((SYS_CLKRST_VER_DATE_V)<<(SYS_CLKRST_VER_DATE_S)) -#define SYS_CLKRST_VER_DATE_V 0xFFFFFFFF -#define SYS_CLKRST_VER_DATE_S 0 - -#define SYS_CLKRST_SYS_ICM_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x4) -/* SYS_CLKRST_SYS_ICM_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: system icm clock enable.*/ -#define SYS_CLKRST_SYS_ICM_APB_CLK_EN (BIT(0)) -#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_SYS_ICM_APB_CLK_EN_S 0 - -#define SYS_CLKRST_JPEG_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x8) -/* SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_JPEG_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_JPEG_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_M ((SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_JPEG_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_JPEG_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_JPEG_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_JPEG_CLK_DIV_NUM_M ((SYS_CLKRST_JPEG_CLK_DIV_NUM_V)<<(SYS_CLKRST_JPEG_CLK_DIV_NUM_S)) -#define SYS_CLKRST_JPEG_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_JPEG_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_JPEG_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_JPEG_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_JPEG_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_JPEG_FORCE_NORST_V 0x1 -#define SYS_CLKRST_JPEG_FORCE_NORST_S 5 -/* SYS_CLKRST_JPEG_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_JPEG_RSTN (BIT(4)) -#define SYS_CLKRST_JPEG_RSTN_M (BIT(4)) -#define SYS_CLKRST_JPEG_RSTN_V 0x1 -#define SYS_CLKRST_JPEG_RSTN_S 4 -/* SYS_CLKRST_JPEG_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_JPEG_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_JPEG_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_JPEG_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_JPEG_APB_CLK_EN_S 3 -/* SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_JPEG_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_JPEG_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_JPEG_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_JPEG_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_JPEG_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_JPEG_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_JPEG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_JPEG_CLK_EN (BIT(0)) -#define SYS_CLKRST_JPEG_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_JPEG_CLK_EN_V 0x1 -#define SYS_CLKRST_JPEG_CLK_EN_S 0 - -#define SYS_CLKRST_GFX_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0xC) -/* SYS_CLKRST_GFX_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_GFX_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_GFX_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_M ((SYS_CLKRST_GFX_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GFX_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_GFX_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_GFX_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_GFX_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_GFX_CLK_DIV_NUM_M ((SYS_CLKRST_GFX_CLK_DIV_NUM_V)<<(SYS_CLKRST_GFX_CLK_DIV_NUM_S)) -#define SYS_CLKRST_GFX_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_GFX_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_GFX_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_GFX_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_GFX_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_GFX_FORCE_NORST_V 0x1 -#define SYS_CLKRST_GFX_FORCE_NORST_S 5 -/* SYS_CLKRST_GFX_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_GFX_RSTN (BIT(4)) -#define SYS_CLKRST_GFX_RSTN_M (BIT(4)) -#define SYS_CLKRST_GFX_RSTN_V 0x1 -#define SYS_CLKRST_GFX_RSTN_S 4 -/* SYS_CLKRST_GFX_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_GFX_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_GFX_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_GFX_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_GFX_APB_CLK_EN_S 3 -/* SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_GFX_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_GFX_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_GFX_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_GFX_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_GFX_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_GFX_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_GFX_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_GFX_CLK_EN (BIT(0)) -#define SYS_CLKRST_GFX_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_GFX_CLK_EN_V 0x1 -#define SYS_CLKRST_GFX_CLK_EN_S 0 - -#define SYS_CLKRST_PSRAM_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x10) -/* SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_PSRAM_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_M ((SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_PSRAM_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_PSRAM_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_PSRAM_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_M ((SYS_CLKRST_PSRAM_CLK_DIV_NUM_V)<<(SYS_CLKRST_PSRAM_CLK_DIV_NUM_S)) -#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_PSRAM_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_PSRAM_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_PSRAM_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_PSRAM_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_PSRAM_FORCE_NORST_V 0x1 -#define SYS_CLKRST_PSRAM_FORCE_NORST_S 5 -/* SYS_CLKRST_PSRAM_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_PSRAM_RSTN (BIT(4)) -#define SYS_CLKRST_PSRAM_RSTN_M (BIT(4)) -#define SYS_CLKRST_PSRAM_RSTN_V 0x1 -#define SYS_CLKRST_PSRAM_RSTN_S 4 -/* SYS_CLKRST_PSRAM_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_PSRAM_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_PSRAM_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_PSRAM_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_PSRAM_APB_CLK_EN_S 3 -/* SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_PSRAM_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_PSRAM_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_PSRAM_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_PSRAM_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_PSRAM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_PSRAM_CLK_EN (BIT(0)) -#define SYS_CLKRST_PSRAM_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_PSRAM_CLK_EN_V 0x1 -#define SYS_CLKRST_PSRAM_CLK_EN_S 0 - -#define SYS_CLKRST_MSPI_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x14) -/* SYS_CLKRST_MSPI_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_MSPI_FORCE_NORST (BIT(2)) -#define SYS_CLKRST_MSPI_FORCE_NORST_M (BIT(2)) -#define SYS_CLKRST_MSPI_FORCE_NORST_V 0x1 -#define SYS_CLKRST_MSPI_FORCE_NORST_S 2 -/* SYS_CLKRST_MSPI_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_MSPI_RSTN (BIT(1)) -#define SYS_CLKRST_MSPI_RSTN_M (BIT(1)) -#define SYS_CLKRST_MSPI_RSTN_V 0x1 -#define SYS_CLKRST_MSPI_RSTN_S 1 -/* SYS_CLKRST_MSPI_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_MSPI_APB_CLK_EN (BIT(0)) -#define SYS_CLKRST_MSPI_APB_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_MSPI_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_MSPI_APB_CLK_EN_S 0 - -#define SYS_CLKRST_DSI_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x18) -/* SYS_CLKRST_DSI_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_DSI_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_DSI_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_M ((SYS_CLKRST_DSI_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_DSI_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_DSI_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_DSI_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_DSI_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_DSI_CLK_DIV_NUM_M ((SYS_CLKRST_DSI_CLK_DIV_NUM_V)<<(SYS_CLKRST_DSI_CLK_DIV_NUM_S)) -#define SYS_CLKRST_DSI_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_DSI_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_DSI_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_DSI_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_DSI_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_DSI_FORCE_NORST_V 0x1 -#define SYS_CLKRST_DSI_FORCE_NORST_S 5 -/* SYS_CLKRST_DSI_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_DSI_RSTN (BIT(4)) -#define SYS_CLKRST_DSI_RSTN_M (BIT(4)) -#define SYS_CLKRST_DSI_RSTN_V 0x1 -#define SYS_CLKRST_DSI_RSTN_S 4 -/* SYS_CLKRST_DSI_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_DSI_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_DSI_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_DSI_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_DSI_APB_CLK_EN_S 3 -/* SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_DSI_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_DSI_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_DSI_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_DSI_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_DSI_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_DSI_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_DSI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_DSI_CLK_EN (BIT(0)) -#define SYS_CLKRST_DSI_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_DSI_CLK_EN_V 0x1 -#define SYS_CLKRST_DSI_CLK_EN_S 0 - -#define SYS_CLKRST_CSI_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x1C) -/* SYS_CLKRST_CSI_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_CSI_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_CSI_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_M ((SYS_CLKRST_CSI_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_CSI_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_CSI_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_CSI_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_CSI_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_CSI_CLK_DIV_NUM_M ((SYS_CLKRST_CSI_CLK_DIV_NUM_V)<<(SYS_CLKRST_CSI_CLK_DIV_NUM_S)) -#define SYS_CLKRST_CSI_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_CSI_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_CSI_BRG_RSTN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_CSI_BRG_RSTN (BIT(6)) -#define SYS_CLKRST_CSI_BRG_RSTN_M (BIT(6)) -#define SYS_CLKRST_CSI_BRG_RSTN_V 0x1 -#define SYS_CLKRST_CSI_BRG_RSTN_S 6 -/* SYS_CLKRST_CSI_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_CSI_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_CSI_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_CSI_FORCE_NORST_V 0x1 -#define SYS_CLKRST_CSI_FORCE_NORST_S 5 -/* SYS_CLKRST_CSI_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_CSI_RSTN (BIT(4)) -#define SYS_CLKRST_CSI_RSTN_M (BIT(4)) -#define SYS_CLKRST_CSI_RSTN_V 0x1 -#define SYS_CLKRST_CSI_RSTN_S 4 -/* SYS_CLKRST_CSI_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_CSI_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_CSI_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_CSI_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_CSI_APB_CLK_EN_S 3 -/* SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_CSI_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_CSI_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_CSI_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_CSI_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_CSI_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_CSI_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_CSI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_CSI_CLK_EN (BIT(0)) -#define SYS_CLKRST_CSI_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_CSI_CLK_EN_V 0x1 -#define SYS_CLKRST_CSI_CLK_EN_S 0 - -#define SYS_CLKRST_USB_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x20) -/* SYS_CLKRST_USB_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_USB_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_USB_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_USB_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_USB_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_USB_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_M ((SYS_CLKRST_USB_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_USB_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_USB_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_USB_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_USB_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_USB_CLK_DIV_NUM_M ((SYS_CLKRST_USB_CLK_DIV_NUM_V)<<(SYS_CLKRST_USB_CLK_DIV_NUM_S)) -#define SYS_CLKRST_USB_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_USB_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_USB_PHY_FORCE_NORST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Usb phy software force no reset.*/ -#define SYS_CLKRST_USB_PHY_FORCE_NORST (BIT(7)) -#define SYS_CLKRST_USB_PHY_FORCE_NORST_M (BIT(7)) -#define SYS_CLKRST_USB_PHY_FORCE_NORST_V 0x1 -#define SYS_CLKRST_USB_PHY_FORCE_NORST_S 7 -/* SYS_CLKRST_USB_FORCE_NORST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Usb software force no reset.*/ -#define SYS_CLKRST_USB_FORCE_NORST (BIT(6)) -#define SYS_CLKRST_USB_FORCE_NORST_M (BIT(6)) -#define SYS_CLKRST_USB_FORCE_NORST_V 0x1 -#define SYS_CLKRST_USB_FORCE_NORST_S 6 -/* SYS_CLKRST_USB_PHY_RSTN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: Usb phy software reset : low active.*/ -#define SYS_CLKRST_USB_PHY_RSTN (BIT(5)) -#define SYS_CLKRST_USB_PHY_RSTN_M (BIT(5)) -#define SYS_CLKRST_USB_PHY_RSTN_V 0x1 -#define SYS_CLKRST_USB_PHY_RSTN_S 5 -/* SYS_CLKRST_USB_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: Usb software reset : low active.*/ -#define SYS_CLKRST_USB_RSTN (BIT(4)) -#define SYS_CLKRST_USB_RSTN_M (BIT(4)) -#define SYS_CLKRST_USB_RSTN_V 0x1 -#define SYS_CLKRST_USB_RSTN_S 4 -/* SYS_CLKRST_USB_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_USB_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_USB_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_USB_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_USB_APB_CLK_EN_S 3 -/* SYS_CLKRST_USB_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_USB_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_USB_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_USB_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_USB_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_USB_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_USB_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_USB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_USB_CLK_EN (BIT(0)) -#define SYS_CLKRST_USB_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_USB_CLK_EN_V 0x1 -#define SYS_CLKRST_USB_CLK_EN_S 0 - -#define SYS_CLKRST_GMAC_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x24) -/* SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'b0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_GMAC_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_GMAC_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_M ((SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_GMAC_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_GMAC_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_GMAC_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_GMAC_CLK_DIV_NUM_M ((SYS_CLKRST_GMAC_CLK_DIV_NUM_V)<<(SYS_CLKRST_GMAC_CLK_DIV_NUM_S)) -#define SYS_CLKRST_GMAC_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_GMAC_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_GMAC_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_GMAC_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_GMAC_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_GMAC_FORCE_NORST_V 0x1 -#define SYS_CLKRST_GMAC_FORCE_NORST_S 5 -/* SYS_CLKRST_GMAC_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_GMAC_RSTN (BIT(4)) -#define SYS_CLKRST_GMAC_RSTN_M (BIT(4)) -#define SYS_CLKRST_GMAC_RSTN_V 0x1 -#define SYS_CLKRST_GMAC_RSTN_S 4 -/* SYS_CLKRST_GMAC_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_GMAC_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_GMAC_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_GMAC_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_GMAC_APB_CLK_EN_S 3 -/* SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_GMAC_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_GMAC_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_GMAC_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_GMAC_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_GMAC_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_GMAC_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_GMAC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_GMAC_CLK_EN (BIT(0)) -#define SYS_CLKRST_GMAC_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_GMAC_CLK_EN_V 0x1 -#define SYS_CLKRST_GMAC_CLK_EN_S 0 - -#define SYS_CLKRST_SDMMC_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x28) -/* SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_SDMMC_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_M ((SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_SDMMC_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_SDMMC_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_SDMMC_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_M ((SYS_CLKRST_SDMMC_CLK_DIV_NUM_V)<<(SYS_CLKRST_SDMMC_CLK_DIV_NUM_S)) -#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_SDMMC_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_SDMMC_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_SDMMC_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_SDMMC_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_SDMMC_FORCE_NORST_V 0x1 -#define SYS_CLKRST_SDMMC_FORCE_NORST_S 5 -/* SYS_CLKRST_SDMMC_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_SDMMC_RSTN (BIT(4)) -#define SYS_CLKRST_SDMMC_RSTN_M (BIT(4)) -#define SYS_CLKRST_SDMMC_RSTN_V 0x1 -#define SYS_CLKRST_SDMMC_RSTN_S 4 -/* SYS_CLKRST_SDMMC_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_SDMMC_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_SDMMC_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_SDMMC_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_SDMMC_APB_CLK_EN_S 3 -/* SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_SDMMC_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_SDMMC_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_SDMMC_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_SDMMC_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_SDMMC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_SDMMC_CLK_EN (BIT(0)) -#define SYS_CLKRST_SDMMC_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_SDMMC_CLK_EN_V 0x1 -#define SYS_CLKRST_SDMMC_CLK_EN_S 0 - -#define SYS_CLKRST_DDRC_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x2C) -/* SYS_CLKRST_DDRC_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_DDRC_FORCE_NORST (BIT(2)) -#define SYS_CLKRST_DDRC_FORCE_NORST_M (BIT(2)) -#define SYS_CLKRST_DDRC_FORCE_NORST_V 0x1 -#define SYS_CLKRST_DDRC_FORCE_NORST_S 2 -/* SYS_CLKRST_DDRC_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_DDRC_RSTN (BIT(1)) -#define SYS_CLKRST_DDRC_RSTN_M (BIT(1)) -#define SYS_CLKRST_DDRC_RSTN_V 0x1 -#define SYS_CLKRST_DDRC_RSTN_S 1 -/* SYS_CLKRST_DDRC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_DDRC_CLK_EN (BIT(0)) -#define SYS_CLKRST_DDRC_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_DDRC_CLK_EN_V 0x1 -#define SYS_CLKRST_DDRC_CLK_EN_S 0 - -#define SYS_CLKRST_GDMA_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x30) -/* SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: current clock divider number.*/ -#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_GDMA_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_GDMA_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: clock phase offset compare to hp clock sync signal.*/ -#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_M ((SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_GDMA_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_GDMA_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: clock divider number.*/ -#define SYS_CLKRST_GDMA_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_GDMA_CLK_DIV_NUM_M ((SYS_CLKRST_GDMA_CLK_DIV_NUM_V)<<(SYS_CLKRST_GDMA_CLK_DIV_NUM_S)) -#define SYS_CLKRST_GDMA_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_GDMA_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_GDMA_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: software force no reset.*/ -#define SYS_CLKRST_GDMA_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_GDMA_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_GDMA_FORCE_NORST_V 0x1 -#define SYS_CLKRST_GDMA_FORCE_NORST_S 5 -/* SYS_CLKRST_GDMA_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: software reset : low active.*/ -#define SYS_CLKRST_GDMA_RSTN (BIT(4)) -#define SYS_CLKRST_GDMA_RSTN_M (BIT(4)) -#define SYS_CLKRST_GDMA_RSTN_V 0x1 -#define SYS_CLKRST_GDMA_RSTN_S 4 -/* SYS_CLKRST_GDMA_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: apb clock enable.*/ -#define SYS_CLKRST_GDMA_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_GDMA_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_GDMA_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_GDMA_APB_CLK_EN_S 3 -/* SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: clock force sync enable : clock output only available when clock is synced.*/ -#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_GDMA_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_GDMA_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/ -#define SYS_CLKRST_GDMA_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_GDMA_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_GDMA_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_GDMA_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_GDMA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: clock output enable.*/ -#define SYS_CLKRST_GDMA_CLK_EN (BIT(0)) -#define SYS_CLKRST_GDMA_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_GDMA_CLK_EN_V 0x1 -#define SYS_CLKRST_GDMA_CLK_EN_S 0 - -#define SYS_CLKRST_USBOTG_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x34) -/* SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_USBOTG_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_M ((SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_USBOTG_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_USBOTG_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_M ((SYS_CLKRST_USBOTG_CLK_DIV_NUM_V)<<(SYS_CLKRST_USBOTG_CLK_DIV_NUM_S)) -#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_USBOTG_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_USBOTG_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_USBOTG_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_USBOTG_FORCE_NORST_V 0x1 -#define SYS_CLKRST_USBOTG_FORCE_NORST_S 5 -/* SYS_CLKRST_USBOTG_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_RSTN (BIT(4)) -#define SYS_CLKRST_USBOTG_RSTN_M (BIT(4)) -#define SYS_CLKRST_USBOTG_RSTN_V 0x1 -#define SYS_CLKRST_USBOTG_RSTN_S 4 -/* SYS_CLKRST_USBOTG_APB_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_APB_CLK_EN (BIT(3)) -#define SYS_CLKRST_USBOTG_APB_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_USBOTG_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_USBOTG_APB_CLK_EN_S 3 -/* SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_USBOTG_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_USBOTG_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_USBOTG_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_USBOTG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_USBOTG_CLK_EN (BIT(0)) -#define SYS_CLKRST_USBOTG_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_USBOTG_CLK_EN_V 0x1 -#define SYS_CLKRST_USBOTG_CLK_EN_S 0 - -#define SYS_CLKRST_SDIO_SLAVE_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x38) -/* SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM 0x000000FF -#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_M ((SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_S)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_V 0xFF -#define SYS_CLKRST_SDIO_SLAVE_CLK_CUR_DIV_NUM_S 24 -/* SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET 0x000000FF -#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_M ((SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_S)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_V 0xFF -#define SYS_CLKRST_SDIO_SLAVE_CLK_PHASE_OFFSET_S 16 -/* SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM 0x000000FF -#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_M ((SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_V)<<(SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_S)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_V 0xFF -#define SYS_CLKRST_SDIO_SLAVE_CLK_DIV_NUM_S 8 -/* SYS_CLKRST_SDIO_SLAVE_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST (BIT(5)) -#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_M (BIT(5)) -#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_V 0x1 -#define SYS_CLKRST_SDIO_SLAVE_FORCE_NORST_S 5 -/* SYS_CLKRST_SDIO_SLAVE_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_RSTN (BIT(4)) -#define SYS_CLKRST_SDIO_SLAVE_RSTN_M (BIT(4)) -#define SYS_CLKRST_SDIO_SLAVE_RSTN_V 0x1 -#define SYS_CLKRST_SDIO_SLAVE_RSTN_S 4 -/* SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN (BIT(2)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_M (BIT(2)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_V 0x1 -#define SYS_CLKRST_SDIO_SLAVE_CLK_FORCE_SYNC_EN_S 2 -/* SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN (BIT(1)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_M (BIT(1)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_V 0x1 -#define SYS_CLKRST_SDIO_SLAVE_CLK_SYNC_EN_S 1 -/* SYS_CLKRST_SDIO_SLAVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_CLK_EN (BIT(0)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_V 0x1 -#define SYS_CLKRST_SDIO_SLAVE_CLK_EN_S 0 - -#define SYS_CLKRST_ISP_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x40) -/* SYS_CLKRST_ISP_CLK_DIV_NUM : R/W ;bitpos:[6:3] ;default: 4'd1 ; */ -/*description: .*/ -#define SYS_CLKRST_ISP_CLK_DIV_NUM 0x0000000F -#define SYS_CLKRST_ISP_CLK_DIV_NUM_M ((SYS_CLKRST_ISP_CLK_DIV_NUM_V)<<(SYS_CLKRST_ISP_CLK_DIV_NUM_S)) -#define SYS_CLKRST_ISP_CLK_DIV_NUM_V 0xF -#define SYS_CLKRST_ISP_CLK_DIV_NUM_S 3 -/* SYS_CLKRST_ISP_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_ISP_FORCE_NORST (BIT(2)) -#define SYS_CLKRST_ISP_FORCE_NORST_M (BIT(2)) -#define SYS_CLKRST_ISP_FORCE_NORST_V 0x1 -#define SYS_CLKRST_ISP_FORCE_NORST_S 2 -/* SYS_CLKRST_ISP_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_ISP_RSTN (BIT(1)) -#define SYS_CLKRST_ISP_RSTN_M (BIT(1)) -#define SYS_CLKRST_ISP_RSTN_V 0x1 -#define SYS_CLKRST_ISP_RSTN_S 1 -/* SYS_CLKRST_ISP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_ISP_CLK_EN (BIT(0)) -#define SYS_CLKRST_ISP_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_ISP_CLK_EN_V 0x1 -#define SYS_CLKRST_ISP_CLK_EN_S 0 - -#define SYS_CLKRST_DMA2D_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x44) -/* SYS_CLKRST_DMA2D_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_DMA2D_FORCE_NORST (BIT(2)) -#define SYS_CLKRST_DMA2D_FORCE_NORST_M (BIT(2)) -#define SYS_CLKRST_DMA2D_FORCE_NORST_V 0x1 -#define SYS_CLKRST_DMA2D_FORCE_NORST_S 2 -/* SYS_CLKRST_DMA2D_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_DMA2D_RSTN (BIT(1)) -#define SYS_CLKRST_DMA2D_RSTN_M (BIT(1)) -#define SYS_CLKRST_DMA2D_RSTN_V 0x1 -#define SYS_CLKRST_DMA2D_RSTN_S 1 -/* SYS_CLKRST_DMA2D_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_DMA2D_CLK_EN (BIT(0)) -#define SYS_CLKRST_DMA2D_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_DMA2D_CLK_EN_V 0x1 -#define SYS_CLKRST_DMA2D_CLK_EN_S 0 - -#define SYS_CLKRST_PPA_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x48) -/* SYS_CLKRST_PPA_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PPA_FORCE_NORST (BIT(2)) -#define SYS_CLKRST_PPA_FORCE_NORST_M (BIT(2)) -#define SYS_CLKRST_PPA_FORCE_NORST_V 0x1 -#define SYS_CLKRST_PPA_FORCE_NORST_S 2 -/* SYS_CLKRST_PPA_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_PPA_RSTN (BIT(1)) -#define SYS_CLKRST_PPA_RSTN_M (BIT(1)) -#define SYS_CLKRST_PPA_RSTN_V 0x1 -#define SYS_CLKRST_PPA_RSTN_S 1 -/* SYS_CLKRST_PPA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_PPA_CLK_EN (BIT(0)) -#define SYS_CLKRST_PPA_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_PPA_CLK_EN_V 0x1 -#define SYS_CLKRST_PPA_CLK_EN_S 0 - -#define SYS_CLKRST_GDMA_DBG_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x50) -/* SYS_CLKRST_DEBUG_CH_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_DEBUG_CH_NUM 0x00000003 -#define SYS_CLKRST_DEBUG_CH_NUM_M ((SYS_CLKRST_DEBUG_CH_NUM_V)<<(SYS_CLKRST_DEBUG_CH_NUM_S)) -#define SYS_CLKRST_DEBUG_CH_NUM_V 0x3 -#define SYS_CLKRST_DEBUG_CH_NUM_S 0 - -#define SYS_CLKRST_GMAC_PTP_RD0_REG (DR_REG_SYS_CLKRST_BASE + 0x54) -/* SYS_CLKRST_PTP_TIMESTAMP_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_PTP_TIMESTAMP_LO 0xFFFFFFFF -#define SYS_CLKRST_PTP_TIMESTAMP_LO_M ((SYS_CLKRST_PTP_TIMESTAMP_LO_V)<<(SYS_CLKRST_PTP_TIMESTAMP_LO_S)) -#define SYS_CLKRST_PTP_TIMESTAMP_LO_V 0xFFFFFFFF -#define SYS_CLKRST_PTP_TIMESTAMP_LO_S 0 - -#define SYS_CLKRST_GMAC_PTP_RD1_REG (DR_REG_SYS_CLKRST_BASE + 0x58) -/* SYS_CLKRST_PTP_TIMESTAMP_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_PTP_TIMESTAMP_HI 0xFFFFFFFF -#define SYS_CLKRST_PTP_TIMESTAMP_HI_M ((SYS_CLKRST_PTP_TIMESTAMP_HI_V)<<(SYS_CLKRST_PTP_TIMESTAMP_HI_S)) -#define SYS_CLKRST_PTP_TIMESTAMP_HI_V 0xFFFFFFFF -#define SYS_CLKRST_PTP_TIMESTAMP_HI_S 0 - -#define SYS_CLKRST_GMAC_PTP_PPS_REG (DR_REG_SYS_CLKRST_BASE + 0x5C) -/* SYS_CLKRST_PTP_PPS : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_PTP_PPS (BIT(0)) -#define SYS_CLKRST_PTP_PPS_M (BIT(0)) -#define SYS_CLKRST_PTP_PPS_V 0x1 -#define SYS_CLKRST_PTP_PPS_S 0 - -#define SYS_CLKRST_GMAC_CLK_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x60) -/* SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON (BIT(13)) -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_M (BIT(13)) -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_V 0x1 -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_FORCE_ON_S 13 -/* SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON (BIT(12)) -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_M (BIT(12)) -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_V 0x1 -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_FORCE_ON_S 12 -/* SYS_CLKRST_GMAC_FUNC_RX_CLK_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN (BIT(11)) -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_M (BIT(11)) -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_V 0x1 -#define SYS_CLKRST_GMAC_FUNC_RX_CLK_EN_S 11 -/* SYS_CLKRST_GMAC_FUNC_TX_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN (BIT(10)) -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_M (BIT(10)) -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_V 0x1 -#define SYS_CLKRST_GMAC_FUNC_TX_CLK_EN_S 10 -/* SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON (BIT(9)) -#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_M (BIT(9)) -#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_V 0x1 -#define SYS_CLKRST_GMAC_MEM_CLK_FORCE_ON_S 9 -/* SYS_CLKRST_REVMII_PMA_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_REVMII_PMA_CLK_EN (BIT(8)) -#define SYS_CLKRST_REVMII_PMA_CLK_EN_M (BIT(8)) -#define SYS_CLKRST_REVMII_PMA_CLK_EN_V 0x1 -#define SYS_CLKRST_REVMII_PMA_CLK_EN_S 8 -/* SYS_CLKRST_RMII_CLK_PORT_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_RMII_CLK_PORT_SEL (BIT(7)) -#define SYS_CLKRST_RMII_CLK_PORT_SEL_M (BIT(7)) -#define SYS_CLKRST_RMII_CLK_PORT_SEL_V 0x1 -#define SYS_CLKRST_RMII_CLK_PORT_SEL_S 7 -/* SYS_CLKRST_SBD_FLOWCTRL : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_SBD_FLOWCTRL (BIT(6)) -#define SYS_CLKRST_SBD_FLOWCTRL_M (BIT(6)) -#define SYS_CLKRST_SBD_FLOWCTRL_V 0x1 -#define SYS_CLKRST_SBD_FLOWCTRL_S 6 -/* SYS_CLKRST_PHY_INTF_SEL : R/W ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_INTF_SEL 0x00000007 -#define SYS_CLKRST_PHY_INTF_SEL_M ((SYS_CLKRST_PHY_INTF_SEL_V)<<(SYS_CLKRST_PHY_INTF_SEL_S)) -#define SYS_CLKRST_PHY_INTF_SEL_V 0x7 -#define SYS_CLKRST_PHY_INTF_SEL_S 3 -/* SYS_CLKRST_PTP_REF_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PTP_REF_CLK_SEL (BIT(2)) -#define SYS_CLKRST_PTP_REF_CLK_SEL_M (BIT(2)) -#define SYS_CLKRST_PTP_REF_CLK_SEL_V 0x1 -#define SYS_CLKRST_PTP_REF_CLK_SEL_S 2 -/* SYS_CLKRST_REVERSE_GMAC_TX : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_REVERSE_GMAC_TX (BIT(1)) -#define SYS_CLKRST_REVERSE_GMAC_TX_M (BIT(1)) -#define SYS_CLKRST_REVERSE_GMAC_TX_V 0x1 -#define SYS_CLKRST_REVERSE_GMAC_TX_S 1 -/* SYS_CLKRST_REVERSE_GMAC_RX : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_REVERSE_GMAC_RX (BIT(0)) -#define SYS_CLKRST_REVERSE_GMAC_RX_M (BIT(0)) -#define SYS_CLKRST_REVERSE_GMAC_RX_V 0x1 -#define SYS_CLKRST_REVERSE_GMAC_RX_S 0 - -#define SYS_CLKRST_OTG_PHY_CLK_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x64) -/* SYS_CLKRST_OTG_EXT_PHY_SEL : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_OTG_EXT_PHY_SEL (BIT(10)) -#define SYS_CLKRST_OTG_EXT_PHY_SEL_M (BIT(10)) -#define SYS_CLKRST_OTG_EXT_PHY_SEL_V 0x1 -#define SYS_CLKRST_OTG_EXT_PHY_SEL_S 10 -/* SYS_CLKRST_PHY_REF_CLK_SEL : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_REF_CLK_SEL (BIT(9)) -#define SYS_CLKRST_PHY_REF_CLK_SEL_M (BIT(9)) -#define SYS_CLKRST_PHY_REF_CLK_SEL_V 0x1 -#define SYS_CLKRST_PHY_REF_CLK_SEL_S 9 -/* SYS_CLKRST_PHY_RESET_FORCE_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_RESET_FORCE_EN (BIT(8)) -#define SYS_CLKRST_PHY_RESET_FORCE_EN_M (BIT(8)) -#define SYS_CLKRST_PHY_RESET_FORCE_EN_V 0x1 -#define SYS_CLKRST_PHY_RESET_FORCE_EN_S 8 -/* SYS_CLKRST_PHY_RSTN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_RSTN (BIT(7)) -#define SYS_CLKRST_PHY_RSTN_M (BIT(7)) -#define SYS_CLKRST_PHY_RSTN_V 0x1 -#define SYS_CLKRST_PHY_RSTN_S 7 -/* SYS_CLKRST_PHY_PLL_FORCE_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_PLL_FORCE_EN (BIT(6)) -#define SYS_CLKRST_PHY_PLL_FORCE_EN_M (BIT(6)) -#define SYS_CLKRST_PHY_PLL_FORCE_EN_V 0x1 -#define SYS_CLKRST_PHY_PLL_FORCE_EN_S 6 -/* SYS_CLKRST_PHY_PLL_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_PLL_EN (BIT(5)) -#define SYS_CLKRST_PHY_PLL_EN_M (BIT(5)) -#define SYS_CLKRST_PHY_PLL_EN_V 0x1 -#define SYS_CLKRST_PHY_PLL_EN_S 5 -/* SYS_CLKRST_PHY_SUSPEND_FORCE_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN (BIT(4)) -#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_M (BIT(4)) -#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_V 0x1 -#define SYS_CLKRST_PHY_SUSPEND_FORCE_EN_S 4 -/* SYS_CLKRST_PHY_SUSPENDM : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_PHY_SUSPENDM (BIT(3)) -#define SYS_CLKRST_PHY_SUSPENDM_M (BIT(3)) -#define SYS_CLKRST_PHY_SUSPENDM_V 0x1 -#define SYS_CLKRST_PHY_SUSPENDM_S 3 -/* SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN (BIT(2)) -#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_M (BIT(2)) -#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_V 0x1 -#define SYS_CLKRST_OTG_PHY_TXBITSTUFF_EN_S 2 -/* SYS_CLKRST_OTG_SUSPENDM : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_OTG_SUSPENDM (BIT(1)) -#define SYS_CLKRST_OTG_SUSPENDM_M (BIT(1)) -#define SYS_CLKRST_OTG_SUSPENDM_V 0x1 -#define SYS_CLKRST_OTG_SUSPENDM_S 1 -/* SYS_CLKRST_OTG_PHY_REFCLK_MODE : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_OTG_PHY_REFCLK_MODE (BIT(0)) -#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_M (BIT(0)) -#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_V 0x1 -#define SYS_CLKRST_OTG_PHY_REFCLK_MODE_S 0 - -#define SYS_CLKRST_SYS_PERI_APB_POSTW_CNTL_REG (DR_REG_SYS_CLKRST_BASE + 0x68) -/* SYS_CLKRST_DSI_HOST_APB_POSTW_EN : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN (BIT(6)) -#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_M (BIT(6)) -#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_V 0x1 -#define SYS_CLKRST_DSI_HOST_APB_POSTW_EN_S 6 -/* SYS_CLKRST_CSI_HOST_APB_POSTW_EN : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN (BIT(5)) -#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_M (BIT(5)) -#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_V 0x1 -#define SYS_CLKRST_CSI_HOST_APB_POSTW_EN_S 5 -/* SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN (BIT(4)) -#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_M (BIT(4)) -#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_V 0x1 -#define SYS_CLKRST_SDIO_SLAVE_APB_POSTW_EN_S 4 -/* SYS_CLKRST_USB11_APB_POSTW_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_USB11_APB_POSTW_EN (BIT(3)) -#define SYS_CLKRST_USB11_APB_POSTW_EN_M (BIT(3)) -#define SYS_CLKRST_USB11_APB_POSTW_EN_V 0x1 -#define SYS_CLKRST_USB11_APB_POSTW_EN_S 3 -/* SYS_CLKRST_DMA2D_APB_POSTW_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_DMA2D_APB_POSTW_EN (BIT(2)) -#define SYS_CLKRST_DMA2D_APB_POSTW_EN_M (BIT(2)) -#define SYS_CLKRST_DMA2D_APB_POSTW_EN_V 0x1 -#define SYS_CLKRST_DMA2D_APB_POSTW_EN_S 2 -/* SYS_CLKRST_JPEG_APB_POSTW_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_JPEG_APB_POSTW_EN (BIT(1)) -#define SYS_CLKRST_JPEG_APB_POSTW_EN_M (BIT(1)) -#define SYS_CLKRST_JPEG_APB_POSTW_EN_V 0x1 -#define SYS_CLKRST_JPEG_APB_POSTW_EN_S 1 -/* SYS_CLKRST_GMAC_APB_POSTW_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_GMAC_APB_POSTW_EN (BIT(0)) -#define SYS_CLKRST_GMAC_APB_POSTW_EN_M (BIT(0)) -#define SYS_CLKRST_GMAC_APB_POSTW_EN_V 0x1 -#define SYS_CLKRST_GMAC_APB_POSTW_EN_S 0 - -#define SYS_CLKRST_SYS_LSLP_MEM_PD_REG (DR_REG_SYS_CLKRST_BASE + 0x6C) -/* SYS_CLKRST_JPEG_SDSLP_MEM_PD : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_JPEG_SDSLP_MEM_PD (BIT(4)) -#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_M (BIT(4)) -#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_V 0x1 -#define SYS_CLKRST_JPEG_SDSLP_MEM_PD_S 4 -/* SYS_CLKRST_JPEG_DSLP_MEM_PD : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_JPEG_DSLP_MEM_PD (BIT(3)) -#define SYS_CLKRST_JPEG_DSLP_MEM_PD_M (BIT(3)) -#define SYS_CLKRST_JPEG_DSLP_MEM_PD_V 0x1 -#define SYS_CLKRST_JPEG_DSLP_MEM_PD_S 3 -/* SYS_CLKRST_JPEG_LSLP_MEM_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_JPEG_LSLP_MEM_PD (BIT(2)) -#define SYS_CLKRST_JPEG_LSLP_MEM_PD_M (BIT(2)) -#define SYS_CLKRST_JPEG_LSLP_MEM_PD_V 0x1 -#define SYS_CLKRST_JPEG_LSLP_MEM_PD_S 2 -/* SYS_CLKRST_PPA_LSLP_MEM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_PPA_LSLP_MEM_PD (BIT(1)) -#define SYS_CLKRST_PPA_LSLP_MEM_PD_M (BIT(1)) -#define SYS_CLKRST_PPA_LSLP_MEM_PD_V 0x1 -#define SYS_CLKRST_PPA_LSLP_MEM_PD_S 1 -/* SYS_CLKRST_DMA2D_LSLP_MEM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_DMA2D_LSLP_MEM_PD (BIT(0)) -#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_M (BIT(0)) -#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_V 0x1 -#define SYS_CLKRST_DMA2D_LSLP_MEM_PD_S 0 - -#define SYS_CLKRST_ECO_CELL_EN_AND_DATA_REG (DR_REG_SYS_CLKRST_BASE + 0x70) -/* SYS_CLKRST_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_CLK_EN (BIT(3)) -#define SYS_CLKRST_CLK_EN_M (BIT(3)) -#define SYS_CLKRST_CLK_EN_V 0x1 -#define SYS_CLKRST_CLK_EN_S 3 -/* SYS_CLKRST_BIT_IN : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_BIT_IN (BIT(2)) -#define SYS_CLKRST_BIT_IN_M (BIT(2)) -#define SYS_CLKRST_BIT_IN_V 0x1 -#define SYS_CLKRST_BIT_IN_S 2 -/* SYS_CLKRST_BIT_OUT : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_BIT_OUT (BIT(1)) -#define SYS_CLKRST_BIT_OUT_M (BIT(1)) -#define SYS_CLKRST_BIT_OUT_V 0x1 -#define SYS_CLKRST_BIT_OUT_S 1 -/* SYS_CLKRST_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: .*/ -#define SYS_CLKRST_EN (BIT(0)) -#define SYS_CLKRST_EN_M (BIT(0)) -#define SYS_CLKRST_EN_V 0x1 -#define SYS_CLKRST_EN_S 0 - -#define SYS_CLKRST_USB_MEM_AUX_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x74) -/* SYS_CLKRST_OTG_PHY_BISTEN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_OTG_PHY_BISTEN (BIT(15)) -#define SYS_CLKRST_OTG_PHY_BISTEN_M (BIT(15)) -#define SYS_CLKRST_OTG_PHY_BISTEN_V 0x1 -#define SYS_CLKRST_OTG_PHY_BISTEN_S 15 -/* SYS_CLKRST_OTG_PHY_TEST_DONE : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_OTG_PHY_TEST_DONE (BIT(14)) -#define SYS_CLKRST_OTG_PHY_TEST_DONE_M (BIT(14)) -#define SYS_CLKRST_OTG_PHY_TEST_DONE_V 0x1 -#define SYS_CLKRST_OTG_PHY_TEST_DONE_S 14 -/* SYS_CLKRST_USB_MEM_AUX_CTRL : R/W ;bitpos:[13:0] ;default: 14'h1320 ; */ -/*description: .*/ -#define SYS_CLKRST_USB_MEM_AUX_CTRL 0x00003FFF -#define SYS_CLKRST_USB_MEM_AUX_CTRL_M ((SYS_CLKRST_USB_MEM_AUX_CTRL_V)<<(SYS_CLKRST_USB_MEM_AUX_CTRL_S)) -#define SYS_CLKRST_USB_MEM_AUX_CTRL_V 0x3FFF -#define SYS_CLKRST_USB_MEM_AUX_CTRL_S 0 - -#define SYS_CLKRST_DUAL_MSPI_CTRL_REG (DR_REG_SYS_CLKRST_BASE + 0x78) -/* SYS_CLKRST_DUAL_MSPI_FORCE_NORST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST (BIT(2)) -#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_M (BIT(2)) -#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_V 0x1 -#define SYS_CLKRST_DUAL_MSPI_FORCE_NORST_S 2 -/* SYS_CLKRST_DUAL_MSPI_RSTN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_DUAL_MSPI_RSTN (BIT(1)) -#define SYS_CLKRST_DUAL_MSPI_RSTN_M (BIT(1)) -#define SYS_CLKRST_DUAL_MSPI_RSTN_V 0x1 -#define SYS_CLKRST_DUAL_MSPI_RSTN_S 1 -/* SYS_CLKRST_DUAL_MSPI_APB_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN (BIT(0)) -#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_M (BIT(0)) -#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_V 0x1 -#define SYS_CLKRST_DUAL_MSPI_APB_CLK_EN_S 0 - -#define SYS_CLKRST_HP_PERI_RDN_ECO_CS_REG (DR_REG_SYS_CLKRST_BASE + 0x7C) -/* SYS_CLKRST_HP_PERI_RDN_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT (BIT(1)) -#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_M (BIT(1)) -#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_V 0x1 -#define SYS_CLKRST_HP_PERI_RDN_ECO_RESULT_S 1 -/* SYS_CLKRST_HP_PERI_RDN_ECO_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_HP_PERI_RDN_ECO_EN (BIT(0)) -#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_M (BIT(0)) -#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_V 0x1 -#define SYS_CLKRST_HP_PERI_RDN_ECO_EN_S 0 - -#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_REG (DR_REG_SYS_CLKRST_BASE + 0x80) -/* SYS_CLKRST_HP_PERI_RDN_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW 0xFFFFFFFF -#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_M ((SYS_CLKRST_HP_PERI_RDN_ECO_LOW_V)<<(SYS_CLKRST_HP_PERI_RDN_ECO_LOW_S)) -#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_V 0xFFFFFFFF -#define SYS_CLKRST_HP_PERI_RDN_ECO_LOW_S 0 - -#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_REG (DR_REG_SYS_CLKRST_BASE + 0x84) -/* SYS_CLKRST_HP_PERI_RDN_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: .*/ -#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH 0xFFFFFFFF -#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_M ((SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_V)<<(SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_S)) -#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_V 0xFFFFFFFF -#define SYS_CLKRST_HP_PERI_RDN_ECO_HIGH_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SYS_CLKRST_REG_H_ */ diff --git a/components/soc/esp32p4/include/soc/tee_reg.h b/components/soc/esp32p4/include/soc/tee_reg.h deleted file mode 100644 index 553ad23442..0000000000 --- a/components/soc/esp32p4/include/soc/tee_reg.h +++ /dev/null @@ -1,455 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TEE_M0_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) -/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; - * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M0_MODE 0x00000003U -#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) -#define TEE_M0_MODE_V 0x00000003U -#define TEE_M0_MODE_S 0 - -/** TEE_M1_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) -/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3; - * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M1_MODE 0x00000003U -#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) -#define TEE_M1_MODE_V 0x00000003U -#define TEE_M1_MODE_S 0 - -/** TEE_M2_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) -/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; - * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M2_MODE 0x00000003U -#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) -#define TEE_M2_MODE_V 0x00000003U -#define TEE_M2_MODE_S 0 - -/** TEE_M3_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) -/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3; - * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M3_MODE 0x00000003U -#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) -#define TEE_M3_MODE_V 0x00000003U -#define TEE_M3_MODE_S 0 - -/** TEE_M4_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) -/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3; - * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M4_MODE 0x00000003U -#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) -#define TEE_M4_MODE_V 0x00000003U -#define TEE_M4_MODE_S 0 - -/** TEE_M5_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) -/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3; - * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M5_MODE 0x00000003U -#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) -#define TEE_M5_MODE_V 0x00000003U -#define TEE_M5_MODE_S 0 - -/** TEE_M6_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) -/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3; - * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M6_MODE 0x00000003U -#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) -#define TEE_M6_MODE_V 0x00000003U -#define TEE_M6_MODE_S 0 - -/** TEE_M7_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) -/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3; - * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M7_MODE 0x00000003U -#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) -#define TEE_M7_MODE_V 0x00000003U -#define TEE_M7_MODE_S 0 - -/** TEE_M8_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) -/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3; - * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M8_MODE 0x00000003U -#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) -#define TEE_M8_MODE_V 0x00000003U -#define TEE_M8_MODE_S 0 - -/** TEE_M9_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) -/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3; - * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M9_MODE 0x00000003U -#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) -#define TEE_M9_MODE_V 0x00000003U -#define TEE_M9_MODE_S 0 - -/** TEE_M10_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) -/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3; - * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M10_MODE 0x00000003U -#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) -#define TEE_M10_MODE_V 0x00000003U -#define TEE_M10_MODE_S 0 - -/** TEE_M11_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) -/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3; - * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M11_MODE 0x00000003U -#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) -#define TEE_M11_MODE_V 0x00000003U -#define TEE_M11_MODE_S 0 - -/** TEE_M12_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) -/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3; - * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M12_MODE 0x00000003U -#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) -#define TEE_M12_MODE_V 0x00000003U -#define TEE_M12_MODE_S 0 - -/** TEE_M13_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) -/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3; - * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M13_MODE 0x00000003U -#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) -#define TEE_M13_MODE_V 0x00000003U -#define TEE_M13_MODE_S 0 - -/** TEE_M14_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) -/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3; - * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M14_MODE 0x00000003U -#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) -#define TEE_M14_MODE_V 0x00000003U -#define TEE_M14_MODE_S 0 - -/** TEE_M15_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) -/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3; - * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M15_MODE 0x00000003U -#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) -#define TEE_M15_MODE_V 0x00000003U -#define TEE_M15_MODE_S 0 - -/** TEE_M16_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) -/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3; - * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M16_MODE 0x00000003U -#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) -#define TEE_M16_MODE_V 0x00000003U -#define TEE_M16_MODE_S 0 - -/** TEE_M17_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) -/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3; - * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M17_MODE 0x00000003U -#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) -#define TEE_M17_MODE_V 0x00000003U -#define TEE_M17_MODE_S 0 - -/** TEE_M18_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) -/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3; - * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M18_MODE 0x00000003U -#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) -#define TEE_M18_MODE_V 0x00000003U -#define TEE_M18_MODE_S 0 - -/** TEE_M19_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) -/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3; - * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M19_MODE 0x00000003U -#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) -#define TEE_M19_MODE_V 0x00000003U -#define TEE_M19_MODE_S 0 - -/** TEE_M20_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) -/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3; - * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M20_MODE 0x00000003U -#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) -#define TEE_M20_MODE_V 0x00000003U -#define TEE_M20_MODE_S 0 - -/** TEE_M21_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) -/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3; - * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M21_MODE 0x00000003U -#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) -#define TEE_M21_MODE_V 0x00000003U -#define TEE_M21_MODE_S 0 - -/** TEE_M22_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) -/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3; - * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M22_MODE 0x00000003U -#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) -#define TEE_M22_MODE_V 0x00000003U -#define TEE_M22_MODE_S 0 - -/** TEE_M23_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) -/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3; - * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M23_MODE 0x00000003U -#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) -#define TEE_M23_MODE_V 0x00000003U -#define TEE_M23_MODE_S 0 - -/** TEE_M24_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) -/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3; - * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M24_MODE 0x00000003U -#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) -#define TEE_M24_MODE_V 0x00000003U -#define TEE_M24_MODE_S 0 - -/** TEE_M25_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) -/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3; - * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M25_MODE 0x00000003U -#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) -#define TEE_M25_MODE_V 0x00000003U -#define TEE_M25_MODE_S 0 - -/** TEE_M26_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) -/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3; - * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M26_MODE 0x00000003U -#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) -#define TEE_M26_MODE_V 0x00000003U -#define TEE_M26_MODE_S 0 - -/** TEE_M27_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) -/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3; - * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M27_MODE 0x00000003U -#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) -#define TEE_M27_MODE_V 0x00000003U -#define TEE_M27_MODE_S 0 - -/** TEE_M28_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) -/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3; - * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M28_MODE 0x00000003U -#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) -#define TEE_M28_MODE_V 0x00000003U -#define TEE_M28_MODE_S 0 - -/** TEE_M29_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) -/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3; - * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M29_MODE 0x00000003U -#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) -#define TEE_M29_MODE_V 0x00000003U -#define TEE_M29_MODE_S 0 - -/** TEE_M30_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) -/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3; - * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M30_MODE 0x00000003U -#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) -#define TEE_M30_MODE_V 0x00000003U -#define TEE_M30_MODE_S 0 - -/** TEE_M31_MODE_CTRL_REG register - * Tee mode control register - */ -#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) -/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3; - * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ -#define TEE_M31_MODE 0x00000003U -#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) -#define TEE_M31_MODE_V 0x00000003U -#define TEE_M31_MODE_S 0 - -/** TEE_CLOCK_GATE_REG register - * Clock gating register - */ -#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80) -/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ -#define TEE_CLK_EN (BIT(0)) -#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) -#define TEE_CLK_EN_V 0x00000001U -#define TEE_CLK_EN_S 0 - -/** TEE_DATE_REG register - * Version register - */ -#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) -/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706; - * reg_tee_date - */ -#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) -#define TEE_DATE_REG_V 0x0FFFFFFFU -#define TEE_DATE_REG_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/tee_struct.h b/components/soc/esp32p4/include/soc/tee_struct.h deleted file mode 100644 index 47f806da1a..0000000000 --- a/components/soc/esp32p4/include/soc/tee_struct.h +++ /dev/null @@ -1,573 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Tee mode control register */ -/** Type of m0_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m0_mode : R/W; bitpos: [1:0]; default: 0; - * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m0_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m0_mode_ctrl_reg_t; - -/** Type of m1_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m1_mode : R/W; bitpos: [1:0]; default: 3; - * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m1_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m1_mode_ctrl_reg_t; - -/** Type of m2_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m2_mode : R/W; bitpos: [1:0]; default: 0; - * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m2_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m2_mode_ctrl_reg_t; - -/** Type of m3_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m3_mode : R/W; bitpos: [1:0]; default: 3; - * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m3_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m3_mode_ctrl_reg_t; - -/** Type of m4_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m4_mode : R/W; bitpos: [1:0]; default: 3; - * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m4_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m4_mode_ctrl_reg_t; - -/** Type of m5_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m5_mode : R/W; bitpos: [1:0]; default: 3; - * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m5_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m5_mode_ctrl_reg_t; - -/** Type of m6_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m6_mode : R/W; bitpos: [1:0]; default: 3; - * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m6_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m6_mode_ctrl_reg_t; - -/** Type of m7_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m7_mode : R/W; bitpos: [1:0]; default: 3; - * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m7_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m7_mode_ctrl_reg_t; - -/** Type of m8_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m8_mode : R/W; bitpos: [1:0]; default: 3; - * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m8_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m8_mode_ctrl_reg_t; - -/** Type of m9_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m9_mode : R/W; bitpos: [1:0]; default: 3; - * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m9_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m9_mode_ctrl_reg_t; - -/** Type of m10_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m10_mode : R/W; bitpos: [1:0]; default: 3; - * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m10_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m10_mode_ctrl_reg_t; - -/** Type of m11_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m11_mode : R/W; bitpos: [1:0]; default: 3; - * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m11_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m11_mode_ctrl_reg_t; - -/** Type of m12_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m12_mode : R/W; bitpos: [1:0]; default: 3; - * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m12_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m12_mode_ctrl_reg_t; - -/** Type of m13_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m13_mode : R/W; bitpos: [1:0]; default: 3; - * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m13_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m13_mode_ctrl_reg_t; - -/** Type of m14_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m14_mode : R/W; bitpos: [1:0]; default: 3; - * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m14_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m14_mode_ctrl_reg_t; - -/** Type of m15_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m15_mode : R/W; bitpos: [1:0]; default: 3; - * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m15_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m15_mode_ctrl_reg_t; - -/** Type of m16_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m16_mode : R/W; bitpos: [1:0]; default: 3; - * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m16_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m16_mode_ctrl_reg_t; - -/** Type of m17_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m17_mode : R/W; bitpos: [1:0]; default: 3; - * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m17_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m17_mode_ctrl_reg_t; - -/** Type of m18_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m18_mode : R/W; bitpos: [1:0]; default: 3; - * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m18_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m18_mode_ctrl_reg_t; - -/** Type of m19_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m19_mode : R/W; bitpos: [1:0]; default: 3; - * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m19_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m19_mode_ctrl_reg_t; - -/** Type of m20_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m20_mode : R/W; bitpos: [1:0]; default: 3; - * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m20_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m20_mode_ctrl_reg_t; - -/** Type of m21_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m21_mode : R/W; bitpos: [1:0]; default: 3; - * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m21_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m21_mode_ctrl_reg_t; - -/** Type of m22_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m22_mode : R/W; bitpos: [1:0]; default: 3; - * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m22_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m22_mode_ctrl_reg_t; - -/** Type of m23_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m23_mode : R/W; bitpos: [1:0]; default: 3; - * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m23_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m23_mode_ctrl_reg_t; - -/** Type of m24_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m24_mode : R/W; bitpos: [1:0]; default: 3; - * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m24_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m24_mode_ctrl_reg_t; - -/** Type of m25_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m25_mode : R/W; bitpos: [1:0]; default: 3; - * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m25_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m25_mode_ctrl_reg_t; - -/** Type of m26_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m26_mode : R/W; bitpos: [1:0]; default: 3; - * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m26_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m26_mode_ctrl_reg_t; - -/** Type of m27_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m27_mode : R/W; bitpos: [1:0]; default: 3; - * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m27_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m27_mode_ctrl_reg_t; - -/** Type of m28_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m28_mode : R/W; bitpos: [1:0]; default: 3; - * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m28_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m28_mode_ctrl_reg_t; - -/** Type of m29_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m29_mode : R/W; bitpos: [1:0]; default: 3; - * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m29_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m29_mode_ctrl_reg_t; - -/** Type of m30_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m30_mode : R/W; bitpos: [1:0]; default: 3; - * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m30_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m30_mode_ctrl_reg_t; - -/** Type of m31_mode_ctrl register - * Tee mode control register - */ -typedef union { - struct { - /** m31_mode : R/W; bitpos: [1:0]; default: 3; - * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: - * tee_mode - */ - uint32_t m31_mode:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} tee_m31_mode_ctrl_reg_t; - - -/** Group: clock gating register */ -/** Type of clock_gate register - * Clock gating register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * reg_clk_en - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} tee_clock_gate_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version register - */ -typedef union { - struct { - /** date_reg : R/W; bitpos: [27:0]; default: 35672706; - * reg_tee_date - */ - uint32_t date_reg:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} tee_date_reg_t; - - -typedef struct tee_dev_t { - volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl; - volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl; - volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl; - volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl; - volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl; - volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl; - volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl; - volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl; - volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl; - volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl; - volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl; - volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl; - volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl; - volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl; - volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl; - volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl; - volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl; - volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl; - volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl; - volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl; - volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl; - volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl; - volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl; - volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl; - volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl; - volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl; - volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl; - volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl; - volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl; - volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl; - volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl; - volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl; - volatile tee_clock_gate_reg_t clock_gate; - uint32_t reserved_084[990]; - volatile tee_date_reg_t date; -} tee_dev_t; - -extern tee_dev_t TEE; - -#ifndef __cplusplus -_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/twaifd_reg.h b/components/soc/esp32p4/include/soc/twaifd_reg.h deleted file mode 100644 index 933e0dc154..0000000000 --- a/components/soc/esp32p4/include/soc/twaifd_reg.h +++ /dev/null @@ -1,1795 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TWAIFD_DEVICE_ID_REG register - * TWAI FD device id status register - */ -#define TWAIFD_DEVICE_ID_REG (DR_REG_TWAIFD_BASE + 0x0) -/** TWAIFD_DEVICE_ID : R/W; bitpos: [31:0]; default: 51965; - * Represents whether CAN IP function is mapped correctly on its base address. - */ -#define TWAIFD_DEVICE_ID 0xFFFFFFFFU -#define TWAIFD_DEVICE_ID_M (TWAIFD_DEVICE_ID_V << TWAIFD_DEVICE_ID_S) -#define TWAIFD_DEVICE_ID_V 0xFFFFFFFFU -#define TWAIFD_DEVICE_ID_S 0 - -/** TWAIFD_MODE_SETTING_REG register - * TWAI FD mode setting register - */ -#define TWAIFD_MODE_SETTING_REG (DR_REG_TWAIFD_BASE + 0x4) -/** TWAIFD_SW_RESET : R/W; bitpos: [0]; default: 0; - * Configures whether or not to reset the TWAI FD controller.\\ - * 0: invalid\\ - * 1: reset.\\ - */ -#define TWAIFD_SW_RESET (BIT(0)) -#define TWAIFD_SW_RESET_M (TWAIFD_SW_RESET_V << TWAIFD_SW_RESET_S) -#define TWAIFD_SW_RESET_V 0x00000001U -#define TWAIFD_SW_RESET_S 0 -/** TWAIFD_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; - * bus monitor enable - */ -#define TWAIFD_LISTEN_ONLY_MODE (BIT(1)) -#define TWAIFD_LISTEN_ONLY_MODE_M (TWAIFD_LISTEN_ONLY_MODE_V << TWAIFD_LISTEN_ONLY_MODE_S) -#define TWAIFD_LISTEN_ONLY_MODE_V 0x00000001U -#define TWAIFD_LISTEN_ONLY_MODE_S 1 -/** TWAIFD_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the self test mode.\\ - * 0: disable\\ - * 1: enable\\ - */ -#define TWAIFD_SELF_TEST_MODE (BIT(2)) -#define TWAIFD_SELF_TEST_MODE_M (TWAIFD_SELF_TEST_MODE_V << TWAIFD_SELF_TEST_MODE_S) -#define TWAIFD_SELF_TEST_MODE_V 0x00000001U -#define TWAIFD_SELF_TEST_MODE_S 2 -/** TWAIFD_ACCEPT_FILTER_MODE : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the usage of acceptance filters.\\ - * 0: disable\\ - * 1: enable\\ - */ -#define TWAIFD_ACCEPT_FILTER_MODE (BIT(3)) -#define TWAIFD_ACCEPT_FILTER_MODE_M (TWAIFD_ACCEPT_FILTER_MODE_V << TWAIFD_ACCEPT_FILTER_MODE_S) -#define TWAIFD_ACCEPT_FILTER_MODE_V 0x00000001U -#define TWAIFD_ACCEPT_FILTER_MODE_S 3 -/** TWAIFD_FLEXIBLE_DATA_RATE : R/W; bitpos: [4]; default: 1; - * Configures whether or not to support flexible data rate.\\ - * 0: not support\\ - * 1: support\\ - */ -#define TWAIFD_FLEXIBLE_DATA_RATE (BIT(4)) -#define TWAIFD_FLEXIBLE_DATA_RATE_M (TWAIFD_FLEXIBLE_DATA_RATE_V << TWAIFD_FLEXIBLE_DATA_RATE_S) -#define TWAIFD_FLEXIBLE_DATA_RATE_V 0x00000001U -#define TWAIFD_FLEXIBLE_DATA_RATE_S 4 -/** TWAIFD_RTR_FRM_BEHAVIOR : R/W; bitpos: [5]; default: 0; - * time_triggered transmission mode - */ -#define TWAIFD_RTR_FRM_BEHAVIOR (BIT(5)) -#define TWAIFD_RTR_FRM_BEHAVIOR_M (TWAIFD_RTR_FRM_BEHAVIOR_V << TWAIFD_RTR_FRM_BEHAVIOR_S) -#define TWAIFD_RTR_FRM_BEHAVIOR_V 0x00000001U -#define TWAIFD_RTR_FRM_BEHAVIOR_S 5 -/** TWAIFD_ROM : R/W; bitpos: [6]; default: 0; - * a\\ - */ -#define TWAIFD_ROM (BIT(6)) -#define TWAIFD_ROM_M (TWAIFD_ROM_V << TWAIFD_ROM_S) -#define TWAIFD_ROM_V 0x00000001U -#define TWAIFD_ROM_S 6 -/** TWAIFD_ACK_BEHAVIOR : R/W; bitpos: [7]; default: 0; - * Configures the acknowledge behavior.\\ - * 0: normal behavior.\\ - * 1: acknowledge is not sent.\\ - */ -#define TWAIFD_ACK_BEHAVIOR (BIT(7)) -#define TWAIFD_ACK_BEHAVIOR_M (TWAIFD_ACK_BEHAVIOR_V << TWAIFD_ACK_BEHAVIOR_S) -#define TWAIFD_ACK_BEHAVIOR_V 0x00000001U -#define TWAIFD_ACK_BEHAVIOR_S 7 -/** TWAIFD_TEST_MODE : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the triple sampling mode.\\ - * 0: disable\\ - * 1: enable\\ - */ -#define TWAIFD_TEST_MODE (BIT(8)) -#define TWAIFD_TEST_MODE_M (TWAIFD_TEST_MODE_V << TWAIFD_TEST_MODE_S) -#define TWAIFD_TEST_MODE_V 0x00000001U -#define TWAIFD_TEST_MODE_S 8 -/** TWAIFD_RXBAM : R/W; bitpos: [9]; default: 1; - * a\\ - */ -#define TWAIFD_RXBAM (BIT(9)) -#define TWAIFD_RXBAM_M (TWAIFD_RXBAM_V << TWAIFD_RXBAM_S) -#define TWAIFD_RXBAM_V 0x00000001U -#define TWAIFD_RXBAM_S 9 -/** TWAIFD_LIMIT_RETX_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the limit of retransmission.\\ - * 0: disable\\ - * 1: enable\\ - */ -#define TWAIFD_LIMIT_RETX_EN (BIT(16)) -#define TWAIFD_LIMIT_RETX_EN_M (TWAIFD_LIMIT_RETX_EN_V << TWAIFD_LIMIT_RETX_EN_S) -#define TWAIFD_LIMIT_RETX_EN_V 0x00000001U -#define TWAIFD_LIMIT_RETX_EN_S 16 -/** TWAIFD_RETX_THRES : R/W; bitpos: [20:17]; default: 0; - * Configures the threshold of retransmission attempts. \\ - */ -#define TWAIFD_RETX_THRES 0x0000000FU -#define TWAIFD_RETX_THRES_M (TWAIFD_RETX_THRES_V << TWAIFD_RETX_THRES_S) -#define TWAIFD_RETX_THRES_V 0x0000000FU -#define TWAIFD_RETX_THRES_S 17 -/** TWAIFD_ILBP : R/W; bitpos: [21]; default: 0; - * acknowledge forbidden mode - */ -#define TWAIFD_ILBP (BIT(21)) -#define TWAIFD_ILBP_M (TWAIFD_ILBP_V << TWAIFD_ILBP_S) -#define TWAIFD_ILBP_V 0x00000001U -#define TWAIFD_ILBP_S 21 -/** TWAIFD_CTRL_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the twai FD controller.\\ - * 0: disable\\ - * 1: enable\\ - */ -#define TWAIFD_CTRL_EN (BIT(22)) -#define TWAIFD_CTRL_EN_M (TWAIFD_CTRL_EN_V << TWAIFD_CTRL_EN_S) -#define TWAIFD_CTRL_EN_V 0x00000001U -#define TWAIFD_CTRL_EN_S 22 -/** TWAIFD_FD_TYPE : R/W; bitpos: [23]; default: 0; - * Configure the twai fd frame type.\\ - * 0: ISO CAN FD\\ - * 1: CAN FD 1.0\\ - */ -#define TWAIFD_FD_TYPE (BIT(23)) -#define TWAIFD_FD_TYPE_M (TWAIFD_FD_TYPE_V << TWAIFD_FD_TYPE_S) -#define TWAIFD_FD_TYPE_V 0x00000001U -#define TWAIFD_FD_TYPE_S 23 -/** TWAIFD_PEX : R/W; bitpos: [24]; default: 0; - * protocol expection mode\\ - */ -#define TWAIFD_PEX (BIT(24)) -#define TWAIFD_PEX_M (TWAIFD_PEX_V << TWAIFD_PEX_S) -#define TWAIFD_PEX_V 0x00000001U -#define TWAIFD_PEX_S 24 -/** TWAIFD_TBFBO : R/W; bitpos: [25]; default: 1; - * a\\ - */ -#define TWAIFD_TBFBO (BIT(25)) -#define TWAIFD_TBFBO_M (TWAIFD_TBFBO_V << TWAIFD_TBFBO_S) -#define TWAIFD_TBFBO_V 0x00000001U -#define TWAIFD_TBFBO_S 25 -/** TWAIFD_FDRF : R/W; bitpos: [26]; default: 0; - * a\\ - */ -#define TWAIFD_FDRF (BIT(26)) -#define TWAIFD_FDRF_M (TWAIFD_FDRF_V << TWAIFD_FDRF_S) -#define TWAIFD_FDRF_V 0x00000001U -#define TWAIFD_FDRF_S 26 - -/** TWAIFD_COMMAND_REG register - * TWAI FD command register - */ -#define TWAIFD_COMMAND_REG (DR_REG_TWAIFD_BASE + 0x8) -/** TWAIFD_RXRPMV : WO; bitpos: [1]; default: 0; - * a\\ - */ -#define TWAIFD_RXRPMV (BIT(1)) -#define TWAIFD_RXRPMV_M (TWAIFD_RXRPMV_V << TWAIFD_RXRPMV_S) -#define TWAIFD_RXRPMV_V 0x00000001U -#define TWAIFD_RXRPMV_S 1 -/** TWAIFD_RELEASE_RX_BUF : WO; bitpos: [2]; default: 0; - * Configures whether or not to delete all data from the receive buffer.\\ - * 0: invalid\\ - * 1: delete\\ - */ -#define TWAIFD_RELEASE_RX_BUF (BIT(2)) -#define TWAIFD_RELEASE_RX_BUF_M (TWAIFD_RELEASE_RX_BUF_V << TWAIFD_RELEASE_RX_BUF_S) -#define TWAIFD_RELEASE_RX_BUF_V 0x00000001U -#define TWAIFD_RELEASE_RX_BUF_S 2 -/** TWAIFD_CLR_OVERRUN_FLG : WO; bitpos: [3]; default: 0; - * Configures whether or not to clear the data overrun flag.\\ - * 0: invalid\\ - * 1: clear\\ - */ -#define TWAIFD_CLR_OVERRUN_FLG (BIT(3)) -#define TWAIFD_CLR_OVERRUN_FLG_M (TWAIFD_CLR_OVERRUN_FLG_V << TWAIFD_CLR_OVERRUN_FLG_S) -#define TWAIFD_CLR_OVERRUN_FLG_V 0x00000001U -#define TWAIFD_CLR_OVERRUN_FLG_S 3 -/** TWAIFD_ERCRST : WO; bitpos: [4]; default: 0; - * a\\ - */ -#define TWAIFD_ERCRST (BIT(4)) -#define TWAIFD_ERCRST_M (TWAIFD_ERCRST_V << TWAIFD_ERCRST_S) -#define TWAIFD_ERCRST_V 0x00000001U -#define TWAIFD_ERCRST_S 4 -/** TWAIFD_RXFCRST : WO; bitpos: [5]; default: 0; - * a\\ - */ -#define TWAIFD_RXFCRST (BIT(5)) -#define TWAIFD_RXFCRST_M (TWAIFD_RXFCRST_V << TWAIFD_RXFCRST_S) -#define TWAIFD_RXFCRST_V 0x00000001U -#define TWAIFD_RXFCRST_S 5 -/** TWAIFD_TXFCRST : WO; bitpos: [6]; default: 0; - * a\\ - */ -#define TWAIFD_TXFCRST (BIT(6)) -#define TWAIFD_TXFCRST_M (TWAIFD_TXFCRST_V << TWAIFD_TXFCRST_S) -#define TWAIFD_TXFCRST_V 0x00000001U -#define TWAIFD_TXFCRST_S 6 -/** TWAIFD_CPEXS : WO; bitpos: [7]; default: 0; - * a\\ - */ -#define TWAIFD_CPEXS (BIT(7)) -#define TWAIFD_CPEXS_M (TWAIFD_CPEXS_V << TWAIFD_CPEXS_S) -#define TWAIFD_CPEXS_V 0x00000001U -#define TWAIFD_CPEXS_S 7 - -/** TWAIFD_STATUS_REG register - * TWAI FD status register - */ -#define TWAIFD_STATUS_REG (DR_REG_TWAIFD_BASE + 0xc) -/** TWAIFD_RX_BUF_STAT : RO; bitpos: [0]; default: 0; - * Represents whether or not the receive buffer is empty.\\ - * 0: empty\\ - * 1: not empty\\ - */ -#define TWAIFD_RX_BUF_STAT (BIT(0)) -#define TWAIFD_RX_BUF_STAT_M (TWAIFD_RX_BUF_STAT_V << TWAIFD_RX_BUF_STAT_S) -#define TWAIFD_RX_BUF_STAT_V 0x00000001U -#define TWAIFD_RX_BUF_STAT_S 0 -/** TWAIFD_DATA_OVERRUN_FLG : RO; bitpos: [1]; default: 0; - * Represents whether or not the receive buffer is full and the frame is - * overrun(lost).\\ - * 0: not overrun\\ - * 1: overrun\\ - */ -#define TWAIFD_DATA_OVERRUN_FLG (BIT(1)) -#define TWAIFD_DATA_OVERRUN_FLG_M (TWAIFD_DATA_OVERRUN_FLG_V << TWAIFD_DATA_OVERRUN_FLG_S) -#define TWAIFD_DATA_OVERRUN_FLG_V 0x00000001U -#define TWAIFD_DATA_OVERRUN_FLG_S 1 -/** TWAIFD_TX_BUF_SAT : RO; bitpos: [2]; default: 0; - * Represents whether or not the transmit buffer is full.\\ - * 0: not full\\ - * 1: full\\ - */ -#define TWAIFD_TX_BUF_SAT (BIT(2)) -#define TWAIFD_TX_BUF_SAT_M (TWAIFD_TX_BUF_SAT_V << TWAIFD_TX_BUF_SAT_S) -#define TWAIFD_TX_BUF_SAT_V 0x00000001U -#define TWAIFD_TX_BUF_SAT_S 2 -/** TWAIFD_ERR_FRM_TX : RO; bitpos: [3]; default: 0; - * Represents whether or not the error frame is being transmitted.\\ - * 0: not being transmitted\\ - * 1: being transmitted\\ - */ -#define TWAIFD_ERR_FRM_TX (BIT(3)) -#define TWAIFD_ERR_FRM_TX_M (TWAIFD_ERR_FRM_TX_V << TWAIFD_ERR_FRM_TX_S) -#define TWAIFD_ERR_FRM_TX_V 0x00000001U -#define TWAIFD_ERR_FRM_TX_S 3 -/** TWAIFD_RX_FRM_STAT : RO; bitpos: [4]; default: 0; - * Represents whether or not the controller is receiving a frame.\\ - * 0: not receiving\\ - * 1: receiving\\ - */ -#define TWAIFD_RX_FRM_STAT (BIT(4)) -#define TWAIFD_RX_FRM_STAT_M (TWAIFD_RX_FRM_STAT_V << TWAIFD_RX_FRM_STAT_S) -#define TWAIFD_RX_FRM_STAT_V 0x00000001U -#define TWAIFD_RX_FRM_STAT_S 4 -/** TWAIFD_TX_FRM_STAT : RO; bitpos: [5]; default: 0; - * Represents whether or not the controller is transmitting a frame.\\ - * 0: not transmitting\\ - * 1: transmitting\\ - */ -#define TWAIFD_TX_FRM_STAT (BIT(5)) -#define TWAIFD_TX_FRM_STAT_M (TWAIFD_TX_FRM_STAT_V << TWAIFD_TX_FRM_STAT_S) -#define TWAIFD_TX_FRM_STAT_V 0x00000001U -#define TWAIFD_TX_FRM_STAT_S 5 -/** TWAIFD_ERR_STAT : RO; bitpos: [6]; default: 0; - * Represents whether or not the error warning limit is reached.\\ - * 0: not reached\\ - * 1: reached\\ - */ -#define TWAIFD_ERR_STAT (BIT(6)) -#define TWAIFD_ERR_STAT_M (TWAIFD_ERR_STAT_V << TWAIFD_ERR_STAT_S) -#define TWAIFD_ERR_STAT_V 0x00000001U -#define TWAIFD_ERR_STAT_S 6 -/** TWAIFD_BUS_STAT : RO; bitpos: [7]; default: 1; - * Represents whether or not bus is active.\\ - * 0: active\\ - * 1: not active\\ - */ -#define TWAIFD_BUS_STAT (BIT(7)) -#define TWAIFD_BUS_STAT_M (TWAIFD_BUS_STAT_V << TWAIFD_BUS_STAT_S) -#define TWAIFD_BUS_STAT_V 0x00000001U -#define TWAIFD_BUS_STAT_S 7 -/** TWAIFD_PEXS : RO; bitpos: [8]; default: 0; - * a\\ - */ -#define TWAIFD_PEXS (BIT(8)) -#define TWAIFD_PEXS_M (TWAIFD_PEXS_V << TWAIFD_PEXS_S) -#define TWAIFD_PEXS_V 0x00000001U -#define TWAIFD_PEXS_S 8 -/** TWAIFD_REINTEGRATING_WAIT : RO; bitpos: [9]; default: 0; - * fsm is in reintegrating wait status - */ -#define TWAIFD_REINTEGRATING_WAIT (BIT(9)) -#define TWAIFD_REINTEGRATING_WAIT_M (TWAIFD_REINTEGRATING_WAIT_V << TWAIFD_REINTEGRATING_WAIT_S) -#define TWAIFD_REINTEGRATING_WAIT_V 0x00000001U -#define TWAIFD_REINTEGRATING_WAIT_S 9 -/** TWAIFD_STCNT : RO; bitpos: [16]; default: 0; - * a\\ - */ -#define TWAIFD_STCNT (BIT(16)) -#define TWAIFD_STCNT_M (TWAIFD_STCNT_V << TWAIFD_STCNT_S) -#define TWAIFD_STCNT_V 0x00000001U -#define TWAIFD_STCNT_S 16 -/** TWAIFD_STRGS : RO; bitpos: [17]; default: 0; - * a\\ - */ -#define TWAIFD_STRGS (BIT(17)) -#define TWAIFD_STRGS_M (TWAIFD_STRGS_V << TWAIFD_STRGS_S) -#define TWAIFD_STRGS_V 0x00000001U -#define TWAIFD_STRGS_S 17 - -/** TWAIFD_INT_RAW_REG register - * TWAI FD interrupt raw register - */ -#define TWAIFD_INT_RAW_REG (DR_REG_TWAIFD_BASE + 0x10) -/** TWAIFD_RX_FRM_SUC_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of TWAIFD_RX_FRM_SUC_INT. - */ -#define TWAIFD_RX_FRM_SUC_INT_RAW (BIT(0)) -#define TWAIFD_RX_FRM_SUC_INT_RAW_M (TWAIFD_RX_FRM_SUC_INT_RAW_V << TWAIFD_RX_FRM_SUC_INT_RAW_S) -#define TWAIFD_RX_FRM_SUC_INT_RAW_V 0x00000001U -#define TWAIFD_RX_FRM_SUC_INT_RAW_S 0 -/** TWAIFD_TX_FRM_SUC_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of TWAIFD_TX_FRM_SUC_INT. - */ -#define TWAIFD_TX_FRM_SUC_INT_RAW (BIT(1)) -#define TWAIFD_TX_FRM_SUC_INT_RAW_M (TWAIFD_TX_FRM_SUC_INT_RAW_V << TWAIFD_TX_FRM_SUC_INT_RAW_S) -#define TWAIFD_TX_FRM_SUC_INT_RAW_V 0x00000001U -#define TWAIFD_TX_FRM_SUC_INT_RAW_S 1 -/** TWAIFD_ERR_WARNING_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of TWAIFD_ERR_WARNING_INT. - */ -#define TWAIFD_ERR_WARNING_INT_RAW (BIT(2)) -#define TWAIFD_ERR_WARNING_INT_RAW_M (TWAIFD_ERR_WARNING_INT_RAW_V << TWAIFD_ERR_WARNING_INT_RAW_S) -#define TWAIFD_ERR_WARNING_INT_RAW_V 0x00000001U -#define TWAIFD_ERR_WARNING_INT_RAW_S 2 -/** TWAIFD_RX_DATA_OVERRUN_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of TWAIFD_RX_DATA_OVERRUN_INT. - */ -#define TWAIFD_RX_DATA_OVERRUN_INT_RAW (BIT(3)) -#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_M (TWAIFD_RX_DATA_OVERRUN_INT_RAW_V << TWAIFD_RX_DATA_OVERRUN_INT_RAW_S) -#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_V 0x00000001U -#define TWAIFD_RX_DATA_OVERRUN_INT_RAW_S 3 -/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW (BIT(5)) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_M (TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_S) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_V 0x00000001U -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_RAW_S 5 -/** TWAIFD_ARB_LOST_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of TWAIFD_ARB_LOST_INT. - */ -#define TWAIFD_ARB_LOST_INT_RAW (BIT(6)) -#define TWAIFD_ARB_LOST_INT_RAW_M (TWAIFD_ARB_LOST_INT_RAW_V << TWAIFD_ARB_LOST_INT_RAW_S) -#define TWAIFD_ARB_LOST_INT_RAW_V 0x00000001U -#define TWAIFD_ARB_LOST_INT_RAW_S 6 -/** TWAIFD_ERR_DETECTED_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of TWAIFD_ERR_DETECTED_INT. - */ -#define TWAIFD_ERR_DETECTED_INT_RAW (BIT(7)) -#define TWAIFD_ERR_DETECTED_INT_RAW_M (TWAIFD_ERR_DETECTED_INT_RAW_V << TWAIFD_ERR_DETECTED_INT_RAW_S) -#define TWAIFD_ERR_DETECTED_INT_RAW_V 0x00000001U -#define TWAIFD_ERR_DETECTED_INT_RAW_S 7 -/** TWAIFD_IS_OVERLOAD_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt status of TWAIFD_IS_OVERLOAD_INT. - */ -#define TWAIFD_IS_OVERLOAD_INT_RAW (BIT(8)) -#define TWAIFD_IS_OVERLOAD_INT_RAW_M (TWAIFD_IS_OVERLOAD_INT_RAW_V << TWAIFD_IS_OVERLOAD_INT_RAW_S) -#define TWAIFD_IS_OVERLOAD_INT_RAW_V 0x00000001U -#define TWAIFD_IS_OVERLOAD_INT_RAW_S 8 -/** TWAIFD_RX_BUF_FULL_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt status of TWAIFD_RX_BUF_FULL_INT. - */ -#define TWAIFD_RX_BUF_FULL_INT_RAW (BIT(9)) -#define TWAIFD_RX_BUF_FULL_INT_RAW_M (TWAIFD_RX_BUF_FULL_INT_RAW_V << TWAIFD_RX_BUF_FULL_INT_RAW_S) -#define TWAIFD_RX_BUF_FULL_INT_RAW_V 0x00000001U -#define TWAIFD_RX_BUF_FULL_INT_RAW_S 9 -/** TWAIFD_BIT_RATE_SHIFT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt status of TWAIFD_BIT_RATE_SHIFT_INT. - */ -#define TWAIFD_BIT_RATE_SHIFT_INT_RAW (BIT(10)) -#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_M (TWAIFD_BIT_RATE_SHIFT_INT_RAW_V << TWAIFD_BIT_RATE_SHIFT_INT_RAW_S) -#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_V 0x00000001U -#define TWAIFD_BIT_RATE_SHIFT_INT_RAW_S 10 -/** TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW (BIT(11)) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_M (TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_S) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_V 0x00000001U -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_RAW_S 11 -/** TWAIFD_TX_BUF_STATUS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT. - */ -#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW (BIT(12)) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_M (TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_V << TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_S) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_V 0x00000001U -#define TWAIFD_TX_BUF_STATUS_CHG_INT_RAW_S 12 - -/** TWAIFD_INT_ENA_REG register - * TWAI FD interrupt enable register - */ -#define TWAIFD_INT_ENA_REG (DR_REG_TWAIFD_BASE + 0x14) -/** TWAIFD_RX_FRM_SUC_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable TWAIFD_RX_FRM_SUC_INT. - */ -#define TWAIFD_RX_FRM_SUC_INT_ENA (BIT(0)) -#define TWAIFD_RX_FRM_SUC_INT_ENA_M (TWAIFD_RX_FRM_SUC_INT_ENA_V << TWAIFD_RX_FRM_SUC_INT_ENA_S) -#define TWAIFD_RX_FRM_SUC_INT_ENA_V 0x00000001U -#define TWAIFD_RX_FRM_SUC_INT_ENA_S 0 -/** TWAIFD_TX_FRM_SUC_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable TWAIFD_TX_FRM_SUC_INT. - */ -#define TWAIFD_TX_FRM_SUC_INT_ENA (BIT(1)) -#define TWAIFD_TX_FRM_SUC_INT_ENA_M (TWAIFD_TX_FRM_SUC_INT_ENA_V << TWAIFD_TX_FRM_SUC_INT_ENA_S) -#define TWAIFD_TX_FRM_SUC_INT_ENA_V 0x00000001U -#define TWAIFD_TX_FRM_SUC_INT_ENA_S 1 -/** TWAIFD_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable TWAIFD_ERR_WARNING_INT. - */ -#define TWAIFD_ERR_WARNING_INT_ENA (BIT(2)) -#define TWAIFD_ERR_WARNING_INT_ENA_M (TWAIFD_ERR_WARNING_INT_ENA_V << TWAIFD_ERR_WARNING_INT_ENA_S) -#define TWAIFD_ERR_WARNING_INT_ENA_V 0x00000001U -#define TWAIFD_ERR_WARNING_INT_ENA_S 2 -/** TWAIFD_RX_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable TWAIFD_RX_DATA_OVERRUN_INT. - */ -#define TWAIFD_RX_DATA_OVERRUN_INT_ENA (BIT(3)) -#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_M (TWAIFD_RX_DATA_OVERRUN_INT_ENA_V << TWAIFD_RX_DATA_OVERRUN_INT_ENA_S) -#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_V 0x00000001U -#define TWAIFD_RX_DATA_OVERRUN_INT_ENA_S 3 -/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA (BIT(5)) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_M (TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_S) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_V 0x00000001U -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ENA_S 5 -/** TWAIFD_ARB_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable TWAIFD_ARB_LOST_INT. - */ -#define TWAIFD_ARB_LOST_INT_ENA (BIT(6)) -#define TWAIFD_ARB_LOST_INT_ENA_M (TWAIFD_ARB_LOST_INT_ENA_V << TWAIFD_ARB_LOST_INT_ENA_S) -#define TWAIFD_ARB_LOST_INT_ENA_V 0x00000001U -#define TWAIFD_ARB_LOST_INT_ENA_S 6 -/** TWAIFD_ERR_DETECTED_INT_ENA : R/W; bitpos: [7]; default: 0; - * Write 1 to enable TWAIFD_ERR_DETECTED_INT. - */ -#define TWAIFD_ERR_DETECTED_INT_ENA (BIT(7)) -#define TWAIFD_ERR_DETECTED_INT_ENA_M (TWAIFD_ERR_DETECTED_INT_ENA_V << TWAIFD_ERR_DETECTED_INT_ENA_S) -#define TWAIFD_ERR_DETECTED_INT_ENA_V 0x00000001U -#define TWAIFD_ERR_DETECTED_INT_ENA_S 7 -/** TWAIFD_IS_OVERLOAD_INT_ENA : R/W; bitpos: [8]; default: 0; - * Write 1 to enable TWAIFD_IS_OVERLOAD_INT. - */ -#define TWAIFD_IS_OVERLOAD_INT_ENA (BIT(8)) -#define TWAIFD_IS_OVERLOAD_INT_ENA_M (TWAIFD_IS_OVERLOAD_INT_ENA_V << TWAIFD_IS_OVERLOAD_INT_ENA_S) -#define TWAIFD_IS_OVERLOAD_INT_ENA_V 0x00000001U -#define TWAIFD_IS_OVERLOAD_INT_ENA_S 8 -/** TWAIFD_RX_BUF_FULL_INT_ENA : R/W; bitpos: [9]; default: 0; - * Write 1 to enable TWAIFD_RX_BUF_FULL_INT. - */ -#define TWAIFD_RX_BUF_FULL_INT_ENA (BIT(9)) -#define TWAIFD_RX_BUF_FULL_INT_ENA_M (TWAIFD_RX_BUF_FULL_INT_ENA_V << TWAIFD_RX_BUF_FULL_INT_ENA_S) -#define TWAIFD_RX_BUF_FULL_INT_ENA_V 0x00000001U -#define TWAIFD_RX_BUF_FULL_INT_ENA_S 9 -/** TWAIFD_BIT_RATE_SHIFT_INT_ENA : R/W; bitpos: [10]; default: 0; - * Write 1 to enable TWAIFD_BIT_RATE_SHIFT_INT. - */ -#define TWAIFD_BIT_RATE_SHIFT_INT_ENA (BIT(10)) -#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_M (TWAIFD_BIT_RATE_SHIFT_INT_ENA_V << TWAIFD_BIT_RATE_SHIFT_INT_ENA_S) -#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_V 0x00000001U -#define TWAIFD_BIT_RATE_SHIFT_INT_ENA_S 10 -/** TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA : R/W; bitpos: [11]; default: 0; - * Write 1 to enable TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA (BIT(11)) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_M (TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_S) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_V 0x00000001U -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ENA_S 11 -/** TWAIFD_TX_BUF_STATUS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; - * Write 1 to enable TWAIFD_TX_BUF_STATUS_CHG_INT. - */ -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA (BIT(12)) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_M (TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_V << TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_S) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_V 0x00000001U -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ENA_S 12 - -/** TWAIFD_INT_ST_REG register - * TWAI FD interrupt status register - */ -#define TWAIFD_INT_ST_REG (DR_REG_TWAIFD_BASE + 0x18) -/** TWAIFD_RX_FRM_SUC_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of TWAIFD_RX_FRM_SUC_INT. - */ -#define TWAIFD_RX_FRM_SUC_INT_ST (BIT(0)) -#define TWAIFD_RX_FRM_SUC_INT_ST_M (TWAIFD_RX_FRM_SUC_INT_ST_V << TWAIFD_RX_FRM_SUC_INT_ST_S) -#define TWAIFD_RX_FRM_SUC_INT_ST_V 0x00000001U -#define TWAIFD_RX_FRM_SUC_INT_ST_S 0 -/** TWAIFD_TX_FRM_SUC_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of TWAIFD_TX_FRM_SUC_INT. - */ -#define TWAIFD_TX_FRM_SUC_INT_ST (BIT(1)) -#define TWAIFD_TX_FRM_SUC_INT_ST_M (TWAIFD_TX_FRM_SUC_INT_ST_V << TWAIFD_TX_FRM_SUC_INT_ST_S) -#define TWAIFD_TX_FRM_SUC_INT_ST_V 0x00000001U -#define TWAIFD_TX_FRM_SUC_INT_ST_S 1 -/** TWAIFD_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of TWAIFD_ERR_WARNING_INT. - */ -#define TWAIFD_ERR_WARNING_INT_ST (BIT(2)) -#define TWAIFD_ERR_WARNING_INT_ST_M (TWAIFD_ERR_WARNING_INT_ST_V << TWAIFD_ERR_WARNING_INT_ST_S) -#define TWAIFD_ERR_WARNING_INT_ST_V 0x00000001U -#define TWAIFD_ERR_WARNING_INT_ST_S 2 -/** TWAIFD_RX_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of TWAIFD_RX_DATA_OVERRUN_INT. - */ -#define TWAIFD_RX_DATA_OVERRUN_INT_ST (BIT(3)) -#define TWAIFD_RX_DATA_OVERRUN_INT_ST_M (TWAIFD_RX_DATA_OVERRUN_INT_ST_V << TWAIFD_RX_DATA_OVERRUN_INT_ST_S) -#define TWAIFD_RX_DATA_OVERRUN_INT_ST_V 0x00000001U -#define TWAIFD_RX_DATA_OVERRUN_INT_ST_S 3 -/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST (BIT(5)) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_M (TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_S) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_V 0x00000001U -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_ST_S 5 -/** TWAIFD_ARB_LOST_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of TWAIFD_ARB_LOST_INT. - */ -#define TWAIFD_ARB_LOST_INT_ST (BIT(6)) -#define TWAIFD_ARB_LOST_INT_ST_M (TWAIFD_ARB_LOST_INT_ST_V << TWAIFD_ARB_LOST_INT_ST_S) -#define TWAIFD_ARB_LOST_INT_ST_V 0x00000001U -#define TWAIFD_ARB_LOST_INT_ST_S 6 -/** TWAIFD_ERR_DETECTED_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status of TWAIFD_ERR_DETECTED_INT. - */ -#define TWAIFD_ERR_DETECTED_INT_ST (BIT(7)) -#define TWAIFD_ERR_DETECTED_INT_ST_M (TWAIFD_ERR_DETECTED_INT_ST_V << TWAIFD_ERR_DETECTED_INT_ST_S) -#define TWAIFD_ERR_DETECTED_INT_ST_V 0x00000001U -#define TWAIFD_ERR_DETECTED_INT_ST_S 7 -/** TWAIFD_IS_OVERLOAD_INT_ST : RO; bitpos: [8]; default: 0; - * The masked interrupt status of TWAIFD_IS_OVERLOAD_INT. - */ -#define TWAIFD_IS_OVERLOAD_INT_ST (BIT(8)) -#define TWAIFD_IS_OVERLOAD_INT_ST_M (TWAIFD_IS_OVERLOAD_INT_ST_V << TWAIFD_IS_OVERLOAD_INT_ST_S) -#define TWAIFD_IS_OVERLOAD_INT_ST_V 0x00000001U -#define TWAIFD_IS_OVERLOAD_INT_ST_S 8 -/** TWAIFD_RX_BUF_FULL_INT_ST : RO; bitpos: [9]; default: 0; - * The masked interrupt status of TWAIFD_RX_BUF_FULL_INT. - */ -#define TWAIFD_RX_BUF_FULL_INT_ST (BIT(9)) -#define TWAIFD_RX_BUF_FULL_INT_ST_M (TWAIFD_RX_BUF_FULL_INT_ST_V << TWAIFD_RX_BUF_FULL_INT_ST_S) -#define TWAIFD_RX_BUF_FULL_INT_ST_V 0x00000001U -#define TWAIFD_RX_BUF_FULL_INT_ST_S 9 -/** TWAIFD_BIT_RATE_SHIFT_INT_ST : RO; bitpos: [10]; default: 0; - * The masked interrupt status of TWAIFD_BIT_RATE_SHIFT_INT. - */ -#define TWAIFD_BIT_RATE_SHIFT_INT_ST (BIT(10)) -#define TWAIFD_BIT_RATE_SHIFT_INT_ST_M (TWAIFD_BIT_RATE_SHIFT_INT_ST_V << TWAIFD_BIT_RATE_SHIFT_INT_ST_S) -#define TWAIFD_BIT_RATE_SHIFT_INT_ST_V 0x00000001U -#define TWAIFD_BIT_RATE_SHIFT_INT_ST_S 10 -/** TWAIFD_RX_BUF_NOT_EMPTY_INT_ST : RO; bitpos: [11]; default: 0; - * The masked interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST (BIT(11)) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_M (TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_S) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_V 0x00000001U -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_ST_S 11 -/** TWAIFD_TX_BUF_STATUS_CHG_INT_ST : RO; bitpos: [12]; default: 0; - * The masked interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT. - */ -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST (BIT(12)) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_M (TWAIFD_TX_BUF_STATUS_CHG_INT_ST_V << TWAIFD_TX_BUF_STATUS_CHG_INT_ST_S) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_V 0x00000001U -#define TWAIFD_TX_BUF_STATUS_CHG_INT_ST_S 12 - -/** TWAIFD_INT_CLR_REG register - * TWAI FD interrupt clear register - */ -#define TWAIFD_INT_CLR_REG (DR_REG_TWAIFD_BASE + 0x1c) -/** TWAIFD_RX_FRM_SUC_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear TWAIFD_RX_FRM_SUC_INT. - */ -#define TWAIFD_RX_FRM_SUC_INT_CLR (BIT(0)) -#define TWAIFD_RX_FRM_SUC_INT_CLR_M (TWAIFD_RX_FRM_SUC_INT_CLR_V << TWAIFD_RX_FRM_SUC_INT_CLR_S) -#define TWAIFD_RX_FRM_SUC_INT_CLR_V 0x00000001U -#define TWAIFD_RX_FRM_SUC_INT_CLR_S 0 -/** TWAIFD_TX_FRM_SUC_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear TWAIFD_TX_FRM_SUC_INT. - */ -#define TWAIFD_TX_FRM_SUC_INT_CLR (BIT(1)) -#define TWAIFD_TX_FRM_SUC_INT_CLR_M (TWAIFD_TX_FRM_SUC_INT_CLR_V << TWAIFD_TX_FRM_SUC_INT_CLR_S) -#define TWAIFD_TX_FRM_SUC_INT_CLR_V 0x00000001U -#define TWAIFD_TX_FRM_SUC_INT_CLR_S 1 -/** TWAIFD_ERR_WARNING_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear TWAIFD_ERR_WARNING_INT. - */ -#define TWAIFD_ERR_WARNING_INT_CLR (BIT(2)) -#define TWAIFD_ERR_WARNING_INT_CLR_M (TWAIFD_ERR_WARNING_INT_CLR_V << TWAIFD_ERR_WARNING_INT_CLR_S) -#define TWAIFD_ERR_WARNING_INT_CLR_V 0x00000001U -#define TWAIFD_ERR_WARNING_INT_CLR_S 2 -/** TWAIFD_RX_DATA_OVERRUN_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear TWAIFD_RX_DATA_OVERRUN_INT. - */ -#define TWAIFD_RX_DATA_OVERRUN_INT_CLR (BIT(3)) -#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_M (TWAIFD_RX_DATA_OVERRUN_INT_CLR_V << TWAIFD_RX_DATA_OVERRUN_INT_CLR_S) -#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_V 0x00000001U -#define TWAIFD_RX_DATA_OVERRUN_INT_CLR_S 3 -/** TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR (BIT(5)) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_M (TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_V << TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_S) -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_V 0x00000001U -#define TWAIFD_FAULT_CONFINEMENT_CHG_INT_CLR_S 5 -/** TWAIFD_ARB_LOST_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear TWAIFD_ARB_LOST_INT. - */ -#define TWAIFD_ARB_LOST_INT_CLR (BIT(6)) -#define TWAIFD_ARB_LOST_INT_CLR_M (TWAIFD_ARB_LOST_INT_CLR_V << TWAIFD_ARB_LOST_INT_CLR_S) -#define TWAIFD_ARB_LOST_INT_CLR_V 0x00000001U -#define TWAIFD_ARB_LOST_INT_CLR_S 6 -/** TWAIFD_ERR_DETECTED_INT_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear TWAIFD_ERR_DETECTED_INT. - */ -#define TWAIFD_ERR_DETECTED_INT_CLR (BIT(7)) -#define TWAIFD_ERR_DETECTED_INT_CLR_M (TWAIFD_ERR_DETECTED_INT_CLR_V << TWAIFD_ERR_DETECTED_INT_CLR_S) -#define TWAIFD_ERR_DETECTED_INT_CLR_V 0x00000001U -#define TWAIFD_ERR_DETECTED_INT_CLR_S 7 -/** TWAIFD_IS_OVERLOAD_INT_CLR : WT; bitpos: [8]; default: 0; - * Write 1 to clear TWAIFD_IS_OVERLOAD_INT. - */ -#define TWAIFD_IS_OVERLOAD_INT_CLR (BIT(8)) -#define TWAIFD_IS_OVERLOAD_INT_CLR_M (TWAIFD_IS_OVERLOAD_INT_CLR_V << TWAIFD_IS_OVERLOAD_INT_CLR_S) -#define TWAIFD_IS_OVERLOAD_INT_CLR_V 0x00000001U -#define TWAIFD_IS_OVERLOAD_INT_CLR_S 8 -/** TWAIFD_RX_BUF_FULL_INT_CLR : WT; bitpos: [9]; default: 0; - * Write 1 to clear TWAIFD_RX_BUF_FULL_INT. - */ -#define TWAIFD_RX_BUF_FULL_INT_CLR (BIT(9)) -#define TWAIFD_RX_BUF_FULL_INT_CLR_M (TWAIFD_RX_BUF_FULL_INT_CLR_V << TWAIFD_RX_BUF_FULL_INT_CLR_S) -#define TWAIFD_RX_BUF_FULL_INT_CLR_V 0x00000001U -#define TWAIFD_RX_BUF_FULL_INT_CLR_S 9 -/** TWAIFD_BIT_RATE_SHIFT_INT_CLR : WT; bitpos: [10]; default: 0; - * Write 1 to clear TWAIFD_BIT_RATE_SHIFT_INT. - */ -#define TWAIFD_BIT_RATE_SHIFT_INT_CLR (BIT(10)) -#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_M (TWAIFD_BIT_RATE_SHIFT_INT_CLR_V << TWAIFD_BIT_RATE_SHIFT_INT_CLR_S) -#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_V 0x00000001U -#define TWAIFD_BIT_RATE_SHIFT_INT_CLR_S 10 -/** TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR : WT; bitpos: [11]; default: 0; - * Write 1 to clear TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR (BIT(11)) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_M (TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_V << TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_S) -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_V 0x00000001U -#define TWAIFD_RX_BUF_NOT_EMPTY_INT_CLR_S 11 -/** TWAIFD_TX_BUF_STATUS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; - * Write 1 to clear TWAIFD_TX_BUF_STATUS_CHG_INT. - */ -#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR (BIT(12)) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_M (TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_V << TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_S) -#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_V 0x00000001U -#define TWAIFD_TX_BUF_STATUS_CHG_INT_CLR_S 12 - -/** TWAIFD_BIT_TIMING_REG register - * TWAI FD bit-timing register - */ -#define TWAIFD_BIT_TIMING_REG (DR_REG_TWAIFD_BASE + 0x20) -/** TWAIFD_PROP : R/W; bitpos: [6:0]; default: 5; - * Configures the propagation segment of nominal bit rate.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_PROP 0x0000007FU -#define TWAIFD_PROP_M (TWAIFD_PROP_V << TWAIFD_PROP_S) -#define TWAIFD_PROP_V 0x0000007FU -#define TWAIFD_PROP_S 0 -/** TWAIFD_PH1 : R/W; bitpos: [12:7]; default: 3; - * Configures the phase 1 segment of nominal bit rate.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_PH1 0x0000003FU -#define TWAIFD_PH1_M (TWAIFD_PH1_V << TWAIFD_PH1_S) -#define TWAIFD_PH1_V 0x0000003FU -#define TWAIFD_PH1_S 7 -/** TWAIFD_PH2 : R/W; bitpos: [18:13]; default: 5; - * Configures the phase 2 segment of nominal bit rate.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_PH2 0x0000003FU -#define TWAIFD_PH2_M (TWAIFD_PH2_V << TWAIFD_PH2_S) -#define TWAIFD_PH2_V 0x0000003FU -#define TWAIFD_PH2_S 13 -/** TWAIFD_BRP : R/W; bitpos: [26:19]; default: 16; - * Configures the baud-rate prescaler of nominal bit rate.\\ - * Measurement unit: cycle of core clock. - */ -#define TWAIFD_BRP 0x000000FFU -#define TWAIFD_BRP_M (TWAIFD_BRP_V << TWAIFD_BRP_S) -#define TWAIFD_BRP_V 0x000000FFU -#define TWAIFD_BRP_S 19 -/** TWAIFD_SJW : R/W; bitpos: [31:27]; default: 2; - * Represents the synchronization jump width in nominal bit time.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_SJW 0x0000001FU -#define TWAIFD_SJW_M (TWAIFD_SJW_V << TWAIFD_SJW_S) -#define TWAIFD_SJW_V 0x0000001FU -#define TWAIFD_SJW_S 27 - -/** TWAIFD_BIT_TIMEING_FD_REG register - * TWAI FD bit-timing of FD register - */ -#define TWAIFD_BIT_TIMEING_FD_REG (DR_REG_TWAIFD_BASE + 0x24) -/** TWAIFD_PROP_FD : R/W; bitpos: [5:0]; default: 3; - * Configures the propagation segment of data bit rate.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_PROP_FD 0x0000003FU -#define TWAIFD_PROP_FD_M (TWAIFD_PROP_FD_V << TWAIFD_PROP_FD_S) -#define TWAIFD_PROP_FD_V 0x0000003FU -#define TWAIFD_PROP_FD_S 0 -/** TWAIFD_PH1_FD : R/W; bitpos: [11:7]; default: 3; - * Configures the phase 1 segment of data bit rate.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_PH1_FD 0x0000001FU -#define TWAIFD_PH1_FD_M (TWAIFD_PH1_FD_V << TWAIFD_PH1_FD_S) -#define TWAIFD_PH1_FD_V 0x0000001FU -#define TWAIFD_PH1_FD_S 7 -/** TWAIFD_PH2_FD : R/W; bitpos: [17:13]; default: 3; - * Configures the phase 2 segment of data bit rate.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_PH2_FD 0x0000001FU -#define TWAIFD_PH2_FD_M (TWAIFD_PH2_FD_V << TWAIFD_PH2_FD_S) -#define TWAIFD_PH2_FD_V 0x0000001FU -#define TWAIFD_PH2_FD_S 13 -/** TWAIFD_BRP_FD : R/W; bitpos: [26:19]; default: 4; - * Configures the baud-rate prescaler of data bit rate.\\ - * Measurement unit: cycle of core clock. - */ -#define TWAIFD_BRP_FD 0x000000FFU -#define TWAIFD_BRP_FD_M (TWAIFD_BRP_FD_V << TWAIFD_BRP_FD_S) -#define TWAIFD_BRP_FD_V 0x000000FFU -#define TWAIFD_BRP_FD_S 19 -/** TWAIFD_SJW_FD : R/W; bitpos: [31:27]; default: 2; - * Represents the synchronization jump width in data bit time.\\ - * Measurement unit: time quanta\\ - */ -#define TWAIFD_SJW_FD 0x0000001FU -#define TWAIFD_SJW_FD_M (TWAIFD_SJW_FD_V << TWAIFD_SJW_FD_S) -#define TWAIFD_SJW_FD_V 0x0000001FU -#define TWAIFD_SJW_FD_S 27 - -/** TWAIFD_ERR_TH_STAT_REG register - * TWAI FD error threshold and status register - */ -#define TWAIFD_ERR_TH_STAT_REG (DR_REG_TWAIFD_BASE + 0x28) -/** TWAIFD_ERR_WARNING_THRES : R/W; bitpos: [7:0]; default: 96; - * Configures the error warning threshold.\\ - */ -#define TWAIFD_ERR_WARNING_THRES 0x000000FFU -#define TWAIFD_ERR_WARNING_THRES_M (TWAIFD_ERR_WARNING_THRES_V << TWAIFD_ERR_WARNING_THRES_S) -#define TWAIFD_ERR_WARNING_THRES_V 0x000000FFU -#define TWAIFD_ERR_WARNING_THRES_S 0 -/** TWAIFD_ERR_PASSIVE_THRES : R/W; bitpos: [15:8]; default: 128; - * Configures the error passive threshold.\\ - */ -#define TWAIFD_ERR_PASSIVE_THRES 0x000000FFU -#define TWAIFD_ERR_PASSIVE_THRES_M (TWAIFD_ERR_PASSIVE_THRES_V << TWAIFD_ERR_PASSIVE_THRES_S) -#define TWAIFD_ERR_PASSIVE_THRES_V 0x000000FFU -#define TWAIFD_ERR_PASSIVE_THRES_S 8 -/** TWAIFD_ERR_ACTIVE : RO; bitpos: [16]; default: 1; - * Represents the fault state of error active.\\ - */ -#define TWAIFD_ERR_ACTIVE (BIT(16)) -#define TWAIFD_ERR_ACTIVE_M (TWAIFD_ERR_ACTIVE_V << TWAIFD_ERR_ACTIVE_S) -#define TWAIFD_ERR_ACTIVE_V 0x00000001U -#define TWAIFD_ERR_ACTIVE_S 16 -/** TWAIFD_ERR_PASSIVE : RO; bitpos: [17]; default: 0; - * Represents the fault state of error passive.\\ - */ -#define TWAIFD_ERR_PASSIVE (BIT(17)) -#define TWAIFD_ERR_PASSIVE_M (TWAIFD_ERR_PASSIVE_V << TWAIFD_ERR_PASSIVE_S) -#define TWAIFD_ERR_PASSIVE_V 0x00000001U -#define TWAIFD_ERR_PASSIVE_S 17 -/** TWAIFD_BUS_OFF : RO; bitpos: [18]; default: 0; - * Represents the fault state of bus off.\\ - */ -#define TWAIFD_BUS_OFF (BIT(18)) -#define TWAIFD_BUS_OFF_M (TWAIFD_BUS_OFF_V << TWAIFD_BUS_OFF_S) -#define TWAIFD_BUS_OFF_V 0x00000001U -#define TWAIFD_BUS_OFF_S 18 - -/** TWAIFD_ERROR_COUNTERS_REG register - * TWAI FD error counters status register - */ -#define TWAIFD_ERROR_COUNTERS_REG (DR_REG_TWAIFD_BASE + 0x2c) -/** TWAIFD_RXC_VAL : RO; bitpos: [15:0]; default: 0; - * Represents the receiver error counter value.\\ - */ -#define TWAIFD_RXC_VAL 0x0000FFFFU -#define TWAIFD_RXC_VAL_M (TWAIFD_RXC_VAL_V << TWAIFD_RXC_VAL_S) -#define TWAIFD_RXC_VAL_V 0x0000FFFFU -#define TWAIFD_RXC_VAL_S 0 -/** TWAIFD_TXC_VAL : RO; bitpos: [31:16]; default: 0; - * Represents the transmitter error counter value.\\ - */ -#define TWAIFD_TXC_VAL 0x0000FFFFU -#define TWAIFD_TXC_VAL_M (TWAIFD_TXC_VAL_V << TWAIFD_TXC_VAL_S) -#define TWAIFD_TXC_VAL_V 0x0000FFFFU -#define TWAIFD_TXC_VAL_S 16 - -/** TWAIFD_ERROR_COUNTERS_SP_REG register - * TWAI FD special error counters status register - */ -#define TWAIFD_ERROR_COUNTERS_SP_REG (DR_REG_TWAIFD_BASE + 0x30) -/** TWAIFD_ERR_FD_VAL : RO; bitpos: [15:0]; default: 0; - * Represents the number of error in the data bit time.\\ - */ -#define TWAIFD_ERR_FD_VAL 0x0000FFFFU -#define TWAIFD_ERR_FD_VAL_M (TWAIFD_ERR_FD_VAL_V << TWAIFD_ERR_FD_VAL_S) -#define TWAIFD_ERR_FD_VAL_V 0x0000FFFFU -#define TWAIFD_ERR_FD_VAL_S 0 -/** TWAIFD_ERR_NORM_VAL : RO; bitpos: [31:16]; default: 0; - * Represents the number of error in the nominal bit time.\\ - */ -#define TWAIFD_ERR_NORM_VAL 0x0000FFFFU -#define TWAIFD_ERR_NORM_VAL_M (TWAIFD_ERR_NORM_VAL_V << TWAIFD_ERR_NORM_VAL_S) -#define TWAIFD_ERR_NORM_VAL_V 0x0000FFFFU -#define TWAIFD_ERR_NORM_VAL_S 16 - -/** TWAIFD_CTR_PRES_REG register - * TWAI FD error counters pre-define configuration register - */ -#define TWAIFD_CTR_PRES_REG (DR_REG_TWAIFD_BASE + 0x34) -/** TWAIFD_CTR_PRES_VAL : WO; bitpos: [8:0]; default: 0; - * Configures the pre-defined value to set the error counter.\\ - */ -#define TWAIFD_CTR_PRES_VAL 0x000001FFU -#define TWAIFD_CTR_PRES_VAL_M (TWAIFD_CTR_PRES_VAL_V << TWAIFD_CTR_PRES_VAL_S) -#define TWAIFD_CTR_PRES_VAL_V 0x000001FFU -#define TWAIFD_CTR_PRES_VAL_S 0 -/** TWAIFD_PTX : WT; bitpos: [9]; default: 0; - * Configures whether or not to set the receiver error counter into the value of - * pre-defined value.\\ - * 0: invalid\\ - * 1: set\\ - */ -#define TWAIFD_PTX (BIT(9)) -#define TWAIFD_PTX_M (TWAIFD_PTX_V << TWAIFD_PTX_S) -#define TWAIFD_PTX_V 0x00000001U -#define TWAIFD_PTX_S 9 -/** TWAIFD_PRX : WT; bitpos: [10]; default: 0; - * Configures whether or not to set the transmitter error counter into the value of - * pre-defined value.\\ - * 0: invalid\\ - * 1: set\\ - */ -#define TWAIFD_PRX (BIT(10)) -#define TWAIFD_PRX_M (TWAIFD_PRX_V << TWAIFD_PRX_S) -#define TWAIFD_PRX_V 0x00000001U -#define TWAIFD_PRX_S 10 -/** TWAIFD_ENORM : WO; bitpos: [11]; default: 0; - * Configures whether or not to erase the error counter of nominal bit time.\\ - * 0: invalid\\ - * 1: erase\\ - */ -#define TWAIFD_ENORM (BIT(11)) -#define TWAIFD_ENORM_M (TWAIFD_ENORM_V << TWAIFD_ENORM_S) -#define TWAIFD_ENORM_V 0x00000001U -#define TWAIFD_ENORM_S 11 -/** TWAIFD_EFD : WO; bitpos: [12]; default: 0; - * Configures whether or not to erase the error counter of data bit time.\\ - * 0: invalid\\ - * 1: erase\\ - */ -#define TWAIFD_EFD (BIT(12)) -#define TWAIFD_EFD_M (TWAIFD_EFD_V << TWAIFD_EFD_S) -#define TWAIFD_EFD_V 0x00000001U -#define TWAIFD_EFD_S 12 - -/** TWAIFD_RX_MEM_INFO_REG register - * TWAI FD rx memory information register - */ -#define TWAIFD_RX_MEM_INFO_REG (DR_REG_TWAIFD_BASE + 0x38) -/** TWAIFD_RX_BUFF_SIZE_VAL : RO; bitpos: [12:0]; default: 0; - * Represents the size of RX buffer.\\ - */ -#define TWAIFD_RX_BUFF_SIZE_VAL 0x00001FFFU -#define TWAIFD_RX_BUFF_SIZE_VAL_M (TWAIFD_RX_BUFF_SIZE_VAL_V << TWAIFD_RX_BUFF_SIZE_VAL_S) -#define TWAIFD_RX_BUFF_SIZE_VAL_V 0x00001FFFU -#define TWAIFD_RX_BUFF_SIZE_VAL_S 0 -/** TWAIFD_RX_FREE_CTR : RO; bitpos: [28:16]; default: 0; - * Represents the number of free words in RX buffer.\\ - */ -#define TWAIFD_RX_FREE_CTR 0x00001FFFU -#define TWAIFD_RX_FREE_CTR_M (TWAIFD_RX_FREE_CTR_V << TWAIFD_RX_FREE_CTR_S) -#define TWAIFD_RX_FREE_CTR_V 0x00001FFFU -#define TWAIFD_RX_FREE_CTR_S 16 - -/** TWAIFD_RX_POINTERS_REG register - * TWAI FD rx memory pointer information register - */ -#define TWAIFD_RX_POINTERS_REG (DR_REG_TWAIFD_BASE + 0x3c) -/** TWAIFD_RX_WPT_VAL : RO; bitpos: [11:0]; default: 0; - * Represents the write pointer position in RX buffer.\\ - */ -#define TWAIFD_RX_WPT_VAL 0x00000FFFU -#define TWAIFD_RX_WPT_VAL_M (TWAIFD_RX_WPT_VAL_V << TWAIFD_RX_WPT_VAL_S) -#define TWAIFD_RX_WPT_VAL_V 0x00000FFFU -#define TWAIFD_RX_WPT_VAL_S 0 -/** TWAIFD_RX_RPT_VAL : RO; bitpos: [27:16]; default: 0; - * Represents the read pointer position in RX buffer.\\ - */ -#define TWAIFD_RX_RPT_VAL 0x00000FFFU -#define TWAIFD_RX_RPT_VAL_M (TWAIFD_RX_RPT_VAL_V << TWAIFD_RX_RPT_VAL_S) -#define TWAIFD_RX_RPT_VAL_V 0x00000FFFU -#define TWAIFD_RX_RPT_VAL_S 16 - -/** TWAIFD_RX_STATUS_SETTING_REG register - * TWAI FD tx status & setting register - */ -#define TWAIFD_RX_STATUS_SETTING_REG (DR_REG_TWAIFD_BASE + 0x40) -/** TWAIFD_RX_EMPTY : RO; bitpos: [0]; default: 0; - * Represents whether or not the RX buffer is empty.\\ - * 0: not empty\\ - * 1: empty\\ - */ -#define TWAIFD_RX_EMPTY (BIT(0)) -#define TWAIFD_RX_EMPTY_M (TWAIFD_RX_EMPTY_V << TWAIFD_RX_EMPTY_S) -#define TWAIFD_RX_EMPTY_V 0x00000001U -#define TWAIFD_RX_EMPTY_S 0 -/** TWAIFD_RX_FULL : RO; bitpos: [1]; default: 0; - * Represents whether or not the RX buffer is full.\\ - * 0: not full\\ - * 1: full\\ - */ -#define TWAIFD_RX_FULL (BIT(1)) -#define TWAIFD_RX_FULL_M (TWAIFD_RX_FULL_V << TWAIFD_RX_FULL_S) -#define TWAIFD_RX_FULL_V 0x00000001U -#define TWAIFD_RX_FULL_S 1 -/** TWAIFD_RX_FRM_CTR : RO; bitpos: [14:4]; default: 0; - * Represents the number of received frame in RX buffer.\\ - */ -#define TWAIFD_RX_FRM_CTR 0x000007FFU -#define TWAIFD_RX_FRM_CTR_M (TWAIFD_RX_FRM_CTR_V << TWAIFD_RX_FRM_CTR_S) -#define TWAIFD_RX_FRM_CTR_V 0x000007FFU -#define TWAIFD_RX_FRM_CTR_S 4 -/** TWAIFD_RTSOP : R/W; bitpos: [16]; default: 0; - * a\\ - */ -#define TWAIFD_RTSOP (BIT(16)) -#define TWAIFD_RTSOP_M (TWAIFD_RTSOP_V << TWAIFD_RTSOP_S) -#define TWAIFD_RTSOP_V 0x00000001U -#define TWAIFD_RTSOP_S 16 - -/** TWAIFD_RX_DATA_REG register - * TWAI FD received data register - */ -#define TWAIFD_RX_DATA_REG (DR_REG_TWAIFD_BASE + 0x44) -/** TWAIFD_RX_DATA : RO; bitpos: [31:0]; default: 0; - * Data received. - */ -#define TWAIFD_RX_DATA 0xFFFFFFFFU -#define TWAIFD_RX_DATA_M (TWAIFD_RX_DATA_V << TWAIFD_RX_DATA_S) -#define TWAIFD_RX_DATA_V 0xFFFFFFFFU -#define TWAIFD_RX_DATA_S 0 - -/** TWAIFD_FILTER_A_MASK_REG register - * TWAI FD filter A mask value register - */ -#define TWAIFD_FILTER_A_MASK_REG (DR_REG_TWAIFD_BASE + 0x60) -/** TWAIFD_BIT_MASK_A : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ -#define TWAIFD_BIT_MASK_A 0x1FFFFFFFU -#define TWAIFD_BIT_MASK_A_M (TWAIFD_BIT_MASK_A_V << TWAIFD_BIT_MASK_A_S) -#define TWAIFD_BIT_MASK_A_V 0x1FFFFFFFU -#define TWAIFD_BIT_MASK_A_S 0 - -/** TWAIFD_FILTER_A_VAL_REG register - * TWAI FD filter A bit value register - */ -#define TWAIFD_FILTER_A_VAL_REG (DR_REG_TWAIFD_BASE + 0x64) -/** TWAIFD_BIT_VAL_A : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ -#define TWAIFD_BIT_VAL_A 0x1FFFFFFFU -#define TWAIFD_BIT_VAL_A_M (TWAIFD_BIT_VAL_A_V << TWAIFD_BIT_VAL_A_S) -#define TWAIFD_BIT_VAL_A_V 0x1FFFFFFFU -#define TWAIFD_BIT_VAL_A_S 0 - -/** TWAIFD_FILTER_B_MASK_REG register - * TWAI FD filter B mask value register - */ -#define TWAIFD_FILTER_B_MASK_REG (DR_REG_TWAIFD_BASE + 0x68) -/** TWAIFD_BIT_MASK_B : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ -#define TWAIFD_BIT_MASK_B 0x1FFFFFFFU -#define TWAIFD_BIT_MASK_B_M (TWAIFD_BIT_MASK_B_V << TWAIFD_BIT_MASK_B_S) -#define TWAIFD_BIT_MASK_B_V 0x1FFFFFFFU -#define TWAIFD_BIT_MASK_B_S 0 - -/** TWAIFD_FILTER_B_VAL_REG register - * TWAI FD filter B bit value register - */ -#define TWAIFD_FILTER_B_VAL_REG (DR_REG_TWAIFD_BASE + 0x6c) -/** TWAIFD_BIT_VAL_B : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ -#define TWAIFD_BIT_VAL_B 0x1FFFFFFFU -#define TWAIFD_BIT_VAL_B_M (TWAIFD_BIT_VAL_B_V << TWAIFD_BIT_VAL_B_S) -#define TWAIFD_BIT_VAL_B_V 0x1FFFFFFFU -#define TWAIFD_BIT_VAL_B_S 0 - -/** TWAIFD_FILTER_C_MASK_REG register - * TWAI FD filter C mask value register - */ -#define TWAIFD_FILTER_C_MASK_REG (DR_REG_TWAIFD_BASE + 0x70) -/** TWAIFD_BIT_MASK_C : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ -#define TWAIFD_BIT_MASK_C 0x1FFFFFFFU -#define TWAIFD_BIT_MASK_C_M (TWAIFD_BIT_MASK_C_V << TWAIFD_BIT_MASK_C_S) -#define TWAIFD_BIT_MASK_C_V 0x1FFFFFFFU -#define TWAIFD_BIT_MASK_C_S 0 - -/** TWAIFD_FILTER_C_VAL_REG register - * TWAI FD filter C bit value register - */ -#define TWAIFD_FILTER_C_VAL_REG (DR_REG_TWAIFD_BASE + 0x74) -/** TWAIFD_BIT_VAL_C : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ -#define TWAIFD_BIT_VAL_C 0x1FFFFFFFU -#define TWAIFD_BIT_VAL_C_M (TWAIFD_BIT_VAL_C_V << TWAIFD_BIT_VAL_C_S) -#define TWAIFD_BIT_VAL_C_V 0x1FFFFFFFU -#define TWAIFD_BIT_VAL_C_S 0 - -/** TWAIFD_FILTER_RAN_LOW_REG register - * TWAI FD filter range low value register - */ -#define TWAIFD_FILTER_RAN_LOW_REG (DR_REG_TWAIFD_BASE + 0x78) -/** TWAIFD_BIT_RAN_LOW : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ -#define TWAIFD_BIT_RAN_LOW 0x1FFFFFFFU -#define TWAIFD_BIT_RAN_LOW_M (TWAIFD_BIT_RAN_LOW_V << TWAIFD_BIT_RAN_LOW_S) -#define TWAIFD_BIT_RAN_LOW_V 0x1FFFFFFFU -#define TWAIFD_BIT_RAN_LOW_S 0 - -/** TWAIFD_FILTER_RAN_HIGH_REG register - * TWAI FD filter range high value register - */ -#define TWAIFD_FILTER_RAN_HIGH_REG (DR_REG_TWAIFD_BASE + 0x7c) -/** TWAIFD_BIT_RAN_HIGH : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ -#define TWAIFD_BIT_RAN_HIGH 0x1FFFFFFFU -#define TWAIFD_BIT_RAN_HIGH_M (TWAIFD_BIT_RAN_HIGH_V << TWAIFD_BIT_RAN_HIGH_S) -#define TWAIFD_BIT_RAN_HIGH_V 0x1FFFFFFFU -#define TWAIFD_BIT_RAN_HIGH_S 0 - -/** TWAIFD_FILTER_CONTROL_REG register - * TWAI FD filter control register - */ -#define TWAIFD_FILTER_CONTROL_REG (DR_REG_TWAIFD_BASE + 0x80) -/** TWAIFD_FANB : R/W; bitpos: [0]; default: 1; - * filter A with nominal and base mode. - */ -#define TWAIFD_FANB (BIT(0)) -#define TWAIFD_FANB_M (TWAIFD_FANB_V << TWAIFD_FANB_S) -#define TWAIFD_FANB_V 0x00000001U -#define TWAIFD_FANB_S 0 -/** TWAIFD_FANE : R/W; bitpos: [1]; default: 1; - * filter A with nominal and extended mode. - */ -#define TWAIFD_FANE (BIT(1)) -#define TWAIFD_FANE_M (TWAIFD_FANE_V << TWAIFD_FANE_S) -#define TWAIFD_FANE_V 0x00000001U -#define TWAIFD_FANE_S 1 -/** TWAIFD_FAFB : R/W; bitpos: [2]; default: 1; - * filter A with FD and base mode. - */ -#define TWAIFD_FAFB (BIT(2)) -#define TWAIFD_FAFB_M (TWAIFD_FAFB_V << TWAIFD_FAFB_S) -#define TWAIFD_FAFB_V 0x00000001U -#define TWAIFD_FAFB_S 2 -/** TWAIFD_FAFE : R/W; bitpos: [3]; default: 1; - * filter A with FD and extended mode. - */ -#define TWAIFD_FAFE (BIT(3)) -#define TWAIFD_FAFE_M (TWAIFD_FAFE_V << TWAIFD_FAFE_S) -#define TWAIFD_FAFE_V 0x00000001U -#define TWAIFD_FAFE_S 3 -/** TWAIFD_FBNB : R/W; bitpos: [4]; default: 0; - * filter B with nominal and base mode. - */ -#define TWAIFD_FBNB (BIT(4)) -#define TWAIFD_FBNB_M (TWAIFD_FBNB_V << TWAIFD_FBNB_S) -#define TWAIFD_FBNB_V 0x00000001U -#define TWAIFD_FBNB_S 4 -/** TWAIFD_FBNE : R/W; bitpos: [5]; default: 0; - * filter B with nominal and extended mode. - */ -#define TWAIFD_FBNE (BIT(5)) -#define TWAIFD_FBNE_M (TWAIFD_FBNE_V << TWAIFD_FBNE_S) -#define TWAIFD_FBNE_V 0x00000001U -#define TWAIFD_FBNE_S 5 -/** TWAIFD_FBFB : R/W; bitpos: [6]; default: 0; - * filter B with FD and base mode. - */ -#define TWAIFD_FBFB (BIT(6)) -#define TWAIFD_FBFB_M (TWAIFD_FBFB_V << TWAIFD_FBFB_S) -#define TWAIFD_FBFB_V 0x00000001U -#define TWAIFD_FBFB_S 6 -/** TWAIFD_FBFE : R/W; bitpos: [7]; default: 0; - * filter B with FD and extended mode. - */ -#define TWAIFD_FBFE (BIT(7)) -#define TWAIFD_FBFE_M (TWAIFD_FBFE_V << TWAIFD_FBFE_S) -#define TWAIFD_FBFE_V 0x00000001U -#define TWAIFD_FBFE_S 7 -/** TWAIFD_FCNB : R/W; bitpos: [8]; default: 0; - * filter C with nominal and base mode. - */ -#define TWAIFD_FCNB (BIT(8)) -#define TWAIFD_FCNB_M (TWAIFD_FCNB_V << TWAIFD_FCNB_S) -#define TWAIFD_FCNB_V 0x00000001U -#define TWAIFD_FCNB_S 8 -/** TWAIFD_FCNE : R/W; bitpos: [9]; default: 0; - * filter C with nominal and extended mode. - */ -#define TWAIFD_FCNE (BIT(9)) -#define TWAIFD_FCNE_M (TWAIFD_FCNE_V << TWAIFD_FCNE_S) -#define TWAIFD_FCNE_V 0x00000001U -#define TWAIFD_FCNE_S 9 -/** TWAIFD_FCFB : R/W; bitpos: [10]; default: 0; - * filter C with FD and base mode. - */ -#define TWAIFD_FCFB (BIT(10)) -#define TWAIFD_FCFB_M (TWAIFD_FCFB_V << TWAIFD_FCFB_S) -#define TWAIFD_FCFB_V 0x00000001U -#define TWAIFD_FCFB_S 10 -/** TWAIFD_FCFE : R/W; bitpos: [11]; default: 0; - * filter C with FD and extended mode. - */ -#define TWAIFD_FCFE (BIT(11)) -#define TWAIFD_FCFE_M (TWAIFD_FCFE_V << TWAIFD_FCFE_S) -#define TWAIFD_FCFE_V 0x00000001U -#define TWAIFD_FCFE_S 11 -/** TWAIFD_FRNB : R/W; bitpos: [12]; default: 0; - * filter range with nominal and base mode. - */ -#define TWAIFD_FRNB (BIT(12)) -#define TWAIFD_FRNB_M (TWAIFD_FRNB_V << TWAIFD_FRNB_S) -#define TWAIFD_FRNB_V 0x00000001U -#define TWAIFD_FRNB_S 12 -/** TWAIFD_FRNE : R/W; bitpos: [13]; default: 0; - * filter range with nominal and extended mode. - */ -#define TWAIFD_FRNE (BIT(13)) -#define TWAIFD_FRNE_M (TWAIFD_FRNE_V << TWAIFD_FRNE_S) -#define TWAIFD_FRNE_V 0x00000001U -#define TWAIFD_FRNE_S 13 -/** TWAIFD_FRFB : R/W; bitpos: [14]; default: 0; - * filter range with FD and base mode. - */ -#define TWAIFD_FRFB (BIT(14)) -#define TWAIFD_FRFB_M (TWAIFD_FRFB_V << TWAIFD_FRFB_S) -#define TWAIFD_FRFB_V 0x00000001U -#define TWAIFD_FRFB_S 14 -/** TWAIFD_FRFE : R/W; bitpos: [15]; default: 0; - * filter range with FD and extended mode. - */ -#define TWAIFD_FRFE (BIT(15)) -#define TWAIFD_FRFE_M (TWAIFD_FRFE_V << TWAIFD_FRFE_S) -#define TWAIFD_FRFE_V 0x00000001U -#define TWAIFD_FRFE_S 15 -/** TWAIFD_SFA : RO; bitpos: [16]; default: 0; - * filter A status - */ -#define TWAIFD_SFA (BIT(16)) -#define TWAIFD_SFA_M (TWAIFD_SFA_V << TWAIFD_SFA_S) -#define TWAIFD_SFA_V 0x00000001U -#define TWAIFD_SFA_S 16 -/** TWAIFD_SFB : RO; bitpos: [17]; default: 0; - * filter B status - */ -#define TWAIFD_SFB (BIT(17)) -#define TWAIFD_SFB_M (TWAIFD_SFB_V << TWAIFD_SFB_S) -#define TWAIFD_SFB_V 0x00000001U -#define TWAIFD_SFB_S 17 -/** TWAIFD_SFC : RO; bitpos: [18]; default: 0; - * filter C status - */ -#define TWAIFD_SFC (BIT(18)) -#define TWAIFD_SFC_M (TWAIFD_SFC_V << TWAIFD_SFC_S) -#define TWAIFD_SFC_V 0x00000001U -#define TWAIFD_SFC_S 18 -/** TWAIFD_SFR : RO; bitpos: [19]; default: 0; - * filter range status - */ -#define TWAIFD_SFR (BIT(19)) -#define TWAIFD_SFR_M (TWAIFD_SFR_V << TWAIFD_SFR_S) -#define TWAIFD_SFR_V 0x00000001U -#define TWAIFD_SFR_S 19 - -/** TWAIFD_TX_STAT_REG register - * TWAI FD TX buffer status register - */ -#define TWAIFD_TX_STAT_REG (DR_REG_TWAIFD_BASE + 0x94) -/** TWAIFD_TXT_1_EMPTY : RO; bitpos: [0]; default: 0; - * Represents whether or not the TX buffer1 is empty.\\ - * 0: not empty\\ - * 1: empty\\ - */ -#define TWAIFD_TXT_1_EMPTY (BIT(0)) -#define TWAIFD_TXT_1_EMPTY_M (TWAIFD_TXT_1_EMPTY_V << TWAIFD_TXT_1_EMPTY_S) -#define TWAIFD_TXT_1_EMPTY_V 0x00000001U -#define TWAIFD_TXT_1_EMPTY_S 0 -/** TWAIFD_TXT_2_EMPTY : RO; bitpos: [1]; default: 0; - * Represents whether or not the TX buffer2 is empty.\\ - * 0: not empty\\ - * 1: empty\\ - */ -#define TWAIFD_TXT_2_EMPTY (BIT(1)) -#define TWAIFD_TXT_2_EMPTY_M (TWAIFD_TXT_2_EMPTY_V << TWAIFD_TXT_2_EMPTY_S) -#define TWAIFD_TXT_2_EMPTY_V 0x00000001U -#define TWAIFD_TXT_2_EMPTY_S 1 - -/** TWAIFD_TX_CFG_REG register - * TWAI FD TX buffer configuration register - */ -#define TWAIFD_TX_CFG_REG (DR_REG_TWAIFD_BASE + 0x98) -/** TWAIFD_TXT_1_ALLOW : R/W; bitpos: [0]; default: 1; - * Configures whether or not allow transmitting frames from TX buffer1.\\ - * 0: not allow\\ - * 1: allow\\ - */ -#define TWAIFD_TXT_1_ALLOW (BIT(0)) -#define TWAIFD_TXT_1_ALLOW_M (TWAIFD_TXT_1_ALLOW_V << TWAIFD_TXT_1_ALLOW_S) -#define TWAIFD_TXT_1_ALLOW_V 0x00000001U -#define TWAIFD_TXT_1_ALLOW_S 0 -/** TWAIFD_TXT_2_ALLOW : R/W; bitpos: [1]; default: 1; - * Configures whether or not allow transmitting frames from TX buffer2.\\ - * 0: not allow\\ - * 1: allow\\ - */ -#define TWAIFD_TXT_2_ALLOW (BIT(1)) -#define TWAIFD_TXT_2_ALLOW_M (TWAIFD_TXT_2_ALLOW_V << TWAIFD_TXT_2_ALLOW_S) -#define TWAIFD_TXT_2_ALLOW_V 0x00000001U -#define TWAIFD_TXT_2_ALLOW_S 1 -/** TWAIFD_TXT_1_COMMIT : WT; bitpos: [2]; default: 0; - * Configures whether or not the frames from TX register are inserted into TX - * buffer1.\\ - * 0: not inserted\\ - * 1: inserted\\ - */ -#define TWAIFD_TXT_1_COMMIT (BIT(2)) -#define TWAIFD_TXT_1_COMMIT_M (TWAIFD_TXT_1_COMMIT_V << TWAIFD_TXT_1_COMMIT_S) -#define TWAIFD_TXT_1_COMMIT_V 0x00000001U -#define TWAIFD_TXT_1_COMMIT_S 2 -/** TWAIFD_TXT_2_COMMIT : WT; bitpos: [3]; default: 0; - * Configures whether or not the frames from TX register are inserted into TX - * buffer2.\\ - * 0: not inserted\\ - * 1: inserted\\ - */ -#define TWAIFD_TXT_2_COMMIT (BIT(3)) -#define TWAIFD_TXT_2_COMMIT_M (TWAIFD_TXT_2_COMMIT_V << TWAIFD_TXT_2_COMMIT_S) -#define TWAIFD_TXT_2_COMMIT_V 0x00000001U -#define TWAIFD_TXT_2_COMMIT_S 3 - -/** TWAIFD_TX_DATA_0_REG register - * TWAI FD transmit data register 0 - */ -#define TWAIFD_TX_DATA_0_REG (DR_REG_TWAIFD_BASE + 0x9c) -/** TWAIFD_DLC_TX : R/W; bitpos: [3:0]; default: 0; - * Configures the brs to be transmitted. - */ -#define TWAIFD_DLC_TX 0x0000000FU -#define TWAIFD_DLC_TX_M (TWAIFD_DLC_TX_V << TWAIFD_DLC_TX_S) -#define TWAIFD_DLC_TX_V 0x0000000FU -#define TWAIFD_DLC_TX_S 0 -/** TWAIFD_RTR_TX : R/W; bitpos: [5]; default: 0; - * Configures the rtr bit to be transmitted. - */ -#define TWAIFD_RTR_TX (BIT(5)) -#define TWAIFD_RTR_TX_M (TWAIFD_RTR_TX_V << TWAIFD_RTR_TX_S) -#define TWAIFD_RTR_TX_V 0x00000001U -#define TWAIFD_RTR_TX_S 5 -/** TWAIFD_ID_TYPE_TX : R/W; bitpos: [6]; default: 0; - * Configures the frame type to be transmitted. - */ -#define TWAIFD_ID_TYPE_TX (BIT(6)) -#define TWAIFD_ID_TYPE_TX_M (TWAIFD_ID_TYPE_TX_V << TWAIFD_ID_TYPE_TX_S) -#define TWAIFD_ID_TYPE_TX_V 0x00000001U -#define TWAIFD_ID_TYPE_TX_S 6 -/** TWAIFD_FR_TYPE_TX : R/W; bitpos: [7]; default: 0; - * Configures the fd type to be transmitted. - */ -#define TWAIFD_FR_TYPE_TX (BIT(7)) -#define TWAIFD_FR_TYPE_TX_M (TWAIFD_FR_TYPE_TX_V << TWAIFD_FR_TYPE_TX_S) -#define TWAIFD_FR_TYPE_TX_V 0x00000001U -#define TWAIFD_FR_TYPE_TX_S 7 -/** TWAIFD_TBF_TX : R/W; bitpos: [8]; default: 0; - * Configures the tbf bit to be transmitted. - */ -#define TWAIFD_TBF_TX (BIT(8)) -#define TWAIFD_TBF_TX_M (TWAIFD_TBF_TX_V << TWAIFD_TBF_TX_S) -#define TWAIFD_TBF_TX_V 0x00000001U -#define TWAIFD_TBF_TX_S 8 -/** TWAIFD_BRS_TX : R/W; bitpos: [9]; default: 0; - * Configures the brs bit to be transmitted. - */ -#define TWAIFD_BRS_TX (BIT(9)) -#define TWAIFD_BRS_TX_M (TWAIFD_BRS_TX_V << TWAIFD_BRS_TX_S) -#define TWAIFD_BRS_TX_V 0x00000001U -#define TWAIFD_BRS_TX_S 9 - -/** TWAIFD_TX_DATA_1_REG register - * TWAI FD transmit data register 1 - */ -#define TWAIFD_TX_DATA_1_REG (DR_REG_TWAIFD_BASE + 0xa0) -/** TWAIFD_TS_VAL_U_TX : R/W; bitpos: [31:0]; default: 0; - * Configures the upper timestamp to be transmitted - */ -#define TWAIFD_TS_VAL_U_TX 0xFFFFFFFFU -#define TWAIFD_TS_VAL_U_TX_M (TWAIFD_TS_VAL_U_TX_V << TWAIFD_TS_VAL_U_TX_S) -#define TWAIFD_TS_VAL_U_TX_V 0xFFFFFFFFU -#define TWAIFD_TS_VAL_U_TX_S 0 - -/** TWAIFD_TX_DATA_2_REG register - * TWAI FD transmit data register 2 - */ -#define TWAIFD_TX_DATA_2_REG (DR_REG_TWAIFD_BASE + 0xa4) -/** TWAIFD_TS_VAL_L_TX : R/W; bitpos: [31:0]; default: 0; - * Configures the lower timestamp to be transmitted - */ -#define TWAIFD_TS_VAL_L_TX 0xFFFFFFFFU -#define TWAIFD_TS_VAL_L_TX_M (TWAIFD_TS_VAL_L_TX_V << TWAIFD_TS_VAL_L_TX_S) -#define TWAIFD_TS_VAL_L_TX_V 0xFFFFFFFFU -#define TWAIFD_TS_VAL_L_TX_S 0 - -/** TWAIFD_TX_DATA_3_REG register - * TWAI FD transmit data register 3 - */ -#define TWAIFD_TX_DATA_3_REG (DR_REG_TWAIFD_BASE + 0xa8) -/** TWAIFD_ID_EXT_TX : R/W; bitpos: [17:0]; default: 0; - * Configures the base ID to be transmitted - */ -#define TWAIFD_ID_EXT_TX 0x0003FFFFU -#define TWAIFD_ID_EXT_TX_M (TWAIFD_ID_EXT_TX_V << TWAIFD_ID_EXT_TX_S) -#define TWAIFD_ID_EXT_TX_V 0x0003FFFFU -#define TWAIFD_ID_EXT_TX_S 0 -/** TWAIFD_ID_BASE_TX : R/W; bitpos: [28:18]; default: 0; - * Configures the extended ID to be transmitted - */ -#define TWAIFD_ID_BASE_TX 0x000007FFU -#define TWAIFD_ID_BASE_TX_M (TWAIFD_ID_BASE_TX_V << TWAIFD_ID_BASE_TX_S) -#define TWAIFD_ID_BASE_TX_V 0x000007FFU -#define TWAIFD_ID_BASE_TX_S 18 - -/** TWAIFD_TX_DATA_4_REG register - * TWAI FD transmit data register 4 - */ -#define TWAIFD_TX_DATA_4_REG (DR_REG_TWAIFD_BASE + 0xac) -/** TWAIFD_TX_DATA0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th word to be transmitted - */ -#define TWAIFD_TX_DATA0 0xFFFFFFFFU -#define TWAIFD_TX_DATA0_M (TWAIFD_TX_DATA0_V << TWAIFD_TX_DATA0_S) -#define TWAIFD_TX_DATA0_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA0_S 0 - -/** TWAIFD_TX_DATA_5_REG register - * TWAI FD transmit data register 5 - */ -#define TWAIFD_TX_DATA_5_REG (DR_REG_TWAIFD_BASE + 0xb0) -/** TWAIFD_TX_DATA1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th word to be transmitted - */ -#define TWAIFD_TX_DATA1 0xFFFFFFFFU -#define TWAIFD_TX_DATA1_M (TWAIFD_TX_DATA1_V << TWAIFD_TX_DATA1_S) -#define TWAIFD_TX_DATA1_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA1_S 0 - -/** TWAIFD_TX_DATA_6_REG register - * TWAI FD transmit data register 6 - */ -#define TWAIFD_TX_DATA_6_REG (DR_REG_TWAIFD_BASE + 0xb4) -/** TWAIFD_TX_DATA2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th word to be transmitted - */ -#define TWAIFD_TX_DATA2 0xFFFFFFFFU -#define TWAIFD_TX_DATA2_M (TWAIFD_TX_DATA2_V << TWAIFD_TX_DATA2_S) -#define TWAIFD_TX_DATA2_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA2_S 0 - -/** TWAIFD_TX_DATA_7_REG register - * TWAI FD transmit data register 7 - */ -#define TWAIFD_TX_DATA_7_REG (DR_REG_TWAIFD_BASE + 0xb8) -/** TWAIFD_TX_DATA3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3th word to be transmitted - */ -#define TWAIFD_TX_DATA3 0xFFFFFFFFU -#define TWAIFD_TX_DATA3_M (TWAIFD_TX_DATA3_V << TWAIFD_TX_DATA3_S) -#define TWAIFD_TX_DATA3_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA3_S 0 - -/** TWAIFD_TX_DATA_8_REG register - * TWAI FD transmit data register 8 - */ -#define TWAIFD_TX_DATA_8_REG (DR_REG_TWAIFD_BASE + 0xbc) -/** TWAIFD_TX_DATA4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th word to be transmitted - */ -#define TWAIFD_TX_DATA4 0xFFFFFFFFU -#define TWAIFD_TX_DATA4_M (TWAIFD_TX_DATA4_V << TWAIFD_TX_DATA4_S) -#define TWAIFD_TX_DATA4_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA4_S 0 - -/** TWAIFD_TX_DATA_9_REG register - * TWAI FD transmit data register 9 - */ -#define TWAIFD_TX_DATA_9_REG (DR_REG_TWAIFD_BASE + 0xc0) -/** TWAIFD_TX_DATA5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th word to be transmitted - */ -#define TWAIFD_TX_DATA5 0xFFFFFFFFU -#define TWAIFD_TX_DATA5_M (TWAIFD_TX_DATA5_V << TWAIFD_TX_DATA5_S) -#define TWAIFD_TX_DATA5_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA5_S 0 - -/** TWAIFD_TX_DATA_10_REG register - * TWAI FD transmit data register 10 - */ -#define TWAIFD_TX_DATA_10_REG (DR_REG_TWAIFD_BASE + 0xc4) -/** TWAIFD_TX_DATA6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th word to be transmitted - */ -#define TWAIFD_TX_DATA6 0xFFFFFFFFU -#define TWAIFD_TX_DATA6_M (TWAIFD_TX_DATA6_V << TWAIFD_TX_DATA6_S) -#define TWAIFD_TX_DATA6_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA6_S 0 - -/** TWAIFD_TX_DATA_11_REG register - * TWAI FD transmit data register 11 - */ -#define TWAIFD_TX_DATA_11_REG (DR_REG_TWAIFD_BASE + 0xc8) -/** TWAIFD_TX_DATA7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th word to be transmitted - */ -#define TWAIFD_TX_DATA7 0xFFFFFFFFU -#define TWAIFD_TX_DATA7_M (TWAIFD_TX_DATA7_V << TWAIFD_TX_DATA7_S) -#define TWAIFD_TX_DATA7_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA7_S 0 - -/** TWAIFD_TX_DATA_12_REG register - * TWAI FD transmit data register 12 - */ -#define TWAIFD_TX_DATA_12_REG (DR_REG_TWAIFD_BASE + 0xcc) -/** TWAIFD_TX_DATA8 : R/W; bitpos: [31:0]; default: 0; - * Configures the 8th word to be transmitted - */ -#define TWAIFD_TX_DATA8 0xFFFFFFFFU -#define TWAIFD_TX_DATA8_M (TWAIFD_TX_DATA8_V << TWAIFD_TX_DATA8_S) -#define TWAIFD_TX_DATA8_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA8_S 0 - -/** TWAIFD_TX_DATA_13_REG register - * TWAI FD transmit data register 13 - */ -#define TWAIFD_TX_DATA_13_REG (DR_REG_TWAIFD_BASE + 0xd0) -/** TWAIFD_TX_DATA9 : R/W; bitpos: [31:0]; default: 0; - * Configures the 9th word to be transmitted - */ -#define TWAIFD_TX_DATA9 0xFFFFFFFFU -#define TWAIFD_TX_DATA9_M (TWAIFD_TX_DATA9_V << TWAIFD_TX_DATA9_S) -#define TWAIFD_TX_DATA9_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA9_S 0 - -/** TWAIFD_TX_DATA_14_REG register - * TWAI FD transmit data register 14 - */ -#define TWAIFD_TX_DATA_14_REG (DR_REG_TWAIFD_BASE + 0xd4) -/** TWAIFD_TX_DATA10 : R/W; bitpos: [31:0]; default: 0; - * Configures the 10th word to be transmitted - */ -#define TWAIFD_TX_DATA10 0xFFFFFFFFU -#define TWAIFD_TX_DATA10_M (TWAIFD_TX_DATA10_V << TWAIFD_TX_DATA10_S) -#define TWAIFD_TX_DATA10_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA10_S 0 - -/** TWAIFD_TX_DATA_15_REG register - * TWAI FD transmit data register 15 - */ -#define TWAIFD_TX_DATA_15_REG (DR_REG_TWAIFD_BASE + 0xd8) -/** TWAIFD_TX_DATA11 : R/W; bitpos: [31:0]; default: 0; - * Configures the 11th word to be transmitted - */ -#define TWAIFD_TX_DATA11 0xFFFFFFFFU -#define TWAIFD_TX_DATA11_M (TWAIFD_TX_DATA11_V << TWAIFD_TX_DATA11_S) -#define TWAIFD_TX_DATA11_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA11_S 0 - -/** TWAIFD_TX_DATA_16_REG register - * TWAI FD transmit data register 16 - */ -#define TWAIFD_TX_DATA_16_REG (DR_REG_TWAIFD_BASE + 0xdc) -/** TWAIFD_TX_DATA12 : R/W; bitpos: [31:0]; default: 0; - * Configures the 12th word to be transmitted - */ -#define TWAIFD_TX_DATA12 0xFFFFFFFFU -#define TWAIFD_TX_DATA12_M (TWAIFD_TX_DATA12_V << TWAIFD_TX_DATA12_S) -#define TWAIFD_TX_DATA12_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA12_S 0 - -/** TWAIFD_TX_DATA_17_REG register - * TWAI FD transmit data register 17 - */ -#define TWAIFD_TX_DATA_17_REG (DR_REG_TWAIFD_BASE + 0xe0) -/** TWAIFD_TX_DATA13 : R/W; bitpos: [31:0]; default: 0; - * Configures the 13th word to be transmitted - */ -#define TWAIFD_TX_DATA13 0xFFFFFFFFU -#define TWAIFD_TX_DATA13_M (TWAIFD_TX_DATA13_V << TWAIFD_TX_DATA13_S) -#define TWAIFD_TX_DATA13_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA13_S 0 - -/** TWAIFD_TX_DATA_18_REG register - * TWAI FD transmit data register 18 - */ -#define TWAIFD_TX_DATA_18_REG (DR_REG_TWAIFD_BASE + 0xe4) -/** TWAIFD_TX_DATA14 : R/W; bitpos: [31:0]; default: 0; - * Configures the 14th word to be transmitted - */ -#define TWAIFD_TX_DATA14 0xFFFFFFFFU -#define TWAIFD_TX_DATA14_M (TWAIFD_TX_DATA14_V << TWAIFD_TX_DATA14_S) -#define TWAIFD_TX_DATA14_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA14_S 0 - -/** TWAIFD_TX_DATA_19_REG register - * TWAI FD transmit data register 19 - */ -#define TWAIFD_TX_DATA_19_REG (DR_REG_TWAIFD_BASE + 0xe8) -/** TWAIFD_TX_DATA15 : R/W; bitpos: [31:0]; default: 0; - * Configures the 15th word to be transmitted - */ -#define TWAIFD_TX_DATA15 0xFFFFFFFFU -#define TWAIFD_TX_DATA15_M (TWAIFD_TX_DATA15_V << TWAIFD_TX_DATA15_S) -#define TWAIFD_TX_DATA15_V 0xFFFFFFFFU -#define TWAIFD_TX_DATA15_S 0 - -/** TWAIFD_TX_CAMMAND_INFO_REG register - * TWAI FD TXT buffer command & information register - */ -#define TWAIFD_TX_CAMMAND_INFO_REG (DR_REG_TWAIFD_BASE + 0x14c) -/** TWAIFD_TXTB_SW_SET_ETY : R/W; bitpos: [0]; default: 0; - * a\\ - */ -#define TWAIFD_TXTB_SW_SET_ETY (BIT(0)) -#define TWAIFD_TXTB_SW_SET_ETY_M (TWAIFD_TXTB_SW_SET_ETY_V << TWAIFD_TXTB_SW_SET_ETY_S) -#define TWAIFD_TXTB_SW_SET_ETY_V 0x00000001U -#define TWAIFD_TXTB_SW_SET_ETY_S 0 -/** TWAIFD_TXTB_SW_SET_RDY : R/W; bitpos: [1]; default: 0; - * a\\ - */ -#define TWAIFD_TXTB_SW_SET_RDY (BIT(1)) -#define TWAIFD_TXTB_SW_SET_RDY_M (TWAIFD_TXTB_SW_SET_RDY_V << TWAIFD_TXTB_SW_SET_RDY_S) -#define TWAIFD_TXTB_SW_SET_RDY_V 0x00000001U -#define TWAIFD_TXTB_SW_SET_RDY_S 1 -/** TWAIFD_TXTB_SW_SET_ABT : R/W; bitpos: [2]; default: 0; - * a\\ - */ -#define TWAIFD_TXTB_SW_SET_ABT (BIT(2)) -#define TWAIFD_TXTB_SW_SET_ABT_M (TWAIFD_TXTB_SW_SET_ABT_V << TWAIFD_TXTB_SW_SET_ABT_S) -#define TWAIFD_TXTB_SW_SET_ABT_V 0x00000001U -#define TWAIFD_TXTB_SW_SET_ABT_S 2 -/** TWAIFD_TXB1 : R/W; bitpos: [8]; default: 0; - * a\\ - */ -#define TWAIFD_TXB1 (BIT(8)) -#define TWAIFD_TXB1_M (TWAIFD_TXB1_V << TWAIFD_TXB1_S) -#define TWAIFD_TXB1_V 0x00000001U -#define TWAIFD_TXB1_S 8 -/** TWAIFD_TXB2 : R/W; bitpos: [9]; default: 0; - * a\\ - */ -#define TWAIFD_TXB2 (BIT(9)) -#define TWAIFD_TXB2_M (TWAIFD_TXB2_V << TWAIFD_TXB2_S) -#define TWAIFD_TXB2_V 0x00000001U -#define TWAIFD_TXB2_S 9 -/** TWAIFD_TXB3 : R/W; bitpos: [10]; default: 0; - * a\\ - */ -#define TWAIFD_TXB3 (BIT(10)) -#define TWAIFD_TXB3_M (TWAIFD_TXB3_V << TWAIFD_TXB3_S) -#define TWAIFD_TXB3_V 0x00000001U -#define TWAIFD_TXB3_S 10 -/** TWAIFD_TXB4 : R/W; bitpos: [11]; default: 0; - * a\\ - */ -#define TWAIFD_TXB4 (BIT(11)) -#define TWAIFD_TXB4_M (TWAIFD_TXB4_V << TWAIFD_TXB4_S) -#define TWAIFD_TXB4_V 0x00000001U -#define TWAIFD_TXB4_S 11 -/** TWAIFD_TXB5 : R/W; bitpos: [12]; default: 0; - * a\\ - */ -#define TWAIFD_TXB5 (BIT(12)) -#define TWAIFD_TXB5_M (TWAIFD_TXB5_V << TWAIFD_TXB5_S) -#define TWAIFD_TXB5_V 0x00000001U -#define TWAIFD_TXB5_S 12 -/** TWAIFD_TXB6 : R/W; bitpos: [13]; default: 0; - * a\\ - */ -#define TWAIFD_TXB6 (BIT(13)) -#define TWAIFD_TXB6_M (TWAIFD_TXB6_V << TWAIFD_TXB6_S) -#define TWAIFD_TXB6_V 0x00000001U -#define TWAIFD_TXB6_S 13 -/** TWAIFD_TXB7 : R/W; bitpos: [14]; default: 0; - * a\\ - */ -#define TWAIFD_TXB7 (BIT(14)) -#define TWAIFD_TXB7_M (TWAIFD_TXB7_V << TWAIFD_TXB7_S) -#define TWAIFD_TXB7_V 0x00000001U -#define TWAIFD_TXB7_S 14 -/** TWAIFD_TXB8 : R/W; bitpos: [15]; default: 0; - * a\\ - */ -#define TWAIFD_TXB8 (BIT(15)) -#define TWAIFD_TXB8_M (TWAIFD_TXB8_V << TWAIFD_TXB8_S) -#define TWAIFD_TXB8_V 0x00000001U -#define TWAIFD_TXB8_S 15 -/** TWAIFD_TXT_BUF_CTR : R/W; bitpos: [19:16]; default: 0; - * a\\ - */ -#define TWAIFD_TXT_BUF_CTR 0x0000000FU -#define TWAIFD_TXT_BUF_CTR_M (TWAIFD_TXT_BUF_CTR_V << TWAIFD_TXT_BUF_CTR_S) -#define TWAIFD_TXT_BUF_CTR_V 0x0000000FU -#define TWAIFD_TXT_BUF_CTR_S 16 - -/** TWAIFD_ERR_CAP_RETR_CTR_ALC_REG register - * TWAI FD error capture & retransmit counter & arbitration lost register - */ -#define TWAIFD_ERR_CAP_RETR_CTR_ALC_REG (DR_REG_TWAIFD_BASE + 0x160) -/** TWAIFD_ERR_TYPE : RO; bitpos: [4:0]; default: 0; - * a\\ - */ -#define TWAIFD_ERR_TYPE 0x0000001FU -#define TWAIFD_ERR_TYPE_M (TWAIFD_ERR_TYPE_V << TWAIFD_ERR_TYPE_S) -#define TWAIFD_ERR_TYPE_V 0x0000001FU -#define TWAIFD_ERR_TYPE_S 0 -/** TWAIFD_ERR_POS : RO; bitpos: [7:5]; default: 0; - * a\\ - */ -#define TWAIFD_ERR_POS 0x00000007U -#define TWAIFD_ERR_POS_M (TWAIFD_ERR_POS_V << TWAIFD_ERR_POS_S) -#define TWAIFD_ERR_POS_V 0x00000007U -#define TWAIFD_ERR_POS_S 5 -/** TWAIFD_RETR_CTR : RO; bitpos: [11:8]; default: 0; - * a\\ - */ -#define TWAIFD_RETR_CTR 0x0000000FU -#define TWAIFD_RETR_CTR_M (TWAIFD_RETR_CTR_V << TWAIFD_RETR_CTR_S) -#define TWAIFD_RETR_CTR_V 0x0000000FU -#define TWAIFD_RETR_CTR_S 8 -/** TWAIFD_ALC_BIT : RO; bitpos: [20:16]; default: 0; - * a\\ - */ -#define TWAIFD_ALC_BIT 0x0000001FU -#define TWAIFD_ALC_BIT_M (TWAIFD_ALC_BIT_V << TWAIFD_ALC_BIT_S) -#define TWAIFD_ALC_BIT_V 0x0000001FU -#define TWAIFD_ALC_BIT_S 16 -/** TWAIFD_ALC_ID_FIELD : RO; bitpos: [23:21]; default: 0; - * a\\ - */ -#define TWAIFD_ALC_ID_FIELD 0x00000007U -#define TWAIFD_ALC_ID_FIELD_M (TWAIFD_ALC_ID_FIELD_V << TWAIFD_ALC_ID_FIELD_S) -#define TWAIFD_ALC_ID_FIELD_V 0x00000007U -#define TWAIFD_ALC_ID_FIELD_S 21 - -/** TWAIFD_TRV_DELAY_SSP_CFG_REG register - * TWAI FD transmit delay & secondary sample point configuration register - */ -#define TWAIFD_TRV_DELAY_SSP_CFG_REG (DR_REG_TWAIFD_BASE + 0x164) -/** TWAIFD_TRV_DELAY_VALUE : RO; bitpos: [6:0]; default: 0; - * a\\ - */ -#define TWAIFD_TRV_DELAY_VALUE 0x0000007FU -#define TWAIFD_TRV_DELAY_VALUE_M (TWAIFD_TRV_DELAY_VALUE_V << TWAIFD_TRV_DELAY_VALUE_S) -#define TWAIFD_TRV_DELAY_VALUE_V 0x0000007FU -#define TWAIFD_TRV_DELAY_VALUE_S 0 -/** TWAIFD_SSP_OFFSET : R/W; bitpos: [23:16]; default: 10; - * a\\ - */ -#define TWAIFD_SSP_OFFSET 0x000000FFU -#define TWAIFD_SSP_OFFSET_M (TWAIFD_SSP_OFFSET_V << TWAIFD_SSP_OFFSET_S) -#define TWAIFD_SSP_OFFSET_V 0x000000FFU -#define TWAIFD_SSP_OFFSET_S 16 -/** TWAIFD_SSP_SRC : R/W; bitpos: [25:24]; default: 0; - * a\\ - */ -#define TWAIFD_SSP_SRC 0x00000003U -#define TWAIFD_SSP_SRC_M (TWAIFD_SSP_SRC_V << TWAIFD_SSP_SRC_S) -#define TWAIFD_SSP_SRC_V 0x00000003U -#define TWAIFD_SSP_SRC_S 24 - -/** TWAIFD_RX_FRM_COUNTER_REG register - * TWAI FD received frame counter register - */ -#define TWAIFD_RX_FRM_COUNTER_REG (DR_REG_TWAIFD_BASE + 0x180) -/** TWAIFD_RX_COUNTER_VAL : RO; bitpos: [31:0]; default: 0; - * Configures the received frame counters to enable bus traffic measurement. - */ -#define TWAIFD_RX_COUNTER_VAL 0xFFFFFFFFU -#define TWAIFD_RX_COUNTER_VAL_M (TWAIFD_RX_COUNTER_VAL_V << TWAIFD_RX_COUNTER_VAL_S) -#define TWAIFD_RX_COUNTER_VAL_V 0xFFFFFFFFU -#define TWAIFD_RX_COUNTER_VAL_S 0 - -/** TWAIFD_TX_FRM_COUNTER_REG register - * TWAI FD transmitted frame counter register - */ -#define TWAIFD_TX_FRM_COUNTER_REG (DR_REG_TWAIFD_BASE + 0x184) -/** TWAIFD_TX_COUNTER_VAL : RO; bitpos: [31:0]; default: 0; - * Configures the transcieved frame counters to enable bus traffic measurement. - */ -#define TWAIFD_TX_COUNTER_VAL 0xFFFFFFFFU -#define TWAIFD_TX_COUNTER_VAL_M (TWAIFD_TX_COUNTER_VAL_V << TWAIFD_TX_COUNTER_VAL_S) -#define TWAIFD_TX_COUNTER_VAL_V 0xFFFFFFFFU -#define TWAIFD_TX_COUNTER_VAL_S 0 - -/** TWAIFD_CLK_REG register - * TWAI FD clock configuration register - */ -#define TWAIFD_CLK_REG (DR_REG_TWAIFD_BASE + 0x18c) -/** TWAIFD_CLK_EN : R/W; bitpos: [31]; default: 0; - * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes - * registers. - */ -#define TWAIFD_CLK_EN (BIT(31)) -#define TWAIFD_CLK_EN_M (TWAIFD_CLK_EN_V << TWAIFD_CLK_EN_S) -#define TWAIFD_CLK_EN_V 0x00000001U -#define TWAIFD_CLK_EN_S 31 - -/** TWAIFD_DATE_REG register - * TWAI FD version register - */ -#define TWAIFD_DATE_REG (DR_REG_TWAIFD_BASE + 0x190) -/** TWAIFD_TWAIFD_DATE : R/W; bitpos: [31:0]; default: 35717712; - * This is the version register. - */ -#define TWAIFD_TWAIFD_DATE 0xFFFFFFFFU -#define TWAIFD_TWAIFD_DATE_M (TWAIFD_TWAIFD_DATE_V << TWAIFD_TWAIFD_DATE_S) -#define TWAIFD_TWAIFD_DATE_V 0xFFFFFFFFU -#define TWAIFD_TWAIFD_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/twaifd_struct.h b/components/soc/esp32p4/include/soc/twaifd_struct.h deleted file mode 100644 index d0c0a3cd1e..0000000000 --- a/components/soc/esp32p4/include/soc/twaifd_struct.h +++ /dev/null @@ -1,1548 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: ID register */ -/** Type of device_id register - * TWAI FD device id status register - */ -typedef union { - struct { - /** device_id : R/W; bitpos: [31:0]; default: 51965; - * Represents whether CAN IP function is mapped correctly on its base address. - */ - uint32_t device_id:32; - }; - uint32_t val; -} twaifd_device_id_reg_t; - - -/** Group: Configuration register */ -/** Type of mode_setting register - * TWAI FD mode setting register - */ -typedef union { - struct { - /** sw_reset : R/W; bitpos: [0]; default: 0; - * Configures whether or not to reset the TWAI FD controller.\\ - * 0: invalid\\ - * 1: reset.\\ - */ - uint32_t sw_reset:1; - /** listen_only_mode : R/W; bitpos: [1]; default: 0; - * bus monitor enable - */ - uint32_t listen_only_mode:1; - /** self_test_mode : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the self test mode.\\ - * 0: disable\\ - * 1: enable\\ - */ - uint32_t self_test_mode:1; - /** accept_filter_mode : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the usage of acceptance filters.\\ - * 0: disable\\ - * 1: enable\\ - */ - uint32_t accept_filter_mode:1; - /** flexible_data_rate : R/W; bitpos: [4]; default: 1; - * Configures whether or not to support flexible data rate.\\ - * 0: not support\\ - * 1: support\\ - */ - uint32_t flexible_data_rate:1; - /** rtr_frm_behavior : R/W; bitpos: [5]; default: 0; - * time_triggered transmission mode - */ - uint32_t rtr_frm_behavior:1; - /** rom : R/W; bitpos: [6]; default: 0; - * a\\ - */ - uint32_t rom:1; - /** ack_behavior : R/W; bitpos: [7]; default: 0; - * Configures the acknowledge behavior.\\ - * 0: normal behavior.\\ - * 1: acknowledge is not sent.\\ - */ - uint32_t ack_behavior:1; - /** test_mode : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the triple sampling mode.\\ - * 0: disable\\ - * 1: enable\\ - */ - uint32_t test_mode:1; - /** rxbam : R/W; bitpos: [9]; default: 1; - * a\\ - */ - uint32_t rxbam:1; - uint32_t reserved_10:6; - /** limit_retx_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the limit of retransmission.\\ - * 0: disable\\ - * 1: enable\\ - */ - uint32_t limit_retx_en:1; - /** retx_thres : R/W; bitpos: [20:17]; default: 0; - * Configures the threshold of retransmission attempts. \\ - */ - uint32_t retx_thres:4; - /** ilbp : R/W; bitpos: [21]; default: 0; - * acknowledge forbidden mode - */ - uint32_t ilbp:1; - /** ctrl_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the twai FD controller.\\ - * 0: disable\\ - * 1: enable\\ - */ - uint32_t ctrl_en:1; - /** fd_type : R/W; bitpos: [23]; default: 0; - * Configure the twai fd frame type.\\ - * 0: ISO CAN FD\\ - * 1: CAN FD 1.0\\ - */ - uint32_t fd_type:1; - /** pex : R/W; bitpos: [24]; default: 0; - * protocol expection mode\\ - */ - uint32_t pex:1; - /** tbfbo : R/W; bitpos: [25]; default: 1; - * a\\ - */ - uint32_t tbfbo:1; - /** fdrf : R/W; bitpos: [26]; default: 0; - * a\\ - */ - uint32_t fdrf:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} twaifd_mode_setting_reg_t; - -/** Type of command register - * TWAI FD command register - */ -typedef union { - struct { - uint32_t reserved_0:1; - /** rxrpmv : WO; bitpos: [1]; default: 0; - * a\\ - */ - uint32_t rxrpmv:1; - /** release_rx_buf : WO; bitpos: [2]; default: 0; - * Configures whether or not to delete all data from the receive buffer.\\ - * 0: invalid\\ - * 1: delete\\ - */ - uint32_t release_rx_buf:1; - /** clr_overrun_flg : WO; bitpos: [3]; default: 0; - * Configures whether or not to clear the data overrun flag.\\ - * 0: invalid\\ - * 1: clear\\ - */ - uint32_t clr_overrun_flg:1; - /** ercrst : WO; bitpos: [4]; default: 0; - * a\\ - */ - uint32_t ercrst:1; - /** rxfcrst : WO; bitpos: [5]; default: 0; - * a\\ - */ - uint32_t rxfcrst:1; - /** txfcrst : WO; bitpos: [6]; default: 0; - * a\\ - */ - uint32_t txfcrst:1; - /** cpexs : WO; bitpos: [7]; default: 0; - * a\\ - */ - uint32_t cpexs:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} twaifd_command_reg_t; - -/** Type of bit_timing register - * TWAI FD bit-timing register - */ -typedef union { - struct { - /** prop : R/W; bitpos: [6:0]; default: 5; - * Configures the propagation segment of nominal bit rate.\\ - * Measurement unit: time quanta\\ - */ - uint32_t prop:7; - /** ph1 : R/W; bitpos: [12:7]; default: 3; - * Configures the phase 1 segment of nominal bit rate.\\ - * Measurement unit: time quanta\\ - */ - uint32_t ph1:6; - /** ph2 : R/W; bitpos: [18:13]; default: 5; - * Configures the phase 2 segment of nominal bit rate.\\ - * Measurement unit: time quanta\\ - */ - uint32_t ph2:6; - /** brp : R/W; bitpos: [26:19]; default: 16; - * Configures the baud-rate prescaler of nominal bit rate.\\ - * Measurement unit: cycle of core clock. - */ - uint32_t brp:8; - /** sjw : R/W; bitpos: [31:27]; default: 2; - * Represents the synchronization jump width in nominal bit time.\\ - * Measurement unit: time quanta\\ - */ - uint32_t sjw:5; - }; - uint32_t val; -} twaifd_bit_timing_reg_t; - -/** Type of bit_timeing_fd register - * TWAI FD bit-timing of FD register - */ -typedef union { - struct { - /** prop_fd : R/W; bitpos: [5:0]; default: 3; - * Configures the propagation segment of data bit rate.\\ - * Measurement unit: time quanta\\ - */ - uint32_t prop_fd:6; - uint32_t reserved_6:1; - /** ph1_fd : R/W; bitpos: [11:7]; default: 3; - * Configures the phase 1 segment of data bit rate.\\ - * Measurement unit: time quanta\\ - */ - uint32_t ph1_fd:5; - uint32_t reserved_12:1; - /** ph2_fd : R/W; bitpos: [17:13]; default: 3; - * Configures the phase 2 segment of data bit rate.\\ - * Measurement unit: time quanta\\ - */ - uint32_t ph2_fd:5; - uint32_t reserved_18:1; - /** brp_fd : R/W; bitpos: [26:19]; default: 4; - * Configures the baud-rate prescaler of data bit rate.\\ - * Measurement unit: cycle of core clock. - */ - uint32_t brp_fd:8; - /** sjw_fd : R/W; bitpos: [31:27]; default: 2; - * Represents the synchronization jump width in data bit time.\\ - * Measurement unit: time quanta\\ - */ - uint32_t sjw_fd:5; - }; - uint32_t val; -} twaifd_bit_timeing_fd_reg_t; - -/** Type of tx_cfg register - * TWAI FD TX buffer configuration register - */ -typedef union { - struct { - /** txt_1_allow : R/W; bitpos: [0]; default: 1; - * Configures whether or not allow transmitting frames from TX buffer1.\\ - * 0: not allow\\ - * 1: allow\\ - */ - uint32_t txt_1_allow:1; - /** txt_2_allow : R/W; bitpos: [1]; default: 1; - * Configures whether or not allow transmitting frames from TX buffer2.\\ - * 0: not allow\\ - * 1: allow\\ - */ - uint32_t txt_2_allow:1; - /** txt_1_commit : WT; bitpos: [2]; default: 0; - * Configures whether or not the frames from TX register are inserted into TX - * buffer1.\\ - * 0: not inserted\\ - * 1: inserted\\ - */ - uint32_t txt_1_commit:1; - /** txt_2_commit : WT; bitpos: [3]; default: 0; - * Configures whether or not the frames from TX register are inserted into TX - * buffer2.\\ - * 0: not inserted\\ - * 1: inserted\\ - */ - uint32_t txt_2_commit:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} twaifd_tx_cfg_reg_t; - -/** Type of trv_delay_ssp_cfg register - * TWAI FD transmit delay & secondary sample point configuration register - */ -typedef union { - struct { - /** trv_delay_value : RO; bitpos: [6:0]; default: 0; - * a\\ - */ - uint32_t trv_delay_value:7; - uint32_t reserved_7:9; - /** ssp_offset : R/W; bitpos: [23:16]; default: 10; - * a\\ - */ - uint32_t ssp_offset:8; - /** ssp_src : R/W; bitpos: [25:24]; default: 0; - * a\\ - */ - uint32_t ssp_src:2; - uint32_t reserved_26:6; - }; - uint32_t val; -} twaifd_trv_delay_ssp_cfg_reg_t; - - -/** Group: Status register */ -/** Type of status register - * TWAI FD status register - */ -typedef union { - struct { - /** rx_buf_stat : RO; bitpos: [0]; default: 0; - * Represents whether or not the receive buffer is empty.\\ - * 0: empty\\ - * 1: not empty\\ - */ - uint32_t rx_buf_stat:1; - /** data_overrun_flg : RO; bitpos: [1]; default: 0; - * Represents whether or not the receive buffer is full and the frame is - * overrun(lost).\\ - * 0: not overrun\\ - * 1: overrun\\ - */ - uint32_t data_overrun_flg:1; - /** tx_buf_sat : RO; bitpos: [2]; default: 0; - * Represents whether or not the transmit buffer is full.\\ - * 0: not full\\ - * 1: full\\ - */ - uint32_t tx_buf_sat:1; - /** err_frm_tx : RO; bitpos: [3]; default: 0; - * Represents whether or not the error frame is being transmitted.\\ - * 0: not being transmitted\\ - * 1: being transmitted\\ - */ - uint32_t err_frm_tx:1; - /** rx_frm_stat : RO; bitpos: [4]; default: 0; - * Represents whether or not the controller is receiving a frame.\\ - * 0: not receiving\\ - * 1: receiving\\ - */ - uint32_t rx_frm_stat:1; - /** tx_frm_stat : RO; bitpos: [5]; default: 0; - * Represents whether or not the controller is transmitting a frame.\\ - * 0: not transmitting\\ - * 1: transmitting\\ - */ - uint32_t tx_frm_stat:1; - /** err_stat : RO; bitpos: [6]; default: 0; - * Represents whether or not the error warning limit is reached.\\ - * 0: not reached\\ - * 1: reached\\ - */ - uint32_t err_stat:1; - /** bus_stat : RO; bitpos: [7]; default: 1; - * Represents whether or not bus is active.\\ - * 0: active\\ - * 1: not active\\ - */ - uint32_t bus_stat:1; - /** pexs : RO; bitpos: [8]; default: 0; - * a\\ - */ - uint32_t pexs:1; - /** reintegrating_wait : RO; bitpos: [9]; default: 0; - * fsm is in reintegrating wait status - */ - uint32_t reintegrating_wait:1; - uint32_t reserved_10:6; - /** stcnt : RO; bitpos: [16]; default: 0; - * a\\ - */ - uint32_t stcnt:1; - /** strgs : RO; bitpos: [17]; default: 0; - * a\\ - */ - uint32_t strgs:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} twaifd_status_reg_t; - -/** Type of rx_mem_info register - * TWAI FD rx memory information register - */ -typedef union { - struct { - /** rx_buff_size_val : RO; bitpos: [12:0]; default: 0; - * Represents the size of RX buffer.\\ - */ - uint32_t rx_buff_size_val:13; - uint32_t reserved_13:3; - /** rx_free_ctr : RO; bitpos: [28:16]; default: 0; - * Represents the number of free words in RX buffer.\\ - */ - uint32_t rx_free_ctr:13; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_rx_mem_info_reg_t; - -/** Type of rx_pointers register - * TWAI FD rx memory pointer information register - */ -typedef union { - struct { - /** rx_wpt_val : RO; bitpos: [11:0]; default: 0; - * Represents the write pointer position in RX buffer.\\ - */ - uint32_t rx_wpt_val:12; - uint32_t reserved_12:4; - /** rx_rpt_val : RO; bitpos: [27:16]; default: 0; - * Represents the read pointer position in RX buffer.\\ - */ - uint32_t rx_rpt_val:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} twaifd_rx_pointers_reg_t; - -/** Type of rx_status_setting register - * TWAI FD tx status & setting register - */ -typedef union { - struct { - /** rx_empty : RO; bitpos: [0]; default: 0; - * Represents whether or not the RX buffer is empty.\\ - * 0: not empty\\ - * 1: empty\\ - */ - uint32_t rx_empty:1; - /** rx_full : RO; bitpos: [1]; default: 0; - * Represents whether or not the RX buffer is full.\\ - * 0: not full\\ - * 1: full\\ - */ - uint32_t rx_full:1; - uint32_t reserved_2:2; - /** rx_frm_ctr : RO; bitpos: [14:4]; default: 0; - * Represents the number of received frame in RX buffer.\\ - */ - uint32_t rx_frm_ctr:11; - uint32_t reserved_15:1; - /** rtsop : R/W; bitpos: [16]; default: 0; - * a\\ - */ - uint32_t rtsop:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} twaifd_rx_status_setting_reg_t; - -/** Type of tx_stat register - * TWAI FD TX buffer status register - */ -typedef union { - struct { - /** txt_1_empty : RO; bitpos: [0]; default: 0; - * Represents whether or not the TX buffer1 is empty.\\ - * 0: not empty\\ - * 1: empty\\ - */ - uint32_t txt_1_empty:1; - /** txt_2_empty : RO; bitpos: [1]; default: 0; - * Represents whether or not the TX buffer2 is empty.\\ - * 0: not empty\\ - * 1: empty\\ - */ - uint32_t txt_2_empty:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} twaifd_tx_stat_reg_t; - -/** Type of err_cap_retr_ctr_alc register - * TWAI FD error capture & retransmit counter & arbitration lost register - */ -typedef union { - struct { - /** err_type : RO; bitpos: [4:0]; default: 0; - * a\\ - */ - uint32_t err_type:5; - /** err_pos : RO; bitpos: [7:5]; default: 0; - * a\\ - */ - uint32_t err_pos:3; - /** retr_ctr : RO; bitpos: [11:8]; default: 0; - * a\\ - */ - uint32_t retr_ctr:4; - uint32_t reserved_12:4; - /** alc_bit : RO; bitpos: [20:16]; default: 0; - * a\\ - */ - uint32_t alc_bit:5; - /** alc_id_field : RO; bitpos: [23:21]; default: 0; - * a\\ - */ - uint32_t alc_id_field:3; - uint32_t reserved_24:8; - }; - uint32_t val; -} twaifd_err_cap_retr_ctr_alc_reg_t; - - -/** Group: interrupt register */ -/** Type of int_raw register - * TWAI FD interrupt raw register - */ -typedef union { - struct { - /** rx_frm_suc_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of TWAIFD_RX_FRM_SUC_INT. - */ - uint32_t rx_frm_suc_int_raw:1; - /** tx_frm_suc_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of TWAIFD_TX_FRM_SUC_INT. - */ - uint32_t tx_frm_suc_int_raw:1; - /** err_warning_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of TWAIFD_ERR_WARNING_INT. - */ - uint32_t err_warning_int_raw:1; - /** rx_data_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of TWAIFD_RX_DATA_OVERRUN_INT. - */ - uint32_t rx_data_overrun_int_raw:1; - uint32_t reserved_4:1; - /** fault_confinement_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ - uint32_t fault_confinement_chg_int_raw:1; - /** arb_lost_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of TWAIFD_ARB_LOST_INT. - */ - uint32_t arb_lost_int_raw:1; - /** err_detected_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of TWAIFD_ERR_DETECTED_INT. - */ - uint32_t err_detected_int_raw:1; - /** is_overload_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt status of TWAIFD_IS_OVERLOAD_INT. - */ - uint32_t is_overload_int_raw:1; - /** rx_buf_full_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt status of TWAIFD_RX_BUF_FULL_INT. - */ - uint32_t rx_buf_full_int_raw:1; - /** bit_rate_shift_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt status of TWAIFD_BIT_RATE_SHIFT_INT. - */ - uint32_t bit_rate_shift_int_raw:1; - /** rx_buf_not_empty_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ - uint32_t rx_buf_not_empty_int_raw:1; - /** tx_buf_status_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT. - */ - uint32_t tx_buf_status_chg_int_raw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} twaifd_int_raw_reg_t; - -/** Type of int_ena register - * TWAI FD interrupt enable register - */ -typedef union { - struct { - /** rx_frm_suc_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable TWAIFD_RX_FRM_SUC_INT. - */ - uint32_t rx_frm_suc_int_ena:1; - /** tx_frm_suc_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable TWAIFD_TX_FRM_SUC_INT. - */ - uint32_t tx_frm_suc_int_ena:1; - /** err_warning_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable TWAIFD_ERR_WARNING_INT. - */ - uint32_t err_warning_int_ena:1; - /** rx_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable TWAIFD_RX_DATA_OVERRUN_INT. - */ - uint32_t rx_data_overrun_int_ena:1; - uint32_t reserved_4:1; - /** fault_confinement_chg_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ - uint32_t fault_confinement_chg_int_ena:1; - /** arb_lost_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable TWAIFD_ARB_LOST_INT. - */ - uint32_t arb_lost_int_ena:1; - /** err_detected_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable TWAIFD_ERR_DETECTED_INT. - */ - uint32_t err_detected_int_ena:1; - /** is_overload_int_ena : R/W; bitpos: [8]; default: 0; - * Write 1 to enable TWAIFD_IS_OVERLOAD_INT. - */ - uint32_t is_overload_int_ena:1; - /** rx_buf_full_int_ena : R/W; bitpos: [9]; default: 0; - * Write 1 to enable TWAIFD_RX_BUF_FULL_INT. - */ - uint32_t rx_buf_full_int_ena:1; - /** bit_rate_shift_int_ena : R/W; bitpos: [10]; default: 0; - * Write 1 to enable TWAIFD_BIT_RATE_SHIFT_INT. - */ - uint32_t bit_rate_shift_int_ena:1; - /** rx_buf_not_empty_int_ena : R/W; bitpos: [11]; default: 0; - * Write 1 to enable TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ - uint32_t rx_buf_not_empty_int_ena:1; - /** tx_buf_status_chg_int_ena : R/W; bitpos: [12]; default: 0; - * Write 1 to enable TWAIFD_TX_BUF_STATUS_CHG_INT. - */ - uint32_t tx_buf_status_chg_int_ena:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} twaifd_int_ena_reg_t; - -/** Type of int_st register - * TWAI FD interrupt status register - */ -typedef union { - struct { - /** rx_frm_suc_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of TWAIFD_RX_FRM_SUC_INT. - */ - uint32_t rx_frm_suc_int_st:1; - /** tx_frm_suc_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of TWAIFD_TX_FRM_SUC_INT. - */ - uint32_t tx_frm_suc_int_st:1; - /** err_warning_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of TWAIFD_ERR_WARNING_INT. - */ - uint32_t err_warning_int_st:1; - /** rx_data_overrun_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of TWAIFD_RX_DATA_OVERRUN_INT. - */ - uint32_t rx_data_overrun_int_st:1; - uint32_t reserved_4:1; - /** fault_confinement_chg_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ - uint32_t fault_confinement_chg_int_st:1; - /** arb_lost_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of TWAIFD_ARB_LOST_INT. - */ - uint32_t arb_lost_int_st:1; - /** err_detected_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status of TWAIFD_ERR_DETECTED_INT. - */ - uint32_t err_detected_int_st:1; - /** is_overload_int_st : RO; bitpos: [8]; default: 0; - * The masked interrupt status of TWAIFD_IS_OVERLOAD_INT. - */ - uint32_t is_overload_int_st:1; - /** rx_buf_full_int_st : RO; bitpos: [9]; default: 0; - * The masked interrupt status of TWAIFD_RX_BUF_FULL_INT. - */ - uint32_t rx_buf_full_int_st:1; - /** bit_rate_shift_int_st : RO; bitpos: [10]; default: 0; - * The masked interrupt status of TWAIFD_BIT_RATE_SHIFT_INT. - */ - uint32_t bit_rate_shift_int_st:1; - /** rx_buf_not_empty_int_st : RO; bitpos: [11]; default: 0; - * The masked interrupt status of TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ - uint32_t rx_buf_not_empty_int_st:1; - /** tx_buf_status_chg_int_st : RO; bitpos: [12]; default: 0; - * The masked interrupt status of TWAIFD_TX_BUF_STATUS_CHG_INT. - */ - uint32_t tx_buf_status_chg_int_st:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} twaifd_int_st_reg_t; - -/** Type of int_clr register - * TWAI FD interrupt clear register - */ -typedef union { - struct { - /** rx_frm_suc_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear TWAIFD_RX_FRM_SUC_INT. - */ - uint32_t rx_frm_suc_int_clr:1; - /** tx_frm_suc_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear TWAIFD_TX_FRM_SUC_INT. - */ - uint32_t tx_frm_suc_int_clr:1; - /** err_warning_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear TWAIFD_ERR_WARNING_INT. - */ - uint32_t err_warning_int_clr:1; - /** rx_data_overrun_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear TWAIFD_RX_DATA_OVERRUN_INT. - */ - uint32_t rx_data_overrun_int_clr:1; - uint32_t reserved_4:1; - /** fault_confinement_chg_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear TWAIFD_FAULT_CONFINEMENT_CHG_INT. - */ - uint32_t fault_confinement_chg_int_clr:1; - /** arb_lost_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear TWAIFD_ARB_LOST_INT. - */ - uint32_t arb_lost_int_clr:1; - /** err_detected_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear TWAIFD_ERR_DETECTED_INT. - */ - uint32_t err_detected_int_clr:1; - /** is_overload_int_clr : WT; bitpos: [8]; default: 0; - * Write 1 to clear TWAIFD_IS_OVERLOAD_INT. - */ - uint32_t is_overload_int_clr:1; - /** rx_buf_full_int_clr : WT; bitpos: [9]; default: 0; - * Write 1 to clear TWAIFD_RX_BUF_FULL_INT. - */ - uint32_t rx_buf_full_int_clr:1; - /** bit_rate_shift_int_clr : WT; bitpos: [10]; default: 0; - * Write 1 to clear TWAIFD_BIT_RATE_SHIFT_INT. - */ - uint32_t bit_rate_shift_int_clr:1; - /** rx_buf_not_empty_int_clr : WT; bitpos: [11]; default: 0; - * Write 1 to clear TWAIFD_RX_BUF_NOT_EMPTY_INT. - */ - uint32_t rx_buf_not_empty_int_clr:1; - /** tx_buf_status_chg_int_clr : WT; bitpos: [12]; default: 0; - * Write 1 to clear TWAIFD_TX_BUF_STATUS_CHG_INT. - */ - uint32_t tx_buf_status_chg_int_clr:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} twaifd_int_clr_reg_t; - - -/** Group: error confinement register */ -/** Type of err_th_stat register - * TWAI FD error threshold and status register - */ -typedef union { - struct { - /** err_warning_thres : R/W; bitpos: [7:0]; default: 96; - * Configures the error warning threshold.\\ - */ - uint32_t err_warning_thres:8; - /** err_passive_thres : R/W; bitpos: [15:8]; default: 128; - * Configures the error passive threshold.\\ - */ - uint32_t err_passive_thres:8; - /** err_active : RO; bitpos: [16]; default: 1; - * Represents the fault state of error active.\\ - */ - uint32_t err_active:1; - /** err_passive : RO; bitpos: [17]; default: 0; - * Represents the fault state of error passive.\\ - */ - uint32_t err_passive:1; - /** bus_off : RO; bitpos: [18]; default: 0; - * Represents the fault state of bus off.\\ - */ - uint32_t bus_off:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} twaifd_err_th_stat_reg_t; - -/** Type of error_counters register - * TWAI FD error counters status register - */ -typedef union { - struct { - /** rxc_val : RO; bitpos: [15:0]; default: 0; - * Represents the receiver error counter value.\\ - */ - uint32_t rxc_val:16; - /** txc_val : RO; bitpos: [31:16]; default: 0; - * Represents the transmitter error counter value.\\ - */ - uint32_t txc_val:16; - }; - uint32_t val; -} twaifd_error_counters_reg_t; - -/** Type of error_counters_sp register - * TWAI FD special error counters status register - */ -typedef union { - struct { - /** err_fd_val : RO; bitpos: [15:0]; default: 0; - * Represents the number of error in the data bit time.\\ - */ - uint32_t err_fd_val:16; - /** err_norm_val : RO; bitpos: [31:16]; default: 0; - * Represents the number of error in the nominal bit time.\\ - */ - uint32_t err_norm_val:16; - }; - uint32_t val; -} twaifd_error_counters_sp_reg_t; - -/** Type of ctr_pres register - * TWAI FD error counters pre-define configuration register - */ -typedef union { - struct { - /** ctr_pres_val : WO; bitpos: [8:0]; default: 0; - * Configures the pre-defined value to set the error counter.\\ - */ - uint32_t ctr_pres_val:9; - /** ptx : WT; bitpos: [9]; default: 0; - * Configures whether or not to set the receiver error counter into the value of - * pre-defined value.\\ - * 0: invalid\\ - * 1: set\\ - */ - uint32_t ptx:1; - /** prx : WT; bitpos: [10]; default: 0; - * Configures whether or not to set the transmitter error counter into the value of - * pre-defined value.\\ - * 0: invalid\\ - * 1: set\\ - */ - uint32_t prx:1; - /** enorm : WO; bitpos: [11]; default: 0; - * Configures whether or not to erase the error counter of nominal bit time.\\ - * 0: invalid\\ - * 1: erase\\ - */ - uint32_t enorm:1; - /** efd : WO; bitpos: [12]; default: 0; - * Configures whether or not to erase the error counter of data bit time.\\ - * 0: invalid\\ - * 1: erase\\ - */ - uint32_t efd:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} twaifd_ctr_pres_reg_t; - - -/** Group: receiver register */ -/** Type of rx_data register - * TWAI FD received data register - */ -typedef union { - struct { - /** rx_data : RO; bitpos: [31:0]; default: 0; - * Data received. - */ - uint32_t rx_data:32; - }; - uint32_t val; -} twaifd_rx_data_reg_t; - - -/** Group: filter register */ -/** Type of filter_a_mask register - * TWAI FD filter A mask value register - */ -typedef union { - struct { - /** bit_mask_a : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ - uint32_t bit_mask_a:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_a_mask_reg_t; - -/** Type of filter_a_val register - * TWAI FD filter A bit value register - */ -typedef union { - struct { - /** bit_val_a : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ - uint32_t bit_val_a:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_a_val_reg_t; - -/** Type of filter_b_mask register - * TWAI FD filter B mask value register - */ -typedef union { - struct { - /** bit_mask_b : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ - uint32_t bit_mask_b:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_b_mask_reg_t; - -/** Type of filter_b_val register - * TWAI FD filter B bit value register - */ -typedef union { - struct { - /** bit_val_b : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ - uint32_t bit_val_b:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_b_val_reg_t; - -/** Type of filter_c_mask register - * TWAI FD filter C mask value register - */ -typedef union { - struct { - /** bit_mask_c : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ - uint32_t bit_mask_c:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_c_mask_reg_t; - -/** Type of filter_c_val register - * TWAI FD filter C bit value register - */ -typedef union { - struct { - /** bit_val_c : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ - uint32_t bit_val_c:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_c_val_reg_t; - -/** Type of filter_ran_low register - * TWAI FD filter range low value register - */ -typedef union { - struct { - /** bit_ran_low : R/W; bitpos: [28:0]; default: 0; - * filter A bit masked value. - */ - uint32_t bit_ran_low:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_ran_low_reg_t; - -/** Type of filter_ran_high register - * TWAI FD filter range high value register - */ -typedef union { - struct { - /** bit_ran_high : R/W; bitpos: [28:0]; default: 0; - * filter A bit value. - */ - uint32_t bit_ran_high:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_ran_high_reg_t; - -/** Type of filter_control register - * TWAI FD filter control register - */ -typedef union { - struct { - /** fanb : R/W; bitpos: [0]; default: 1; - * filter A with nominal and base mode. - */ - uint32_t fanb:1; - /** fane : R/W; bitpos: [1]; default: 1; - * filter A with nominal and extended mode. - */ - uint32_t fane:1; - /** fafb : R/W; bitpos: [2]; default: 1; - * filter A with FD and base mode. - */ - uint32_t fafb:1; - /** fafe : R/W; bitpos: [3]; default: 1; - * filter A with FD and extended mode. - */ - uint32_t fafe:1; - /** fbnb : R/W; bitpos: [4]; default: 0; - * filter B with nominal and base mode. - */ - uint32_t fbnb:1; - /** fbne : R/W; bitpos: [5]; default: 0; - * filter B with nominal and extended mode. - */ - uint32_t fbne:1; - /** fbfb : R/W; bitpos: [6]; default: 0; - * filter B with FD and base mode. - */ - uint32_t fbfb:1; - /** fbfe : R/W; bitpos: [7]; default: 0; - * filter B with FD and extended mode. - */ - uint32_t fbfe:1; - /** fcnb : R/W; bitpos: [8]; default: 0; - * filter C with nominal and base mode. - */ - uint32_t fcnb:1; - /** fcne : R/W; bitpos: [9]; default: 0; - * filter C with nominal and extended mode. - */ - uint32_t fcne:1; - /** fcfb : R/W; bitpos: [10]; default: 0; - * filter C with FD and base mode. - */ - uint32_t fcfb:1; - /** fcfe : R/W; bitpos: [11]; default: 0; - * filter C with FD and extended mode. - */ - uint32_t fcfe:1; - /** frnb : R/W; bitpos: [12]; default: 0; - * filter range with nominal and base mode. - */ - uint32_t frnb:1; - /** frne : R/W; bitpos: [13]; default: 0; - * filter range with nominal and extended mode. - */ - uint32_t frne:1; - /** frfb : R/W; bitpos: [14]; default: 0; - * filter range with FD and base mode. - */ - uint32_t frfb:1; - /** frfe : R/W; bitpos: [15]; default: 0; - * filter range with FD and extended mode. - */ - uint32_t frfe:1; - /** sfa : RO; bitpos: [16]; default: 0; - * filter A status - */ - uint32_t sfa:1; - /** sfb : RO; bitpos: [17]; default: 0; - * filter B status - */ - uint32_t sfb:1; - /** sfc : RO; bitpos: [18]; default: 0; - * filter C status - */ - uint32_t sfc:1; - /** sfr : RO; bitpos: [19]; default: 0; - * filter range status - */ - uint32_t sfr:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} twaifd_filter_control_reg_t; - - -/** Group: transmitter register */ -/** Type of tx_data_0 register - * TWAI FD transmit data register 0 - */ -typedef union { - struct { - /** dlc_tx : R/W; bitpos: [3:0]; default: 0; - * Configures the brs to be transmitted. - */ - uint32_t dlc_tx:4; - uint32_t reserved_4:1; - /** rtr_tx : R/W; bitpos: [5]; default: 0; - * Configures the rtr bit to be transmitted. - */ - uint32_t rtr_tx:1; - /** id_type_tx : R/W; bitpos: [6]; default: 0; - * Configures the frame type to be transmitted. - */ - uint32_t id_type_tx:1; - /** fr_type_tx : R/W; bitpos: [7]; default: 0; - * Configures the fd type to be transmitted. - */ - uint32_t fr_type_tx:1; - /** tbf_tx : R/W; bitpos: [8]; default: 0; - * Configures the tbf bit to be transmitted. - */ - uint32_t tbf_tx:1; - /** brs_tx : R/W; bitpos: [9]; default: 0; - * Configures the brs bit to be transmitted. - */ - uint32_t brs_tx:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} twaifd_tx_data_0_reg_t; - -/** Type of tx_data_1 register - * TWAI FD transmit data register 1 - */ -typedef union { - struct { - /** ts_val_u_tx : R/W; bitpos: [31:0]; default: 0; - * Configures the upper timestamp to be transmitted - */ - uint32_t ts_val_u_tx:32; - }; - uint32_t val; -} twaifd_tx_data_1_reg_t; - -/** Type of tx_data_2 register - * TWAI FD transmit data register 2 - */ -typedef union { - struct { - /** ts_val_l_tx : R/W; bitpos: [31:0]; default: 0; - * Configures the lower timestamp to be transmitted - */ - uint32_t ts_val_l_tx:32; - }; - uint32_t val; -} twaifd_tx_data_2_reg_t; - -/** Type of tx_data_3 register - * TWAI FD transmit data register 3 - */ -typedef union { - struct { - /** id_ext_tx : R/W; bitpos: [17:0]; default: 0; - * Configures the base ID to be transmitted - */ - uint32_t id_ext_tx:18; - /** id_base_tx : R/W; bitpos: [28:18]; default: 0; - * Configures the extended ID to be transmitted - */ - uint32_t id_base_tx:11; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_tx_data_3_reg_t; - -/** Type of tx_data_4 register - * TWAI FD transmit data register 4 - */ -typedef union { - struct { - /** tx_data0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th word to be transmitted - */ - uint32_t tx_data0:32; - }; - uint32_t val; -} twaifd_tx_data_4_reg_t; - -/** Type of tx_data_5 register - * TWAI FD transmit data register 5 - */ -typedef union { - struct { - /** tx_data1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th word to be transmitted - */ - uint32_t tx_data1:32; - }; - uint32_t val; -} twaifd_tx_data_5_reg_t; - -/** Type of tx_data_6 register - * TWAI FD transmit data register 6 - */ -typedef union { - struct { - /** tx_data2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th word to be transmitted - */ - uint32_t tx_data2:32; - }; - uint32_t val; -} twaifd_tx_data_6_reg_t; - -/** Type of tx_data_7 register - * TWAI FD transmit data register 7 - */ -typedef union { - struct { - /** tx_data3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3th word to be transmitted - */ - uint32_t tx_data3:32; - }; - uint32_t val; -} twaifd_tx_data_7_reg_t; - -/** Type of tx_data_8 register - * TWAI FD transmit data register 8 - */ -typedef union { - struct { - /** tx_data4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th word to be transmitted - */ - uint32_t tx_data4:32; - }; - uint32_t val; -} twaifd_tx_data_8_reg_t; - -/** Type of tx_data_9 register - * TWAI FD transmit data register 9 - */ -typedef union { - struct { - /** tx_data5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th word to be transmitted - */ - uint32_t tx_data5:32; - }; - uint32_t val; -} twaifd_tx_data_9_reg_t; - -/** Type of tx_data_10 register - * TWAI FD transmit data register 10 - */ -typedef union { - struct { - /** tx_data6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th word to be transmitted - */ - uint32_t tx_data6:32; - }; - uint32_t val; -} twaifd_tx_data_10_reg_t; - -/** Type of tx_data_11 register - * TWAI FD transmit data register 11 - */ -typedef union { - struct { - /** tx_data7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th word to be transmitted - */ - uint32_t tx_data7:32; - }; - uint32_t val; -} twaifd_tx_data_11_reg_t; - -/** Type of tx_data_12 register - * TWAI FD transmit data register 12 - */ -typedef union { - struct { - /** tx_data8 : R/W; bitpos: [31:0]; default: 0; - * Configures the 8th word to be transmitted - */ - uint32_t tx_data8:32; - }; - uint32_t val; -} twaifd_tx_data_12_reg_t; - -/** Type of tx_data_13 register - * TWAI FD transmit data register 13 - */ -typedef union { - struct { - /** tx_data9 : R/W; bitpos: [31:0]; default: 0; - * Configures the 9th word to be transmitted - */ - uint32_t tx_data9:32; - }; - uint32_t val; -} twaifd_tx_data_13_reg_t; - -/** Type of tx_data_14 register - * TWAI FD transmit data register 14 - */ -typedef union { - struct { - /** tx_data10 : R/W; bitpos: [31:0]; default: 0; - * Configures the 10th word to be transmitted - */ - uint32_t tx_data10:32; - }; - uint32_t val; -} twaifd_tx_data_14_reg_t; - -/** Type of tx_data_15 register - * TWAI FD transmit data register 15 - */ -typedef union { - struct { - /** tx_data11 : R/W; bitpos: [31:0]; default: 0; - * Configures the 11th word to be transmitted - */ - uint32_t tx_data11:32; - }; - uint32_t val; -} twaifd_tx_data_15_reg_t; - -/** Type of tx_data_16 register - * TWAI FD transmit data register 16 - */ -typedef union { - struct { - /** tx_data12 : R/W; bitpos: [31:0]; default: 0; - * Configures the 12th word to be transmitted - */ - uint32_t tx_data12:32; - }; - uint32_t val; -} twaifd_tx_data_16_reg_t; - -/** Type of tx_data_17 register - * TWAI FD transmit data register 17 - */ -typedef union { - struct { - /** tx_data13 : R/W; bitpos: [31:0]; default: 0; - * Configures the 13th word to be transmitted - */ - uint32_t tx_data13:32; - }; - uint32_t val; -} twaifd_tx_data_17_reg_t; - -/** Type of tx_data_18 register - * TWAI FD transmit data register 18 - */ -typedef union { - struct { - /** tx_data14 : R/W; bitpos: [31:0]; default: 0; - * Configures the 14th word to be transmitted - */ - uint32_t tx_data14:32; - }; - uint32_t val; -} twaifd_tx_data_18_reg_t; - -/** Type of tx_data_19 register - * TWAI FD transmit data register 19 - */ -typedef union { - struct { - /** tx_data15 : R/W; bitpos: [31:0]; default: 0; - * Configures the 15th word to be transmitted - */ - uint32_t tx_data15:32; - }; - uint32_t val; -} twaifd_tx_data_19_reg_t; - -/** Type of tx_cammand_info register - * TWAI FD TXT buffer command & information register - */ -typedef union { - struct { - /** txtb_sw_set_ety : R/W; bitpos: [0]; default: 0; - * a\\ - */ - uint32_t txtb_sw_set_ety:1; - /** txtb_sw_set_rdy : R/W; bitpos: [1]; default: 0; - * a\\ - */ - uint32_t txtb_sw_set_rdy:1; - /** txtb_sw_set_abt : R/W; bitpos: [2]; default: 0; - * a\\ - */ - uint32_t txtb_sw_set_abt:1; - uint32_t reserved_3:5; - /** txb1 : R/W; bitpos: [8]; default: 0; - * a\\ - */ - uint32_t txb1:1; - /** txb2 : R/W; bitpos: [9]; default: 0; - * a\\ - */ - uint32_t txb2:1; - /** txb3 : R/W; bitpos: [10]; default: 0; - * a\\ - */ - uint32_t txb3:1; - /** txb4 : R/W; bitpos: [11]; default: 0; - * a\\ - */ - uint32_t txb4:1; - /** txb5 : R/W; bitpos: [12]; default: 0; - * a\\ - */ - uint32_t txb5:1; - /** txb6 : R/W; bitpos: [13]; default: 0; - * a\\ - */ - uint32_t txb6:1; - /** txb7 : R/W; bitpos: [14]; default: 0; - * a\\ - */ - uint32_t txb7:1; - /** txb8 : R/W; bitpos: [15]; default: 0; - * a\\ - */ - uint32_t txb8:1; - /** txt_buf_ctr : R/W; bitpos: [19:16]; default: 0; - * a\\ - */ - uint32_t txt_buf_ctr:4; - uint32_t reserved_20:12; - }; - uint32_t val; -} twaifd_tx_cammand_info_reg_t; - - -/** Group: controller register */ -/** Type of rx_frm_counter register - * TWAI FD received frame counter register - */ -typedef union { - struct { - /** rx_counter_val : RO; bitpos: [31:0]; default: 0; - * Configures the received frame counters to enable bus traffic measurement. - */ - uint32_t rx_counter_val:32; - }; - uint32_t val; -} twaifd_rx_frm_counter_reg_t; - -/** Type of tx_frm_counter register - * TWAI FD transmitted frame counter register - */ -typedef union { - struct { - /** tx_counter_val : RO; bitpos: [31:0]; default: 0; - * Configures the transcieved frame counters to enable bus traffic measurement. - */ - uint32_t tx_counter_val:32; - }; - uint32_t val; -} twaifd_tx_frm_counter_reg_t; - - -/** Group: clock register */ -/** Type of clk register - * TWAI FD clock configuration register - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - }; - uint32_t val; -} twaifd_clk_reg_t; - - -/** Group: Version register */ -/** Type of date register - * TWAI FD version register - */ -typedef union { - struct { - /** twaifd_date : R/W; bitpos: [31:0]; default: 35717712; - * This is the version register. - */ - uint32_t twaifd_date:32; - }; - uint32_t val; -} twaifd_date_reg_t; - - -typedef struct { - volatile twaifd_device_id_reg_t device_id; - volatile twaifd_mode_setting_reg_t mode_setting; - volatile twaifd_command_reg_t command; - volatile twaifd_status_reg_t status; - volatile twaifd_int_raw_reg_t int_raw; - volatile twaifd_int_ena_reg_t int_ena; - volatile twaifd_int_st_reg_t int_st; - volatile twaifd_int_clr_reg_t int_clr; - volatile twaifd_bit_timing_reg_t bit_timing; - volatile twaifd_bit_timeing_fd_reg_t bit_timeing_fd; - volatile twaifd_err_th_stat_reg_t err_th_stat; - volatile twaifd_error_counters_reg_t error_counters; - volatile twaifd_error_counters_sp_reg_t error_counters_sp; - volatile twaifd_ctr_pres_reg_t ctr_pres; - volatile twaifd_rx_mem_info_reg_t rx_mem_info; - volatile twaifd_rx_pointers_reg_t rx_pointers; - volatile twaifd_rx_status_setting_reg_t rx_status_setting; - volatile twaifd_rx_data_reg_t rx_data; - uint32_t reserved_048[6]; - volatile twaifd_filter_a_mask_reg_t filter_a_mask; - volatile twaifd_filter_a_val_reg_t filter_a_val; - volatile twaifd_filter_b_mask_reg_t filter_b_mask; - volatile twaifd_filter_b_val_reg_t filter_b_val; - volatile twaifd_filter_c_mask_reg_t filter_c_mask; - volatile twaifd_filter_c_val_reg_t filter_c_val; - volatile twaifd_filter_ran_low_reg_t filter_ran_low; - volatile twaifd_filter_ran_high_reg_t filter_ran_high; - volatile twaifd_filter_control_reg_t filter_control; - uint32_t reserved_084[4]; - volatile twaifd_tx_stat_reg_t tx_stat; - volatile twaifd_tx_cfg_reg_t tx_cfg; - volatile twaifd_tx_data_0_reg_t tx_data_0; - volatile twaifd_tx_data_1_reg_t tx_data_1; - volatile twaifd_tx_data_2_reg_t tx_data_2; - volatile twaifd_tx_data_3_reg_t tx_data_3; - volatile twaifd_tx_data_4_reg_t tx_data_4; - volatile twaifd_tx_data_5_reg_t tx_data_5; - volatile twaifd_tx_data_6_reg_t tx_data_6; - volatile twaifd_tx_data_7_reg_t tx_data_7; - volatile twaifd_tx_data_8_reg_t tx_data_8; - volatile twaifd_tx_data_9_reg_t tx_data_9; - volatile twaifd_tx_data_10_reg_t tx_data_10; - volatile twaifd_tx_data_11_reg_t tx_data_11; - volatile twaifd_tx_data_12_reg_t tx_data_12; - volatile twaifd_tx_data_13_reg_t tx_data_13; - volatile twaifd_tx_data_14_reg_t tx_data_14; - volatile twaifd_tx_data_15_reg_t tx_data_15; - volatile twaifd_tx_data_16_reg_t tx_data_16; - volatile twaifd_tx_data_17_reg_t tx_data_17; - volatile twaifd_tx_data_18_reg_t tx_data_18; - volatile twaifd_tx_data_19_reg_t tx_data_19; - uint32_t reserved_0ec[24]; - volatile twaifd_tx_cammand_info_reg_t tx_cammand_info; - uint32_t reserved_150[4]; - volatile twaifd_err_cap_retr_ctr_alc_reg_t err_cap_retr_ctr_alc; - volatile twaifd_trv_delay_ssp_cfg_reg_t trv_delay_ssp_cfg; - uint32_t reserved_168[6]; - volatile twaifd_rx_frm_counter_reg_t rx_frm_counter; - volatile twaifd_tx_frm_counter_reg_t tx_frm_counter; - uint32_t reserved_188; - volatile twaifd_clk_reg_t clk; - volatile twaifd_date_reg_t date; -} twaifd_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(twaifd_dev_t) == 0x194, "Invalid size of twaifd_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/uart_channel.h b/components/soc/esp32p4/include/soc/uart_channel.h index 9d9fb454fd..c04136b38d 100644 --- a/components/soc/esp32p4/include/soc/uart_channel.h +++ b/components/soc/esp32p4/include/soc/uart_channel.h @@ -7,12 +7,3 @@ // This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6. #pragma once - -//UART channels -#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16 -#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17 - -#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL -#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL diff --git a/components/soc/esp32p4/include/soc/uart_pins.h b/components/soc/esp32p4/include/soc/uart_pins.h index 7164eeae56..a5d49ea6e7 100644 --- a/components/soc/esp32p4/include/soc/uart_pins.h +++ b/components/soc/esp32p4/include/soc/uart_pins.h @@ -10,27 +10,3 @@ /* Specify the number of pins for UART */ #define SOC_UART_PINS_COUNT (4) - -/* Specify the GPIO pin number for each UART signal in the IOMUX */ -#define U0RXD_GPIO_NUM 17 -#define U0TXD_GPIO_NUM 16 -#define U0RTS_GPIO_NUM (-1) -#define U0CTS_GPIO_NUM (-1) - -#define U1RXD_GPIO_NUM (-1) -#define U1TXD_GPIO_NUM (-1) -#define U1RTS_GPIO_NUM (-1) -#define U1CTS_GPIO_NUM (-1) - -/* The following defines are necessary for reconfiguring the UART - * to use IOMUX, at runtime. */ -#define U0TXD_MUX_FUNC (FUNC_GPIO37_UART0_TXD_PAD) -#define U0RXD_MUX_FUNC (FUNC_GPIO38_UART0_RXD_PAD) -/* No func for the following pins, they shall not be used */ -#define U0RTS_MUX_FUNC (-1) -#define U0CTS_MUX_FUNC (-1) -/* Same goes for UART1 */ -#define U1TXD_MUX_FUNC (-1) -#define U1RXD_MUX_FUNC (-1) -#define U1RTS_MUX_FUNC (-1) -#define U1CTS_MUX_FUNC (-1) diff --git a/components/soc/esp32p4/include/soc/usb_device_reg.h b/components/soc/esp32p4/include/soc/usb_device_reg.h deleted file mode 100644 index 478c734ea8..0000000000 --- a/components/soc/esp32p4/include/soc/usb_device_reg.h +++ /dev/null @@ -1,1282 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** USB_SERIAL_JTAG_EP1_REG register - * FIFO access for the CDC-ACM data IN and OUT endpoints. - */ -#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) -/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; - * Write and read byte data to/from UART Tx/Rx FIFO through this field. When - * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) - * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check - * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is - * received, then read data from UART Rx FIFO. - */ -#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU -#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) -#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU -#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 - -/** USB_SERIAL_JTAG_EP1_CONF_REG register - * Configuration and control registers for the CDC-ACM FIFOs. - */ -#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) -/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; - * Set this bit to indicate writing byte data to UART Tx FIFO is done. - */ -#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) -#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) -#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U -#define USB_SERIAL_JTAG_WR_DONE_S 0 -/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; - * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing - * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB - * Host. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; - * 1'b1: Indicate there is data in UART Rx FIFO. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 - -/** USB_SERIAL_JTAG_INT_RAW_REG register - * Interrupt raw status register. - */ -#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when flush cmd is received for IN - * endpoint 2 of JTAG. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 -/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when SOF frame is received. - */ -#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) -#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received - * one packet. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; - * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when pid error is detected. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when CRC5 error is detected. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when CRC16 error is detected. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when stuff error is detected. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is - * received. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when usb bus reset is detected. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with - * zero palyload. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with - * zero palyload. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 -/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when level of RTS from usb serial channel - * is changed. - */ -#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) -#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) -#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 -/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when level of DTR from usb serial channel - * is changed. - */ -#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) -#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) -#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 -/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * The raw interrupt bit turns to high level when level of GET LINE CODING request is - * received. - */ -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 -/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * The raw interrupt bit turns to high level when level of SET LINE CODING request is - * received. - */ -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 - -/** USB_SERIAL_JTAG_INT_ST_REG register - * Interrupt status register. - */ -#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 -/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) -#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 -/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. - */ -#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) -#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) -#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 -/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. - */ -#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) -#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) -#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 -/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. - */ -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 -/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. - */ -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 - -/** USB_SERIAL_JTAG_INT_ENA_REG register - * Interrupt enable status register. - */ -#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 -/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) -#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 -/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. - */ -#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) -#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) -#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 -/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. - */ -#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) -#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) -#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 -/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. - */ -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 -/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. - */ -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 - -/** USB_SERIAL_JTAG_INT_CLR_REG register - * Interrupt clear status register. - */ -#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 -/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) -#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 -/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. - */ -#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) -#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) -#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 -/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. - */ -#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) -#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) -#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 -/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. - */ -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 -/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. - */ -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 - -/** USB_SERIAL_JTAG_CONF0_REG register - * PHY hardware configuration. - */ -#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) -/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; - * Select internal/external PHY - */ -#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) -#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U -#define USB_SERIAL_JTAG_PHY_SEL_S 0 -/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; - * Enable software control USB D+ D- exchange - */ -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 -/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; - * USB D+ D- exchange - */ -#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) -#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) -#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U -#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 -/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; - * Control single-end input high threshold,1.76V to 2V, step 80mV - */ -#define USB_SERIAL_JTAG_VREFH 0x00000003U -#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) -#define USB_SERIAL_JTAG_VREFH_V 0x00000003U -#define USB_SERIAL_JTAG_VREFH_S 3 -/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; - * Control single-end input low threshold,0.8V to 1.04V, step 80mV - */ -#define USB_SERIAL_JTAG_VREFL 0x00000003U -#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) -#define USB_SERIAL_JTAG_VREFL_V 0x00000003U -#define USB_SERIAL_JTAG_VREFL_S 5 -/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; - * Enable software control input threshold - */ -#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) -#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) -#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U -#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 -/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; - * Enable software control USB D+ D- pullup pulldown - */ -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 -/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; - * Control USB D+ pull up. - */ -#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) -#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) -#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U -#define USB_SERIAL_JTAG_DP_PULLUP_S 9 -/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; - * Control USB D+ pull down. - */ -#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) -#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) -#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U -#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 -/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; - * Control USB D- pull up. - */ -#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) -#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) -#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U -#define USB_SERIAL_JTAG_DM_PULLUP_S 11 -/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; - * Control USB D- pull down. - */ -#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) -#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) -#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U -#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 -/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; - * Control pull up value. - */ -#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) -#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) -#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U -#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 -/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; - * Enable USB pad function. - */ -#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 -/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; - * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is - * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input - * through GPIO Matrix. - */ -#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) -#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) -#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U -#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 - -/** USB_SERIAL_JTAG_TEST_REG register - * Registers used for debugging the PHY. - */ -#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) -/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; - * Enable test of the USB pad - */ -#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) -#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) -#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 -/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; - * USB pad oen in test - */ -#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) -#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) -#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 -/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; - * USB D+ tx value in test - */ -#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) -#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) -#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 -/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; - * USB D- tx value in test - */ -#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) -#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) -#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 -/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; - * USB RCV value in test - */ -#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) -#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) -#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 -/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; - * USB D+ rx value in test - */ -#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) -#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) -#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 -/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; - * USB D- rx value in test - */ -#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) -#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) -#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 - -/** USB_SERIAL_JTAG_JFIFO_ST_REG register - * JTAG FIFO status and control registers. - */ -#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) -/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; - * JTAT in fifo counter. - */ -#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U -#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) -#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U -#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 -/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; - * 1: JTAG in fifo is empty. - */ -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 -/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; - * 1: JTAG in fifo is full. - */ -#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) -#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) -#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U -#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 -/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; - * JTAT out fifo counter. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 -/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; - * 1: JTAG out fifo is empty. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 -/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; - * 1: JTAG out fifo is full. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 -/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; - * Write 1 to reset JTAG in fifo. - */ -#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) -#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) -#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U -#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 -/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; - * Write 1 to reset JTAG out fifo. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 - -/** USB_SERIAL_JTAG_FRAM_NUM_REG register - * Last received SOF frame index register. - */ -#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) -/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; - * Frame index of received SOF frame. - */ -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 - -/** USB_SERIAL_JTAG_IN_EP0_ST_REG register - * Control IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) -/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) -#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP1_ST_REG register - * CDC-ACM IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) -/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) -#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP2_ST_REG register - * CDC-ACM interrupt IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) -/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) -#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP3_ST_REG register - * JTAG IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) -/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) -#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register - * Control OUT endpoint status information. - */ -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) -/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 -/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register - * CDC-ACM OUT endpoint status information. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) -/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 -/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; - * Data count in OUT endpoint 1 when one packet is received. - */ -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 - -/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register - * JTAG OUT endpoint status information. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) -/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 -/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_MISC_CONF_REG register - * Clock enable control - */ -#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) -/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ -#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) -#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) -#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U -#define USB_SERIAL_JTAG_CLK_EN_S 0 - -/** USB_SERIAL_JTAG_MEM_CONF_REG register - * Memory power control - */ -#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) -/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; - * 1: power down usb memory. - */ -#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) -#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) -#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U -#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 -/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; - * 1: Force clock on for usb memory. - */ -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 - -/** USB_SERIAL_JTAG_CHIP_RST_REG register - * CDC-ACM chip reset control. - */ -#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) -/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; - * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. - */ -#define USB_SERIAL_JTAG_RTS (BIT(0)) -#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) -#define USB_SERIAL_JTAG_RTS_V 0x00000001U -#define USB_SERIAL_JTAG_RTS_S 0 -/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; - * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. - */ -#define USB_SERIAL_JTAG_DTR (BIT(1)) -#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) -#define USB_SERIAL_JTAG_DTR_V 0x00000001U -#define USB_SERIAL_JTAG_DTR_S 1 -/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; - * Set this bit to disable chip reset from usb serial channel to reset chip. - */ -#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) -#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) -#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U -#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 - -/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register - * W0 of SET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) -/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; - * The value of dwDTERate set by host through SET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU -#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) -#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 - -/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register - * W1 of SET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) -/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; - * The value of bCharFormat set by host through SET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU -#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) -#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU -#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 -/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; - * The value of bParityTpye set by host through SET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU -#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) -#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU -#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 -/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; - * The value of bDataBits set by host through SET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU -#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) -#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU -#define USB_SERIAL_JTAG_BDATA_BITS_S 16 - -/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register - * W0 of GET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) -/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; - * The value of dwDTERate set by software which is requested by GET_LINE_CODING - * command. - */ -#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU -#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) -#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 - -/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register - * W1 of GET_LINE_CODING command. - */ -#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) -/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; - * The value of bCharFormat set by software which is requested by GET_LINE_CODING - * command. - */ -#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU -#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) -#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU -#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 -/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; - * The value of bParityTpye set by software which is requested by GET_LINE_CODING - * command. - */ -#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU -#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) -#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU -#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 -/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; - * The value of bDataBits set by software which is requested by GET_LINE_CODING - * command. - */ -#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU -#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) -#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU -#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 - -/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register - * Configuration registers' value update - */ -#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) -/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; - * Write 1 to this register would update the value of configure registers from APB - * clock domain to 48MHz clock domain. - */ -#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) -#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) -#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U -#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 - -/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register - * Serial AFIFO configure register - */ -#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) -/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; - * Write 1 to reset CDC_ACM IN async FIFO write clock domain. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 -/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; - * Write 1 to reset CDC_ACM IN async FIFO read clock domain. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; - * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 -/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; - * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 -/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; - * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 -/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; - * CDC_ACM OUT IN async FIFO empty signal in write clock domain. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 - -/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register - * USB Bus reset status register - */ -#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) -/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; - * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus - * reset is released. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 - -/** USB_SERIAL_JTAG_ECO_LOW_48_REG register - * Reserved. - */ -#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) -/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; - * Reserved. - */ -#define USB_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S) -#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S 0 - -/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register - * Reserved. - */ -#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) -/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; - * Reserved. - */ -#define USB_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S) -#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 - -/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register - * Reserved. - */ -#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74) -/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; - * Reserved. - */ -#define USB_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) -#define USB_SERIAL_JTAG_RDN_RESULT_48_M (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S) -#define USB_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U -#define USB_SERIAL_JTAG_RDN_RESULT_48_S 0 -/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; - * Reserved. - */ -#define USB_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) -#define USB_SERIAL_JTAG_RDN_ENA_48_M (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S) -#define USB_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U -#define USB_SERIAL_JTAG_RDN_ENA_48_S 1 - -/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register - * Reserved. - */ -#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78) -/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; - * Reserved. - */ -#define USB_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S) -#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 - -/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register - * Reserved. - */ -#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c) -/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; - * Reserved. - */ -#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S) -#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 - -/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register - * Reserved. - */ -#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) -/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; - * Reserved. - */ -#define USB_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) -#define USB_SERIAL_JTAG_RDN_RESULT_APB_M (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S) -#define USB_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U -#define USB_SERIAL_JTAG_RDN_RESULT_APB_S 0 -/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; - * Reserved. - */ -#define USB_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) -#define USB_SERIAL_JTAG_RDN_ENA_APB_M (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S) -#define USB_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U -#define USB_SERIAL_JTAG_RDN_ENA_APB_S 1 - -/** USB_SERIAL_JTAG_SRAM_CTRL_REG register - * PPA SRAM Control Register - */ -#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84) -/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; - * Control signals - */ -#define USB_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU -#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S) -#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU -#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S 0 - -/** USB_SERIAL_JTAG_DATE_REG register - * Date register - */ -#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88) -/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; - * register version. - */ -#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU -#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) -#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/usb_device_struct.h b/components/soc/esp32p4/include/soc/usb_device_struct.h deleted file mode 100644 index ed400ae548..0000000000 --- a/components/soc/esp32p4/include/soc/usb_device_struct.h +++ /dev/null @@ -1,1044 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of ep1 register - * FIFO access for the CDC-ACM data IN and OUT endpoints. - */ -typedef union { - struct { - /** rdwr_byte : RO; bitpos: [7:0]; default: 0; - * Write and read byte data to/from UART Tx/Rx FIFO through this field. When - * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) - * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check - * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is - * received, then read data from UART Rx FIFO. - */ - uint32_t rdwr_byte:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} usb_serial_jtag_ep1_reg_t; - -/** Type of ep1_conf register - * Configuration and control registers for the CDC-ACM FIFOs. - */ -typedef union { - struct { - /** wr_done : WT; bitpos: [0]; default: 0; - * Set this bit to indicate writing byte data to UART Tx FIFO is done. - */ - uint32_t wr_done:1; - /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; - * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing - * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB - * Host. - */ - uint32_t serial_in_ep_data_free:1; - /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; - * 1'b1: Indicate there is data in UART Rx FIFO. - */ - uint32_t serial_out_ep_data_avail:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} usb_serial_jtag_ep1_conf_reg_t; - -/** Type of conf0 register - * PHY hardware configuration. - */ -typedef union { - struct { - /** phy_sel : R/W; bitpos: [0]; default: 0; - * Select internal/external PHY - */ - uint32_t phy_sel:1; - /** exchg_pins_override : R/W; bitpos: [1]; default: 0; - * Enable software control USB D+ D- exchange - */ - uint32_t exchg_pins_override:1; - /** exchg_pins : R/W; bitpos: [2]; default: 0; - * USB D+ D- exchange - */ - uint32_t exchg_pins:1; - /** vrefh : R/W; bitpos: [4:3]; default: 0; - * Control single-end input high threshold,1.76V to 2V, step 80mV - */ - uint32_t vrefh:2; - /** vrefl : R/W; bitpos: [6:5]; default: 0; - * Control single-end input low threshold,0.8V to 1.04V, step 80mV - */ - uint32_t vrefl:2; - /** vref_override : R/W; bitpos: [7]; default: 0; - * Enable software control input threshold - */ - uint32_t vref_override:1; - /** pad_pull_override : R/W; bitpos: [8]; default: 0; - * Enable software control USB D+ D- pullup pulldown - */ - uint32_t pad_pull_override:1; - /** dp_pullup : R/W; bitpos: [9]; default: 1; - * Control USB D+ pull up. - */ - uint32_t dp_pullup:1; - /** dp_pulldown : R/W; bitpos: [10]; default: 0; - * Control USB D+ pull down. - */ - uint32_t dp_pulldown:1; - /** dm_pullup : R/W; bitpos: [11]; default: 0; - * Control USB D- pull up. - */ - uint32_t dm_pullup:1; - /** dm_pulldown : R/W; bitpos: [12]; default: 0; - * Control USB D- pull down. - */ - uint32_t dm_pulldown:1; - /** pullup_value : R/W; bitpos: [13]; default: 0; - * Control pull up value. - */ - uint32_t pullup_value:1; - /** usb_pad_enable : R/W; bitpos: [14]; default: 1; - * Enable USB pad function. - */ - uint32_t usb_pad_enable:1; - /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; - * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is - * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input - * through GPIO Matrix. - */ - uint32_t usb_jtag_bridge_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_conf0_reg_t; - -/** Type of test register - * Registers used for debugging the PHY. - */ -typedef union { - struct { - /** test_enable : R/W; bitpos: [0]; default: 0; - * Enable test of the USB pad - */ - uint32_t test_enable:1; - /** test_usb_oe : R/W; bitpos: [1]; default: 0; - * USB pad oen in test - */ - uint32_t test_usb_oe:1; - /** test_tx_dp : R/W; bitpos: [2]; default: 0; - * USB D+ tx value in test - */ - uint32_t test_tx_dp:1; - /** test_tx_dm : R/W; bitpos: [3]; default: 0; - * USB D- tx value in test - */ - uint32_t test_tx_dm:1; - /** test_rx_rcv : RO; bitpos: [4]; default: 1; - * USB RCV value in test - */ - uint32_t test_rx_rcv:1; - /** test_rx_dp : RO; bitpos: [5]; default: 1; - * USB D+ rx value in test - */ - uint32_t test_rx_dp:1; - /** test_rx_dm : RO; bitpos: [6]; default: 0; - * USB D- rx value in test - */ - uint32_t test_rx_dm:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} usb_serial_jtag_test_reg_t; - -/** Type of misc_conf register - * Clock enable control - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} usb_serial_jtag_misc_conf_reg_t; - -/** Type of mem_conf register - * Memory power control - */ -typedef union { - struct { - /** usb_mem_pd : R/W; bitpos: [0]; default: 0; - * 1: power down usb memory. - */ - uint32_t usb_mem_pd:1; - /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; - * 1: Force clock on for usb memory. - */ - uint32_t usb_mem_clk_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} usb_serial_jtag_mem_conf_reg_t; - -/** Type of chip_rst register - * CDC-ACM chip reset control. - */ -typedef union { - struct { - /** rts : RO; bitpos: [0]; default: 0; - * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. - */ - uint32_t rts:1; - /** dtr : RO; bitpos: [1]; default: 0; - * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. - */ - uint32_t dtr:1; - /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; - * Set this bit to disable chip reset from usb serial channel to reset chip. - */ - uint32_t usb_uart_chip_rst_dis:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} usb_serial_jtag_chip_rst_reg_t; - -/** Type of get_line_code_w0 register - * W0 of GET_LINE_CODING command. - */ -typedef union { - struct { - /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; - * The value of dwDTERate set by software which is requested by GET_LINE_CODING - * command. - */ - uint32_t get_dw_dte_rate:32; - }; - uint32_t val; -} usb_serial_jtag_get_line_code_w0_reg_t; - -/** Type of get_line_code_w1 register - * W1 of GET_LINE_CODING command. - */ -typedef union { - struct { - /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0; - * The value of bCharFormat set by software which is requested by GET_LINE_CODING - * command. - */ - uint32_t get_bdata_bits:8; - /** get_bparity_type : R/W; bitpos: [15:8]; default: 0; - * The value of bParityTpye set by software which is requested by GET_LINE_CODING - * command. - */ - uint32_t get_bparity_type:8; - /** get_bchar_format : R/W; bitpos: [23:16]; default: 0; - * The value of bDataBits set by software which is requested by GET_LINE_CODING - * command. - */ - uint32_t get_bchar_format:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} usb_serial_jtag_get_line_code_w1_reg_t; - -/** Type of config_update register - * Configuration registers' value update - */ -typedef union { - struct { - /** config_update : WT; bitpos: [0]; default: 0; - * Write 1 to this register would update the value of configure registers from APB - * clock domain to 48MHz clock domain. - */ - uint32_t config_update:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} usb_serial_jtag_config_update_reg_t; - -/** Type of ser_afifo_config register - * Serial AFIFO configure register - */ -typedef union { - struct { - /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; - * Write 1 to reset CDC_ACM IN async FIFO write clock domain. - */ - uint32_t serial_in_afifo_reset_wr:1; - /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; - * Write 1 to reset CDC_ACM IN async FIFO read clock domain. - */ - uint32_t serial_in_afifo_reset_rd:1; - /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; - * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. - */ - uint32_t serial_out_afifo_reset_wr:1; - /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; - * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. - */ - uint32_t serial_out_afifo_reset_rd:1; - /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; - * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. - */ - uint32_t serial_out_afifo_rempty:1; - /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; - * CDC_ACM OUT IN async FIFO empty signal in write clock domain. - */ - uint32_t serial_in_afifo_wfull:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} usb_serial_jtag_ser_afifo_config_reg_t; - -/** Type of eco_low_48 register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_low_48 : R/W; bitpos: [31:0]; default: 0; - * Reserved. - */ - uint32_t rnd_eco_low_48:32; - }; - uint32_t val; -} usb_serial_jtag_eco_low_48_reg_t; - -/** Type of eco_high_48 register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_high_48 : R/W; bitpos: [31:0]; default: 4294967295; - * Reserved. - */ - uint32_t rnd_eco_high_48:32; - }; - uint32_t val; -} usb_serial_jtag_eco_high_48_reg_t; - -/** Type of eco_low_apb register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_low_apb : R/W; bitpos: [31:0]; default: 0; - * Reserved. - */ - uint32_t rnd_eco_low_apb:32; - }; - uint32_t val; -} usb_serial_jtag_eco_low_apb_reg_t; - -/** Type of eco_high_apb register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_high_apb : R/W; bitpos: [31:0]; default: 4294967295; - * Reserved. - */ - uint32_t rnd_eco_high_apb:32; - }; - uint32_t val; -} usb_serial_jtag_eco_high_apb_reg_t; - -/** Type of sram_ctrl register - * PPA SRAM Control Register - */ -typedef union { - struct { - /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * Control signals - */ - uint32_t mem_aux_ctrl:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} usb_serial_jtag_sram_ctrl_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * Interrupt raw status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when flush cmd is received for IN - * endpoint 2 of JTAG. - */ - uint32_t jtag_in_flush_int_raw:1; - /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when SOF frame is received. - */ - uint32_t sof_int_raw:1; - /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received - * one packet. - */ - uint32_t serial_out_recv_pkt_int_raw:1; - /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; - * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. - */ - uint32_t serial_in_empty_int_raw:1; - /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when pid error is detected. - */ - uint32_t pid_err_int_raw:1; - /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when CRC5 error is detected. - */ - uint32_t crc5_err_int_raw:1; - /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when CRC16 error is detected. - */ - uint32_t crc16_err_int_raw:1; - /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when stuff error is detected. - */ - uint32_t stuff_err_int_raw:1; - /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is - * received. - */ - uint32_t in_token_rec_in_ep1_int_raw:1; - /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when usb bus reset is detected. - */ - uint32_t usb_bus_reset_int_raw:1; - /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with - * zero palyload. - */ - uint32_t out_ep1_zero_payload_int_raw:1; - /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with - * zero palyload. - */ - uint32_t out_ep2_zero_payload_int_raw:1; - /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when level of RTS from usb serial channel - * is changed. - */ - uint32_t rts_chg_int_raw:1; - /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when level of DTR from usb serial channel - * is changed. - */ - uint32_t dtr_chg_int_raw:1; - /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The raw interrupt bit turns to high level when level of GET LINE CODING request is - * received. - */ - uint32_t get_line_code_int_raw:1; - /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The raw interrupt bit turns to high level when level of SET LINE CODING request is - * received. - */ - uint32_t set_line_code_int_raw:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_int_raw_reg_t; - -/** Type of int_st register - * Interrupt status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - */ - uint32_t jtag_in_flush_int_st:1; - /** sof_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. - */ - uint32_t sof_int_st:1; - /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - */ - uint32_t serial_out_recv_pkt_int_st:1; - /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - */ - uint32_t serial_in_empty_int_st:1; - /** pid_err_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. - */ - uint32_t pid_err_int_st:1; - /** crc5_err_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. - */ - uint32_t crc5_err_int_st:1; - /** crc16_err_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. - */ - uint32_t crc16_err_int_st:1; - /** stuff_err_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. - */ - uint32_t stuff_err_int_st:1; - /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. - */ - uint32_t in_token_rec_in_ep1_int_st:1; - /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. - */ - uint32_t usb_bus_reset_int_st:1; - /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep1_zero_payload_int_st:1; - /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep2_zero_payload_int_st:1; - /** rts_chg_int_st : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. - */ - uint32_t rts_chg_int_st:1; - /** dtr_chg_int_st : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. - */ - uint32_t dtr_chg_int_st:1; - /** get_line_code_int_st : RO; bitpos: [14]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. - */ - uint32_t get_line_code_int_st:1; - /** set_line_code_int_st : RO; bitpos: [15]; default: 0; - * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. - */ - uint32_t set_line_code_int_st:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - */ - uint32_t jtag_in_flush_int_ena:1; - /** sof_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. - */ - uint32_t sof_int_ena:1; - /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - */ - uint32_t serial_out_recv_pkt_int_ena:1; - /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - */ - uint32_t serial_in_empty_int_ena:1; - /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. - */ - uint32_t pid_err_int_ena:1; - /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. - */ - uint32_t crc5_err_int_ena:1; - /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. - */ - uint32_t crc16_err_int_ena:1; - /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. - */ - uint32_t stuff_err_int_ena:1; - /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. - */ - uint32_t in_token_rec_in_ep1_int_ena:1; - /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. - */ - uint32_t usb_bus_reset_int_ena:1; - /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep1_zero_payload_int_ena:1; - /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep2_zero_payload_int_ena:1; - /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. - */ - uint32_t rts_chg_int_ena:1; - /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. - */ - uint32_t dtr_chg_int_ena:1; - /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. - */ - uint32_t get_line_code_int_ena:1; - /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. - */ - uint32_t set_line_code_int_ena:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - */ - uint32_t jtag_in_flush_int_clr:1; - /** sof_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. - */ - uint32_t sof_int_clr:1; - /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - */ - uint32_t serial_out_recv_pkt_int_clr:1; - /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - */ - uint32_t serial_in_empty_int_clr:1; - /** pid_err_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. - */ - uint32_t pid_err_int_clr:1; - /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. - */ - uint32_t crc5_err_int_clr:1; - /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. - */ - uint32_t crc16_err_int_clr:1; - /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. - */ - uint32_t stuff_err_int_clr:1; - /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. - */ - uint32_t in_token_rec_in_ep1_int_clr:1; - /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. - */ - uint32_t usb_bus_reset_int_clr:1; - /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep1_zero_payload_int_clr:1; - /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep2_zero_payload_int_clr:1; - /** rts_chg_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. - */ - uint32_t rts_chg_int_clr:1; - /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. - */ - uint32_t dtr_chg_int_clr:1; - /** get_line_code_int_clr : WT; bitpos: [14]; default: 0; - * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. - */ - uint32_t get_line_code_int_clr:1; - /** set_line_code_int_clr : WT; bitpos: [15]; default: 0; - * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. - */ - uint32_t set_line_code_int_clr:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_int_clr_reg_t; - - -/** Group: Status Registers */ -/** Type of jfifo_st register - * JTAG FIFO status and control registers. - */ -typedef union { - struct { - /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; - * JTAT in fifo counter. - */ - uint32_t in_fifo_cnt:2; - /** in_fifo_empty : RO; bitpos: [2]; default: 1; - * 1: JTAG in fifo is empty. - */ - uint32_t in_fifo_empty:1; - /** in_fifo_full : RO; bitpos: [3]; default: 0; - * 1: JTAG in fifo is full. - */ - uint32_t in_fifo_full:1; - /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; - * JTAT out fifo counter. - */ - uint32_t out_fifo_cnt:2; - /** out_fifo_empty : RO; bitpos: [6]; default: 1; - * 1: JTAG out fifo is empty. - */ - uint32_t out_fifo_empty:1; - /** out_fifo_full : RO; bitpos: [7]; default: 0; - * 1: JTAG out fifo is full. - */ - uint32_t out_fifo_full:1; - /** in_fifo_reset : R/W; bitpos: [8]; default: 0; - * Write 1 to reset JTAG in fifo. - */ - uint32_t in_fifo_reset:1; - /** out_fifo_reset : R/W; bitpos: [9]; default: 0; - * Write 1 to reset JTAG out fifo. - */ - uint32_t out_fifo_reset:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} usb_serial_jtag_jfifo_st_reg_t; - -/** Type of fram_num register - * Last received SOF frame index register. - */ -typedef union { - struct { - /** sof_frame_index : RO; bitpos: [10:0]; default: 0; - * Frame index of received SOF frame. - */ - uint32_t sof_frame_index:11; - uint32_t reserved_11:21; - }; - uint32_t val; -} usb_serial_jtag_fram_num_reg_t; - -/** Type of in_ep0_st register - * Control IN endpoint status information. - */ -typedef union { - struct { - /** in_ep0_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 0. - */ - uint32_t in_ep0_state:2; - /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 0. - */ - uint32_t in_ep0_wr_addr:7; - /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 0. - */ - uint32_t in_ep0_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep0_st_reg_t; - -/** Type of in_ep1_st register - * CDC-ACM IN endpoint status information. - */ -typedef union { - struct { - /** in_ep1_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 1. - */ - uint32_t in_ep1_state:2; - /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 1. - */ - uint32_t in_ep1_wr_addr:7; - /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 1. - */ - uint32_t in_ep1_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep1_st_reg_t; - -/** Type of in_ep2_st register - * CDC-ACM interrupt IN endpoint status information. - */ -typedef union { - struct { - /** in_ep2_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 2. - */ - uint32_t in_ep2_state:2; - /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 2. - */ - uint32_t in_ep2_wr_addr:7; - /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 2. - */ - uint32_t in_ep2_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep2_st_reg_t; - -/** Type of in_ep3_st register - * JTAG IN endpoint status information. - */ -typedef union { - struct { - /** in_ep3_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 3. - */ - uint32_t in_ep3_state:2; - /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 3. - */ - uint32_t in_ep3_wr_addr:7; - /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 3. - */ - uint32_t in_ep3_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep3_st_reg_t; - -/** Type of out_ep0_st register - * Control OUT endpoint status information. - */ -typedef union { - struct { - /** out_ep0_state : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 0. - */ - uint32_t out_ep0_state:2; - /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. - */ - uint32_t out_ep0_wr_addr:7; - /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 0. - */ - uint32_t out_ep0_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_out_ep0_st_reg_t; - -/** Type of out_ep1_st register - * CDC-ACM OUT endpoint status information. - */ -typedef union { - struct { - /** out_ep1_state : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 1. - */ - uint32_t out_ep1_state:2; - /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. - */ - uint32_t out_ep1_wr_addr:7; - /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 1. - */ - uint32_t out_ep1_rd_addr:7; - /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; - * Data count in OUT endpoint 1 when one packet is received. - */ - uint32_t out_ep1_rec_data_cnt:7; - uint32_t reserved_23:9; - }; - uint32_t val; -} usb_serial_jtag_out_ep1_st_reg_t; - -/** Type of out_ep2_st register - * JTAG OUT endpoint status information. - */ -typedef union { - struct { - /** out_ep2_state : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 2. - */ - uint32_t out_ep2_state:2; - /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. - */ - uint32_t out_ep2_wr_addr:7; - /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 2. - */ - uint32_t out_ep2_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_out_ep2_st_reg_t; - -/** Type of set_line_code_w0 register - * W0 of SET_LINE_CODING command. - */ -typedef union { - struct { - /** dw_dte_rate : RO; bitpos: [31:0]; default: 0; - * The value of dwDTERate set by host through SET_LINE_CODING command. - */ - uint32_t dw_dte_rate:32; - }; - uint32_t val; -} usb_serial_jtag_set_line_code_w0_reg_t; - -/** Type of set_line_code_w1 register - * W1 of SET_LINE_CODING command. - */ -typedef union { - struct { - /** bchar_format : RO; bitpos: [7:0]; default: 0; - * The value of bCharFormat set by host through SET_LINE_CODING command. - */ - uint32_t bchar_format:8; - /** bparity_type : RO; bitpos: [15:8]; default: 0; - * The value of bParityTpye set by host through SET_LINE_CODING command. - */ - uint32_t bparity_type:8; - /** bdata_bits : RO; bitpos: [23:16]; default: 0; - * The value of bDataBits set by host through SET_LINE_CODING command. - */ - uint32_t bdata_bits:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} usb_serial_jtag_set_line_code_w1_reg_t; - -/** Type of bus_reset_st register - * USB Bus reset status register - */ -typedef union { - struct { - /** usb_bus_reset_st : RO; bitpos: [0]; default: 1; - * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus - * reset is released. - */ - uint32_t usb_bus_reset_st:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} usb_serial_jtag_bus_reset_st_reg_t; - -/** Type of eco_cell_ctrl_48 register - * Reserved. - */ -typedef union { - struct { - /** rdn_result_48 : RO; bitpos: [0]; default: 0; - * Reserved. - */ - uint32_t rdn_result_48:1; - /** rdn_ena_48 : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t rdn_ena_48:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} usb_serial_jtag_eco_cell_ctrl_48_reg_t; - -/** Type of eco_cell_ctrl_apb register - * Reserved. - */ -typedef union { - struct { - /** rdn_result_apb : RO; bitpos: [0]; default: 0; - * Reserved. - */ - uint32_t rdn_result_apb:1; - /** rdn_ena_apb : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t rdn_ena_apb:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} usb_serial_jtag_eco_cell_ctrl_apb_reg_t; - - -/** Group: Version Registers */ -/** Type of date register - * Date register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 34676752; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} usb_serial_jtag_date_reg_t; - - -typedef struct { - volatile usb_serial_jtag_ep1_reg_t ep1; - volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; - volatile usb_serial_jtag_int_raw_reg_t int_raw; - volatile usb_serial_jtag_int_st_reg_t int_st; - volatile usb_serial_jtag_int_ena_reg_t int_ena; - volatile usb_serial_jtag_int_clr_reg_t int_clr; - volatile usb_serial_jtag_conf0_reg_t conf0; - volatile usb_serial_jtag_test_reg_t test; - volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; - volatile usb_serial_jtag_fram_num_reg_t fram_num; - volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; - volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; - volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; - volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; - volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; - volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; - volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; - volatile usb_serial_jtag_misc_conf_reg_t misc_conf; - volatile usb_serial_jtag_mem_conf_reg_t mem_conf; - volatile usb_serial_jtag_chip_rst_reg_t chip_rst; - volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; - volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; - volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; - volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; - volatile usb_serial_jtag_config_update_reg_t config_update; - volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; - volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; - volatile usb_serial_jtag_eco_low_48_reg_t eco_low_48; - volatile usb_serial_jtag_eco_high_48_reg_t eco_high_48; - volatile usb_serial_jtag_eco_cell_ctrl_48_reg_t eco_cell_ctrl_48; - volatile usb_serial_jtag_eco_low_apb_reg_t eco_low_apb; - volatile usb_serial_jtag_eco_high_apb_reg_t eco_high_apb; - volatile usb_serial_jtag_eco_cell_ctrl_apb_reg_t eco_cell_ctrl_apb; - volatile usb_serial_jtag_sram_ctrl_reg_t sram_ctrl; - volatile usb_serial_jtag_date_reg_t date; -} usb_serial_jtag_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index 64aaa0c3e6..0f3e87e1e5 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -27,12 +27,11 @@ PROVIDE ( I2S1 = 0x500C7000 ); PROVIDE ( I2S2 = 0x500C8000 ); PROVIDE ( TWAI1 = 0x500D8000 ); PROVIDE ( TWAI2 = 0x500D9000 ); -PROVIDE ( APB_SARADC = 0x6000E000 ); /* need remove */ +PROVIDE ( ADC = 0x500DE000 ); PROVIDE ( USB_SERIAL_JTAG = 0x500D2000 ); PROVIDE ( SDMMC = 0x50083000 ); PROVIDE ( INTMTX = 0x500D6000 ); -PROVIDE ( ATOMIC_LOCKER = 0x60011000 ); /* need remove */ PROVIDE ( PCNT = 0x500C9000 ); PROVIDE ( SOC_ETM = 0x500D5000 ); PROVIDE ( MCPWM0 = 0x500C0000 ); @@ -42,6 +41,7 @@ PROVIDE ( PVT_MONITOR = 0x5009E000 ); PROVIDE ( GDMA = 0x50081000 ); PROVIDE ( GPSPI2 = 0x500D0000 ); +PROVIDE ( GPSPI3 = 0x500D1000 ); PROVIDE ( AES = 0x50090000 ); PROVIDE ( SHA = 0x50091000 ); @@ -51,14 +51,13 @@ PROVIDE ( DS = 0x50094000 ); PROVIDE ( HMAC = 0x50095000 ); PROVIDE ( ECDSA = 0x50096000 ); -PROVIDE ( IO_MUX = 0x500e1000 ); PROVIDE ( IOMUX = 0x500e1000 ); PROVIDE ( GPIO = 0x500E0000 ); PROVIDE ( SIGMADELTA = 0x500E0F00 ); PROVIDE ( HP_SYSTEM = 0x500E5000 ); -PROVIDE ( TEE = 0x60098000 ); /* need update */ -PROVIDE ( HP_APM = 0x60099000 ); /* need update */ +PROVIDE ( TEE = 0x60098000 ); /* TODO: IDF-7542 */ +PROVIDE ( HP_APM = 0x60099000 ); /* TODO: IDF-7542 */ PROVIDE ( PMU = 0x50115000 ); PROVIDE ( LP_AON_CLKRST = 0x50111000 ); @@ -66,12 +65,13 @@ PROVIDE ( EFUSE = 0x5012D000 ); PROVIDE ( LP_TIMER = 0x50112000 ); PROVIDE ( LP_UART = 0x50121000 ); PROVIDE ( LP_I2C = 0x50122000 ); +PROVIDE ( LP_SPI = 0x50123000 ); PROVIDE ( LP_WDT = 0x50116000 ); PROVIDE ( LP_I2S = 0x50125000 ); PROVIDE ( LP_GPIO = 0x5012A000 ); PROVIDE ( LP_I2C_ANA_MST = 0x50124000 ); PROVIDE ( LP_ANA_PERI = 0x50113000 ); -PROVIDE ( LP_APM = 0x600B3800 ); /* need update */ +PROVIDE ( LP_APM = 0x600B3800 ); /* TODO: IDF-7542 */ PROVIDE ( AHB_DMA = 0x50085000 ); PROVIDE ( AXI_DMA = 0x5008a000 ); PROVIDE ( LCD_CAM = 0x500dc000 ); diff --git a/components/soc/esp32p4/ledc_periph.c b/components/soc/esp32p4/ledc_periph.c index 18e9d9a68d..867ad4bfd6 100644 --- a/components/soc/esp32p4/ledc_periph.c +++ b/components/soc/esp32p4/ledc_periph.c @@ -11,7 +11,5 @@ Bunch of constants for every LEDC peripheral: GPIO signals */ const ledc_signal_conn_t ledc_periph_signal[1] = { - { - .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, - } + }; diff --git a/components/soc/esp32p4/mcpwm_periph.c b/components/soc/esp32p4/mcpwm_periph.c index 6de1cfa631..fea03e5a8d 100644 --- a/components/soc/esp32p4/mcpwm_periph.c +++ b/components/soc/esp32p4/mcpwm_periph.c @@ -9,75 +9,5 @@ #include "soc/gpio_sig_map.h" const mcpwm_signal_conn_t mcpwm_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_MCPWM0_MODULE, - .irq_id = ETS_PWM0_INTR_SOURCE, - .operators = { - [0] = { - .generators = { - [0] = { - .pwm_sig = 0 - }, - [1] = { - .pwm_sig = 0 - } - } - }, - [1] = { - .generators = { - [0] = { - .pwm_sig = 0 - }, - [1] = { - .pwm_sig = 0 - } - } - }, - [2] = { - .generators = { - [0] = { - .pwm_sig = 0 - }, - [1] = { - .pwm_sig = 0 - } - } - } - }, - .gpio_faults = { - [0] = { - .fault_sig = 0 - }, - [1] = { - .fault_sig = 0 - }, - [2] = { - .fault_sig = 0 - } - }, - .captures = { - [0] = { - .cap_sig = 0 - }, - [1] = { - .cap_sig = 0 - }, - [2] = { - .cap_sig = 0 - } - }, - .gpio_synchros = { - [0] = { - .sync_sig = 0 - }, - [1] = { - .sync_sig = 0 - }, - [2] = { - .sync_sig = 0 - } - } - }, - } + }; diff --git a/components/soc/esp32p4/parlio_periph.c b/components/soc/esp32p4/parlio_periph.c index 40ac06320c..827c614415 100644 --- a/components/soc/esp32p4/parlio_periph.c +++ b/components/soc/esp32p4/parlio_periph.c @@ -8,59 +8,5 @@ #include "soc/gpio_sig_map.h" const parlio_signal_conn_t parlio_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_PARLIO_MODULE, - .tx_irq_id = ETS_PARL_IO_INTR_SOURCE, - .rx_irq_id = ETS_PARL_IO_INTR_SOURCE, - .tx_units = { - [0] = { - .data_sigs = { - PARL_TX_DATA0_IDX, - PARL_TX_DATA1_IDX, - PARL_TX_DATA2_IDX, - PARL_TX_DATA3_IDX, - PARL_TX_DATA4_IDX, - PARL_TX_DATA5_IDX, - PARL_TX_DATA6_IDX, - PARL_TX_DATA7_IDX, - PARL_TX_DATA8_IDX, - PARL_TX_DATA9_IDX, - PARL_TX_DATA10_IDX, - PARL_TX_DATA11_IDX, - PARL_TX_DATA12_IDX, - PARL_TX_DATA13_IDX, - PARL_TX_DATA14_IDX, - PARL_TX_DATA15_IDX, - }, - .clk_out_sig = PARL_TX_CLK_OUT_IDX, - .clk_in_sig = PARL_TX_CLK_IN_IDX, - } - }, - .rx_units = { - [0] = { - .data_sigs = { - PARL_RX_DATA0_IDX, - PARL_RX_DATA1_IDX, - PARL_RX_DATA2_IDX, - PARL_RX_DATA3_IDX, - PARL_RX_DATA4_IDX, - PARL_RX_DATA5_IDX, - PARL_RX_DATA6_IDX, - PARL_RX_DATA7_IDX, - PARL_RX_DATA8_IDX, - PARL_RX_DATA9_IDX, - PARL_RX_DATA10_IDX, - PARL_RX_DATA11_IDX, - PARL_RX_DATA12_IDX, - PARL_RX_DATA13_IDX, - PARL_RX_DATA14_IDX, - PARL_RX_DATA15_IDX, - }, - .clk_out_sig = -1, - .clk_in_sig = PARL_RX_CLK_IN_IDX, - } - } - }, - }, + }; diff --git a/components/soc/esp32p4/pcnt_periph.c b/components/soc/esp32p4/pcnt_periph.c index a3b2adaee2..ca289c2e28 100644 --- a/components/soc/esp32p4/pcnt_periph.c +++ b/components/soc/esp32p4/pcnt_periph.c @@ -8,60 +8,5 @@ #include "soc/gpio_sig_map.h" const pcnt_signal_conn_t pcnt_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_PCNT_MODULE, - .irq = ETS_PCNT_INTR_SOURCE, - .units = { - [0] = { - .channels = { - [0] = { - .control_sig = 0, - .pulse_sig = 0 - }, - [1] = { - .control_sig = 0, - .pulse_sig = 0 - } - } - }, - [1] = { - .channels = { - [0] = { - .control_sig = 0, - .pulse_sig = 0 - }, - [1] = { - .control_sig = 0, - .pulse_sig = 0 - } - } - }, - [2] = { - .channels = { - [0] = { - .control_sig = 0, - .pulse_sig = 0 - }, - [1] = { - .control_sig = 0, - .pulse_sig = 0 - } - } - }, - [3] = { - .channels = { - [0] = { - .control_sig = 0, - .pulse_sig = 0 - }, - [1] = { - .control_sig = 0, - .pulse_sig = 0 - } - } - } - } - } - } + }; diff --git a/components/soc/esp32p4/rmt_periph.c b/components/soc/esp32p4/rmt_periph.c index 06ed9e3b74..650b4ddcf1 100644 --- a/components/soc/esp32p4/rmt_periph.c +++ b/components/soc/esp32p4/rmt_periph.c @@ -8,28 +8,5 @@ #include "soc/gpio_sig_map.h" const rmt_signal_conn_t rmt_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_RMT_MODULE, - .irq = ETS_RMT_INTR_SOURCE, - .channels = { - [0] = { - .tx_sig = RMT_SIG_PAD_OUT0_IDX, - .rx_sig = -1 - }, - [1] = { - .tx_sig = RMT_SIG_PAD_OUT1_IDX, - .rx_sig = -1 - }, - [2] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_PAD_IN0_IDX - }, - [3] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_PAD_IN1_IDX - }, - } - } - } + }; diff --git a/components/soc/esp32p4/rtc_io_periph.c b/components/soc/esp32p4/rtc_io_periph.c index 51befd2bae..c8273e3f5b 100644 --- a/components/soc/esp32p4/rtc_io_periph.c +++ b/components/soc/esp32p4/rtc_io_periph.c @@ -7,35 +7,5 @@ #include "soc/rtc_periph.h" const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { - RTCIO_GPIO0_CHANNEL, //GPIO0 - RTCIO_GPIO1_CHANNEL, //GPIO1 - RTCIO_GPIO2_CHANNEL, //GPIO2 - RTCIO_GPIO3_CHANNEL, //GPIO3 - RTCIO_GPIO4_CHANNEL, //GPIO4 - RTCIO_GPIO5_CHANNEL, //GPIO5 - RTCIO_GPIO6_CHANNEL, //GPIO6 - RTCIO_GPIO7_CHANNEL, //GPIO7 - -1,//GPIO8 - -1,//GPIO9 - -1,//GPIO10 - -1,//GPIO11 - -1,//GPIO12 - -1,//GPIO13 - -1,//GPIO14 - -1,//GPIO15 - -1,//GPIO16 - -1,//GPIO17 - -1,//GPIO18 - -1,//GPIO19 - -1,//GPIO20 - -1,//GPIO21 - -1,//GPIO22 - -1,//GPIO23 - -1,//GPIO24 - -1,//GPIO25 - -1,//GPIO26 - -1,//GPIO27 - -1,//GPIO28 - -1,//GPIO29 - -1,//GPIO30 + }; diff --git a/components/soc/esp32p4/sdio_slave_periph.c b/components/soc/esp32p4/sdio_slave_periph.c index 21d9501108..e5f5a19fc5 100644 --- a/components/soc/esp32p4/sdio_slave_periph.c +++ b/components/soc/esp32p4/sdio_slave_periph.c @@ -8,13 +8,5 @@ #include "soc/sdio_slave_pins.h" const sdio_slave_slot_info_t sdio_slave_slot_info[1] = { - { - .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK, - .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD, - .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0, - .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1, - .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2, - .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3, - .func = SDIO_SLAVE_SLOT0_FUNC, - }, + }; diff --git a/components/soc/esp32p4/sdm_periph.c b/components/soc/esp32p4/sdm_periph.c index 2c47c3bee1..da3f711ad8 100644 --- a/components/soc/esp32p4/sdm_periph.c +++ b/components/soc/esp32p4/sdm_periph.c @@ -8,18 +8,5 @@ #include "soc/gpio_sig_map.h" const sigma_delta_signal_conn_t sigma_delta_periph_signals = { - .channels = { - [0] = { - GPIO_SD0_OUT_IDX - }, - [1] = { - GPIO_SD1_OUT_IDX - }, - [2] = { - GPIO_SD2_OUT_IDX - }, - [3] = { - GPIO_SD3_OUT_IDX - } - } + }; diff --git a/components/soc/esp32p4/sdmmc_periph.c b/components/soc/esp32p4/sdmmc_periph.c index 8b12f54d34..1fb72fb2c3 100644 --- a/components/soc/esp32p4/sdmmc_periph.c +++ b/components/soc/esp32p4/sdmmc_periph.c @@ -7,57 +7,13 @@ #include "soc/sdmmc_periph.h" // ESP32P4-TODO: need new iomux and sig map const sdmmc_slot_info_t sdmmc_slot_info[SOC_SDMMC_NUM_SLOTS] = { - { - .width = 8, - .card_detect = 0, - .write_protect = 0, - .card_int = 0, - }, - { - .width = 4, - .card_detect = 0, - .write_protect = 0, - .card_int = 0, - } + }; const sdmmc_slot_io_info_t sdmmc_slot_gpio_num[SOC_SDMMC_NUM_SLOTS] = { - { - .clk = SDMMC_SLOT0_IOMUX_PIN_NUM_CLK, - .cmd = SDMMC_SLOT0_IOMUX_PIN_NUM_CMD, - .d0 = SDMMC_SLOT0_IOMUX_PIN_NUM_D0, - .d1 = SDMMC_SLOT0_IOMUX_PIN_NUM_D1, - .d2 = SDMMC_SLOT0_IOMUX_PIN_NUM_D2, - .d3 = SDMMC_SLOT0_IOMUX_PIN_NUM_D3, - .d4 = SDMMC_SLOT0_IOMUX_PIN_NUM_D4, - .d5 = SDMMC_SLOT0_IOMUX_PIN_NUM_D5, - .d6 = SDMMC_SLOT0_IOMUX_PIN_NUM_D6, - .d7 = SDMMC_SLOT0_IOMUX_PIN_NUM_D7, - }, - { - .clk = SDMMC_SLOT1_IOMUX_PIN_NUM_CLK, - .cmd = SDMMC_SLOT1_IOMUX_PIN_NUM_CMD, - .d0 = SDMMC_SLOT1_IOMUX_PIN_NUM_D0, - .d1 = SDMMC_SLOT1_IOMUX_PIN_NUM_D1, - .d2 = SDMMC_SLOT1_IOMUX_PIN_NUM_D2, - .d3 = SDMMC_SLOT1_IOMUX_PIN_NUM_D3, - } + }; const sdmmc_slot_io_info_t sdmmc_slot_gpio_sig[SOC_SDMMC_NUM_SLOTS] = { - { - }, - { - .clk = SD_CARD_CCLK_2_PAD_OUT_IDX, - .cmd = SD_CARD_CCMD_2_PAD_OUT_IDX, - .d0 = SD_CARD_CDATA0_2_PAD_OUT_IDX, - .d1 = SD_CARD_CDATA1_2_PAD_OUT_IDX, - .d2 = SD_CARD_CDATA2_2_PAD_OUT_IDX, - .d3 = SD_CARD_CDATA3_2_PAD_OUT_IDX, - .d4 = SD_CARD_CDATA4_2_PAD_OUT_IDX, - .d5 = SD_CARD_CDATA5_2_PAD_OUT_IDX, - .d6 = SD_CARD_CDATA6_2_PAD_OUT_IDX, - .d7 = SD_CARD_CDATA7_2_PAD_OUT_IDX, - }, }; diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c index 86c2e7bbfe..3534bb9428 100644 --- a/components/soc/esp32p4/spi_periph.c +++ b/components/soc/esp32p4/spi_periph.c @@ -11,43 +11,5 @@ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc */ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { - { - .spiclk_in = 0,/* SPI clock is not an input signal*/ - .spics_in = 0,/* SPI cs is not an input signal*/ - .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, - .irq = ETS_MSPI_INTR_SOURCE, - .irq_dma = -1, - .module = PERIPH_SPI_MODULE, - .hw = (spi_dev_t *) &SPIMEM1, - .func = SPI_FUNC_NUM, - }, { // TODO: IDF-5334 Need check - .spiclk_out = FSPICLK_OUT_IDX, - .spiclk_in = FSPICLK_IN_IDX, - .spid_out = FSPID_OUT_IDX, - .spiq_out = FSPIQ_OUT_IDX, - .spiwp_out = FSPIWP_OUT_IDX, - .spihd_out = FSPIHD_OUT_IDX, - .spid_in = FSPID_IN_IDX, - .spiq_in = FSPIQ_IN_IDX, - .spiwp_in = FSPIWP_IN_IDX, - .spihd_in = FSPIHD_IN_IDX, - .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, - .spics_in = FSPICS0_IN_IDX, - .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, - .irq = ETS_GSPI2_INTR_SOURCE, - .irq_dma = -1, - .module = PERIPH_SPI2_MODULE, - .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, - } + }; diff --git a/components/soc/esp32p4/temperature_sensor_periph.c b/components/soc/esp32p4/temperature_sensor_periph.c index a681a41e3b..a9812ecc72 100644 --- a/components/soc/esp32p4/temperature_sensor_periph.c +++ b/components/soc/esp32p4/temperature_sensor_periph.c @@ -7,10 +7,5 @@ #include "soc/temperature_sensor_periph.h" const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { - /*Offset reg_val min max error */ - {-2, 5, 50, 125, 3}, - {-1, 7, 20, 100, 2}, - { 0, 15, -10, 80, 1}, - { 1, 11, -30, 50, 2}, - { 2, 10, -40, 20, 3}, + }; diff --git a/components/soc/esp32p4/timer_periph.c b/components/soc/esp32p4/timer_periph.c index d0d4ca2e81..96eb286c20 100644 --- a/components/soc/esp32p4/timer_periph.c +++ b/components/soc/esp32p4/timer_periph.c @@ -7,18 +7,5 @@ #include "soc/timer_periph.h" const timer_group_signal_conn_t timer_group_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_TIMG0_MODULE, - .timer_irq_id = { - [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE, - } - }, - [1] = { - .module = PERIPH_TIMG1_MODULE, - .timer_irq_id = { - [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE, - } - } - } + }; diff --git a/components/soc/esp32p4/twai_periph.c b/components/soc/esp32p4/twai_periph.c index 3f7d17c41d..061cd4a4d7 100644 --- a/components/soc/esp32p4/twai_periph.c +++ b/components/soc/esp32p4/twai_periph.c @@ -8,24 +8,5 @@ #include "soc/gpio_sig_map.h" const twai_controller_signal_conn_t twai_controller_periph_signals = { - .controllers = { - [0] = { - .module = PERIPH_TWAI0_MODULE, - .irq_id = ETS_TWAI0_INTR_SOURCE, - .tx_sig = TWAI0_TX_IDX, - .rx_sig = TWAI0_RX_IDX, - .bus_off_sig = TWAI0_BUS_OFF_ON_IDX, - .clk_out_sig = TWAI0_CLKOUT_IDX, - .stand_by_sig = TWAI0_STANDBY_IDX, - }, - [1] = { - .module = PERIPH_TWAI1_MODULE, - .irq_id = ETS_TWAI1_INTR_SOURCE, - .tx_sig = TWAI1_TX_IDX, - .rx_sig = TWAI1_RX_IDX, - .bus_off_sig = TWAI1_BUS_OFF_ON_IDX, - .clk_out_sig = TWAI1_CLKOUT_IDX, - .stand_by_sig = TWAI1_STANDBY_IDX, - } - } + }; diff --git a/components/soc/esp32p4/uart_periph.c b/components/soc/esp32p4/uart_periph.c index 506d808273..2b0c63eb1b 100644 --- a/components/soc/esp32p4/uart_periph.c +++ b/components/soc/esp32p4/uart_periph.c @@ -10,71 +10,5 @@ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc */ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { - .pins = { - [SOC_UART_TX_PIN_IDX] = { - .default_gpio = U0TXD_GPIO_NUM, - .iomux_func = U0TXD_MUX_FUNC, - .input = 0, - .signal = 0, - }, - [SOC_UART_RX_PIN_IDX] = { - .default_gpio = U0RXD_GPIO_NUM, - .iomux_func = U0RXD_MUX_FUNC, - .input = 1, - .signal = 0, - }, - - [SOC_UART_RTS_PIN_IDX] = { - .default_gpio = U0RTS_GPIO_NUM, - .iomux_func = U0RTS_MUX_FUNC, - .input = 0, - .signal = 0, - }, - - [SOC_UART_CTS_PIN_IDX] = { - .default_gpio = U0CTS_GPIO_NUM, - .iomux_func = U0CTS_MUX_FUNC, - .input = 1, - .signal = 0, - } - }, - .irq = ETS_UART0_INTR_SOURCE, - .module = PERIPH_UART0_MODULE, - }, - - { - .pins = { - [SOC_UART_TX_PIN_IDX] = { - .default_gpio = U1TXD_GPIO_NUM, - .iomux_func = U1TXD_MUX_FUNC, - .input = 0, - .signal = 0, - }, - - [SOC_UART_RX_PIN_IDX] = { - .default_gpio = U1RXD_GPIO_NUM, - .iomux_func = U1RXD_MUX_FUNC, - .input = 1, - .signal = 0, - }, - - [SOC_UART_RTS_PIN_IDX] = { - .default_gpio = U1RTS_GPIO_NUM, - .iomux_func = U1RTS_MUX_FUNC, - .input = 0, - .signal = 0, - }, - - [SOC_UART_CTS_PIN_IDX] = { - .default_gpio = U1CTS_GPIO_NUM, - .iomux_func = U1CTS_MUX_FUNC, - .input = 1, - .signal = 0, - }, - }, - .irq = ETS_UART1_INTR_SOURCE, - .module = PERIPH_UART1_MODULE, - }, }; diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h index 725486d50f..80fd7187e1 100644 --- a/components/soc/include/soc/rtc_cntl_periph.h +++ b/components/soc/include/soc/rtc_cntl_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,15 +9,28 @@ #include "sdkconfig.h" // TODO: IDF-5645 -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_IDF_TARGET_ESP32C6 +#include "soc/lp_io_reg.h" +#include "soc/lp_io_struct.h" #include "soc/lp_aon_reg.h" + +// ESP32H2-TODO: IDF-6327 +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "soc/lp_aon_reg.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "soc/lp_gpio_reg.h" +#include "soc/lp_gpio_struct.h" +#include "soc/lp_iomux_reg.h" +#include "soc/lp_iomux_struct.h" +#endif + +// TODO: IDF-5645 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 #include "soc/lp_analog_peri_reg.h" #include "soc/lp_clkrst_reg.h" #include "soc/lp_clkrst_struct.h" #include "soc/lp_i2c_reg.h" #include "soc/lp_i2c_struct.h" -#include "soc/lp_io_reg.h" -#include "soc/lp_io_struct.h" #include "soc/lp_timer_reg.h" #include "soc/lp_timer_struct.h" #include "soc/lp_uart_reg.h" @@ -26,7 +39,6 @@ #include "soc/lp_wdt_struct.h" #elif CONFIG_IDF_TARGET_ESP32H2 // ESP32H2-TODO: IDF-6327 -#include "soc/lp_aon_reg.h" #include "soc/lp_analog_peri_reg.h" #include "soc/lp_clkrst_reg.h" #include "soc/lp_clkrst_struct.h"