From 663e88186852f66d4f5dc786d27ebe1016bf4538 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 22 Feb 2023 19:20:15 +0800 Subject: [PATCH] gdma: fix potential unaligned cache writeback issue --- components/esp_hw_support/dma/gdma.c | 5 ++++- components/soc/esp32s3/include/soc/Kconfig.soc_caps.in | 4 ---- components/soc/esp32s3/include/soc/soc_caps.h | 1 - 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index 101ccf4d39..1d55e466d5 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -18,6 +18,7 @@ #include "esp_memory_utils.h" #include "esp_private/periph_ctrl.h" #include "gdma_priv.h" +#include "hal/cache_hal.h" static const char *TAG = "gdma"; @@ -290,6 +291,7 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t ESP_GOTO_ON_FALSE((sram_alignment & (sram_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, err, TAG, "invalid sram alignment: %zu", sram_alignment); #if SOC_GDMA_SUPPORT_PSRAM + uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA); int block_size_index = 0; switch (psram_alignment) { case 64: // 64 Bytes alignment @@ -303,12 +305,13 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t break; case 0: // no alignment is requirement block_size_index = GDMA_LL_EXT_MEM_BK_SIZE_16B; - psram_alignment = SOC_GDMA_PSRAM_MIN_ALIGN; // fall back to minimal alignment + psram_alignment = data_cache_line_size; // fall back to use the same size of the psram data cache line size break; default: ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid psram alignment: %zu", psram_alignment); break; } + ESP_GOTO_ON_FALSE(((psram_alignment % data_cache_line_size) == 0), ESP_ERR_INVALID_ARG, err, TAG, "psram alignment (%d)B should be multiple of the data cache line size (%d)B", psram_alignment, data_cache_line_size); #endif // #if SOC_GDMA_SUPPORT_PSRAM if (dma_chan->direction == GDMA_CHANNEL_DIRECTION_TX) { diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index c800eec0be..4a1b43b728 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -363,10 +363,6 @@ config SOC_GDMA_SUPPORT_PSRAM bool default y -config SOC_GDMA_PSRAM_MIN_ALIGN - int - default 16 - config SOC_GPIO_PORT int default 1 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index db390b2a95..2b7134fc42 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -145,7 +145,6 @@ #define SOC_GDMA_GROUPS (1) // Number of GDMA groups #define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group #define SOC_GDMA_SUPPORT_PSRAM (1) // GDMA can access external PSRAM -#define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-S3 has 1 GPIO peripheral