From 66de4ef8ca590cc455f15daba0c967379cc32aff Mon Sep 17 00:00:00 2001 From: Samuel Obuch Date: Mon, 29 Sep 2025 11:49:35 +0200 Subject: [PATCH] fix(esp_rom): correct typos defalut -> default --- components/esp_rom/esp32c2/include/esp32c2/rom/cache.h | 2 +- components/esp_rom/esp32c2/ld/esp32c2.rom.ld | 2 +- components/esp_rom/esp32c3/include/esp32c3/rom/cache.h | 2 +- components/esp_rom/esp32c3/ld/esp32c3.rom.ld | 2 +- components/esp_rom/esp32s2/include/esp32s2/rom/cache.h | 2 +- components/esp_rom/esp32s2/ld/esp32s2.rom.ld | 2 +- components/esp_rom/esp32s3/include/esp32s3/rom/cache.h | 2 +- components/esp_rom/esp32s3/ld/esp32s3.rom.ld | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/components/esp_rom/esp32c2/include/esp32c2/rom/cache.h b/components/esp_rom/esp32c2/include/esp32c2/rom/cache.h index 39d6bbf9f76..4973003fd1e 100644 --- a/components/esp_rom/esp32c2/include/esp32c2/rom/cache.h +++ b/components/esp_rom/esp32c2/include/esp32c2/rom/cache.h @@ -401,7 +401,7 @@ void Cache_Set_Default_Mode(void); * * @return None */ -void Cache_Enable_Defalut_ICache_Mode(void); +void Cache_Enable_Default_ICache_Mode(void); /** * @brief Enable freeze for ICache. diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld index dd6f3f93324..8808b00589b 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld @@ -304,7 +304,7 @@ PROVIDE( Cache_Get_Mode = 0x400006e4 ); PROVIDE( Cache_Address_Through_IBus = 0x400006e8 ); PROVIDE( Cache_Address_Through_DBus = 0x400006ec ); PROVIDE( Cache_Set_Default_Mode = 0x400006f0 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 ); +PROVIDE( Cache_Enable_Default_ICache_Mode = 0x400006f4 ); PROVIDE( ROM_Boot_Cache_Init = 0x400006f8 ); PROVIDE( MMU_Set_Page_Mode = 0x400006fc ); PROVIDE( MMU_Get_Page_Mode = 0x40000700 ); diff --git a/components/esp_rom/esp32c3/include/esp32c3/rom/cache.h b/components/esp_rom/esp32c3/include/esp32c3/rom/cache.h index 2711cc37646..d9f89abb140 100644 --- a/components/esp_rom/esp32c3/include/esp32c3/rom/cache.h +++ b/components/esp_rom/esp32c3/include/esp32c3/rom/cache.h @@ -561,7 +561,7 @@ void Cache_Set_Default_Mode(void); * * @return None */ -void Cache_Enable_Defalut_ICache_Mode(void); +void Cache_Enable_Default_ICache_Mode(void); /** * @brief Enable freeze for ICache. diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld index d5c11903c5e..44cda153add 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld @@ -292,7 +292,7 @@ PROVIDE( Cache_Get_Mode = 0x400004b4 ); PROVIDE( Cache_Address_Through_IBus = 0x400004b8 ); PROVIDE( Cache_Address_Through_DBus = 0x400004bc ); PROVIDE( Cache_Set_Default_Mode = 0x400004c0 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004c4 ); +PROVIDE( Cache_Enable_Default_ICache_Mode = 0x400004c4 ); PROVIDE( ROM_Boot_Cache_Init = 0x400004c8 ); PROVIDE( Cache_Invalidate_ICache_Items = 0x400004cc ); PROVIDE( Cache_Op_Addr = 0x400004d0 ); diff --git a/components/esp_rom/esp32s2/include/esp32s2/rom/cache.h b/components/esp_rom/esp32s2/include/esp32s2/rom/cache.h index 751d633e6ca..47a0ffa68e4 100644 --- a/components/esp_rom/esp32s2/include/esp32s2/rom/cache.h +++ b/components/esp_rom/esp32s2/include/esp32s2/rom/cache.h @@ -860,7 +860,7 @@ void Cache_Set_Default_Mode(void); * * @return None */ -void Cache_Enable_Defalut_DCache_Mode(void); +void Cache_Enable_Default_DCache_Mode(void); /** * @brief Travel tag memory to run a call back function. diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld index 2256bc2b321..ed003db7a7c 100644 --- a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld +++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld @@ -29,7 +29,7 @@ PROVIDE ( Cache_Disable_ICache_PreLock = 0x4001892c ); PROVIDE ( Cache_Enable_DCache = 0x40018d58 ); PROVIDE ( Cache_Enable_DCache_Autoload = 0x40018874 ); PROVIDE ( Cache_Enable_DCache_PreLock = 0x400189f0 ); -PROVIDE ( Cache_Enable_Defalut_DCache_Mode = 0x40018170 ); +PROVIDE ( Cache_Enable_Default_DCache_Mode = 0x40018170 ); PROVIDE ( Cache_Enable_ICache = 0x40018cf8 ); PROVIDE ( Cache_Enable_ICache_Autoload = 0x40018744 ); PROVIDE ( Cache_Enable_ICache_PreLock = 0x400188c0 ); diff --git a/components/esp_rom/esp32s3/include/esp32s3/rom/cache.h b/components/esp_rom/esp32s3/include/esp32s3/rom/cache.h index 1a90324a05d..bfd4ba70fd0 100644 --- a/components/esp_rom/esp32s3/include/esp32s3/rom/cache.h +++ b/components/esp_rom/esp32s3/include/esp32s3/rom/cache.h @@ -990,7 +990,7 @@ void Cache_Set_Default_Mode(void); * * @return None */ -void Cache_Enable_Defalut_ICache_Mode(void); +void Cache_Enable_Default_ICache_Mode(void); /** * @brief Occupy the cache items for DCache. diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld index 4e9df1c155e..37eaaf71a1a 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld @@ -349,7 +349,7 @@ PROVIDE( Cache_Set_DCache_Mode = 0x4000162c ); PROVIDE( Cache_Address_Through_ICache = 0x40001638 ); PROVIDE( Cache_Address_Through_DCache = 0x40001644 ); PROVIDE( Cache_Set_Default_Mode = 0x40001650 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x4000165c ); +PROVIDE( Cache_Enable_Default_ICache_Mode = 0x4000165c ); PROVIDE( ROM_Boot_Cache_Init = 0x40001668 ); PROVIDE( Cache_Invalidate_ICache_Items = 0x40001674 ); PROVIDE( Cache_Invalidate_DCache_Items = 0x40001680 );