forked from espressif/esp-idf
Merge branch 'feat/c5_sdio' into 'master'
sdio: supported on c5 Closes IDF-12655 and IDF-12641 See merge request espressif/esp-idf!38652
This commit is contained in:
@@ -47,6 +47,13 @@ menu "Example Configuration"
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If the example does not work, please try disabling the HS mode.
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config EXAMPLE_SDIO_HOST_DELAY
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int "SDIO Host Delay"
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range 0 5
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default 0
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help
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SDIO Host delay phase
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config EXAMPLE_ADJUSTABLE_PIN
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bool
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default EXAMPLE_SDIO_OVER_SPI || SOC_SDMMC_USE_GPIO_MATRIX
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@@ -55,36 +62,42 @@ menu "Example Configuration"
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int "CMD (MOSI) GPIO number"
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depends on EXAMPLE_ADJUSTABLE_PIN
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range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
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default 4 if IDF_TARGET_ESP32P4
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default 15
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config EXAMPLE_PIN_CLK
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int "CLK GPIO number"
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depends on EXAMPLE_ADJUSTABLE_PIN
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range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
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default 33 if IDF_TARGET_ESP32P4
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default 14
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config EXAMPLE_PIN_D0
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int "D0 (MISO) GPIO number"
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depends on EXAMPLE_ADJUSTABLE_PIN
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range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
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default 32 if IDF_TARGET_ESP32P4
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default 2
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config EXAMPLE_PIN_D1
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int "D1 (INTR) GPIO number"
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depends on EXAMPLE_ADJUSTABLE_PIN
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range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
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default 23 if IDF_TARGET_ESP32P4
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default 4
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config EXAMPLE_PIN_D2
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int "D2 GPIO number"
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depends on EXAMPLE_ADJUSTABLE_PIN
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range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
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default 53 if IDF_TARGET_ESP32P4
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default 12
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config EXAMPLE_PIN_D3
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int "D3 (CS) GPIO number"
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depends on EXAMPLE_ADJUSTABLE_PIN
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range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
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default 5 if IDF_TARGET_ESP32P4
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default 13
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choice EXAMPLE_SLAVE
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@@ -100,11 +113,11 @@ menu "Example Configuration"
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endchoice
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config EXAMPLE_SLAVE_PWR_NEGTIVE_ACTIVE
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bool "Slave power control pin is negtive active, otherwise postive active"
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bool "Slave power control pin is negative active, otherwise positive active"
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depends on !EXAMPLE_SLAVE_NONE
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default n
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help
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Slave power control pin is negtive active, otherwise postive active
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Slave power control pin is negative active, otherwise positive active
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config EXAMPLE_NO_INTR_LINE
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bool "The host is not connected to the interrupt line (DAT1) of slave"
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@@ -78,12 +78,12 @@
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- 0 is the register to hold tasks. Bits:
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- 0: the slave should reset.
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- 1: the slave should send interrupts.
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- 2: the slave should write the shared registers acoording to the value in register 1.
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- 2: the slave should write the shared registers according to the value in register 1.
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- 1 is the register to hold test value.
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- other registers will be written by the slave for testing.
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- FIFO:
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The receving FIFO is size of 256 bytes.
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The receiving FIFO is size of 256 bytes.
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When the host writes something to slave recv FIFO, the slave should return it as is to the sending FIFO.
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The example works as following process:
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@@ -190,6 +190,7 @@ esp_err_t slave_init(essl_handle_t* handle)
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ESP_LOGI(TAG, "Probe using SD 1-bit...");
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config.flags = SDMMC_HOST_FLAG_1BIT;
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#endif
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config.input_delay_phase = CONFIG_EXAMPLE_SDIO_HOST_DELAY;
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#ifdef CONFIG_EXAMPLE_SDIO_HIGHSPEED
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config.max_freq_khz = SDMMC_FREQ_HIGHSPEED;
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@@ -440,7 +441,7 @@ void job_fifo(essl_handle_t handle)
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/* CAUTION: This example shows that we can send random length of packet to the slave.
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* However it takes time of two transactions if the length is not multiples of 4 bytes.
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* e.g. sending 6 bytes is done by sending 4 + 2 bytes each transaction.
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* Try to avoid unaligned packets if possible to get higher effeciency.
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* Try to avoid unaligned packets if possible to get higher efficiency.
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*/
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for (int i = 0; i < sizeof(packet_len) / sizeof(int); i++) {
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//Prepare data to send. The length can be random, but data should start at the 32-bit boundary.
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@@ -0,0 +1,2 @@
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## On P4-SDMMC + C5 SDIO test runner environment, hardware delay needs to be considered
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CONFIG_EXAMPLE_SDIO_HOST_DELAY=2
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@@ -1,4 +1,4 @@
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| Supported Targets | ESP32 | ESP32-C6 |
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| ----------------- | ----- | -------- |
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| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 |
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| ----------------- | ----- | -------- | -------- |
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See README.md in the parent folder
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