From ff3320ca8aa576e36a5fefd51551bf0c89d97603 Mon Sep 17 00:00:00 2001 From: Shu Chen Date: Fri, 23 Apr 2021 18:10:45 +0800 Subject: [PATCH] esp32c3: fix typos of c3 path --- components/esp_hw_support/sleep_modes.c | 2 +- components/esp_system/port/cpu_start.c | 13 +++++-------- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index d2e6af647a..64a8c49d15 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -68,7 +68,7 @@ #include "soc/extmem_reg.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/clk.h" -#include "esp32s3/rom/cache.h" +#include "esp32c3/rom/cache.h" #include "esp32c3/rom/rtc.h" #include "soc/extmem_reg.h" #include "esp_heap_caps.h" diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 65fd8ec570..59e9eb10ef 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -56,7 +56,7 @@ #include "soc/system_reg.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#include "esp32s3/rom/cache.h" +#include "esp32c3/rom/cache.h" #include "esp32c3/rom/rtc.h" #include "soc/cache_memory.h" #include "esp32c3/memprot.h" @@ -85,16 +85,13 @@ #if CONFIG_APP_BUILD_TYPE_ELF_RAM #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/spi_flash.h" -#endif // CONFIG_IDF_TARGET_ESP32 -#if CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/spi_flash.h" -#endif // CONFIG_IDF_TARGET_ESP32S2 -#if CONFIG_IDF_TARGET_ESP32S3 +#elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/spi_flash.h" -#endif // CONFIG_IDF_TARGET_ESP32S3 -#if CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/spi_flash.h" -#endif // CONFIG_IDF_TARGET_ESP32C3 +#endif #endif // CONFIG_APP_BUILD_TYPE_ELF_RAM // Set efuse ROM_LOG_MODE on first boot