diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 57d254337e..dd5c3335f2 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -29,6 +29,11 @@
 #include "hal/systimer_ll.h"
 #endif
 
+#if SOC_SLEEP_TGWDT_STOP_WORKAROUND
+#include "hal/mwdt_ll.h"
+#include "hal/timer_ll.h"
+#endif
+
 #include "driver/uart.h"
 
 #include "soc/rtc.h"
@@ -305,6 +310,52 @@ void esp_deep_sleep(uint64_t time_in_us)
     esp_deep_sleep_start();
 }
 
+#if SOC_SLEEP_TGWDT_STOP_WORKAROUND
+static uint32_t s_stopped_tgwdt_bmap = 0;
+#endif
+
+// Must be called from critical sections.
+static void IRAM_ATTR suspend_timers(uint32_t pd_flags) {
+    if (!(pd_flags & RTC_SLEEP_PD_XTAL)) {
+#if SOC_SLEEP_TGWDT_STOP_WORKAROUND
+        /* If timegroup implemented task watchdog or interrupt watchdog is running, we have to stop it. */
+        for (uint32_t tg_num = 0; tg_num < SOC_TIMER_GROUPS; ++tg_num) {
+            if (mwdt_ll_check_if_enabled(TIMER_LL_GET_HW(tg_num))) {
+                mwdt_ll_write_protect_disable(TIMER_LL_GET_HW(tg_num));
+                mwdt_ll_disable(TIMER_LL_GET_HW(tg_num));
+                mwdt_ll_write_protect_enable(TIMER_LL_GET_HW(tg_num));
+                s_stopped_tgwdt_bmap |= BIT(tg_num);
+            }
+        }
+#endif
+#if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
+        for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
+            systimer_ll_enable_counter(&SYSTIMER, counter_id, false);
+        }
+#endif
+    }
+}
+
+// Must be called from critical sections.
+static void IRAM_ATTR resume_timers(uint32_t pd_flags) {
+    if (!(pd_flags & RTC_SLEEP_PD_XTAL)) {
+#if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
+        for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
+            systimer_ll_enable_counter(&SYSTIMER, counter_id, true);
+        }
+#endif
+#if SOC_SLEEP_TGWDT_STOP_WORKAROUND
+        for (uint32_t tg_num = 0; tg_num < SOC_TIMER_GROUPS; ++tg_num) {
+            if (s_stopped_tgwdt_bmap & BIT(tg_num)) {
+                mwdt_ll_write_protect_disable(TIMER_LL_GET_HW(tg_num));
+                mwdt_ll_enable(TIMER_LL_GET_HW(tg_num));
+                mwdt_ll_write_protect_enable(TIMER_LL_GET_HW(tg_num));
+            }
+        }
+#endif
+    }
+}
+
 // [refactor-todo] provide target logic for body of uart functions below
 static void IRAM_ATTR flush_uarts(void)
 {
@@ -581,25 +632,13 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
 #endif
 #endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
     } else {
-#if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
-        if (!(pd_flags & RTC_SLEEP_PD_XTAL)) {
-            for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
-                systimer_ll_enable_counter(&SYSTIMER, counter_id, false);
-            }
-        }
-#endif
+        suspend_timers(pd_flags);
         /* Wait cache idle in cache suspend to avoid cache load wrong data after spi io isolation */
         cache_hal_suspend(CACHE_TYPE_ALL);
         result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu);
         /* Resume cache for continue running */
         cache_hal_resume(CACHE_TYPE_ALL);
-#if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
-        if (!(pd_flags & RTC_SLEEP_PD_XTAL)) {
-            for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
-                systimer_ll_enable_counter(&SYSTIMER, counter_id, true);
-            }
-        }
-#endif
+        resume_timers(pd_flags);
     }
 
     // Restore CPU frequency
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index d74a611cdb..49fbbbf26d 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -487,6 +487,10 @@ config SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
     bool
     default y
 
+config SOC_SLEEP_TGWDT_STOP_WORKAROUND
+    bool
+    default y
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 0
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 4898a43132..1ac7d097f8 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -225,6 +225,7 @@
 #define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256       (1)
 
 #define SOC_SLEEP_SYSTIMER_STALL_WORKAROUND     (1)
+#define SOC_SLEEP_TGWDT_STOP_WORKAROUND         (1)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 /* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported