diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt
index 61863f28a1..ad5e37ad64 100644
--- a/components/esp_hw_support/CMakeLists.txt
+++ b/components/esp_hw_support/CMakeLists.txt
@@ -125,6 +125,10 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "sleep_wake_stub.c")
     endif()
 
+    if(CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX OR CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX)
+        list(APPEND srcs "esp_clock_output.c")
+    endif()
+
     if(CONFIG_IDF_TARGET_ESP32P4)
         list(REMOVE_ITEM srcs
                 "sleep_cpu.c"         # TODO: IDF-7528, IDF-7529
diff --git a/components/esp_hw_support/esp_clock_output.c b/components/esp_hw_support/esp_clock_output.c
new file mode 100644
index 0000000000..89397f59fb
--- /dev/null
+++ b/components/esp_hw_support/esp_clock_output.c
@@ -0,0 +1,164 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+
+#include "driver/gpio.h"
+#include "esp_clock_output.h"
+#include "esp_check.h"
+#include "esp_rom_gpio.h"
+#include "esp_private/clkout_channel.h"
+#include "esp_private/startup_internal.h"
+#include "hal/gpio_hal.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+
+typedef struct gpio_clock_out_ctx {
+    bool is_mapped;
+    uint8_t ref_cnt;
+    clock_out_channel_t clk_out;
+    gpio_num_t mapped_io;
+    soc_clkout_sig_id_t mapped_clock;
+} gpio_clock_out_ctx_t;
+
+static const char *TAG = "gpio_output_clk";
+
+static portMUX_TYPE s_clkout_channel_lock = portMUX_INITIALIZER_UNLOCKED;
+
+static gpio_clock_out_ctx_t s_pin_ctrl_clk_out[CLKOUT_CHANNEL_MAX] = {
+    [0 ... CLKOUT_CHANNEL_MAX - 1] = {
+        .is_mapped = false,
+        .ref_cnt = 0,
+    }
+};
+
+static gpio_clock_out_ctx_t* io_mux_pin_ctrl_clk_out_alloc(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num)
+{
+    gpio_clock_out_ctx_t *allocated_clk_out = NULL;
+
+#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
+    portENTER_CRITICAL(&s_clkout_channel_lock);
+    if (!s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].is_mapped) {
+        s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].is_mapped = true;
+        s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].clk_out = IONUM_TO_CLKOUT(gpio_num);
+        allocated_clk_out = &s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)];
+    } else if ((s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].mapped_io == gpio_num) &&
+        (s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].mapped_clock == clk_sig)) {
+        allocated_clk_out = &s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)];
+    }
+    portEXIT_CRITICAL(&s_clkout_channel_lock);
+#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    for(uint32_t i = 0; i < CLKOUT_CHANNEL_MAX; i++) {
+        portENTER_CRITICAL(&s_clkout_channel_lock);
+        if (!s_pin_ctrl_clk_out[i].is_mapped) {
+            s_pin_ctrl_clk_out[i].is_mapped = true;
+            s_pin_ctrl_clk_out[i].clk_out = (clock_out_channel_t)i;
+            allocated_clk_out = &s_pin_ctrl_clk_out[i];
+            portEXIT_CRITICAL(&s_clkout_channel_lock);
+            break;
+        } else if ((s_pin_ctrl_clk_out[i].mapped_io == gpio_num) &&
+            (s_pin_ctrl_clk_out[i].mapped_clock == clk_sig)) {
+            allocated_clk_out = &s_pin_ctrl_clk_out[i];
+            portEXIT_CRITICAL(&s_clkout_channel_lock);
+            break;
+        }
+        portEXIT_CRITICAL(&s_clkout_channel_lock);
+    }
+#endif
+
+    if (allocated_clk_out != NULL) {
+        portENTER_CRITICAL(&s_clkout_channel_lock);
+        allocated_clk_out->mapped_io = gpio_num;
+        allocated_clk_out->mapped_clock = clk_sig;
+        allocated_clk_out->ref_cnt++;
+        portEXIT_CRITICAL(&s_clkout_channel_lock);
+    }
+
+    return allocated_clk_out;
+}
+
+static bool io_mux_pin_ctrl_clk_out_sig_try_free(gpio_clock_out_handle_t clk_out_hdl)
+{
+    bool do_free = false;
+    portENTER_CRITICAL(&s_clkout_channel_lock);
+    if (--clk_out_hdl->ref_cnt == 0) {
+        do_free = true;
+        clk_out_hdl->is_mapped = false;
+    }
+    portEXIT_CRITICAL(&s_clkout_channel_lock);
+    return do_free;
+}
+
+esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, gpio_clock_out_handle_t *clk_out_hdl)
+{
+    ESP_RETURN_ON_FALSE((clk_out_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out handle passed in is invalid");
+
+    ESP_RETURN_ON_FALSE(IS_VALID_CLKOUT_IO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "%s", "Output GPIO number error");
+
+     gpio_clock_out_ctx_t* new_hdl= io_mux_pin_ctrl_clk_out_alloc(clk_sig, gpio_num);
+
+#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
+    ESP_RETURN_ON_FALSE((new_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Selected clock out IO is already mapped to other internal clock source");
+#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    ESP_RETURN_ON_FALSE((new_hdl != NULL), ESP_FAIL, TAG, "Maximum support for %d output clock signals, no available clock_out channel for assignment", CLKOUT_CHANNEL_MAX);
+#endif
+
+    if (new_hdl->ref_cnt == 1) {
+        uint32_t clk_out_mask = (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? CLK_OUT1 :
+                                (new_hdl->clk_out == CLKOUT_CHANNEL_2) ? CLK_OUT2 :
+                                (new_hdl->clk_out == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0;
+        uint32_t clk_out_shift =    (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? CLK_OUT1_S :
+                                    (new_hdl->clk_out == CLKOUT_CHANNEL_2) ? CLK_OUT2_S :
+                                    (new_hdl->clk_out == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0;
+
+        portENTER_CRITICAL(&s_clkout_channel_lock);
+        gpio_ll_set_pin_ctrl(clk_sig, clk_out_mask, clk_out_shift);
+        portEXIT_CRITICAL(&s_clkout_channel_lock);
+
+#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
+        uint32_t clk_out_func = (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? FUNC_CLK_OUT1 :
+                                (new_hdl->clk_out == CLKOUT_CHANNEL_2) ? FUNC_CLK_OUT2 :
+                                (new_hdl->clk_out == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : 0;
+
+        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], clk_out_func);
+#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+        uint32_t gpio_clk_out_sig_idx = (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX :
+                                        (new_hdl->clk_out == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX :
+                                        (new_hdl->clk_out == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX;
+
+        gpio_set_pull_mode(gpio_num, GPIO_FLOATING);
+        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
+        gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
+        esp_rom_gpio_connect_out_signal(gpio_num, gpio_clk_out_sig_idx, false, false);
+#endif
+    }
+
+    *clk_out_hdl = new_hdl;
+    return ESP_OK;
+}
+
+esp_err_t esp_clock_output_stop(gpio_clock_out_handle_t clk_out_hdl)
+{
+    assert(clk_out_hdl != NULL);
+    ESP_RETURN_ON_FALSE(clk_out_hdl->is_mapped, ESP_ERR_INVALID_STATE, TAG, "%s", "Clock outputting is already disabled");
+    if (io_mux_pin_ctrl_clk_out_sig_try_free(clk_out_hdl)) {
+        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[clk_out_hdl->mapped_io], PIN_FUNC_GPIO);
+        esp_rom_gpio_connect_out_signal(clk_out_hdl->mapped_io, SIG_GPIO_OUT_IDX, false, false);
+        gpio_set_direction(clk_out_hdl->mapped_io, GPIO_MODE_DISABLE);
+    }
+    return ESP_OK;
+}
+
+#if CONFIG_IDF_TARGET_ESP32
+// Due to a hardware bug, PIN_CTRL cannot select 0xf output, whereas 0xf is the default value.
+__attribute__((constructor))
+static void esp_clock_output_pin_ctrl_init(void)
+{
+    gpio_ll_set_pin_ctrl(0, CLK_OUT1, CLK_OUT1_S);
+    gpio_ll_set_pin_ctrl(0, CLK_OUT2, CLK_OUT2_S);
+    gpio_ll_set_pin_ctrl(0, CLK_OUT3, CLK_OUT3_S);
+}
+#endif
diff --git a/components/esp_hw_support/include/esp_clock_output.h b/components/esp_hw_support/include/esp_clock_output.h
new file mode 100644
index 0000000000..1ccf58a6a6
--- /dev/null
+++ b/components/esp_hw_support/include/esp_clock_output.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+#include "soc/clk_tree_defs.h"
+
+#include "esp_err.h"
+#include "driver/gpio.h"
+#include "freertos/FreeRTOS.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX || SOC_GPIO_CLOCKOUT_BY_IO_MUX
+typedef struct gpio_clock_out_ctx* gpio_clock_out_handle_t;
+
+/**
+ * @brief Start output specified clock signal to specified GPIO, will also
+ *        initialize the clk_out_hdl.
+ *
+ * @param[in]   clk_src  The clock signal source to be mapped to GPIOs
+ * @param[in]   gpio_num GPIO number to be mapped soc_root_clk signal source
+ * @param[out]  clk_out_hdl Clock output controll handler
+ * @return
+ *      - ESP_OK: Output specified clock signal to specified GPIO successfully
+ *      - ESP_ERR_INVALID_ARG: Specified GPIO not supported to output internal clock
+ *                             or specified GPIO is already mapped to other internal clock source.
+  *     - ESP_FAIL: There are no clock out signals that can be allocated.
+ */
+esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, gpio_clock_out_handle_t *clk_out_hdl);
+
+/**
+ * @brief Stop clock signal to GPIO outputting
+ * @param[in]  clk_out_hdl Clock output controll handle
+ * @return
+ *     - ESP_OK: Disable the clock output on GPIO successfully
+ *     - ESP_ERR_INVALID_STATE  The clock in handle is already in the disabled state
+ */
+esp_err_t esp_clock_output_stop(gpio_clock_out_handle_t clk_out_hdl);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_hw_support/include/esp_private/clkout_channel.h b/components/esp_hw_support/include/esp_private/clkout_channel.h
new file mode 100644
index 0000000000..ff6e580273
--- /dev/null
+++ b/components/esp_hw_support/include/esp_private/clkout_channel.h
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
+#if CONFIG_IDF_TARGET_ESP32
+#define CLKOUT_CHANNEL1_GPIO    GPIO_NUM_0
+#define CLKOUT_CHANNEL2_GPIO    GPIO_NUM_3
+#define CLKOUT_CHANNEL3_GPIO    GPIO_NUM_1
+#define FUNC_CLK_OUT1           FUNC_GPIO0_CLK_OUT1
+#define FUNC_CLK_OUT2           FUNC_U0RXD_CLK_OUT2
+#define FUNC_CLK_OUT3           FUNC_U0TXD_CLK_OUT3
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#define CLKOUT_CHANNEL1_GPIO    GPIO_NUM_20
+#define CLKOUT_CHANNEL2_GPIO    GPIO_NUM_19
+#define CLKOUT_CHANNEL3_GPIO    GPIO_NUM_18
+#define FUNC_CLK_OUT1           FUNC_GPIO20_CLK_OUT1
+#define FUNC_CLK_OUT2           FUNC_GPIO19_CLK_OUT2
+#define FUNC_CLK_OUT3           FUNC_DAC_2_CLK_OUT3
+#endif
+#define IS_VALID_CLKOUT_IO(gpio_num)    ((gpio_num == CLKOUT_CHANNEL1_GPIO) || (gpio_num == CLKOUT_CHANNEL2_GPIO) || (gpio_num == CLKOUT_CHANNEL3_GPIO))
+#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+#define IS_VALID_CLKOUT_IO(gpio_num)    GPIO_IS_VALID_GPIO(gpio_num)
+#endif
+
+#define IONUM_TO_CLKOUT(gpio_num)       ((gpio_num == CLKOUT_CHANNEL1_GPIO) ? CLKOUT_CHANNEL_1 : \
+                                         (gpio_num == CLKOUT_CHANNEL2_GPIO) ? CLKOUT_CHANNEL_2 : \
+                                         (gpio_num == CLKOUT_CHANNEL3_GPIO) ? CLKOUT_CHANNEL_3 : 0)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
index 9e71a8a2c0..e51f180e76 100644
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -315,6 +315,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
     default 0xEF0FEA
 
+config SOC_GPIO_CLOCKOUT_BY_IO_MUX
+    bool
+    default y
+
 config SOC_I2C_NUM
     int
     default 2
diff --git a/components/soc/esp32/include/soc/clk_tree_defs.h b/components/soc/esp32/include/soc/clk_tree_defs.h
index 4f636913d2..e536d0c951 100644
--- a/components/soc/esp32/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32/include/soc/clk_tree_defs.h
@@ -441,6 +441,21 @@ typedef enum {
     SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
 } soc_periph_sdmmc_clk_src_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_I2S0     = 0,    /*!< I2S0 clock, depends on the i2s driver configuration */
+    CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
+    CLKOUT_SIG_RC_SLOW  = 4,    /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_XTAL     = 5,    /*!< Main crystal oscillator clock */
+    CLKOUT_SIG_APLL     = 6,    /*!< Divided by PLL, frequency is configurable */
+    CLKOUT_SIG_REF_TICK = 12,   /*!< Divided by APB clock, usually be 1MHz */
+    CLKOUT_SIG_PLL_F80M = 13,   /*!< From PLL, usually be 80MHz */
+    CLKOUT_SIG_RC_FAST  = 14,   /*!< RC fast clock, about 8MHz */
+    CLKOUT_SIG_I2S1     = 15,   /*!< I2S1 clock, depends on the i2s driver configuration */
+    CLKOUT_SIG_INVALID  = 0xFF,
+} soc_clkout_sig_id_t;
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32/include/soc/clkout_channel.h b/components/soc/esp32/include/soc/clkout_channel.h
deleted file mode 100644
index a2b05fcb2c..0000000000
--- a/components/soc/esp32/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _SOC_CLKOUT_CHANNEL_H
-#define _SOC_CLKOUT_CHANNEL_H
-
-//CLKOUT channels
-#define CLKOUT_IOMUX_FUNC_NUM               1
-
-#define CLKOUT_GPIO0_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
-#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM    0
-#define CLKOUT_GPIO3_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
-#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM    3
-#define CLKOUT_GPIO1_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
-#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM    1
-
-#endif
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index 5d1d1d68fd..7c83fa9949 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -181,6 +181,9 @@
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23)
 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL
 
+// The Clock Out singnal is binding to the pin's IO_MUX function
+#define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
+
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32 has 2 I2C
 #define SOC_I2C_NUM             (2)
diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
index 1c876e0bdc..080f24a2a2 100644
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -279,6 +279,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
     default 0x00000000001FFFC0
 
+config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    bool
+    default y
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h
index 4aaf76d103..ae3668c770 100644
--- a/components/soc/esp32c2/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h
@@ -285,6 +285,16 @@ typedef enum {
     LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
 } soc_periph_ledc_clk_src_legacy_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
+    CLKOUT_SIG_RC_SLOW  = 4,    /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_XTAL     = 5,    /*!< Main crystal oscillator clock */
+    CLKOUT_SIG_PLL_F80M = 13,   /*!< From PLL, usually be 80MHz */
+    CLKOUT_SIG_RC_FAST  = 14,   /*!< RC fast clock, about 8MHz */
+    CLKOUT_SIG_INVALID  = 0xFF,
+} soc_clkout_sig_id_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c2/include/soc/clkout_channel.h b/components/soc/esp32c2/include/soc/clkout_channel.h
deleted file mode 100644
index ceb3369171..0000000000
--- a/components/soc/esp32c2/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _SOC_CLKOUT_CHANNEL_H
-#define _SOC_CLKOUT_CHANNEL_H
-
-// ESP32C2 CLKOUT signals has no corresponding iomux pins
-
-#endif
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index 21940700b5..805dbbf8a5 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -136,6 +136,9 @@
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)
 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL
 
+// The Clock Out singnal is route to the pin by GPIO matrix
+#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index 25c23a3320..0e433b9c2b 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -371,6 +371,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
     default 0x00000000003FFFC0
 
+config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    bool
+    default y
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32c3/include/soc/clk_tree_defs.h b/components/soc/esp32c3/include/soc/clk_tree_defs.h
index 3eb948f397..7dc874c333 100644
--- a/components/soc/esp32c3/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c3/include/soc/clk_tree_defs.h
@@ -357,6 +357,16 @@ typedef enum {
     LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
 } soc_periph_ledc_clk_src_legacy_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
+    CLKOUT_SIG_RC_SLOW  = 4,    /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_XTAL     = 5,    /*!< Main crystal oscillator clock */
+    CLKOUT_SIG_PLL_F80M = 13,   /*!< From PLL, usually be 80MHz */
+    CLKOUT_SIG_RC_FAST  = 14,   /*!< RC fast clock, about 17.5MHz */
+    CLKOUT_SIG_INVALID  = 0xFF,
+} soc_clkout_sig_id_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c3/include/soc/clkout_channel.h b/components/soc/esp32c3/include/soc/clkout_channel.h
deleted file mode 100644
index 0d36368328..0000000000
--- a/components/soc/esp32c3/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _SOC_CLKOUT_CHANNEL_H
-#define _SOC_CLKOUT_CHANNEL_H
-
-// ESP32C3 CLKOUT signals has no corresponding iomux pins
-
-#endif
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index e2bf720dde..27ac1025f5 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -174,6 +174,9 @@
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL
 
+// The Clock Out singnal is route to the pin by GPIO matrix
+#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index c4287d6d54..fd64e06298 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -475,6 +475,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    bool
+    default y
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 8
diff --git a/components/soc/esp32c6/include/soc/clk_tree_defs.h b/components/soc/esp32c6/include/soc/clk_tree_defs.h
index 97539e6355..0d47064956 100644
--- a/components/soc/esp32c6/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c6/include/soc/clk_tree_defs.h
@@ -463,6 +463,22 @@ typedef enum {
     PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M,   /*!< Select PLL_F240M as the default clock choice */
 } soc_periph_parlio_clk_src_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
+    CLKOUT_SIG_XTAL     = 5,    /*!< Main crystal oscillator clock */
+    CLKOUT_SIG_PLL_F80M = 13,   /*!< From PLL, usually be 80MHz */
+    CLKOUT_SIG_CPU      = 16,   /*!< CPU clock */
+    CLKOUT_SIG_AHB      = 17,   /*!< AHB clock */
+    CLKOUT_SIG_APB      = 18,   /*!< APB clock */
+    CLKOUT_SIG_XTAL32K  = 21,   /*!< External 32kHz crystal clock */
+    CLKOUT_SIG_EXT32K   = 22,   /*!< External slow clock input through XTAL_32K_P */
+    CLKOUT_SIG_RC_FAST  = 23,   /*!< RC fast clock, about 17.5MHz */
+    CLKOUT_SIG_RC_32K   = 24,   /*!< Internal slow RC oscillator */
+    CLKOUT_SIG_RC_SLOW  = 25,   /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_INVALID  = 0xFF,
+} soc_clkout_sig_id_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c6/include/soc/clkout_channel.h b/components/soc/esp32c6/include/soc/clkout_channel.h
deleted file mode 100644
index 035248b78d..0000000000
--- a/components/soc/esp32c6/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-// ESP32C6 CLKOUT signals has no corresponding iomux pins
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 737ee15612..ed69e78246 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -208,6 +208,9 @@
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
+// The Clock Out singnal is route to the pin by GPIO matrix
+#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 8
 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1  /* This macro indicates that the target has separate RTC IOMUX hardware feature,
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index d576e5821f..adc34fbbc8 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -467,6 +467,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    bool
+    default y
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 8
diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h
index b8a91f4dfe..d56380c04a 100644
--- a/components/soc/esp32h2/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h
@@ -479,6 +479,20 @@ typedef enum {
     MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as ROM default clock source */
 } soc_periph_mspi_clk_src_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_XTAL    = 5,     /*!< Main crystal oscillator clock */
+    CLKOUT_SIG_CPU     = 16,    /*!< CPU clock */
+    CLKOUT_SIG_AHB     = 17,    /*!< AHB clock */
+    CLKOUT_SIG_APB     = 18,    /*!< APB clock */
+    CLKOUT_SIG_XTAL32K = 21,    /*!< External 32kHz crystal clock */
+    CLKOUT_SIG_EXT32K  = 22,    /*!< External slow clock input through XTAL_32K_P */
+    CLKOUT_SIG_RC_FAST = 23,    /*!< RC fast clock, about 17.5MHz */
+    CLKOUT_SIG_RC_32K  = 24,    /*!< Internal slow RC oscillator */
+    CLKOUT_SIG_RC_SLOW = 25,    /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_INVALID = 0xFF,
+} soc_clkout_sig_id_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32h2/include/soc/clkout_channel.h b/components/soc/esp32h2/include/soc/clkout_channel.h
deleted file mode 100644
index d580d83c49..0000000000
--- a/components/soc/esp32h2/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-// ESP32H2 CLKOUT signals has no corresponding iomux pins
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index bffa8ee12d..9a3231707e 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -210,6 +210,9 @@
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
+// The Clock Out singnal is route to the pin by GPIO matrix
+#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 /* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported
  * for hold, wake & 32kHz crystal functions - via LP_AON registers */
diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h
deleted file mode 100644
index 4064eaf8d2..0000000000
--- a/components/soc/esp32p4/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-// ESP32P4 CLKOUT signals has no corresponding iomux pins
diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
index 3bb460933a..f5813cc213 100644
--- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
@@ -367,6 +367,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
     default 0x00007FFFFC000000
 
+config SOC_GPIO_CLOCKOUT_BY_IO_MUX
+    bool
+    default y
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32s2/include/soc/clk_tree_defs.h b/components/soc/esp32s2/include/soc/clk_tree_defs.h
index 5eb67a1921..bbc4981660 100644
--- a/components/soc/esp32s2/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32s2/include/soc/clk_tree_defs.h
@@ -415,6 +415,18 @@ typedef enum {
     LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
 } soc_periph_ledc_clk_src_legacy_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
+    CLKOUT_SIG_RC_SLOW  = 4,    /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_XTAL     = 5,    /*!< Main crystal oscillator clock */
+    CLKOUT_SIG_APLL     = 6,    /*!< Divided by PLL, frequency is configurable */
+    CLKOUT_SIG_REF_TICK = 12,   /*!< Divided by APB clock, usually be 1MHz */
+    CLKOUT_SIG_PLL_F80M = 13,   /*!< From PLL, usually be 80MHz */
+    CLKOUT_SIG_RC_FAST  = 14,   /*!< RC fast clock, about 17.5MHz */
+    CLKOUT_SIG_INVALID  = 0xFF,
+} soc_clkout_sig_id_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32s2/include/soc/clkout_channel.h b/components/soc/esp32s2/include/soc/clkout_channel.h
deleted file mode 100644
index abecc7bd64..0000000000
--- a/components/soc/esp32s2/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _SOC_CLKOUT_CHANNEL_H
-#define _SOC_CLKOUT_CHANNEL_H
-
-//CLKOUT channels
-#define CLKOUT_IOMUX_FUNC_NUM                3
-
-#define CLKOUT_GPIO20_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
-#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM     20
-#define CLKOUT_GPIO19_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
-#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM     19
-#define CLKOUT_GPIO18_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
-#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM     18
-
-#endif
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index 449847b000..575df03bf6 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -171,6 +171,9 @@
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_46)
 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK  0x00007FFFFC000000ULL
 
+// The Clock Out singnal is binding to the pin's IO_MUX function
+#define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
+
 /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
index 9fa6d132c9..3da46a8c1d 100644
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@@ -435,6 +435,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
     default 0x0001FFFFFC000000
 
+config SOC_GPIO_CLOCKOUT_BY_IO_MUX
+    bool
+    default y
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32s3/include/soc/clk_tree_defs.h b/components/soc/esp32s3/include/soc/clk_tree_defs.h
index d3fadb96b1..881c2b3a1f 100644
--- a/components/soc/esp32s3/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32s3/include/soc/clk_tree_defs.h
@@ -444,6 +444,15 @@ typedef enum {
     SDMMC_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,          /*!< Select XTAL as the source clock */
 } soc_periph_sdmmc_clk_src_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
+    CLKOUT_SIG_RC_SLOW  = 4,    /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
+    CLKOUT_SIG_XTAL     = 5,    /*!< Main crystal oscillator clock */
+    CLKOUT_SIG_PLL_F80M = 13,   /*!< From PLL, usually be 80MHz */
+    CLKOUT_SIG_RC_FAST  = 14,   /*!< RC fast clock, about 17.5MHz */
+    CLKOUT_SIG_INVALID  = 0xFF,
+} soc_clkout_sig_id_t;
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32s3/include/soc/clkout_channel.h b/components/soc/esp32s3/include/soc/clkout_channel.h
deleted file mode 100644
index 2dd19304ba..0000000000
--- a/components/soc/esp32s3/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-//CLKOUT channels
-#define CLKOUT_IOMUX_FUNC_NUM                3
-
-#define CLKOUT_GPIO20_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
-#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM     20
-#define CLKOUT_GPIO19_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
-#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM     19
-#define CLKOUT_GPIO18_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
-#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM     18
-
-// ESP32S3 has two other sets of GPIO pins which could route to CLKOUT_CHANNEL_1/2/3 through IO_MUX
-// Please check TRM IO MUX Function List table if needed
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index c74a883913..42aeff02e3 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -177,6 +177,9 @@
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_48)
 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000ULL
 
+// The Clock Out singnal is binding to the pin's IO_MUX function
+#define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
+
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */